Array substrate and preparation method thereof, display panel and electronic equipment

Abstract

The invention provides an array substrate and a preparation method thereof, a display panel and electronic equipment, relates to the technical field of display, and improves the display effect of the display panel at low gray scale. The array substrate comprises a substrate and a plurality of conductive layers which are arranged on one side of the substrate and insulated from one another, and the plurality of conductive layers comprise a first conductive layer which is stacked on one side of the substrate and comprises a first conductive section; the first metal layer comprises a scanning signal line and a grid electrode; a second metal layer; a third metal layer; a second conductive layer including a second conductive section; the array substrate further comprises an insulating layer which is stacked between the first metal layer and the second conductive layer and comprises a first through hole and a second through hole. The first through hole and the second through hole are filled with the second conductive section, one end of the second conductive section is connected with the first conductive section through the first through hole, and the other end of the second conductive section is connected with the grid electrode through the second through hole, so that stray capacitance generated by the second conductive section and the scanning signal line is small, and the display effect of the display panel at low gray scale is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel and an electronic device. Background Art

[0002] In recent years, organic light-emitting display panels have gradually become mainstream products in the display field. In display panels, transistors are indispensable components. Research has found that in under-screen camera products, there is an overlapping area between the metal layer that bridges the gate and conductive segment of the driving transistor and another metal layer. The two metal layers will generate a large parasitic capacitance, which will cause the secondary display area to display abnormally at low grayscale.

[0003] Therefore, how to improve the display effect of the secondary display area at low grayscale becomes an urgent problem to be solved. Summary of the invention

[0004] In order to solve the above technical problems, the present application is proposed. The embodiments of the present application provide an array substrate and a manufacturing method thereof, a display panel and an electronic device.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, the array substrate comprising a substrate, and a plurality of conductive layers insulated from each other arranged on one side of the substrate, wherein the plurality of conductive layers comprise: a first conductive layer, stacked on one side of the substrate, the first conductive layer comprising a first conductive segment; a first metal layer, stacked on a side of the first conductive layer away from the substrate, the first metal layer comprising a scanning signal line and a gate, an orthographic projection of the first conductive segment on the substrate and an orthographic projection of the gate on the substrate are respectively located on both sides of the orthographic projection of the scanning signal line on the substrate; a second metal layer, stacked on a side of the first metal layer away from the substrate; a third metal layer, stacked on a side of the second metal layer away from the substrate; and the second conductive layer , stacked on the side of the third metal layer away from the substrate, the second conductive layer includes a second conductive segment; the array substrate also includes an insulating layer, stacked between the first metal layer and the second conductive layer, the insulating layer includes a first through hole and a second through hole, the orthographic projection of the first through hole on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate, and the orthographic projection of the second through hole on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate; wherein the second conductive segment fills the first through hole and the second through hole, one end of the second conductive segment is connected to the first conductive segment through the first through hole, and the other end thereof is connected to the gate through the second through hole.

[0006] In combination with the first aspect, in certain implementations of the first aspect, the insulating layer also includes a third through hole and a fourth through hole, the orthographic projection of the third through hole on the substrate at least partially overlaps with the orthographic projection of the first conductive segment on the substrate, and the orthographic projection of the fourth through hole on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate; the third metal layer includes a third conductive segment and a fourth conductive segment, the third conductive segment and the fourth conductive segment are arranged at intervals, the orthographic projection of the third conductive segment on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate, and the orthographic projection of the fourth conductive segment on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate; the third conductive segment fills the third through hole, and the third conductive segment is connected to one end of the second conductive segment through the first through hole, and the fourth conductive segment fills the fourth through hole, and the fourth conductive segment is connected to the other end of the second conductive segment through the second through hole.

[0007] Preferably, the insulating layer includes a capacitor insulating layer, an interlayer insulating layer and a first planarizing layer stacked in sequence in a direction away from the substrate, the first through hole and the second through hole respectively penetrate the first planarizing layer, the third through hole penetrates the capacitor insulating layer and the interlayer insulating layer, and the fourth through hole penetrates the capacitor insulating layer and the interlayer insulating layer.

[0008] In combination with the first aspect, in certain implementations of the first aspect, the third metal layer includes a first power line, the orthographic projection of the first power line on the substrate and the orthographic projection of the scanning signal line on the substrate form a first overlapping area, and the orthographic projection of the second conductive segment on the substrate overlaps with the first overlapping area.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the array substrate further includes: a second planarization layer, stacked on the side of the second conductive layer facing away from the substrate, the second planarization layer includes a fifth through hole and a sixth through hole, the orthographic projection of the fifth through hole on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate, and the orthographic projection of the sixth through hole on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate; the multiple conductive layers further include a third conductive layer, stacked on the side of the second planarization layer facing away from the substrate, the third conductive layer includes a fifth conductive segment, the fifth conductive segment fills the fifth through hole and the sixth through hole, one end of the fifth conductive segment is connected to one end of the second conductive segment through the fifth through hole, and the other end of the fifth conductive segment is connected to the other end of the second conductive segment through the sixth through hole.

[0010] In a second aspect, an embodiment of the present application provides an array substrate, which includes a substrate and a plurality of conductive layers insulated from each other arranged on one side of the substrate, wherein the plurality of conductive layers include: a first conductive layer, stacked on one side of the substrate, the first conductive layer including a first conductive segment; a first metal layer, stacked on a side of the first conductive layer away from the substrate, the first metal layer including a scanning signal line and a gate, the orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate are respectively located on both sides of the orthographic projection of the scanning signal line on the substrate; a second metal layer, stacked on a side of the first metal layer away from the substrate, the second metal layer including a second power line; a third metal layer, stacked on a side of the second metal layer away from the substrate, the third metal layer including a sixth conductive segment, one end of the sixth conductive segment is connected to the first conductive segment, and the other end thereof is connected to the gate, the orthographic projection of the sixth conductive segment on the substrate and the orthographic projection of the scanning signal line on the substrate form a second overlapping area, and the orthographic projection of the second power line on the substrate overlaps with the second overlapping area.

[0011] In a third aspect, an embodiment of the present application provides a method for preparing an array substrate, the method comprising: providing a substrate; preparing a first conductive layer on one side of the substrate, the first conductive layer comprising a first conductive segment; preparing a first metal layer on a side of the first conductive layer away from the substrate, the first metal layer and the first conductive layer being insulated, the first metal layer comprising a scanning signal line and a gate, an orthographic projection of the first conductive segment on the substrate and an orthographic projection of the gate on the substrate being respectively located on both sides of the orthographic projection of the scanning signal line on the substrate; preparing a second metal layer on a side of the first metal layer away from the substrate; preparing a third metal layer on a side of the second metal layer away from the substrate; and A second conductive layer is prepared on a side away from the substrate, the second conductive layer includes a second conductive segment; wherein the array substrate includes an insulating layer stacked between the first metal layer and the second conductive layer, the insulating layer includes a first through hole and a second through hole, the orthographic projection of the first through hole on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate, and the orthographic projection of the second through hole on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate; the second conductive segment fills the first through hole and the second through hole, one end of the second conductive segment is connected to the first conductive segment through the first through hole, and the other end thereof is connected to the gate through the second through hole.

[0012] In combination with the third aspect, in certain implementations of the third aspect, after preparing the first metal layer on the side of the first conductive layer facing away from the substrate, and before preparing the second metal layer on the side of the first metal layer facing away from the substrate, the preparation method further includes: preparing a stacked capacitor insulating layer on the side of the first metal layer facing away from the substrate; after preparing the second metal layer on the side of the first metal layer facing away from the substrate, and before preparing the third metal layer on the side of the second metal layer facing away from the substrate, it also includes: preparing an interlayer insulating layer on the side of the second metal layer facing away from the substrate, the insulating layer also includes a third through hole and a fourth through hole, the third through hole penetrates the capacitor insulating layer and the interlayer insulating layer, and the fourth through hole penetrates the capacitor insulating layer and the interlayer insulating layer; the orthographic projection of the third through hole on the substrate at least partially overlaps with the orthographic projection of the first conductive segment on the substrate, and the orthographic projection of the fourth through hole on the substrate is at least equal to the orthographic projection of the gate on the substrate. Partial overlap; before preparing the second conductive layer on the side of the third metal layer facing away from the substrate, it also includes: preparing a first planarization layer on the side of the third metal layer facing away from the substrate, and the first through hole and the second through hole respectively penetrate the first planarization layer; wherein the third metal layer includes a third conductive segment and a fourth conductive segment, the third conductive segment and the fourth conductive segment are arranged at intervals, the orthographic projection of the third conductive segment on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate, and the orthographic projection of the fourth conductive segment on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate; the third conductive segment fills the third through hole, and the third conductive segment is connected to one end of the second conductive segment through the first through hole, and the fourth conductive segment fills the fourth through hole, and the fourth conductive segment is connected to the other end of the second conductive segment through the second through hole.

[0013] In a fourth aspect, an embodiment of the present application provides a method for preparing an array substrate, the preparation method comprising: providing a substrate; preparing a first conductive layer on one side of the substrate, the first conductive layer comprising a first conductive segment; preparing a first metal layer on a side of the first conductive layer away from the substrate, the first metal layer and the first conductive layer being insulated, the first metal layer comprising a scanning signal line and a gate, the orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate being respectively located on both sides of the orthographic projection of the scanning signal line on the substrate; preparing a second metal layer on a side of the first metal layer away from the substrate, the second metal layer and the first metal layer being insulated, the second metal layer comprising a second power line; preparing a third metal layer on a side of the second metal layer away from the substrate, the second metal layer and the third metal layer being insulated, the third metal layer comprising a sixth conductive segment, one end of the sixth conductive segment being connected to the first conductive segment, and the other end thereof being connected to the gate, the orthographic projection of the sixth conductive segment on the substrate and the orthographic projection of the scanning signal line on the substrate forming a second overlapping region, and the orthographic projection of the second power line on the substrate overlaps with the second overlapping region.

[0014] In a fifth aspect, an embodiment of the present application provides a display panel, which includes the array substrate mentioned in any of the above embodiments.

[0015] In a sixth aspect, an embodiment of the present application provides an electronic device, which includes the display panel mentioned in the above embodiment.

[0016] The array substrate provided by the embodiment of the present application includes a substrate, and a plurality of conductive layers insulated from each other arranged on one side of the substrate, wherein the plurality of conductive layers include: a first conductive layer, stacked on one side of the substrate, the first conductive layer including a first conductive segment; a first metal layer, stacked on a side of the first conductive layer away from the substrate, the first metal layer including a scanning signal line and a gate, the orthographic projection of the first conductive segment on the substrate and the orthographic projection of the gate on the substrate are respectively located on both sides of the orthographic projection of the scanning signal line on the substrate; a second metal layer, stacked on a side of the first metal layer away from the substrate; a third metal layer, stacked on a side of the second metal layer away from the substrate; a second conductive layer, stacked on a side of the third metal layer away from the substrate, the second conductive layer including a second conductive segment; the array substrate also includes an insulating layer, stacked between the first metal layer and the second conductive layer, the insulating layer including a first through hole and a second through hole, the first through hole being located on the positive side of the substrate The projection and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate, and the orthographic projection of the second through hole on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate; wherein, the second conductive segment fills the first through hole and the second through hole, one end of the second conductive segment is connected to the first conductive segment through the first through hole, and the other end of the second conductive segment is connected to the gate through the second through hole, thereby using the second conductive segment in the second conductive layer on the side of the third metal layer away from the substrate as a jumper to connect the first conductive segment and the gate, thereby increasing the distance between the jumper and the scanning signal line, reducing the relative dielectric constant of the jumper and the scanning signal line, thereby reducing the parasitic capacitance generated by the jumper and the scanning signal line, that is, the parasitic capacitance generated by the second conductive segment and the scanning signal line is small, thereby improving the display effect of the display panel at low grayscale. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0018] Figure 1 Shown is a structural schematic diagram of an array substrate provided by related technology.

[0019] Figure 2 Shown Figure 1 A schematic diagram of the cross-sectional structure of the array substrate is shown.

[0020] Figure 3 FIG. 1 is a schematic diagram of the structure of an array substrate provided in one embodiment of the present application.

[0021] Figure 4 Shown Figure 3 A schematic diagram of the cross-sectional structure of the array substrate is shown.

[0022] Figure 5 Shown is a schematic structural diagram of an array substrate provided in another embodiment of the present application.

[0023] Figure 6 Shown Figure 5 A schematic diagram of the cross-sectional structure of the array substrate is shown.

[0024] Figure 7 FIG. 1 is a schematic diagram of a process for preparing an array substrate provided in an embodiment of the present application.

[0025] Figure 8 FIG. 1 is a schematic flow chart of a method for preparing an array substrate provided in another embodiment of the present application.

[0026] Fig. 9 FIG. 1 is a structural schematic diagram of a process for preparing an array substrate provided in an embodiment of the present application.

[0027] Fig.10 FIG. 1 is a schematic structural diagram of a process for preparing an array substrate provided in another embodiment of the present application.

[0028] Fig.11 FIG. 1 is a schematic structural diagram of a process for preparing an array substrate provided in another embodiment of the present application.

[0029] Fig.12 FIG. 1 is a schematic flow chart of a method for preparing an array substrate provided in another embodiment of the present application.

[0030] Fig.13 Shown is a schematic structural diagram of an electronic device provided in one embodiment of the present application.

[0031] Figure numerals: array substrate 100; substrate A; first conductive layer B1; first metal layer M1; capacitor insulating layer CI; interlayer insulating layer ILD; second metal layer M2; third metal layer M3; first planarization layer PLA1; second conductive layer B2; second planarization layer PLA2; third conductive layer B3; first conductive segment Q1; second conductive segment Q2; third conductive segment Q3; fourth conductive segment Q4; fifth conductive segment Q5; sixth conductive segment Q6; seventh conductive segment Q7; gate G; scanning signal line S; first power line E1; second power line E2; first through hole K1; second through hole K2; third through hole K3; fourth through hole K4; fifth through hole K5; sixth through hole K6; main display area U1; auxiliary display area U2; electronic device 10. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods and means well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0034] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0035] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0036] Figure 1 Shown is a structural schematic diagram of an array substrate provided by related technology. Figure 2 Shown Figure 1 The cross-sectional structure diagram of the array substrate is shown in FIG. Figure 1 and 2As shown, the array substrate 100 provided by the related technology includes a substrate A, and a plurality of conductive layers insulated from each other arranged on one side of the substrate A, wherein the plurality of conductive layers include: a first conductive layer B1, stacked on one side of the substrate A, the first conductive layer B1 including a first conductive segment Q1; a first metal layer M1, stacked on the side of the first conductive layer B1 away from the substrate A, the first metal layer M1 including a scanning signal line S and a gate G, the orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A are respectively located on both sides of the orthographic projection of the scanning signal line S on the substrate A; a second metal layer M2, stacked on the side of the first metal layer M1 away from the substrate A; a third metal layer M3, stacked on the side of the second metal layer M2 away from the substrate A; the third metal layer M3 including a seventh conductive segment Q7, one end of the seventh conductive segment Q7 is connected to the first conductive segment Q1, and the other end thereof is connected to the gate G.

[0037] It is understandable that for the sake of comprehensiveness Figure 1 The cross-sectional structure of the array substrate 100 is shown in FIG. Figure 2 Not Figure 1 The cross-sectional structure diagram of a certain position of the array substrate 100 is shown in FIG. Figure 1 The schematic diagram of the structure is a structural diagram formed by splicing cross sections at multiple positions of the array substrate 100. Similarly, the schematic diagrams of the cross-sectional structures mentioned below are structural diagrams formed by splicing cross sections at multiple positions of the corresponding array substrate 100.

[0038] As described in the background technology, it can be seen from the array substrate 100 provided by the relevant technology that the orthographic projection of the seventh conductive segment Q7 on the substrate A and the orthographic projection of the scanning signal line S on the substrate A overlap, and the parasitic capacitance generated by the seventh conductive segment Q7 and the scanning signal line S is large, resulting in poor display effect of the display panel at low gray scales, especially affecting the display effect of the sub-display area U2 of the display panel.

[0039] In order to solve the above technical problems, the present application is proposed. By setting a jumper line on the side of the third metal layer M3 away from the substrate to connect the first conductive segment Q1 and the gate G, compared with setting the jumper line in the third metal layer M3, the distance between the jumper line and the scanning signal line is increased, thereby reducing the parasitic capacitance and improving the display effect of the display panel at low grayscale.

[0040] Figure 3 FIG. 1 is a schematic diagram of the structure of an array substrate provided in one embodiment of the present application. Figure 4 Shown Figure 3 The cross-sectional structure diagram of the array substrate is shown in FIG. Figure 3 and 4As shown, the array substrate 100 provided in the embodiment of the present application includes a substrate A, and a plurality of conductive layers insulated from each other arranged on one side of the substrate A, wherein the plurality of conductive layers include: a first conductive layer B1, stacked on one side of the substrate A, the first conductive layer B1 including a first conductive segment Q1; a first metal layer M1, stacked on a side of the first conductive layer B1 away from the substrate A, the first metal layer M1 including a scanning signal line S and a gate G, the orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A are respectively located on both sides of the orthographic projection of the scanning signal line S on the substrate A; a second metal layer M2, stacked on a side of the first metal layer M1 away from the substrate A; a third metal layer M3, stacked on a side of the second metal layer M2 away from the substrate A; a second conductive layer B2, stacked on the third metal layer On the side of M3 facing away from the substrate A, the second conductive layer B2 includes a second conductive segment Q2; the array substrate 100 also includes an insulating layer, which is stacked between the first metal layer M1 and the second conductive layer B2, and the insulating layer includes a first through hole K1 and a second through hole K2, the orthographic projection of the first through hole K1 on the substrate A and the orthographic projection of the first conductive segment Q1 on the substrate A are located on the same side of the orthographic projection of the scanning signal line S on the substrate A, and the orthographic projection of the second through hole K2 on the substrate A and the orthographic projection of the gate G on the substrate A are located on the same side of the orthographic projection of the scanning signal line S on the substrate A; wherein the second conductive segment Q2 fills the first through hole K1 and the second through hole K2, one end of the second conductive segment Q2 is connected to the first conductive segment Q1 through the first through hole K1, and the other end thereof is connected to the gate G through the second through hole K2.

[0041] It should be noted that, in the entire display panel, the first metal layer M1, the second metal layer M2 and the third metal layer M3 are in a stacked relationship; or, in other words, in the process of manufacturing the display panel, the first metal layer M1, the second metal layer M2 and the third metal layer M3 are manufactured in sequence. However, since the first metal layer M1, the second metal layer M2 and the third metal layer M3 are all patterned film layers, any one of the first metal layer M1, the second metal layer M2 and the third metal layer M3 may exist or may not exist on the cross section at different positions of the array substrate 100.

[0042] For example, in Figure 4 In the cross section shown, there is a third metal layer M3 between the second conductive segment Q2 and the scan signal line S, but there is no second metal layer M2. For another example, in a cross section provided in another embodiment, there is a third metal layer M3 between the second conductive segment Q2 and the scan signal line S, and there may also be a second metal layer M2. For another example, in a cross section provided in yet another embodiment, there may be no third metal layer M3 between the second conductive segment Q2 and the scan signal line S, but there is a second metal layer M2.

[0043] In some embodiments, the material of the first conductive layer B1 may be a semiconductor, such as polysilicon, etc. The material of the second conductive layer B2 may be indium tin oxide.

[0044] It can be known from the array substrate 100 provided in the embodiment of the present application that the wiring bridging the first conductive segment Q1 and the gate G is the second conductive segment Q2 , rather than the seventh conductive segment Q7 mentioned in the related art.

[0045] In the array substrate 100 provided in the embodiment of the present application, the second conductive segment Q2 in the second conductive layer B2 is used to bridge the first conductive segment Q1 and the gate G. Since the second conductive layer B2 is located on the side of the third metal layer M3 away from the substrate, compared with using the seventh conductive segment Q7 in the third metal layer M3 to bridge the first conductive segment Q1 and the gate G, the distance between the bridged wiring and the scanning signal line S is increased (that is, the distance between the second conductive segment Q2 and the scanning signal line S is larger), thereby reducing the parasitic capacitance generated between the bridged wiring and the scanning signal line S, that is, the parasitic capacitance generated between the second conductive segment Q2 and the scanning signal line S is smaller, thereby improving the display effect of the display panel at low grayscale.

[0046] refer to Figure 3 and 4 The insulating layer further includes a third through hole K3 and a fourth through hole K4, the orthographic projection of the third through hole K3 on the substrate A at least partially overlaps with the orthographic projection of the first conductive segment Q1 on the substrate A, and the orthographic projection of the fourth through hole K4 on the substrate A at least partially overlaps with the orthographic projection of the gate G on the substrate A; the third metal layer M3 includes a third conductive segment Q3 and a fourth conductive segment Q4, the third conductive segment Q3 and the fourth conductive segment Q4 are arranged at intervals, and the orthographic projection of the third conductive segment Q3 on the substrate A overlaps with the orthographic projection of the first conductive segment Q1 on the substrate A. The orthographic projection on the bottom A is located on the same side of the orthographic projection of the scanning signal line S on the substrate A, and the orthographic projection of the fourth conductive segment Q4 on the substrate A and the orthographic projection of the gate G on the substrate A are located on the same side of the orthographic projection of the scanning signal line S on the substrate A; the third conductive segment Q3 fills the third through hole K3, and the third conductive segment Q3 is connected to one end of the second conductive segment Q2 through the first through hole K1; the fourth conductive segment Q4 fills the fourth through hole K4, and the fourth conductive segment Q4 is connected to the other end of the second conductive segment Q2 through the second through hole K2.

[0047] The embodiment of the present application provides an implementation method in which one end of the second conductive segment Q2 is connected to the first conductive segment Q1, and the other end thereof is connected to the gate G. Specifically, one end of the second conductive segment Q2 is directly connected to the third conductive segment Q3 through the first through hole K1, and then the third conductive segment Q3 is directly connected to the first conductive segment Q1 through the third through hole K3, thereby achieving the purpose of connecting one end of the second conductive segment Q2 to the first conductive segment Q1. The other end of the second conductive segment Q2 is directly connected to the fourth conductive segment Q4 through the second through hole K2, and then the fourth conductive segment Q4 is directly connected to the gate G through the fourth through hole K4, thereby achieving the purpose of connecting the other end of the second conductive segment Q2 to the gate G.

[0048] In one embodiment, the insulating layer includes a capacitor insulating layer CI, an interlayer insulating layer ILD, and a first planarization layer PLA1 stacked in sequence in a direction away from the substrate A, the first through hole K1 and the second through hole K2 penetrate the first planarization layer PLA1 respectively, the third through hole K3 penetrates the capacitor insulating layer CI and the interlayer insulating layer ILD, and the fourth through hole K4 penetrates the capacitor insulating layer CI and the interlayer insulating layer ILD. In this case, the first planarization layer PLA1 is passed between the jumper line (i.e., the seventh conductive segment Q7) and the scan signal line S, which reduces the relative dielectric constant between the jumper line and the scan signal line S, thereby further reducing the parasitic capacitance.

[0049] refer to Figure 3 and 4 In the array substrate 100 provided in the embodiment of the present application, the third metal layer M3 includes a first power line E1, and the orthographic projection of the first power line E1 on the substrate A and the orthographic projection of the scanning signal line S on the substrate A form a first overlapping area, the orthographic projection of the first power line E1 on the substrate A is located on the same side of the orthographic projections of the first through hole K1 and the second through hole K2 on the substrate A, and the orthographic projection of the second conductive segment Q2 on the substrate A overlaps with the first overlapping area.

[0050] The embodiment of the present application shields the electrical interaction between the second conductive segment Q2 and the scanning signal line S through the first power line E1, so that the parasitic capacitance generated by the two is close to zero, thereby avoiding the problem of abnormal display at low gray scales and greatly improving the display effect of the display panel at low gray scales.

[0051] refer to Figure 3 and 4The array substrate 100 provided in the embodiment of the present application further includes: a second planarization layer PLA2, which is stacked on the side of the second conductive layer B2 away from the substrate A, the second planarization layer PLA2 includes a fifth through hole K5 and a sixth through hole K6, the orthographic projection of the fifth through hole K5 on the substrate A and the orthographic projection of the first conductive segment Q1 on the substrate A are located on the same side of the orthographic projection of the scanning signal line S on the substrate A, and the orthographic projection of the sixth through hole K6 on the substrate A and the orthographic projection of the gate G on the substrate A are located on the same side of the orthographic projection of the scanning signal line S on the substrate A; the multiple conductive layers further include a third conductive layer B3, which is stacked on the side of the second planarization layer PLA2 away from the substrate A, the third conductive layer B3 includes a fifth conductive segment Q5, the fifth conductive segment Q5 fills the fifth through hole K5 and the sixth through hole K6, one end of the fifth conductive segment Q5 is connected to one end of the second conductive segment Q2 through the fifth through hole K5, and the other end of the fifth conductive segment Q5 is connected to the other end of the second conductive segment Q2 through the sixth through hole K6.

[0052] The embodiment of the present application reduces the resistance of the second conductive segment Q2 by providing the fifth conductive segment Q5 and connecting the fifth conductive segment Q5 and the second conductive segment Q2 in parallel, thereby reducing power consumption and achieving the purpose of energy saving and environmental protection.

[0053] It is understandable that the orthographic projection of the fifth conductive segment Q5 on the substrate A also overlaps with the first overlapping area, and the first power line E1 also shields the electrical interaction between the fifth conductive segment Q5 and the scan signal line S, making the parasitic capacitance generated by the two close to zero.

[0054] Figure 5 Shown is a schematic structural diagram of an array substrate provided in another embodiment of the present application. Figure 6 Shown Figure 5 The cross-sectional structure diagram of the array substrate is shown in FIG. Figure 5 and 6As shown, in another embodiment, an array substrate 100 is provided, the array substrate 100 includes a substrate A, and a plurality of conductive layers insulated from each other arranged on one side of the substrate A, wherein the plurality of conductive layers include: a first conductive layer B1, stacked on one side of the substrate A, the first conductive layer B1 including a first conductive segment Q1; a first metal layer M1, stacked on a side of the first conductive layer B1 away from the substrate A, the first metal layer M1 including a scanning signal line S and a gate G, the orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A are respectively located at the orthographic projection of the scanning signal line S on the substrate A. on both sides; a second metal layer M2, stacked on the side of the first metal layer M1 away from the substrate A, the second metal layer M2 includes a second power line E2; a third metal layer M3, stacked on the side of the second metal layer M2 away from the substrate A, the third metal layer M3 includes a sixth conductive segment Q6, one end of the sixth conductive segment Q6 is connected to the first conductive segment Q1, and the other end is connected to the gate G, the orthographic projection of the sixth conductive segment Q6 on the substrate A and the orthographic projection of the scanning signal line S on the substrate A form a second overlapping area, and the orthographic projection of the second power line E2 on the substrate A overlaps with the second overlapping area.

[0055] In the array substrate 100 provided in the embodiment of the present application, the wiring that bridges the first conductive segment Q1 and the gate G is the sixth conductive segment Q6. By setting the second power line E2, the electrical interaction between the sixth conductive segment Q6 and the scanning signal line S is shielded, so that the parasitic capacitance generated by the two is close to zero, thereby avoiding the problem of abnormal display at low gray scales and greatly improving the display effect of the display panel at low gray scales.

[0056] The structure and working principle of the array substrate 100 are described in detail above. Based on the same inventive concept, the present application also provides a method for preparing the array substrate 100 . The specific contents of the preparation method are described below.

[0057] Figure 7 FIG. 1 is a schematic diagram of a process for preparing an array substrate provided by an embodiment of the present application. Figure 7 As shown, the embodiment of the present application further provides a method for preparing an array substrate 100, the method comprising the following steps:

[0058] Step S901: providing a substrate A.

[0059] Step S902 , preparing a first conductive layer B1 on one side of the substrate A.

[0060] The first conductive layer B1 includes a first conductive segment Q1.

[0061] Step S903 , forming a first metal layer M1 on a side of the first conductive layer B1 facing away from the substrate A.

[0062] The first metal layer M1 and the first conductive layer B1 are insulated, the first metal layer M1 includes a scanning signal line S and a gate G, and the orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A are respectively located on both sides of the orthographic projection of the scanning signal line S on the substrate A.

[0063] Step S904 , forming a second metal layer M2 on a side of the first metal layer M1 facing away from the substrate A.

[0064] Step S905 , forming a third metal layer M3 on the side of the second metal layer M2 facing away from the substrate A.

[0065] Step S906 , preparing a second conductive layer B2 on the side of the third metal layer M3 facing away from the substrate A.

[0066] The array substrate includes an insulating layer, the insulating layer includes a first through hole K1 and a second through hole K2, the orthographic projection of the first through hole K1 on the substrate A and the orthographic projection of the first conductive segment Q1 on the substrate A are located on the same side of the orthographic projection of the scanning signal line S on the substrate A, and the orthographic projection of the second through hole K2 on the substrate A and the orthographic projection of the gate G on the substrate A are located on the same side of the orthographic projection of the scanning signal line S on the substrate A. The second conductive layer B2 includes a second conductive segment Q2, the second conductive segment Q2 fills the first through hole K1 and the second through hole K2, one end of the second conductive segment Q2 is connected to the first conductive segment Q1 through the first through hole K1, and the other end thereof is connected to the gate G through the second through hole K2.

[0067] The manufacturing method provided in the embodiment of the present application reduces the parasitic capacitance generated between the second conductive segment Q2 and the scan signal line S, thereby improving the display effect of the display panel at low gray scales.

[0068] Figure 8 FIG. 2 is a schematic diagram of a method for preparing an array substrate according to another embodiment of the present application. Figure 8 As shown, between step S903 and step S904, the preparation method further includes the following steps:

[0069] Step S1001 : forming a capacitor insulating layer CI on a side of the first metal layer M1 facing away from the substrate A.

[0070] In this case, step S904 is performed as follows:

[0071] Step S1002 , forming a second metal layer M2 on the side of the capacitor insulating layer CI facing away from the substrate A.

[0072] Between step S1002 and step S905, the preparation method further includes:

[0073] Step S1003 , forming an interlayer insulating layer ILD on the side of the second metal layer M2 facing away from the substrate A.

[0074] In this case, step S905 is performed as follows:

[0075] Step S1004 , forming a third metal layer M3 on the side of the interlayer insulating layer ILD facing away from the substrate A.

[0076] Between step S1004 and step S906, the preparation method further includes:

[0077] Step S1005 , preparing a first planarization layer PLA1 on the side of the third metal layer M3 facing away from the substrate A.

[0078] In this case, step S906 is performed as follows:

[0079] Step S1006 , preparing a second conductive layer B2 on the side of the first planarization layer PLA1 facing away from the substrate A.

[0080] The first through hole K1 and the second through hole K2 penetrate the first planarization layer PLA1 respectively.

[0081] The insulating layer further includes a third through hole K3 and a fourth through hole K4, wherein the third through hole penetrates the capacitor insulating layer and the interlayer insulating layer, and the fourth through hole penetrates the capacitor insulating layer and the interlayer insulating layer. The orthographic projection of the third through hole K3 on the substrate A at least partially overlaps with the orthographic projection of the first conductive segment Q1 on the substrate A, and the orthographic projection of the fourth through hole K4 on the substrate A at least partially overlaps with the orthographic projection of the gate G on the substrate A.

[0082] The third metal layer M3 includes a third conductive segment Q3 and a fourth conductive segment Q4, and the third conductive segment Q3 and the fourth conductive segment Q4 are arranged at intervals. The orthographic projection of the third conductive segment Q3 on the substrate A and the orthographic projection of the first conductive segment Q1 on the substrate A are located on the same side of the orthographic projection of the scanning signal line S on the substrate A, and the orthographic projection of the fourth conductive segment Q4 on the substrate A and the orthographic projection of the gate G on the substrate A are located on the same side of the orthographic projection of the scanning signal line S on the substrate A; the third conductive segment Q3 fills the third through hole K3, and the third conductive segment Q3 is connected to one end of the second conductive segment Q2 through the first through hole K1, and the fourth conductive segment Q4 fills the fourth through hole K4, and the fourth conductive segment Q4 is connected to the other end of the second conductive segment Q2 through the second through hole K2.

[0083] Combine the following Figures 9 to 11 Specific description Figure 7 and 8 The preparation process corresponding to the preparation method shown. Fig. 9 FIG. 1 is a schematic diagram of a process for preparing an array substrate according to an embodiment of the present application. Fig. 9In the process, a substrate A, a first conductive layer B1, a first metal layer M1, a capacitor insulating layer CI, an interlayer insulating layer ILD, and a second metal layer M2 are prepared in sequence. The first conductive layer B1 may be made of polysilicon with a thickness of 450 angstroms; the first metal layer M1 may be made of molybdenum with a thickness of 2500 angstroms; the capacitor insulating layer CI may be made of silicon nitride with a thickness of 1000 angstroms; the interlayer insulating layer ILD may be made of a mixture of silicon oxide and silicon nitride, with a thickness of 2700 angstroms and a thickness of 2200 angstroms; the second metal layer M2 may be a stacked structure of titanium-aluminum-titanium with thicknesses of 750 angstroms, 7000 angstroms, and 500 angstroms, respectively.

[0084] Fig.10 FIG. 1 is a schematic diagram of a process for preparing an array substrate according to another embodiment of the present invention. Fig.10 In the process, the first planarization layer PLA1 and the second conductive layer B2 are prepared in sequence. The thickness of the first planarization layer PLA1 is 1.2 microns, and the thickness of the second conductive layer B2 is 360 angstroms. The second conductive layer B2 is obtained by wet etching with oxalic acid solution (3% to 4% by weight in the aqueous solution) and annealing at 250°C for 60 minutes.

[0085] Fig.11 FIG. 1 is a schematic diagram of a process for preparing an array substrate according to another embodiment of the present invention. Fig.11 In the process, the second planarization layer PLA2 and the third conductive layer B3 are prepared in sequence. The thickness of the second planarization layer PLA2 is 1.65 microns, and the thickness of the third conductive layer B3 is 360 angstroms. The material of the third conductive layer B3 can be the same as that of the second conductive layer B2, and the preparation process of the two can also be the same, which will not be repeated here.

[0086] Understandably, Figure 7 , Figure 8 The preparation method and Figures 9 to 11 For any content not described in the structural diagram of the preparation process mentioned, please refer to Figure 3 and Figure 4 The contents described in detail in the illustrated embodiments will not be repeated here.

[0087] Fig.12 FIG. 2 is a schematic diagram of a method for preparing an array substrate according to another embodiment of the present application. Fig.12 As shown, the embodiment of the present application further provides a method for preparing an array substrate 100, and the preparation method comprises the following steps:

[0088] Step S1401, providing substrate A.

[0089] Step S1402 , preparing a first conductive layer B1 on one side of the substrate A.

[0090] The first conductive layer B1 includes a first conductive segment Q1 .

[0091] Step S1403 , forming a first metal layer M1 on a side of the first conductive layer B1 facing away from the substrate A.

[0092] The first metal layer M1 and the first conductive layer B1 are insulated, the first metal layer M1 includes a scanning signal line S and a gate G, and the orthographic projection of the first conductive segment Q1 on the substrate A and the orthographic projection of the gate G on the substrate A are respectively located on both sides of the orthographic projection of the scanning signal line S on the substrate A.

[0093] Step S1404 , preparing a second metal layer M2 on a side of the first metal layer M1 facing away from the substrate A.

[0094] The second metal layer M2 and the first metal layer M1 are insulated from each other, and the second metal layer M2 includes a second power line E2.

[0095] Step S1405 , preparing a third metal layer M3 on the side of the second metal layer M2 facing away from the substrate A.

[0096] Among them, the second metal layer M2 and the third metal layer M3 are insulated, the third metal layer M3 includes a sixth conductive segment Q6, one end of the sixth conductive segment Q6 is connected to the first conductive segment Q1, and the other end thereof is connected to the gate G, the orthographic projection of the sixth conductive segment Q6 on the substrate A and the orthographic projection of the scanning signal line S on the substrate A form a second overlapping area, and the orthographic projection of the second power line E2 on the substrate A overlaps with the second overlapping area.

[0097] The preparation method provided in the embodiment of the present application makes the parasitic capacitance generated by the sixth conductive segment Q6 and the scanning signal line S close to zero, thereby avoiding the problem of abnormal display at low gray scales and greatly improving the display effect of the display panel at low gray scales.

[0098] Understandably, Fig.12 For details not described in the preparation method mentioned, please refer to Figures 4 to 6 The contents described in detail in the illustrated embodiments will not be repeated here.

[0099] In another embodiment, the present application further provides a display panel, which includes the array substrate 100 mentioned in any of the above embodiments.

[0100] Fig.13 FIG. 1 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Fig.13As shown, the present application also provides an electronic device 10, which includes a display panel as mentioned in the above embodiment. Its technical principles and effects are similar and will not be repeated here.

[0101] It is understandable that the display panel can also be applied to other display devices, such as tablet computers, computer monitors, televisions, wearable devices, information query machines, and any other products or components with display functions.

[0102] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0103] It should also be noted that, in the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present application. Although multiple exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize some variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An array substrate, characterized in that: The invention comprises a substrate and a plurality of mutually insulated conductive layers arranged on one side of the substrate, wherein the plurality of conductive layers comprises: A first conductive layer, stacked on one side of the substrate, the first conductive layer comprising a first conductive segment; A first metal layer is stacked on a side of the first conductive layer away from the substrate, the first metal layer comprises a scanning signal line and a gate, an orthographic projection of the first conductive segment on the substrate and an orthographic projection of the gate on the substrate are respectively located on both sides of the orthographic projection of the scanning signal line on the substrate; a second metal layer, stacked on a side of the first metal layer facing away from the substrate; a third metal layer, stacked on a side of the second metal layer facing away from the substrate; A second conductive layer, stacked on a side of the third metal layer facing away from the substrate, the second conductive layer comprising a second conductive segment; The array substrate further comprises an insulating layer, which is stacked between the first metal layer and the second conductive layer, the insulating layer comprises a first through hole and a second through hole, the orthographic projection of the first through hole on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side as the orthographic projection of the scanning signal line on the substrate, and the orthographic projection of the second through hole on the substrate and the orthographic projection of the gate on the substrate are located on the same side as the orthographic projection of the scanning signal line on the substrate; The second conductive segment fills the first through hole and the second through hole, one end of the second conductive segment is connected to the first conductive segment through the first through hole, and the other end of the second conductive segment is connected to the gate through the second through hole.

2. The array substrate according to claim 1, characterized in that: The insulating layer further includes a third through hole and a fourth through hole, the orthographic projection of the third through hole on the substrate at least partially overlaps with the orthographic projection of the first conductive segment on the substrate, and the orthographic projection of the fourth through hole on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate; The third metal layer includes a third conductive segment and a fourth conductive segment, the third conductive segment and the fourth conductive segment are arranged at intervals, the orthographic projection of the third conductive segment on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate, and the orthographic projection of the fourth conductive segment on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate; the third conductive segment fills the third through hole, and the third conductive segment is connected to one end of the second conductive segment through the first through hole, and the fourth conductive segment fills the fourth through hole, and the fourth conductive segment is connected to the other end of the second conductive segment through the second through hole; Preferably, the insulating layer includes a capacitor insulating layer, an interlayer insulating layer and a first planarization layer stacked in sequence in a direction away from the substrate, the first through hole and the second through hole respectively penetrate the first planarization layer, the third through hole penetrates the capacitor insulating layer and the interlayer insulating layer, and the fourth through hole penetrates the capacitor insulating layer and the interlayer insulating layer.

3. The array substrate according to claim 1, characterized in that: The third metal layer includes a first power line, an orthographic projection of the first power line on the substrate and an orthographic projection of the scanning signal line on the substrate form a first overlapping area, and an orthographic projection of the second conductive segment on the substrate overlaps with the first overlapping area.

4. The array substrate according to any one of claims 1 to 3, characterized in that: Also includes: a second planarization layer, stacked on a side of the second conductive layer away from the substrate, the second planarization layer comprising a fifth through hole and a sixth through hole, an orthographic projection of the fifth through hole on the substrate and an orthographic projection of the first conductive segment on the substrate being located on the same side as an orthographic projection of the scan signal line on the substrate, and an orthographic projection of the sixth through hole on the substrate and an orthographic projection of the gate on the substrate being located on the same side as an orthographic projection of the scan signal line on the substrate; The multiple conductive layers also include a third conductive layer stacked on a side of the second planarization layer facing away from the substrate, the third conductive layer includes a fifth conductive segment, the fifth conductive segment fills the fifth through hole and the sixth through hole, one end of the fifth conductive segment is connected to one end of the second conductive segment through the fifth through hole, and the other end of the fifth conductive segment is connected to the other end of the second conductive segment through the sixth through hole.

5. An array substrate, characterized in that: The invention comprises a substrate and a plurality of mutually insulated conductive layers arranged on one side of the substrate, wherein the plurality of conductive layers comprises: A first conductive layer, stacked on one side of the substrate, the first conductive layer comprising a first conductive segment; A first metal layer is stacked on a side of the first conductive layer away from the substrate, the first metal layer comprises a scanning signal line and a gate, an orthographic projection of the first conductive segment on the substrate and an orthographic projection of the gate on the substrate are respectively located on both sides of the orthographic projection of the scanning signal line on the substrate; A second metal layer, stacked on a side of the first metal layer facing away from the substrate, the second metal layer comprising a second power line; A third metal layer is stacked on a side of the second metal layer facing away from the substrate, the third metal layer includes a sixth conductive segment, one end of the sixth conductive segment is connected to the first conductive segment, and the other end of the sixth conductive segment is connected to the gate, the orthographic projection of the sixth conductive segment on the substrate and the orthographic projection of the scanning signal line on the substrate form a second overlapping area, and the orthographic projection of the second power line on the substrate overlaps with the second overlapping area.

6. A method for preparing an array substrate, characterized in that: include: providing a substrate; Preparing a first conductive layer on one side of the substrate, wherein the first conductive layer includes a first conductive segment; A first metal layer is prepared on a side of the first conductive layer away from the substrate, the first metal layer and the first conductive layer are insulated, the first metal layer includes a scanning signal line and a gate, and an orthographic projection of the first conductive segment on the substrate and an orthographic projection of the gate on the substrate are respectively located on both sides of the orthographic projection of the scanning signal line on the substrate; forming a second metal layer on a side of the first metal layer facing away from the substrate; forming a third metal layer on a side of the second metal layer facing away from the substrate; Prepare a second conductive layer on a side of the third metal layer facing away from the substrate, wherein the second conductive layer includes a second conductive segment; Wherein, the array substrate includes an insulating layer, the insulating layer includes a first through hole and a second through hole, the orthographic projection of the first through hole on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate, the orthographic projection of the second through hole on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate; the second conductive segment fills the first through hole and the second through hole, one end of the second conductive segment is connected to the first conductive segment through the first through hole, and the other end of the second conductive segment is connected to the gate through the second through hole.

7. The preparation method according to claim 6, characterized in that: After forming a first metal layer on a side of the first conductive layer facing away from the substrate, and before forming a second metal layer on a side of the first metal layer facing away from the substrate, the method further includes: preparing a capacitor insulating layer on a side of the first metal layer away from the substrate; After forming a second metal layer on a side of the first metal layer facing away from the substrate, and before forming a third metal layer on a side of the second metal layer facing away from the substrate, the method further comprises: An interlayer insulating layer is prepared on a side of the second metal layer away from the substrate, the insulating layer further comprising a third through hole and a fourth through hole, the third through hole penetrates the capacitor insulating layer and the interlayer insulating layer, the fourth through hole penetrates the capacitor insulating layer and the interlayer insulating layer; the orthographic projection of the third through hole on the substrate at least partially overlaps with the orthographic projection of the first conductive segment on the substrate, and the orthographic projection of the fourth through hole on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate; After forming a third metal layer on a side of the second metal layer facing away from the substrate, and before forming a second conductive layer on a side of the third metal layer facing away from the substrate, the method further comprises: A first planarization layer is prepared on a side of the third metal layer facing away from the substrate, wherein the first through hole and the second through hole respectively penetrate the first planarization layer; Wherein, the third metal layer includes a third conductive segment and a fourth conductive segment, the third conductive segment and the fourth conductive segment are arranged at intervals, the orthographic projection of the third conductive segment on the substrate and the orthographic projection of the first conductive segment on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate, and the orthographic projection of the fourth conductive segment on the substrate and the orthographic projection of the gate on the substrate are located on the same side of the orthographic projection of the scanning signal line on the substrate; the third conductive segment fills the third through hole, and the third conductive segment is connected to one end of the second conductive segment through the first through hole, and the fourth conductive segment fills the fourth through hole, and the fourth conductive segment is connected to the other end of the second conductive segment through the second through hole.

8. A method for preparing an array substrate, characterized in that: include: providing a substrate; Preparing a first conductive layer on one side of the substrate, wherein the first conductive layer includes a first conductive segment; A first metal layer is prepared on a side of the first conductive layer away from the substrate, the first metal layer and the first conductive layer are insulated, the first metal layer includes a scanning signal line and a gate, and an orthographic projection of the first conductive segment on the substrate and an orthographic projection of the gate on the substrate are respectively located on both sides of the orthographic projection of the scanning signal line on the substrate; A second metal layer is prepared on a side of the first metal layer away from the substrate, the second metal layer is insulated from the first metal layer, and the second metal layer includes a second power line; A third metal layer is prepared on a side of the second metal layer facing away from the substrate, the second metal layer and the third metal layer are insulated, the third metal layer includes a sixth conductive segment, one end of the sixth conductive segment is connected to the first conductive segment, and the other end of the sixth conductive segment is connected to the gate, the orthographic projection of the sixth conductive segment on the substrate and the orthographic projection of the scanning signal line on the substrate form a second overlapping area, and the orthographic projection of the second power line on the substrate overlaps with the second overlapping area.

9. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 5.

10. An electronic device, characterized in that: The display panel comprises the display panel as claimed in claim 9.

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