N-type solar cell and its preparation method and application

Abstract

The present invention belongs to the field of photovoltaic manufacturing technology, and relates to an n-type solar cell and its preparation method and application. The preparation method comprises: (1) depositing a first back intrinsic layer on the surface of any side of a silicon substrate; (2) depositing a front intrinsic layer and a front doped layer in sequence on the surface of the other side of the silicon substrate; (3) depositing a second back intrinsic layer and a back doped layer in sequence on the surface of the first back intrinsic layer; (4) depositing a transparent conductive oxide layer on the surface of the front doped layer and the back doped layer respectively; (5) preparing electrodes on the surface of the transparent conductive oxide layer on the front side and the transparent oxide layer on the back side, respectively, to obtain an n-type solar cell. The preparation method of the present invention ensures that the outermost back intrinsic layer in contact with the back doped layer is not damaged, thereby obtaining a low-resistance and stable tunneling contact solar cell structure, and its thermal attenuation reliability is also improved.

Description

Technical Field

[0001] The invention belongs to the technical field of photovoltaic manufacturing and relates to an n-type solar cell and a preparation method and application thereof. Background Art

[0002] Energy is the cornerstone of modern social development. With the continuous development of the global economy and society, energy consumption has continued to grow. With the passage of time, fossil energy has become increasingly scarce. Against the backdrop of fossil energy shortages, large-scale development and invention of renewable resources has become an important strategy for future energy. Solar energy is the cleanest clean energy and renewable energy. Solar cells are the core of solar power generation. As a new type of solar cell, heterojunction solar cells, how to improve the photoelectric conversion efficiency of heterojunction solar cells is now a key research direction.

[0003] The advantage of heterojunction high-efficiency cells over other types of cells is that the intrinsic amorphous layer has efficient passivation and tunneling. Usually, the inner layer is effectively passivated by inhibiting epitaxial growth, and the outer layer forms an effective contact with the corresponding doped layer. At present, it is found that the tunneling contact on the back of the battery will significantly affect the IV performance of the battery and has a direct relationship with the thermal attenuation reliability. How to obtain a better tunneling contact becomes particularly important.

[0004] In the existing coating technology, the front coating process is usually sandwiched between the deposition of the back intrinsic layer (back i) and the deposition of the back doping layer. For example, CN109411551A discloses a method for preparing a multi-step deposition high-efficiency crystalline silicon heterojunction solar cell electrode structure, which includes the following steps: the first step is to select a substrate N-type single crystal silicon wafer for texturing and cleaning; the second step is to prepare the double intrinsic amorphous silicon layers on the front and back by PECVD, and the intrinsic amorphous silicon on the front and back is deposited in multiple steps, and each deposition step is treated with H plasma for 20~60s; the third step is to select an N-type amorphous silicon film as the light-receiving side doping layer; the fourth step is to use plasma enhanced chemical vapor deposition to prepare an n-type amorphous silicon doping layer; the fifth step is to use plasma chemical vapor deposition to prepare a p-type amorphous silicon doping layer. That is, in the above-mentioned coating deposition process, the front doping layer will be deposited only after the deposition of the back intrinsic layer is completed. During the flip coating process, friction between the carrier, automation, etc. and the contact surface will inevitably be introduced, causing damage to the film layer, thereby affecting the contact effect with the back doping layer.

[0005] Therefore, how to make solar cells have good tunneling contacts and improve thermal attenuation reliability is a technical problem that needs to be solved urgently. Summary of the invention

[0006] In view of the shortcomings of the prior art, the present invention aims to provide an n-type solar cell and a preparation method and application thereof. The preparation method provided by the present invention deposits the back intrinsic layer in steps, ensuring that the outermost back intrinsic layer in contact with the back doping layer is not damaged, thereby obtaining a low-resistance and stable tunneling contact solar cell structure, and its thermal attenuation reliability is also improved.

[0007] In order to achieve the purpose of the invention, the present invention adopts the following technical solutions:

[0008] In a first aspect, the present invention provides a method for preparing a heterojunction solar cell, the preparation method comprising the following steps:

[0009] (1) depositing a first back side intrinsic layer on any side surface of the silicon substrate;

[0010] (2) sequentially depositing a front intrinsic layer and a front doped layer on the other side surface of the silicon substrate;

[0011] (3) sequentially depositing a second back intrinsic layer and a back doping layer on the surface of the first back intrinsic layer;

[0012] (4) depositing a transparent conductive oxide layer on the surface of the front doped layer and the back doped layer respectively;

[0013] (5) Electrodes are prepared on the front transparent conductive oxide layer surface and the back transparent oxide layer surface respectively to obtain the heterojunction solar cell.

[0014] It should be noted that the any one side surface mentioned in step (1) of the present invention is the main light-receiving surface of the silicon substrate; and the other side surface mentioned in step (2) refers to the surface opposite to the any one side surface mentioned in step (1).

[0015] The preparation method, preparation sequence and coordinated structural layers provided by the present invention prepare the back intrinsic layer in steps, thereby avoiding damage to the intrinsic layer when the front side of the silicon substrate (i.e., the light-receiving side) is coated by flipping, and ensuring that the outermost back intrinsic layer in contact with the back doped layer is not damaged, thereby obtaining a low-resistance and stable tunneling contact solar cell structure, and its thermal attenuation reliability is also improved.

[0016] The preparation sequence and the coordinated cooperation of the structural layers in the present invention are indispensable. If the preparation sequence of back intrinsic layer-front intrinsic layer-front doped layer-back doped layer is adopted, it will be impossible to achieve that the intrinsic layer in contact with the back doped layer is intact, which will lead to a large contact resistance; and if the preparation sequence of front intrinsic layer-back intrinsic layer-front doped layer-back doped layer is adopted, the inner intrinsic layers are all damaged; that is, in the present invention, a part of the structural layer of the back intrinsic layer is deposited first, so that the required high-quality intrinsic layer can be obtained.

[0017] The following are preferred technical solutions of the present invention, but are not intended to limit the technical solutions provided by the present invention. Through the following preferred technical solutions, the technical objectives and beneficial effects of the present invention can be better achieved and realized.

[0018] Preferably, in step (1), the surfaces of both sides of the silicon substrate are firstly textured, and then the first back intrinsic layer is deposited.

[0019] The present invention does not impose any special limitation on the specific preparation process of the texturing treatment, and is applicable to conventional technical solutions for texturing a silicon substrate.

[0020] Exemplarily, the present invention provides a method for texturing, the method specifically comprising:

[0021] The oxide layer on the surface of the silicon substrate is removed using a 5% diluted HF solution. The alkaline texturing agent plus alcohol method is used to utilize the anisotropic corrosion of single crystal silicon to form a shallow pyramid structure on the surface, completing the texturing treatment on both sides of the silicon substrate.

[0022] Furthermore, the texturing agent includes at least one of potassium hydroxide (KOH), sodium hydroxide (NaOH) or tetramethylammonium hydroxide (TMAH).

[0023] Preferably, step (1) comprises:

[0024] The first silane is introduced to deposit a first back intrinsic layer on any side surface of the silicon substrate.

[0025] Preferably, during the deposition of the first back intrinsic layer, the flow rate of the first silane is 800-1000 sccm, the pressure is 0.4-0.6 Torr, and the coating power is 500-1000W.

[0026] For example, the flow rate of the first silane can be 800sccm, 850sccm, 900sccm, 950sccm or 1000sccm, etc., the pressure can be 0.4Torr, 0.45Torr, 0.5Torr, 0.55Torr or 0.6Torr, etc., and the coating power can be 500W, 550W, 600W, 650W, 700W, 750W, 800W, 850W, 900W, 950W or 1000W, etc.

[0027] Preferably, the deposition thickness of the first back intrinsic layer is 1-2 nm, for example, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm.

[0028] In the present invention, by regulating the deposition process of the first back side intrinsic layer, the deposition of the first back side intrinsic layer is carried out in a high silicon environment, thereby improving the passivation effect of the first back side intrinsic layer; and further regulating the inlet flow rate of the first silane to 800~1000sccm and / or the deposition thickness of the first back side intrinsic layer to 1~2nm, the intrinsic amorphous passivation effect can be better achieved.

[0029] Preferably, in step (1), in addition to depositing on any one side surface of the silicon substrate, the step also includes a deposition process on the side wall of the silicon substrate perpendicular to the thickness direction.

[0030] In the present invention, while depositing the first back intrinsic layer on one side surface of the silicon substrate, under the same deposition conditions, a back intrinsic layer can also be deposited on the side wall of the silicon substrate perpendicular to the thickness direction to obtain the first back intrinsic layer of the side wall.

[0031] Preferably, step (2) comprises:

[0032] A second silane is introduced to deposit a front intrinsic layer on the other side of the silicon substrate; then the second silane, the first hydrogen and the first doping gas are introduced to deposit a front doping layer on the surface of the front intrinsic layer.

[0033] Preferably, during the deposition of the front intrinsic layer, the flow rate of the second silane is 500-1000 sccm, the pressure is 0.4-0.6 Torr, and the coating power is 200-600W.

[0034] For example, during the deposition of the front intrinsic layer, the flow rate of the second silane can be 500sccm, 550sccm, 600sccm, 650sccm, 700sccm, 750sccm, 800sccm, 850sccm, 900sccm, 950sccm or 1000sccm, etc.; the pressure can be 0.4Torr, 0.45Torr, 0.5Torr, 0.55Torr or 0.6Torr, etc.; the coating power can be 200W, 300W, 400W, 500W or 600W, etc.

[0035] Preferably, during the deposition of the front doping layer, the flow rate of the second silane is 40~70sccm, the flow rate of the first hydrogen is 12000~16000sccm, the flow rate of the first doping gas is 200~500sccm, the pressure is 4~6Torr, and the coating power is 2000~5000W.

[0036] For example, during the deposition of the front doping layer, the flow rate of the second silane can be 40sccm, 45sccm, 50sccm, 55sccm, 60sccm, 65sccm or 70sccm, etc.; the flow rate of the first doping gas can be 12000sccm, 13000sccm, 14000sccm, 15000sccm or 16000sccm, etc.; the pressure can be 4Torr, 4.5Torr, 5Torr, 5.5Torr or 6Torr, etc., and the coating power can be 2000W, 3000W, 4000W or 5000W, etc.

[0037] In the present invention, the methods for depositing the front intrinsic layer and the front doped layer on the other side surface of the silicon substrate are conventional technical solutions, and those skilled in the art can select and adjust the above-mentioned preparation parameters and gas types according to actual needs.

[0038] For example, the first doping gas may be phosphine (PH 3 ) gas.

[0039] Further preferably, the thickness of the front intrinsic layer is 5~8nm (for example, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm or 8nm, etc.); the thickness of the front doped layer is 22~28nm, for example, 22nm, 23nm, 24nm, 25nm, 26nm, 27nm or 28nm.

[0040] Preferably, in step (2), in addition to depositing on any side surface of the silicon substrate, the step also includes a deposition process on the side wall surface of the silicon substrate perpendicular to the thickness direction.

[0041] Preferably, step (3) comprises:

[0042] A third silane and a second hydrogen are introduced to deposit a second back intrinsic layer on the surface of the first back intrinsic layer; then a fourth silane, a third hydrogen and a second doping gas are introduced to deposit a back doping layer on the surface of the second back intrinsic layer.

[0043] Preferably, during the deposition of the second back intrinsic layer, the ratio of the second hydrogen flow rate to the third silane flow rate is (1~5):1, for example, 1:1, 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1 or 5:1, etc.

[0044] In the present invention, during the deposition of the second back intrinsic layer, high hydrogen and high oxygen doping are performed, which is beneficial to the nucleation of microcrystals, thereby facilitating the improvement of the crystallization rate of the subsequent back doped layer, so that the back doped layer has a larger band gap energy (Eg); further regulating the ratio of the second hydrogen flow rate and the third silane flow rate to (1-5):1, the amorphous passivation layer can be better obtained.

[0045] Preferably, during the deposition of the second back intrinsic layer, the flow rate of the third silane is 500-1000 sccm, the flow rate of the second hydrogen is 500-5000 sccm, the pressure is 0.4-0.6 Torr, and the coating power is 100-300W.

[0046] For example, the flow rate of the third silane can be 500sccm, 600sccm, 700sccm, 800sccm, 900sccm or 1000sccm, etc., the flow rate of the second hydrogen can be 500sccm, 1000sccm, 1500sccm, 2000sccm, 2500sccm, 3000sccm, 3500sccm, 4000sccm, 4500sccm or 5000sccm, etc., the pressure can be 0.4Torr, 0.45Torr, 0.5Torr, 0.55Torr or 0.6Torr, etc., and the coating power can be 100W, 150W, 200W, 250W or 300W, etc.

[0047] In the present invention, the flow rate of the third silane is further adjusted to 500-1000 sccm and / or the flow rate of the second hydrogen is adjusted to 500-5000 sccmsccm, which is more conducive to contact with the outer back (p-type) doping layer.

[0048] Preferably, the thickness of the second back intrinsic layer is 3-6 nm, for example, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, etc.

[0049] In the present invention, the thickness of the second back intrinsic layer is thicker than that of the first back intrinsic layer, which further enhances the passivation effect of the intrinsic layer to improve the contact; and the thickness of the second back intrinsic layer is adjusted to 3~6nm, which has the effect of further improving the effective doping effect of the P-type doping layer.

[0050] Preferably, during the deposition of the back doping layer, the flow rate of the fourth silane is 50~80sccm, the flow rate of the third hydrogen is 18000~25000sccm, the flow rate of the second doping gas is 30~200sccm, the pressure is 4~6Torr, and the coating power is 5000~8000W.

[0051] For example, during the deposition process of the back doping layer, the flow rate of the fourth silane can be 50sccm, 60sccm, 70sccm or 80sccm, etc.; the flow rate of the third hydrogen can be 18000sccm, 19000sccm, 20000sccm, 21000sccm, 22000sccm, 23000sccm, 24000sccm or 25000sccm, etc.; the flow rate of the second doping gas can be 30sccm, 50sccm, 75sccm, 100sccm, 125sccm, 150sccm, 175sccm or 200sccm, etc.; the pressure can be 4Torr, 4.5Torr, 5Torr, 5.5Torr or 6Torr, etc.; the coating power can be 5000W, 6000W, 7000W or 8000W, etc.

[0052] In the present invention, the preparation process and preparation parameters of the back doping layer are conventional technical solutions, and those skilled in the art can make adaptive selections and adjustments according to actual needs.

[0053] Further preferably, the thickness of the back doping layer is 24-35 nm, for example, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm or 35 nm.

[0054] Preferably, in step (2), in addition to depositing the surface of the first back intrinsic layer, the step also includes a deposition process on the sidewall of the silicon substrate perpendicular to the thickness direction.

[0055] In the present invention, during the deposition process of step (1), step (2) and step (3), the deposition process of the film layer on the side wall of the silicon substrate perpendicular to the thickness direction can be carried out simultaneously under the corresponding same deposition conditions, that is, the surface of the side wall perpendicular to the thickness direction can sequentially include a first back intrinsic layer, a front intrinsic layer, a front doped layer, a second back intrinsic layer and a back doped layer, so that at least one second back intrinsic layer is included between the front doped layer (n layer) and the back doped layer (p layer).

[0056] The film layer structure is also deposited on the side wall surface of the silicon substrate perpendicular to the thickness direction, and there is at least one back intrinsic layer between the n / p layer, which has a better insulation effect and more effectively solves the battery leakage problem, thereby achieving further improvement in battery performance.

[0057] Further preferably, in the film layer structure deposited in the side wall of the silicon substrate perpendicular to the thickness direction, the thickness of each layer structure is independently 0.5~2nm, for example, 0.5nm, 0.6nm, 0.7nm, 0.8nm, 0.9nm, 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm or 2nm, etc.

[0058] Preferably, in step (4), the thickness of the transparent conductive oxide layer is 30-60 nm, for example, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm or 60 nm.

[0059] It should be noted that the method for preparing the film layer of the transparent conductive oxide layer in the present invention is a conventional technical solution, and the present invention is applicable to any preparation method that can be known within a reasonable range by those skilled in the art.

[0060] Exemplarily, the present invention provides a method for preparing a film layer of a transparent conductive oxide layer, which specifically comprises:

[0061] The surfaces of the front doped layer and the back doped layer are coated by reactive plasma deposition (RPD) or magnetron sputtering; the back side is shielded by edge design of the carrier (shielded by mask), and the specific shielding area around is 0.5~0.8mm (for example, 0.5mm, 0.6mm, 0.7mm or 0.8mm, etc.).

[0062] Furthermore, the material of the transparent conductive oxide layer is ITO (In2O3:XO2=99.5:0.5wt%), and the carrier concentration is 2E20~5E20 / cm 3 (e.g. 2E20 / cm 3 , 2.5E20 / cm 3 、3E20 / cm 3、3.5E20 / cm 3 , 4E20 / cm 3 , 4.5E20 / cm 3 or 5E20 / cm 3 etc.), the mobility is ≥80cm 2 / Vs (e.g. 80cm 2 / Vs, 85cm 2 / Vs, 90cm 2 / Vs, 95cm 2 / Vs or 100cm 2 / Vs, etc.).

[0063] Preferably, in step (5), the electrode preparation method includes a screen printing electrode preparation method.

[0064] Preferably, in step (5), after the electrode preparation is completed, a light injection treatment is performed to obtain the heterojunction solar cell.

[0065] It is understandable that the electrode preparation method and light injection method in the present invention are also conventional technical solutions, and those skilled in the art can make adaptive selections and adjustments based on actual needs.

[0066] Exemplarily, the present invention provides a method for electrode preparation and light injection treatment, specifically comprising:

[0067] Electrode preparation: Use the screen printing method to print a layer of low-temperature conductive silver paste on the transparent conductive oxide film on the front and back sides respectively, and then sinter and solidify at a low temperature of 150~300℃ (for example, 150℃, 175℃, 200℃, 225℃, 250℃, 275℃ or 300℃) to form a good ohmic contact to complete the electrode preparation.

[0068] Light injection treatment: After the battery cell is alkaline washed, the prepared battery cell is subjected to light injection treatment. The temperature of the light injection treatment is 200~220℃ (for example, 200℃, 210℃ or 220℃, etc.), and the time of the light injection treatment is 60~120s (for example, 60s, 70s, 80s, 90s, 100s, 110s or 120s, etc.).

[0069] It should also be noted that the silicon substrate in the present invention is an N-type silicon substrate, the resistivity of which is 0.5~3Ω.cm (for example, 0.5Ω.cm, 1Ω.cm, 1.5Ω.cm, 2Ω.cm, 2.5Ω.cm or 3Ω.cm, etc.), the thickness is 90~120μm (for example, 90μm, 95μm, 100μm, 105μm, 110μm, 115μm or 120μm, etc.), and the size is 210mm.

[0070] Specifically, the types of the silicon substrate include but are not limited to N-type crystalline silicon wafers.

[0071] In addition, it should be noted that the pressure in the present invention refers to the deposition pressure during the film deposition process, that is, the absolute pressure value in the film deposition system.

[0072] In a second aspect, the present invention provides a heterojunction solar cell, wherein the heterojunction solar cell is prepared by the preparation method described in the first aspect.

[0073] The heterojunction solar cell provided by the present invention has a front intrinsic layer, a front doped layer, a transparent conductive oxide layer and an electrode stacked in sequence along any one side surface of a silicon substrate (arranged along the thickness direction); and a first back intrinsic layer, a first back intrinsic layer, a back doped layer, a transparent conductive oxide layer and an electrode stacked in sequence along the other side surface of the silicon substrate; through the coordination of the above structures, a heterojunction solar cell with excellent performance is obtained.

[0074] Furthermore, a film layer structure is also deposited on the side wall of the silicon substrate perpendicular to the thickness direction, and from the surface of the side wall, a first back intrinsic layer, a front intrinsic layer, a front doped layer, a second back intrinsic layer and a back doped layer are stacked in sequence. In addition, the outermost layer may also include a transparent conductive oxide layer on the front side; the film layer structure at the side wall is integrally formed with the corresponding film layer structure at the surface of the silicon substrate.

[0075] In a third aspect, the present invention further provides an application of the heterojunction solar cell as described in the second aspect in a photovoltaic device.

[0076] The numerical range described in the present invention not only includes the point values ​​listed above, but also includes any point values ​​between the above numerical ranges that are not listed. Due to space limitations and for the sake of simplicity, the present invention no longer exhaustively lists the specific point values ​​included in the range.

[0077] Compared with the prior art, the present invention has the following beneficial effects:

[0078] The preparation method, preparation sequence and coordinated structural layers provided by the present invention prepare the back intrinsic layer in steps, thereby avoiding damage to the intrinsic layer when the front side of the silicon substrate (i.e., the light-receiving side) is coated by flipping, and ensuring that the outermost back intrinsic layer in contact with the back doped layer is not damaged, thereby obtaining a low-resistance and stable tunneling contact solar cell structure, and its thermal attenuation reliability is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 Schematic diagram of the structure of a heterojunction solar cell prepared by the preparation method provided in Example 1.

[0080] Among them, 1-silicon substrate, 2-first back intrinsic layer, 3-front intrinsic layer, 4-front doped layer, 5-second back intrinsic layer, 6-back doped layer, 7-transparent oxide conductive layer, 8-electrode. DETAILED DESCRIPTION

[0081] The technical solution of the present invention is further described below by specific implementation methods. It should be understood by those skilled in the art that the embodiments are only to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0082] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in this application are intended to cover non-exclusive inclusions.

[0083] In the description of this application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0084] Example 1

[0085] This embodiment provides a method for preparing a heterojunction solar cell, and the preparation method is as follows:

[0086] (1) Silicon substrate selection: N-type crystalline silicon wafer with a resistivity of 1Ω.cm, a thickness of 100μm, and a size of 210mm;

[0087] (2) Cleaning and texturing: Use a 5% diluted HF solution to remove the surface oxide layer of the silicon substrate, and use the KOH plus alcohol method to form a pyramid structure on the surface by anisotropic etching of single crystal silicon to complete the texturing treatment on both sides of the silicon substrate;

[0088] (3) Deposition of the first back intrinsic layer: SiH4 (silane) gas is introduced into the vacuum chamber, and a first back intrinsic layer (amorphous silicon film i1 layer) is formed on the entire area of ​​the first surface of the silicon substrate (the surface on any side and the side wall perpendicular to the thickness direction of the silicon substrate) by plasma CVD; wherein the silane flow rate is 900 sccm, the pressure is 0.5 Torr, and the coating power is 800 W; the thickness of the first back intrinsic layer on the surface of one side of the silicon substrate (the non-light-receiving surface opposite to the light-receiving surface) obtained by deposition is 2 nm, and the thickness of the first back intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8 nm;

[0089] (4) Deposition of the front intrinsic layer and the front doped layer: Turn the silicon substrate over to expose the surface on the other side of the silicon substrate, replace the tray of the silicon substrate, introduce SiH4 (silane) gas into the vacuum chamber, and form a front intrinsic layer on the entire area of ​​the second surface of the silicon substrate (the surface on the other side of the silicon substrate and the side wall perpendicular to the thickness direction of the silicon substrate) by plasma CVD, wherein the silane flow rate is 800 sccm, the pressure is 0.5 Torr, and the coating power is 400 W; the thickness of the front intrinsic layer on the other side of the silicon substrate (the light-receiving side) obtained by deposition is 6.5 nm, and the thickness of the front intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8 nm;

[0090] Then, SiH4 gas, H2 gas and PH3 (phosphine, the first doping gas) gas are introduced into the vacuum chamber, and a front doping layer is formed on the surface of the front intrinsic layer by a plasma CVD method; wherein, the flow rate of silane is 55 ccm, the flow rate of hydrogen is 14000 sccm, the flow rate of PH3 is 350 sccm, the pressure is 5 Torr, and the coating power is 3500 W; the thickness of the deposited front doping layer on the light-receiving surface is 25 nm, and the thickness of the front doping layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8 nm;

[0091] (5) Deposition of a second back intrinsic layer and a back doped layer: Turn the silicon substrate over again, replace the tray, and then introduce SiH4 (silane) and hydrogen gas into the vacuum chamber, and form a second back intrinsic layer on the entire area of ​​the first back intrinsic layer by plasma CVD; wherein, the ratio of hydrogen to silane flow rate is 2.5:1, the silane flow rate is 750 sccm, the pressure is 0.5 Torr, and the coating power is 200 W; the thickness of the deposited second back intrinsic layer on the non-light-receiving surface is 4 nm, and the thickness of the second back intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8 nm;

[0092] Then, SiH4 gas, H2 gas and B2H6 (diborane, second doping gas) gas are introduced into the vacuum chamber, and a back doping layer is formed on the second back intrinsic layer by a plasma CVD method; wherein, the flow rate of silane is 65sccm, the flow rate of hydrogen is 21000sccm, the flow rate of B2H6 is 100sccm, the pressure is 5Torr, and the coating power is 6500W; the thickness of the deposited back doping layer is 30nm, and the thickness of the back doping layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8nm;

[0093] (6) Deposition of transparent conductive oxide film (TCO): Reactive plasma deposition (RPD) is used to deposit the amorphous silicon thin film layers on the front and back sides. The back side is shielded by the edge of the carrier design (shielded by mask), and the specific shielding area around is 0.8 mm. The TCO used is ITO (99.5:0.5), the film thickness is 40 nm, and the carrier concentration is 3E20 / cm 3 , the mobility is 80cm 2 / Vs;

[0094] (7) Electrode preparation: A layer of low-temperature conductive silver paste is printed on the transparent conductive oxide film on the front and back sides by screen printing, and then sintered and cured at a low temperature of 200°C to form a good ohmic contact;

[0095] (8) Light injection treatment: After the battery obtained in step (7) is alkaline washed, the obtained battery cell is subjected to light injection treatment. The temperature of the light injection treatment is 210° C. and the time of the light injection treatment is 90 s.

[0096] Figure 1 The schematic diagram of the structure of the heterojunction solar cell prepared by the preparation method provided in Example 1 is shown. Figure 1 It can be seen that along the thickness direction of the silicon substrate 1 ( Figure 1 The arrow direction in the figure is the thickness direction), and a first back intrinsic layer 2, a second back intrinsic layer 5 and a back doped layer 6 are arranged on one side of the surface; a front intrinsic layer 3 and a front doped layer 4 are arranged on the surface of the other side of the silicon substrate 1 in sequence; a transparent oxide conductive layer 7 is arranged on the surface of the front doped layer 4 and the back doped layer 6, and an electrode 8 is arranged on the surface of the transparent conductive oxide layer 7; in addition, the first back intrinsic layer 2, the front intrinsic layer 3, the front doped layer 4, the second back intrinsic layer 5, the back doped layer 6 and the transparent oxide conductive layer 7 located on the surface of the front doped layer 4 are arranged on the side wall of the silicon substrate 1 perpendicular to the thickness direction in sequence. The heterojunction solar cell prepared by the preparation method provided in Example 1 has a low resistance and stable tunneling contact, and its thermal attenuation reliability is also improved.

[0097] Example 2

[0098] This embodiment provides a method for preparing a heterojunction solar cell, and the preparation method is as follows:

[0099] (1) Silicon substrate selection: N-type crystalline silicon wafer with a resistivity of 2Ω.cm, a thickness of 100μm, and a size of 210mm;

[0100] (2) Cleaning and texturing: Use a 5% diluted HF solution to remove the surface oxide layer of the silicon substrate, and use the KOH plus alcohol method to form a pyramid structure on the surface by anisotropic etching of single crystal silicon to complete the texturing treatment on both sides of the silicon substrate;

[0101] (3) Deposition of the first back intrinsic layer: SiH4 (silane) gas is introduced into the vacuum chamber, and a first back intrinsic layer (amorphous silicon film i1 layer) is formed on the entire area of ​​the first surface of the silicon substrate (the surface on any side and the side wall perpendicular to the thickness direction of the silicon substrate) by plasma CVD; wherein the silane flow rate is 800 sccm, the pressure is 0.4 Torr, and the coating power is 500 W; the thickness of the first back intrinsic layer on the surface of one side of the silicon substrate (the non-light-receiving surface opposite to the light-receiving surface) obtained by deposition is 1 nm, and the thickness of the first back intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.5 nm;

[0102] (4) Deposition of the front intrinsic layer and the front doped layer: Turn the silicon substrate over to expose the surface on the other side of the silicon substrate, replace the tray of the silicon substrate, introduce SiH4 (silane) gas into the vacuum chamber, and form a front intrinsic layer on the entire area of ​​the second surface of the silicon substrate (the surface on the other side of the silicon substrate and the side wall perpendicular to the thickness direction of the silicon substrate) by plasma CVD, wherein the silane flow rate is 500sccm, the pressure is 0.4Torr, and the coating power is 200W; the thickness of the front intrinsic layer on the other side of the silicon substrate (the light-receiving surface) obtained by deposition is 5nm, and the thickness of the front intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.5nm;

[0103] Then, SiH4 gas, H2 gas and PH3 (phosphine, the first doping gas) gas are introduced into the vacuum chamber, and a front doping layer is formed on the surface of the front intrinsic layer by a plasma CVD method; wherein, the flow rate of silane is 40sccm, the flow rate of hydrogen is 12000sccm, the flow rate of PH3 is 200sccm, the pressure is 4Torr, and the coating power is 2000W; the thickness of the deposited front doping layer on the light-receiving surface is 22nm, and the thickness of the front doping layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.5nm;

[0104] (5) Deposition of a second back intrinsic layer and a back doped layer: Turn the silicon substrate over again, replace the tray, and then introduce SiH4 (silane) and hydrogen gas into the vacuum chamber, and form a second back intrinsic layer on the entire area of ​​the first back intrinsic layer by plasma CVD; wherein, the ratio of hydrogen to silane flow rate is 5:1, the silane flow rate is 500 sccm, the pressure is 0.4 Torr, and the coating power is 200 W; the thickness of the deposited second back intrinsic layer on the non-light-receiving surface is 3 nm, and the thickness of the second back intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.5 nm;

[0105] Then, SiH4 gas, H2 gas and B2H6 (diborane, the second doping gas) gas are introduced into the vacuum chamber, and a back doping layer is formed on the second back intrinsic layer by a plasma CVD method; wherein, the flow rate of silane is 50 sccm, the flow rate of hydrogen is 18000 sccm, the flow rate of B2H6 is 30 sccm, the pressure is 4 Torr, and the coating power is 5000 W; the thickness of the deposited back doping layer is 24 nm, and the thickness of the back doping layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.5 nm;

[0106] Transparent conductive oxide film (TCO) was deposited perpendicular to the thickness direction of the silicon substrate (6): Reactive plasma deposition (RPD) was used to coat the amorphous silicon film layers on the front and back sides; the back side was shielded by the edge of the carrier design (shielded by mask), and the specific shielding area around was 0.8 mm. The TCO used was ITO (99.5:0.5), with a film thickness of 40 nm and a carrier concentration of 4E20 / cm 3 , the mobility is 80cm 2 / Vs;

[0107] (7) Electrode preparation: A layer of low-temperature conductive silver paste is printed on the transparent conductive oxide film on the front and back sides by screen printing, and then sintered and cured at a low temperature of 200°C to form a good ohmic contact;

[0108] (8) Light injection treatment: After the battery obtained in step (7) is alkaline washed, the obtained battery cell is subjected to light injection treatment. The temperature of the light injection treatment is 210° C. and the time of the light injection treatment is 90 s.

[0109] Example 3

[0110] This embodiment provides a method for preparing a heterojunction solar cell, and the preparation method is as follows:

[0111] (1) Silicon substrate selection: N-type crystalline silicon wafer with a resistivity of 3Ω.cm, a thickness of 90μm, and a size of 210mm;

[0112] (2) Cleaning and texturing: Use a 5% diluted HF solution to remove the surface oxide layer of the silicon substrate, and use the KOH plus alcohol method to form a pyramid structure on the surface by anisotropic etching of single crystal silicon to complete the texturing treatment on both sides of the silicon substrate;

[0113] (3) Deposition of the first back intrinsic layer: SiH4 (silane) gas is introduced into the vacuum chamber, and a first back intrinsic layer (amorphous silicon film i1 layer) is formed on the entire area of ​​the first surface of the silicon substrate (the surface on any side and the side wall perpendicular to the thickness direction of the silicon substrate) by plasma CVD; wherein the silane flow rate is 1000 sccm, the pressure is 0.6 Torr, and the coating power is 1000 W; the thickness of the first back intrinsic layer on the surface of one side of the silicon substrate (the non-light-receiving surface on the side opposite to the light-receiving surface) obtained by deposition is 1.5 nm, and the thickness of the first back intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 1.5 nm;

[0114] (4) Deposition of the front intrinsic layer and the front doped layer: Turn the silicon substrate over to expose the surface on the other side of the silicon substrate, replace the tray of the silicon substrate, introduce SiH4 (silane) gas into the vacuum chamber, and form a front intrinsic layer on the entire area of ​​the second surface of the silicon substrate (the surface on the other side of the silicon substrate and the side wall perpendicular to the thickness direction of the silicon substrate) by plasma CVD, wherein the silane flow rate is 1000sccm, the pressure is 0.6Torr, and the coating power is 600W; the thickness of the front intrinsic layer on the other side of the silicon substrate (the light-receiving side) obtained by deposition is 85nm, and the thickness of the front intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 2nm;

[0115] Then, SiH4 gas, H2 gas and PH3 (phosphine, the first doping gas) gas are introduced into the vacuum chamber, and a front doping layer is formed on the surface of the front intrinsic layer by a plasma CVD method; wherein the flow rate of silane is 70sccm, the flow rate of hydrogen is 16000sccm, the flow rate of PH3 is 500, the pressure is 6Torr, and the coating power is 5000W; the thickness of the deposited front doping layer on the light-receiving surface is 28nm, and the thickness of the front doping layer on the side wall perpendicular to the thickness direction of the silicon substrate is 2nm;

[0116] (5) Deposition of a second back intrinsic layer and a back doped layer: Turn the silicon substrate over again, replace the tray, and then introduce SiH4 (silane) and hydrogen gas into the vacuum chamber, and form a second back intrinsic layer on the entire area of ​​the first back intrinsic layer by plasma CVD; wherein, in the introduced gas, the ratio of hydrogen:silane flow rate is 1:1, the silane flow rate is 1000 sccm, the pressure is 0.6 Torr, and the coating power is 300 W; the thickness of the deposited second back intrinsic layer on the non-light-receiving surface is 6 nm, and the thickness of the second back intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 2 nm;

[0117] Then, SiH4 gas, H2 gas and B2H6 (diborane, second doping gas) gas are introduced into the vacuum chamber, and a back doping layer is formed on the second back intrinsic layer by a plasma CVD method; wherein, the flow rate of silane is 80 sccm, the flow rate of hydrogen is 25000 sccm, the flow rate of B2H6 is 200 sccm, the pressure is 6 Torr, and the coating power is 8000 W; the thickness of the deposited back doping layer is 35 nm, and the thickness of the back doping layer on the side wall perpendicular to the thickness direction of the silicon substrate is 2 nm;

[0118] Perpendicular to the thickness direction of the silicon substrate;

[0119] (6) Deposition of transparent conductive oxide film (TCO): On the amorphous silicon thin film layers on the front and back sides, the film is coated by reactive plasma deposition (RPD); the back side is shielded by edge design of the carrier (shielded by mask), and the specific shielding area around is 0.8mm. The TCO used is ITO (99.5:0.5), the film thickness is 40nm, and the carrier concentration is 5E20 / cm 3 , the mobility is 80cm 2 / Vs;

[0120] (7) Electrode preparation: A layer of low-temperature conductive silver paste is printed on the transparent conductive oxide film on the front and back sides by screen printing, and then sintered and cured at a low temperature of 200°C to form a good ohmic contact;

[0121] (8) Light injection treatment: After the battery obtained in step (7) is alkaline washed, the obtained battery cell is subjected to light injection treatment. The temperature of the light injection treatment is 210° C. and the time of the light injection treatment is 90 s.

[0122] Example 4

[0123] The difference between this embodiment and embodiment 1 is that the flow rate of silane in step (3) of this embodiment is 500 sccm.

[0124] The rest of the preparation methods and parameters were the same as those in Example 1.

[0125] Example 5

[0126] The difference between this embodiment and embodiment 1 is that the flow rate of silane in step (3) of this embodiment is 1500 sccm.

[0127] The rest of the preparation methods and parameters were the same as those in Example 1.

[0128] Example 6

[0129] The difference between this embodiment and embodiment 1 is that in step (3) of this embodiment, the thickness of the first back intrinsic layer on one surface of the silicon substrate (the non-light-receiving surface opposite to the light-receiving surface) obtained by deposition is 3 nm.

[0130] The rest of the preparation methods and parameters were the same as those in Example 1.

[0131] Example 7

[0132] The difference between this embodiment and embodiment 1 is that in step (5) of this embodiment, when depositing the second back intrinsic layer, the ratio of the flow rates of hydrogen and silane is 0.5:1.

[0133] The rest of the preparation methods and parameters were the same as those in Example 1.

[0134] Example 8

[0135] The difference between this embodiment and embodiment 1 is that in step (5) of this embodiment, when depositing the second back intrinsic layer, the ratio of the flow rate of hydrogen to that of silane is 10:1.

[0136] The rest of the preparation methods and parameters were the same as those in Example 1.

[0137] Example 9

[0138] The difference between this embodiment and embodiment 1 is that in step (5) of this embodiment, the thickness of the second back intrinsic layer on the non-light-receiving surface deposited is 1.5 nm.

[0139] The rest of the preparation methods and parameters were the same as those in Example 1.

[0140] Example 10

[0141] The difference between this embodiment and embodiment 1 is that in step (5) of this embodiment, the thickness of the second back intrinsic layer on the non-light-receiving surface deposited is 8 nm.

[0142] The rest of the preparation methods and parameters were the same as those in Example 1.

[0143] Embodiment 11

[0144] The difference between this embodiment and embodiment 1 is that in steps (2) to (5) of this embodiment, no film layer structure is deposited on the side wall of the silicon substrate perpendicular to the thickness direction.

[0145] The rest of the preparation methods and parameters were the same as those in Example 1.

[0146] Example 12

[0147] The difference between this embodiment and embodiment 1 is that in step (5) of this embodiment, the second back intrinsic layer is not deposited on the side wall of the silicon substrate perpendicular to the thickness direction, that is, there is no film layer structure between the front doped layer (n layer) and the back doped layer (p layer) at the side wall.

[0148] The rest of the preparation methods and parameters were the same as those in Example 1.

[0149] Comparative Example 1

[0150] This comparative example provides a method for preparing a heterojunction solar cell, and the preparation method is as follows:

[0151] (1) Silicon substrate selection: N-type crystalline silicon wafer with a resistivity of 1Ω.cm, a thickness of 100μm, and a size of 210mm;

[0152] (2) Cleaning and texturing: Use a 5% diluted HF solution to remove the surface oxide layer of the silicon substrate, and use the KOH plus alcohol method to form a pyramid structure on the surface by anisotropic etching of single crystal silicon to complete the texturing treatment on both sides of the silicon substrate;

[0153] (3) Deposition of the front intrinsic layer and the front doped layer: Turn the silicon substrate over to expose the surface on the other side of the silicon substrate, replace the tray of the silicon substrate, introduce SiH4 (silane) gas into the vacuum chamber, and form a front intrinsic layer on the entire area of ​​the second surface of the silicon substrate (the surface on the other side of the silicon substrate and the side wall perpendicular to the thickness direction of the silicon substrate) by plasma CVD, wherein the silane flow rate is 800sccm, the pressure is 0.5Torr, and the coating power is 400W; the thickness of the front intrinsic layer on the other side of the silicon substrate (the light-receiving side) obtained by deposition is 6.5nm, and the thickness of the front intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8nm;

[0154] Then, SiH4 gas, H2 gas and PH3 (phosphine, the first doping gas) gas are introduced into the vacuum chamber, and a front doping layer is formed on the surface of the front intrinsic layer by a plasma CVD method; wherein, the flow rate of silane is 55 ccm, the flow rate of hydrogen is 14000 sccm, the flow rate of PH3 is 350 sccm, the pressure is 5 Torr, and the coating power is 3500 W; the thickness of the deposited front doping layer on the light-receiving surface is 25 nm, and the thickness of the front doping layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8 nm;

[0155] (4) Deposition of the first back intrinsic layer, the second back intrinsic layer and the back doping layer:

[0156] Turn the silicon substrate over, replace the tray, introduce SiH4 (silane) gas into the vacuum chamber, and form the first back intrinsic layer (amorphous silicon film i1 layer) on the entire area of ​​the other side surface of the silicon substrate by plasma CVD; wherein the silane flow rate is 900 sccm, the pressure is 0.5 Torr, and the coating power is 800 W; the thickness of the first back intrinsic layer on the surface of one side of the silicon substrate (the non-light-receiving side opposite to the light-receiving side) obtained by deposition is 2 nm, and the thickness of the first back intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8 nm;

[0157] Then SiH4 (silane) and hydrogen gas are introduced into the vacuum chamber, and a second back intrinsic layer is formed on the entire area of ​​the first back intrinsic layer by plasma CVD; wherein, in the introduced gas, the ratio of hydrogen to silane flow rate is 2.5:1, the silane flow rate is 750 sccm, the pressure is 0.5 Torr, and the coating power is 200 W; the thickness of the deposited second back intrinsic layer on the non-light-receiving surface is 4 nm, and the thickness of the second back intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8 nm;

[0158] Depositing the second back intrinsic layer and the back doping layer: turning the silicon substrate over again, replacing the tray, and then introducing SiH4 (silane) and hydrogen gas into the vacuum chamber, and forming the second back intrinsic layer on the entire area of ​​the first back intrinsic layer by plasma CVD; wherein, in the introduced gas, the ratio of the flow rate of hydrogen:silane is 2.5:1, the flow rate of silane is 750sccm, the pressure is 0.5Torr, and the coating power is 200W; the thickness of the deposited second back intrinsic layer on the non-light-receiving surface is 4nm, and the thickness of the second back intrinsic layer on the side wall perpendicular to the thickness direction of the silicon substrate is 0.8nm perpendicular to the thickness direction of the silicon substrate perpendicular to the thickness direction of the silicon substrate;

[0159] (5) Deposition of transparent conductive oxide film (TCO): On the amorphous silicon thin film layer on the front and back sides, the reactive plasma deposition (RPD) method is used for coating; the back side is shielded by the edge of the carrier design (shielded by mask), and the specific shielding area around is 0.8mm. The TCO used is ITO (99.5:0.5), the film thickness is 40nm, and the carrier concentration is 3×E 20 / cm 3 , mobility ~80cm 2 / Vs;

[0160] (6) Electrode preparation: A layer of low-temperature conductive silver paste is printed on the transparent conductive oxide film on the front and back sides by screen printing, and then sintered and cured at a low temperature of 200°C to form a good ohmic contact;

[0161] (7) Light injection treatment: After the battery obtained in step (7) is alkaline washed, the obtained battery cell is subjected to light injection treatment. The temperature of the light injection treatment is 210° C. and the time of the light injection treatment is 90 s.

[0162] Comparative Example 2

[0163] The difference between this comparative example and Example 1 is that the first back intrinsic layer is not prepared in this comparative example.

[0164] The rest of the preparation methods and parameters were the same as those in Example 1.

[0165] Comparative Example 3

[0166] The difference between this comparative example and Example 1 is that the second back intrinsic layer is not prepared in this comparative example.

[0167] The rest of the preparation methods and parameters were the same as those in Example 1.

[0168] Comparative Example 4

[0169] The difference between this comparative example and Example 1 is that in this comparative example, the preparation order of the first back intrinsic layer and the second back intrinsic layer is exchanged.

[0170] The rest of the preparation methods and parameters were the same as those in Example 1.

[0171] The solar cells prepared in Examples 1-12 and Comparative Examples 1-4 were subjected to performance tests, including open circuit voltage (Voc), fill factor (FF), short circuit current density (Jsc), conversion efficiency (eta) and thermal attenuation (ΔEff); the specific test results are shown in Table 1.

[0172] Table 1

[0173]

[0174] In summary, the preparation method, preparation sequence and coordinated structural layers provided by the present invention prepare the back intrinsic layer in steps, thereby avoiding the destruction of the intrinsic layer when the front side of the silicon substrate (i.e., the light-receiving side) is coated by flipping, and ensuring that the outermost back intrinsic layer in contact with the back doped layer is not damaged, thereby obtaining a low-resistance and stable tunneling contact solar cell structure, and its thermal attenuation reliability is also improved.

[0175] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention are within the protection scope and disclosure scope of the present invention.

Claims

1. A method for preparing an n-type solar cell, characterized in that: The preparation method comprises the following steps: (1) depositing a first back intrinsic layer on any one side surface of the silicon substrate. In step (1), in addition to depositing the first back intrinsic layer on any one side surface of the silicon substrate, the step also includes depositing the first back intrinsic layer on a sidewall surface of the silicon substrate perpendicular to the thickness direction, wherein the any one side surface is a backlit surface; (2) turning over the silicon substrate, and sequentially depositing a front intrinsic layer and a front doped layer on the other side surface of the silicon substrate. In step (2), in addition to depositing on any side surface of the silicon substrate, the step also includes depositing the front intrinsic layer and the front doped layer on the side wall surface of the silicon substrate perpendicular to the thickness direction; (3) turning the silicon substrate over again, and sequentially depositing a second back intrinsic layer and a back doped layer on the surface of the first back intrinsic layer, wherein the thickness of the second back intrinsic layer is greater than the thickness of the first back intrinsic layer. In step (3), in addition to depositing the first back intrinsic layer on the surface, the second back intrinsic layer and the back doped layer are deposited on the sidewall surface of the silicon substrate perpendicular to the thickness direction, wherein the back doped layer is a back p-type doped layer. (4) depositing a transparent conductive oxide layer on the surface of the front doped layer and the back doped layer respectively; (5) Electrodes are prepared on the front transparent conductive oxide layer surface and the back transparent oxide layer surface respectively to obtain the n-type solar cell.

2. The method for preparing an n-type solar cell according to claim 1, characterized in that: In step (1), the surfaces of both sides of the silicon substrate are first textured, and then the first back intrinsic layer is deposited.

3. The method for preparing an n-type solar cell according to claim 1, characterized in that: Step (1) includes: Passing a first silane to deposit a first back intrinsic layer on any side surface of the silicon substrate; During the deposition of the first back intrinsic layer, the flow rate of the first silane is 800-1000 sccm, the pressure is 0.4-0.6 Torr, and the coating power is 500-1000W.

4. The method for preparing an n-type solar cell according to claim 1 or 3, characterized in that: The deposition thickness of the first back intrinsic layer is 1-2 nm.

5. The method for preparing an n-type solar cell according to claim 1, characterized in that: Step (2) includes: Passing a second silane to deposit a front intrinsic layer on the other side surface of the silicon substrate; Then, the second silane, the first hydrogen and the first doping gas are introduced to deposit a front doping layer on the surface of the front intrinsic layer; During the deposition of the front intrinsic layer, the flow rate of the second silane is 500-1000 sccm, the pressure is 0.4-0.6 Torr, and the coating power is 200-600 W; During the deposition of the front doped layer, the flow rate of the second silane is 40~70sccm, the flow rate of the first hydrogen is 12000~16000sccm, the flow rate of the first doping gas is 200~500sccm, the pressure is 4~6Torr, and the coating power is 2000~5000W.

6. The method for preparing an n-type solar cell according to claim 1, characterized in that: Step (3) includes: Passing a third silane and a second hydrogen gas to deposit a second back side intrinsic layer on the surface of the first back side intrinsic layer; Then, the fourth silane, the third hydrogen and the second doping gas are introduced to deposit a back doping layer on the surface of the second back intrinsic layer; During the deposition of the second back intrinsic layer, the ratio of the flow rate of the second hydrogen gas to the flow rate of the third silane is (1-5):1; During the deposition of the second back intrinsic layer, the flow rate of the third silane is 500-1000 sccm, the flow rate of the second hydrogen is 500-5000 sccm, the pressure is 0.4-0.6 Torr, and the coating power is 100-300 W; During the deposition of the back doping layer, the flow rate of the fourth silane is 50~80sccm, the flow rate of the third hydrogen is 18000~25000sccm, the flow rate of the second doping gas is 30~200sccm, the pressure is 4~6Torr, and the coating power is 5000~8000W.

7. The method for preparing an n-type solar cell according to claim 1 or 6, characterized in that: The thickness of the second back intrinsic layer is 3-6 nm.

8. The method for preparing an n-type solar cell according to claim 1, characterized in that: In step (4), the thickness of the transparent conductive oxide layer is 30-60 nm; And / or, in step (5), the method for preparing the electrode includes a screen printing electrode preparation method; And / or, in step (5), after the electrode preparation is completed, a light injection treatment is performed to obtain the n-type solar cell.

9. An n-type solar cell, characterized in that: The n-type solar cell is prepared by the preparation method according to any one of claims 1 to 8.

10. A use of the n-type solar cell according to claim 9, characterized in that: The n-type solar cell is used to manufacture a photovoltaic device.

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