Method for preparing a crystalline silicon battery string with embedded gate line, battery string and photovoltaic module

Abstract

The embodiments of the present invention provide a method for preparing a crystalline silicon cell string with embedded gate lines, a cell string and a photovoltaic module, and relate to the field of solar cell technology. The method for preparing a crystalline silicon cell string with embedded gate lines includes preparing a silicon wafer; performing reverse masking on the front and back of the silicon wafer, thereby forming embedded gate lines and interconnection areas on the front and back of the silicon wafer, and the interconnection areas are connected to the embedded gate lines; leaking the embedded gate lines and interconnection areas, and depositing a transparent conductive film on the front and back of the silicon wafer after reverse masking, thereby forming transparent conductive lines on the embedded gate lines and interconnection areas; preparing a cell; and connecting the interconnection areas of two adjacent cells to form a cell string. There are no protruding metal gate lines on the outer surface of the cell, which ensures that there is no gate line blocking the front and back of the cell, increases the light receiving area, and maximizes the light receiving rate of the cell.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a crystalline silicon cell string with embedded gate lines, a cell string and a photovoltaic module. Background Art

[0002] At present, crystalline silicon cells are one of the most mature and common types of solar cells. Crystalline silicon cells include monocrystalline silicon cells and polycrystalline silicon cells. Crystalline silicon cells have the characteristics of high efficiency and long service life, and are currently widely used in the industrial field.

[0003] Traditional crystalline silicon cells need to print metal grid lines on the outer surface of the cell to collect current. The screen-printed metal grid lines will block the light-receiving surface of the cell, thereby affecting the light-receiving area of ​​the cell. In addition, in the process of preparing the cell string, the cell sheets also need to be connected through the metal grid lines, and the preparation process is complicated. Summary of the invention

[0004] The present invention provides a method for preparing a crystalline silicon battery string with embedded gate lines, a battery string and a photovoltaic module, which can reduce the influence of the gate lines on the light receiving rate of the battery, increase the light receiving area of ​​the battery, and simplify the preparation process.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] An embodiment of the present invention provides a method for preparing a crystalline silicon battery string with embedded gate lines, which comprises:

[0007] preparing silicon wafers;

[0008] Performing reverse mask processing on the front and back sides of the silicon wafer, thereby forming embedded gate lines and interconnection areas on the front and back sides of the silicon wafer, wherein the interconnection areas are connected to the embedded gate lines;

[0009] Leaking the embedded gate lines and interconnection areas, depositing a transparent conductive film on the front and back sides of the silicon wafer after reverse masking, thereby forming transparent conductive lines on the embedded gate lines and interconnection areas;

[0010] preparing battery cells;

[0011] The interconnection regions of two adjacent battery cells are connected to form a battery string.

[0012] Optionally, the step of performing reverse masking on the front and back sides of the silicon wafer to form embedded gate lines and interconnection regions on the front and back sides of the silicon wafer, wherein the interconnection regions are connected to the embedded gate lines, comprises:

[0013] The mask is provided with a pattern for forming a gate line and a pattern for forming an interconnection area, and the mask is covered on the front side of the silicon wafer for reverse masking, thereby forming an embedded gate line and an interconnection area on the front side of the silicon wafer; wherein the interconnection area is located at the edge of the silicon wafer;

[0014] A mask is covered on the back of the silicon wafer for reverse masking, thereby forming embedded gate lines and interconnection areas on the back of the silicon wafer; wherein the interconnection area is located at the edge of the silicon wafer, and the interconnection area on the back of the silicon wafer and the interconnection area on the front of the silicon wafer are located at opposite ends.

[0015] Optionally, the step of performing reverse masking on the front and back sides of the silicon wafer to form embedded gate lines and interconnection regions on the front and back sides of the silicon wafer, wherein the interconnection regions are connected to the embedded gate lines, further comprises:

[0016] The interconnection region is a strip-shaped structure, the length of the interconnection region is consistent with the length of the long side of the silicon wafer, and the width of the interconnection region is no more than 3 mm.

[0017] Optionally, the step of performing reverse mask processing on the front and back sides of the silicon wafer to form embedded gate lines and interconnection areas on the front and back sides of the silicon wafer includes:

[0018] Embedded gate lines with a width of 10 μm to 100 μm are formed on the front and back sides of the silicon wafer.

[0019] Optionally, the step of leaking the embedded gate lines and interconnection areas, depositing a transparent conductive film on the front and back sides of the silicon wafer after reverse masking, thereby forming transparent conductive lines on the embedded gate lines and interconnection areas comprises:

[0020] The mask is moved to reveal the position of the embedded gate line and the position of the interconnection area, and a transparent conductive film is deposited on the front and back of the silicon wafer respectively, thereby forming a transparent conductive line for collecting current.

[0021] Optionally, the step of moving the mask to expose the position of the embedded gate line and the position of the interconnection area, and depositing a transparent conductive film on the front and back sides of the silicon wafer to form a transparent conductive line for collecting current includes:

[0022] The transparent conductive wire is a mesh structure.

[0023] Optionally, the number of the battery cells is N, and the N battery cells are arranged in sequence along a straight line, and the step of connecting the interconnection regions of two adjacent battery cells to form a battery string includes:

[0024] The interconnection area on the back of the battery cell at the end is connected to the interconnection area on the front of the adjacent battery cell, and then the interconnection area on the back of the battery cell is connected to the interconnection area on the front of the next battery cell until the last battery cell is connected.

[0025] Optionally, the step of connecting the interconnection regions of two adjacent battery cells to form a battery string further includes:

[0026] In the interconnection area, transplanted solder balls are used as prefabricated interconnection media. When the front interconnection area and the back interconnection area of ​​two adjacent battery cells are connected, the solder balls are heated to the melting point, thereby realizing the connection between the two adjacent battery cells.

[0027] An embodiment of the present invention further provides a battery string, which is prepared by using the method for preparing a crystalline silicon battery string with embedded gate lines.

[0028] An embodiment of the present invention further provides a photovoltaic assembly, including a battery string.

[0029] The advantageous effects of the method for preparing a crystalline silicon cell string with embedded gate lines, the cell string and the photovoltaic module of the embodiments of the present invention include, for example:

[0030] The method for preparing an embedded gate line crystalline silicon cell string includes preparing a silicon wafer; performing reverse masking on the front and back of the silicon wafer, thereby forming an embedded gate line and an interconnection area on the front and back of the silicon wafer, wherein the interconnection area is connected to the embedded gate line; exposing the embedded gate line and the interconnection area, depositing a transparent conductive film on the front and back of the silicon wafer after the reverse masking, thereby forming a transparent conductive line on the embedded gate line and the interconnection area; preparing a cell; connecting the interconnection areas of two adjacent cells to form a cell string. When in use, reverse masking is performed on the front and back of the silicon wafer to form an embedded gate line and an interconnection area, and then a transparent conductive film is continuously deposited on the silicon wafer to finally prepare a cell, wherein there is no protruding metal gate line on the outer surface of the cell, thereby ensuring that there is no gate line blocking on the front and back of the cell, increasing the light receiving area, realizing double-sided power generation, and maximizing the light receiving rate of the cell; and adjacent cells are connected through the interconnection area to form a cell string, thereby simplifying the overall process and being more convenient to use.

[0031] The cell string is prepared using the method for preparing a crystalline silicon cell string with embedded gate lines. When in use, reverse masking is performed on the front and back of the silicon wafer to form embedded gate lines and interconnection areas, and then a transparent conductive film is deposited on the silicon wafer to finally prepare a cell. There are no protruding metal gate lines on the outer surface of the cell, ensuring that there are no gate line shielding on the front and back of the cell, increasing the light receiving area, and also achieving double-sided power generation, maximizing the light receiving rate of the cell; and adjacent cells are connected through the interconnection area to form a cell string, simplifying the overall process and making it more convenient to use.

[0032] The photovoltaic module comprises a battery string and has all the beneficial effects of the battery string. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the front structure of the battery cell provided in this embodiment;

[0035] Figure 2 A schematic diagram of the back structure of the battery cell provided in this embodiment;

[0036] Figure 3 This is a schematic diagram of the structure of the battery string provided in this embodiment.

[0037] Icon: 10-silicon wafer; 20-embedded gate line; 30-interconnection area; 100-battery cell. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0041] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0042] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0043] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0044] At present, crystalline silicon cells are one of the most mature and common types of solar cells. Crystalline silicon cells include monocrystalline silicon cells and polycrystalline silicon cells. Crystalline silicon cells have the characteristics of high efficiency and long service life, and are currently widely used in the industrial field.

[0045] Traditional crystalline silicon cells need to print metal grid lines on the outer surface of the cell to collect current. The screen-printed metal grid lines will block the light-receiving surface of the cell, thereby affecting the light-receiving area of ​​the cell. In addition, in the process of preparing the cell string, the cell sheets also need to be connected through the metal grid lines, and the preparation process is complicated.

[0046] Please refer to Figure 1-Figure 3 This embodiment provides a photovoltaic module, which includes a battery string, the battery string includes at least two battery cells 100, and the at least two battery cells 100 are connected. And the battery string is prepared by the method for preparing a crystalline silicon battery string with embedded gate lines. The photovoltaic module can effectively improve the above-mentioned technical problems, reduce the influence of the gate line on the light receiving rate of the battery, increase the light receiving area of ​​the battery, and simplify the preparation process.

[0047] Specifically, the battery cell 100 in this embodiment is a rectangular structure. There are four battery cells 100 , which are arranged in sequence along a straight line, and two adjacent battery cells 100 are connected.

[0048] In other embodiments, the structure of a battery string formed by sequentially connecting a plurality of battery cells 100 can be adjusted according to actual production conditions and is not specifically limited here.

[0049] In other embodiments, the number of battery cells 100 may be increased or decreased, which is not specifically limited herein.

[0050] The method for preparing a crystalline silicon battery string with embedded gate lines comprises:

[0051] S1: preparing a silicon wafer 10.

[0052] Specifically, a conventional silicon wafer 10 after cleaning and texturing is selected. The silicon wafer 10 is a rectangular structure.

[0053] S2: performing reverse mask processing on the front and back sides of the silicon wafer 10 , thereby forming embedded gate lines 20 and interconnection regions 30 on the front and back sides of the silicon wafer 10 , wherein the interconnection regions 30 are connected to the embedded gate lines 20 .

[0054] Specifically, a pattern for forming a gate line and a pattern for forming an interconnection area 30 are provided on the mask. The mask is covered on the front side of the silicon wafer 10 for reverse masking, thereby forming an embedded gate line 20 and an interconnection area 30 on the front side of the silicon wafer 10; wherein the interconnection area 30 is located at the edge of the silicon wafer 10; the mask is covered on the back side of the silicon wafer 10 for reverse masking, thereby forming an embedded gate line 20 and an interconnection area 30 on the back side of the silicon wafer 10; wherein the interconnection area 30 is located at the edge of the silicon wafer 10, and the interconnection area 30 on the back side of the silicon wafer 10 and the interconnection area 30 on the front side of the silicon wafer 10 are located at opposite ends.

[0055] by Figure 1 and Figure 2 For example, Figure 1 The front structural diagram of the silicon wafer 10 is shown. Figure 2 The back side structure diagram of the silicon wafer 10 is shown. Figure 1 In the embodiment, the interconnection region 30 is located at the lower edge of the front side of the silicon wafer 10. Figure 2 In the embodiment, the interconnection region 30 is located at the upper edge of the back side of the silicon wafer 10, and the interconnection region 30 on the front side of the silicon wafer 10 and the interconnection region 30 on the back side of the silicon wafer 10 are respectively arranged at opposite ends.

[0056] Specifically, there are a plurality of embedded gate lines 20 , and the plurality of embedded gate lines 20 are arranged in a matrix structure on the front and back sides of the silicon wafer 10 .

[0057] In this embodiment, the interconnection region 30 is a strip structure, the length of the interconnection region 30 is consistent with the length of the long side of the silicon wafer 10, and the width of the interconnection region 30 is not greater than 3 mm. The width of the interconnection region 30 is 3 mm. In other embodiments, the width of the interconnection region 30 can also be 1 mm, 2 mm, or 2.6 mm, etc., which is not specifically limited here.

[0058] It is understandable that the shape of the interconnection area 30 can be changed by re-customizing the screen according to the needs of the component image, so as to facilitate the connection of battery strings of various shapes. Specifically, the interconnection area 30 can also be circular, etc., which is not specifically limited here.

[0059] Furthermore, the location of the interconnection region 30 on the battery cell 100 can be adjusted according to actual conditions, and is not specifically limited here.

[0060] Embedded gate lines 20 with a width of 10 μm to 100 μm are formed on the front and back sides of the silicon wafer 10. Specifically, the width of the embedded gate line 20 is 10 μm. In other embodiments, the width of the embedded gate line 20 can also be 30 μm, 40 μm, 100 μm, etc., which is not specifically limited here.

[0061] S3 : exposing the embedded gate line 20 and the interconnection region 30 , and depositing a transparent conductive film on the front and back sides of the silicon wafer 10 after the reverse masking process, so as to form transparent conductive lines on the embedded gate line 20 and the interconnection region 30 .

[0062] Specifically, the mask is moved to expose the position of the embedded gate line 20 and the position of the interconnection area 30, and transparent conductive films are deposited on the front and back sides of the silicon wafer 10, respectively, so as to form transparent conductive lines for collecting current.

[0063] In this embodiment, the transparent conductive wire is a mesh structure.

[0064] More often, the transparent conductive film is made of materials including but not limited to ITO, AZO, graphene or silver nanowires.

[0065] S4: preparing the battery cell 100 .

[0066] Specifically, the silicon wafer 10 on which the transparent conductive film is deposited is subjected to a mask removal process, and then the interconnection regions 30 on the front and back sides of the silicon wafer 10 are subjected to a mask process, so as to completely cover the interconnection regions 30 .

[0067] Then, a-Si film, a-Si:H (P-type) film, SiN film and so on are sequentially deposited on the front side of the silicon wafer 10. x SiO film is deposited on the back of the silicon wafer 10 2 Thin film, a-Si:H (N-type) thin film, SiN x film, thereby forming the battery cell 100.

[0068] It should be noted that there are no metal grid lines on the front and back surfaces of the prepared battery cell 100. The grid lines are embedded and an interconnection area 30 is prepared at the edge of the battery cell 100. The interconnection area 30 is connected to the embedded grid lines 20. Two adjacent battery cells 100 are connected through the interconnection area 30. The front and back surfaces of the battery cell 100 are no longer blocked by the metal grid lines, which increases the light-receiving area of ​​the battery cell 100 and ensures that the light-receiving rate of the battery is maximized.

[0069] S5: connecting the interconnection regions 30 of two adjacent battery cells 100 to form a battery string.

[0070] Specifically, the number of battery cells 100 is N, and the N battery cells 100 are arranged in sequence along a straight line. The interconnection area 30 on the back of the battery cell 100 located at the end is connected to the interconnection area 30 on the front of the adjacent battery cell 100, and then the interconnection area 30 on the back of the battery cell 100 is connected to the interconnection area 30 on the front of the next battery cell 100 until it is connected to the last battery cell 100.

[0071] In this embodiment, transplanted solder balls are used as prefabricated interconnection media in the interconnection area 30 , and when the front interconnection area 30 and the back interconnection area 30 of two adjacent battery cells 100 are connected, the solder balls are heated to the melting point, thereby achieving the connection between the two adjacent battery cells 100 .

[0072] Furthermore, when two adjacent battery strings are connected, the interconnection area 30 on the front side of the silicon wafer 10 at the end position is connected to the interconnection area 30 on the back side of the silicon wafer 10 at the end position of the adjacent battery string, thereby realizing the connection of the battery strings.

[0073] Specifically, the battery strings are connected with bus bars and finally prepared into photovoltaic modules.

[0074] In summary, the embodiments of the present invention provide a method for preparing an embedded gate line crystalline silicon cell string, a cell string and a photovoltaic module, the method for preparing an embedded gate line crystalline silicon cell string includes preparing a silicon wafer 10; performing reverse masking on the front and back sides of the silicon wafer 10, thereby forming embedded gate lines 20 and interconnection areas 30 on the front and back sides of the silicon wafer 10, and the interconnection areas 30 are connected to the embedded gate lines 20; leaking the embedded gate lines 20 and the interconnection areas 30, and depositing a transparent conductive film on the front and back sides of the silicon wafer 10 after the reverse masking, thereby forming transparent conductive lines on the embedded gate lines 20 and the interconnection areas 30; preparing a cell 100; connecting the interconnection areas 30 of two adjacent cell 100, thereby forming a cell string. When in use, reverse masking is performed on the front and back sides of the silicon wafer 10 to form embedded grid lines 20 and interconnection areas 30, and then a transparent conductive film is deposited on the silicon wafer 10 to finally prepare a cell 100. There are no protruding metal grid lines on the outer surface of the cell 100, ensuring that there are no grid line obstructions on the front and back sides of the cell 100, thereby increasing the light receiving area, realizing double-sided power generation, and maximizing the light receiving rate of the cell 100; and adjacent cells 100 are connected through the interconnection area 30 to form a cell string, which simplifies the overall process and is more convenient to use.

[0075] The cell string is prepared by using the method for preparing an embedded gate line crystalline silicon cell string. When in use, reverse masking is performed on the front and back of the silicon wafer 10 to form an embedded gate line 20 and an interconnection area 30, and then a transparent conductive film is deposited on the silicon wafer 10 to finally prepare a cell 100. There is no protruding metal grid line on the outer surface of the cell 100, ensuring that there is no grid line blocking on the front and back of the cell 100, increasing the light receiving area, and realizing double-sided power generation, and maximizing the light receiving rate of the cell 100; and adjacent cells 100 are connected through the interconnection area 30 to form a cell string, simplifying the overall process and making it more convenient to use.

[0076] The photovoltaic module comprises a battery string and has all the beneficial effects of the battery string.

[0077] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for preparing a crystalline silicon battery string with embedded gate lines, characterized in that: include: preparing a silicon wafer (10); Performing reverse mask processing on the front and back sides of the silicon wafer (10), thereby forming embedded gate lines (20) and interconnection regions (30) on the front and back sides of the silicon wafer (10), wherein the interconnection regions (30) are connected to the embedded gate lines (20); Leaking the embedded gate lines (20) and the interconnection area (30), depositing a transparent conductive film on the front and back sides of the silicon wafer (10) after the reverse masking process, thereby forming transparent conductive lines on the embedded gate lines (20) and the interconnection area (30); Preparing a battery cell (100); The interconnection regions (30) of two adjacent battery cells (100) are connected to form a battery string.

2. The method for preparing a crystalline silicon battery string with embedded gate lines according to claim 1, characterized in that: The step of performing reverse mask processing on the front and back sides of the silicon wafer (10) to form embedded gate lines (20) and interconnection regions (30) on the front and back sides of the silicon wafer (10), wherein the interconnection regions (30) are connected to the embedded gate lines (20) comprises: A pattern for forming a gate line and a pattern for forming an interconnection region (30) are provided on the mask, and the mask is covered on the front side of the silicon wafer (10) for reverse masking, thereby forming an embedded gate line (20) and an interconnection region (30) on the front side of the silicon wafer (10); wherein the interconnection region (30) is located at an edge of the silicon wafer (10); A mask is covered on the back side of a silicon wafer (10) to perform reverse mask processing, thereby forming an embedded gate line (20) and an interconnection region (30) on the back side of the silicon wafer (10); wherein the interconnection region (30) is located at an edge position of the silicon wafer (10), and the interconnection region (30) on the back side of the silicon wafer (10) and the interconnection region (30) on the front side of the silicon wafer (10) are located at opposite ends.

3. The method for preparing a crystalline silicon battery string with embedded gate lines according to claim 2, characterized in that: The step of performing reverse mask processing on the front and back sides of the silicon wafer (10) to form embedded gate lines (20) and interconnection regions (30) on the front and back sides of the silicon wafer (10), wherein the interconnection regions (30) are connected to the embedded gate lines (20) further comprises: The interconnection region (30) is a strip-shaped structure, the length of the interconnection region (30) is consistent with the length of the long side of the silicon wafer (10), and the width of the interconnection region (30) is no greater than 3 mm.

4. The method for preparing a crystalline silicon battery string with embedded gate lines according to claim 2, characterized in that: The step of performing reverse mask processing on the front and back sides of the silicon wafer (10) to form embedded gate lines (20) and interconnection areas (30) on the front and back sides of the silicon wafer (10) comprises: Embedded gate lines (20) with a width of 10 μm to 100 μm are formed on the front and back sides of the silicon wafer (10).

5. The method for preparing a crystalline silicon battery string with embedded gate lines according to claim 1, characterized in that: The steps of leaking the embedded gate lines (20) and the interconnection area (30), depositing a transparent conductive film on the front and back sides of the silicon wafer (10) after reverse mask processing, thereby forming transparent conductive lines on the embedded gate lines (20) and the interconnection area (30) include: The mask is moved to expose the position of the embedded gate line (20) and the position of the interconnection area (30), and transparent conductive films are deposited on the front and back sides of the silicon wafer (10), respectively, thereby forming transparent conductive lines for collecting current.

6. The method for preparing a crystalline silicon battery string with embedded gate lines according to claim 5, characterized in that: The moving mask exposes the position of the embedded gate line (20) and the position of the interconnection area (30), and a transparent conductive film is deposited on the front and back sides of the silicon wafer (10) to form a transparent conductive line for collecting current, comprising the following steps: The transparent conductive wire is a mesh structure.

7. The method for preparing a crystalline silicon battery string with embedded gate lines according to claim 1, characterized in that: The number of the battery cells (100) is N, and the N battery cells (100) are arranged in sequence along a straight line. The step of connecting the interconnection regions (30) of two adjacent battery cells (100) to form a battery string comprises: The interconnection region (30) on the back side of the battery cell (100) at the end is connected to the interconnection region (30) on the front side of the adjacent battery cell (100), and then the interconnection region (30) on the back side of the battery cell (100) is connected to the interconnection region (30) on the front side of the next battery cell (100), until the last battery cell (100) is connected.

8. The method for preparing a crystalline silicon battery string with embedded gate lines according to claim 1, characterized in that: The step of connecting the interconnection regions (30) of two adjacent battery cells (100) to form a battery string further comprises: In the interconnection region (30), transplanted solder balls are used as prefabricated interconnection media, and when the front interconnection regions (30) and the back interconnection regions (30) of two adjacent battery cells (100) are connected, the solder balls are heated to a melting point, thereby achieving connection between the two adjacent battery cells (100).

9. A battery string, characterized in that: The method for preparing a crystalline silicon battery string with embedded gate lines as described in any one of claims 1 to 8 is used for preparing the battery string.

10. A photovoltaic module, characterized in that: Comprising the battery string as claimed in claim 9.

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