Passivation contact cell with selective polysilicon layer and preparation method and application thereof

Abstract

The present invention discloses a passivated contact cell with a selective polysilicon layer and a preparation method thereof. In the present invention, each laser scanning line on the back of the TOPCon solar cell is separated by a phosphorus-heavy doped polysilicon layer in the middle, there is no overlap of the laser scanning path, and a partial phosphorus-doped polysilicon layer structure in the area around the main grid is retained. Such a structural method helps to reduce the transmission distance of carriers in the laser ablation area, and the carriers can be collected more quickly by the fine grid, thereby improving the fill factor FF of the cell, especially under special conditions such as broken grid. In the present invention, the laser grooving area is set to 40% to 80% of the total area of ​​the back of the cell, which is conducive to balancing the passivation performance of the cell while reducing the parasitic absorption of light by polysilicon. The passivated contact cell of the present invention has a higher short-circuit current, open-circuit voltage and fill factor.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a passivation contact cell with a selective polycrystalline silicon layer and a preparation method and application thereof. Background Art

[0002] The emergence of tunnel oxide passivated contact solar cells TOPCon has attracted great attention to high-efficiency crystalline silicon solar cell technology. TOPCon cells use N-type silicon as the substrate material, and are composed of an ultra-thin silicon oxide layer and a highly doped polysilicon layer. Since the tunneling potential of the tunnel oxide layer (4.5eV) is higher than the tunneling potential of electrons (3.1eV), this can reduce the carrier recombination between the metal electrode and silicon, so electrons are more likely to tunnel and be collected; another function of the tunnel oxide layer is full-area passivation, and the excellent passivation ability further improves the efficiency of TOPCon solar cells. At present, the photoelectric conversion efficiency record of TOPCon cells has exceeded 26.5%.

[0003] Selective polysilicon passivation contacts are ideal for reducing parasitic absorption of N-type crystalline silicon solar cells and providing better current collection. TOPCon cells use a passivation contact structure of tunneling oxide layer and doped polysilicon layer. Since the doped polysilicon layer itself has serious parasitic absorption, this tunneling layer and passivation layer structure is only used on the back surface of the TOPCon cell. The current industrialized tunneling oxide layer thickness is 1-2nm, and the thickness of the doped polysilicon layer is 100-150nm. In order to further reduce the negative impact of the parasitic absorption of the doped polysilicon layer itself on the electrical performance of the cell, a processing technology that can form a selectively doped polysilicon layer is usually used. Among them, the most important is to ablate the phosphorus-doped polysilicon in the non-metallized area by laser. The laser patterning scheme is usually parallel to the fine grid line. Because the main grid slurry does not burn through the passivation film, the main grid laser avoidance position is not considered. Compared with the conventional battery structure, the short-circuit current density (Jsc) of this type of battery is increased by about 0.5mA / cm 2 .

[0004] However, this type of laser graphic solution usually adopts a method of partially overlapping the laser spot path, resulting in an area where two laser paths overlap. This part has undergone two laser scans, causing greater damage to the battery silicon substrate than a single laser scan, and the battery Voc electrical performance will be reduced.

[0005] Secondly, the existing laser patterning solution avoids the position of the fine grid lines on the back of the battery and then performs laser processing. The laser area accounts for 90% to 95% of the back surface area of ​​the battery. This solution can maximize the reduction of the parasitic absorption of light by polysilicon and increase the current density Jsc of the battery, but it will destroy the TOPCon characteristic passivation structure of the battery, resulting in a decrease in the passivation performance of the laser area, which is not conducive to the Voc of the battery.

[0006] Finally, the laser patterning scheme of the prior art usually adopts uninterrupted scanning parallel to the fine grid. The heavily doped polysilicon layer in the laser scanning area is removed. The conductive properties of the heavily doped polysilicon layer are similar to those of metals, and the transmission resistance of carriers on it can be ignored. After the heavily doped polysilicon layer is removed, the resistance of carrier transmission in this area will increase rapidly. In addition, in the prior art, because the main grid slurry does not have the property of burning through SiNx, it will not directly contact the silicon substrate or phosphorus-doped polysilicon. When designing the laser pattern structure, whether the main grid part is avoided is ignored. Such a structural scheme causes the transmission distance of carriers in the laser scanning area to be longer, and the resistance loss is larger, which will cause the fill factor FF of the solar cell to decrease. Summary of the invention

[0007] In view of the shortcomings and deficiencies of the prior art, the present invention provides an improved method for preparing a passivated contact cell with a selective polysilicon layer. The cell obtained by the preparation method reduces the parasitic absorption of light by polysilicon while balancing the passivation performance of the cell. The cell has an improved open circuit voltage, fill factor, and a higher short-circuit current.

[0008] Another object of the present invention is to provide a passivated contact cell with a selective polysilicon layer, which cell has an improved open circuit voltage, fill factor, and a higher short circuit current.

[0009] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0010] A method for preparing a passivated contact cell, the method comprising the following steps: providing a silicon wafer body, growing a tunneling oxide layer and a doped polysilicon layer on the back surface of the silicon wafer body; using a laser to ablate a first area on the back surface of the silicon wafer body, so that the tunneling oxide layer and the doped polysilicon layer in the first area are removed to form an opening area; the laser is continuously scanned to form a plurality of spaced-apart laser path lines, and there is no overlapping part between the plurality of laser path lines; forming a back passivation layer on the entire area of ​​the back surface of the silicon wafer body; printing and sintering a back main gate electrode and a back fine gate electrode on the back surface of the silicon wafer body; the area where the back main gate electrode is located is located outside the first area;

[0011] In the back fine gate electrode region, the back surface of the silicon wafer body has a first tunneling oxide layer, a first doped polysilicon layer and a first back passivation layer in sequence;

[0012] There are at least two opening areas between two adjacent back fine gate electrodes, and each two adjacent opening areas are separated by a gap of a laser path line to form a carrier transport area;

[0013] The opening area includes a second back passivation layer formed on the back side of the silicon wafer body;

[0014] The carrier transport region includes a second tunneling oxide layer, a second doped polysilicon layer and a third back passivation layer sequentially formed on the back side of the silicon wafer body;

[0015] The area where the back main gate electrode is located includes a third tunneling oxide layer, a third doped polysilicon layer, a fourth back passivation layer and a back main gate electrode which are sequentially formed on the back side of the silicon wafer body.

[0016] In some embodiments, the laser is a rectangular spot or a square spot, and the rectangular spot or the square spot is continuously scanned to form the laser path line.

[0017] In some embodiments, the rectangular light spot or the square light spot has a length of 100-500 µm and a width of 100-500 µm.

[0018] In some embodiments, the laser has a wavelength of 200 to 1200 nm and is at least one of a picosecond laser and a nanosecond laser.

[0019] In some embodiments, the laser is selected from a 355 nm ultraviolet laser, a 532 nm green laser, a 650 nm red laser, an 820 nm near-infrared laser, or a 1030 nm infrared laser.

[0020] In some embodiments, the frequency of the laser is 50-300 KHz.

[0021] In some embodiments, the scanning speed of the laser is 5 to 25 m / s.

[0022] In some embodiments, the energy density of the laser is 0.1 to 5 J / cm 2 .

[0023] In some embodiments, the line spacing of the laser path lines is 200-600 μm. The spacing between the laser scanning path line and the path line center, referred to as the line spacing, is greater than the length of a single spot, so there is no overlap between the laser path lines.

[0024] In some embodiments, when the ablation process is performed using a laser, the laser does not ablate the area corresponding to the back main gate electrode, and the width of the area is 100~500μm.

[0025] In some embodiments, the preparation method further includes the steps of sequentially forming a boron-doped emitter, a front surface passivation layer, and printing and sintering a front surface metal electrode on the front surface of the silicon wafer body.

[0026] In some embodiments, the preparation method includes the following steps: (1) providing an N-type silicon wafer, and performing texturing on the front side of the N-type silicon wafer to form a texturing surface, and polishing and cleaning the back side to form a flat surface; (2) performing boron diffusion treatment on the N-type silicon wafer, and forming boron-doped emitters on the front and back surfaces of the N-type silicon wafer respectively; (3) removing the emitter on the back surface of the N-type silicon wafer, and polishing the back surface; (4) growing a tunneling oxide layer and a doped polysilicon layer on the back surface; (5) using a laser to perform a process on the back surface of the silicon wafer body; ablation treatment is performed on a first area of ​​the surface to remove the tunnel oxide layer and the doped polysilicon layer in the first area to form an opening area; the laser is a plurality of spaced laser path lines, and there is no overlapping part between the plurality of laser path lines; (6) a front passivation layer is deposited on the front surface, and a back passivation layer is deposited on the back surface; (7) a front surface metal electrode is printed and sintered on the front surface of the N-type silicon wafer, and the back main gate electrode and the back fine gate electrode are printed and sintered on the back surface; the area where the back main gate electrode is located is outside the first area.

[0027] The present invention further provides a passivated contact battery prepared by the above-mentioned passivated contact battery preparation method.

[0028] Furthermore, in the back fine gate electrode region, the back surface of the silicon wafer body has a first tunneling oxide layer, a first doped polysilicon layer and a first back passivation layer in sequence; there are at least two opening regions between two adjacent back fine gate electrodes, and each two adjacent opening regions are separated by the carrier transport region;

[0029] The opening area includes a second back passivation layer formed on the back side of the silicon wafer body;

[0030] The carrier transport region includes a second tunneling oxide layer, a second doped polysilicon layer and a third back passivation layer sequentially formed on the back side of the silicon wafer body;

[0031] The area where the back main gate electrode is located includes a third tunneling oxide layer, a third doped polysilicon layer, a fourth back passivation layer and a back main gate electrode which are sequentially formed on the back side of the silicon wafer body.

[0032] In some embodiments, the cross-section of the open area is selected from a rectangle, a square, a trapezoid or a diamond.

[0033] In some embodiments, the width of each of the opening areas is 100-500 μm.

[0034] In some embodiments, between two adjacent back fine gate electrodes, the spacing between each two adjacent opening regions is equal. The spacing refers to the line spacing, that is, the spacing between the centers of the two opening regions.

[0035] In some embodiments, between two adjacent back fine gate electrodes, the spacing between two adjacent opening areas is 200-600 μm.

[0036] In some embodiments, based on the total area of ​​the back surface of the silicon wafer body excluding the back main gate electrode and the back fine gate electrode, the total area of ​​the opening area accounts for 40% to 80% thereof.

[0037] In some embodiments, the cross-section of the carrier transport region is selected from a rectangle, a square, a trapezoid or a rhombus.

[0038] In some embodiments, in each carrier transport region, the second tunneling oxide layer and the second doped polysilicon layer have the same width.

[0039] In some embodiments, the first tunnel oxide layer, the second tunnel oxide layer, and the third tunnel oxide layer have the same thickness.

[0040] In some embodiments, the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer have the same thickness.

[0041] In some embodiments, the first back passivation layer, the second back passivation layer, the third back passivation layer, and the fourth back passivation layer have the same thickness.

[0042] In some embodiments, the doped polysilicon layer is a phosphorus-doped polysilicon layer.

[0043] Preferably, the doping concentration of phosphorus atoms in phosphorus-doped polysilicon is 3.0×10 20 ~8.0×10 20 / cm 3 , the square resistance is 40~100Ω / sq.

[0044] In some embodiments, the line width of the back main gate electrode is 30-100 μm, and the interval is 10-20 mm.

[0045] In some embodiments, the line width of the back fine gate electrode is 10 to 60 µm, and the interval is 0.9 to 1.5 mm.

[0046] In some embodiments, the back main gate electrode and the back fine gate electrode are perpendicular to each other.

[0047] In some embodiments, the silicon wafer body is an N-type single crystal silicon substrate.

[0048] In some embodiments, the resistivity of the silicon wafer body is 0.8-1.5 Ω•cm, and the thickness is 100-180 μm.

[0049] In some embodiments, the tunnel oxide layer is SiO x layer, and the thickness is 0.5~2.5nm, preferably 1.0~1.5nm.

[0050] In some embodiments, the front surface of the silicon wafer body is velvet-like, and the front structural layer includes a boron-doped emitter formed on the front surface of the silicon wafer body and a front surface passivation layer.

[0051] In some embodiments, the front surface passivation layer is a combination of two or three of aluminum oxide, silicon nitride, silicon oxynitride, silicon dioxide, and magnesium fluoride. Preferably, the front surface passivation layer adopts a passivation stacking design of aluminum oxide + silicon carbide, wherein the preferred thickness of aluminum oxide is 2 to 10 nm, the preferred thickness of silicon nitride is 20 to 50 nm, and the refractive index of silicon nitride is 2.1 to 2.2.

[0052] In some embodiments, the back surface passivation layer is a stacked film consisting of two of aluminum oxide, titanium dioxide, silicon nitride, and silicon oxynitride.

[0053] In some embodiments, the back surface passivation layer is an aluminum oxide / silicon nitride laminate film, wherein the aluminum oxide has a thickness of 15 to 30 nm, and the silicon nitride has a refractive index of 2.1 to 2.2 and a thickness of 50 to 65 nm. The aforementioned passivated contact cell of the present invention can be used in a photovoltaic module. A photovoltaic module generally includes a front encapsulation layer, a photovoltaic cell, and a back encapsulation layer. Among them, the photovoltaic cell includes the aforementioned passivated contact cell.

[0054] The present invention also provides a photovoltaic module, which includes the above-mentioned passivated contact cell.

[0055] Compared with the prior art, the present invention has the following advantages:

[0056] The preparation method of the present invention forms a selective polysilicon passivation contact structure on the back of the TOPCon solar cell. In this method, each laser path is separated (the laser opening area is separated by the carrier transmission area), and there is no overlapping area of ​​the laser paths. In this way, there is no secondary laser damage to the silicon substrate, and the open circuit voltage Voc of the obtained battery will be improved to a certain extent.

[0057] The passivation contact cell with a selective polysilicon layer of the present invention balances the passivation performance of the cell while reducing the parasitic absorption of light by polysilicon, and the cell has an improved open circuit voltage and fill factor. In addition, the cell structure of the present invention helps to reduce the transmission distance of carriers in the laser ablation area, and the carriers can be collected more quickly by the fine grid, thereby improving the fill factor FF of the cell, especially under special conditions such as broken grid, which has great advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 This is a schematic diagram of the structure of an N-type silicon wafer after being processed in step (1) in a specific embodiment of the present invention;

[0059] Figure 2 This is a schematic diagram of the structure of an N-type silicon wafer after being processed in step (2) in a specific embodiment of the present invention;

[0060] Figure 3 This is a schematic diagram of the structure of an N-type silicon wafer after being processed in step (3) in a specific embodiment of the present invention;

[0061] Figure 4 This is a schematic diagram of the structure of an N-type silicon wafer after being processed in step (4) in a specific embodiment of the present invention;

[0062] Figure 5 It is a schematic diagram of the structure of the N-type silicon wafer after being processed in step (5) in the prior art solution;

[0063] Figure 6 This is a schematic diagram of the structure of an N-type silicon wafer after being processed in step (5) in a specific embodiment of the present invention;

[0064] Figure 7 This is a schematic diagram of the structure of an N-type silicon wafer after being processed in step (6) in a specific embodiment of the present invention;

[0065] Figure 8 A top view of the back surface of a battery in a specific embodiment of the present invention;

[0066] Fig. 9 for Figure 8 AA cross-section of the middle cell;

[0067] Fig.10 for Figure 8 Middle cell BB cross-section;

[0068] Fig.11 This is a schematic diagram of the processing area of ​​a traditional battery;

[0069] Fig.12 Schematic diagram of the cross-sectional structure of a traditional battery;

[0070] Fig.13 It is a schematic diagram of the laser processing method of the prior art;

[0071] Fig.14 for Fig.13 AA cross-section of the middle cell;

[0072] Fig.15 for Fig.13 Middle cell BB cross-section;

[0073] Fig.16 It is an image after laser ablation processing on a silicon wafer in the prior art;

[0074] Wherein: 1-silicon wafer body, 2-boron-doped emitter, 3-tunneling oxide layer, 31-first tunneling oxide layer, 32-second tunneling oxide layer, 33-third tunneling oxide layer, 4-doped polysilicon layer, 41-first doped polysilicon layer, 42-second doped polysilicon layer, 43-third doped polysilicon layer, 5-opening area, 6-secondary opening area, 71-front surface passivation layer, 72-back passivation layer, 721-first back passivation layer, 722-second back passivation layer, 723-third back passivation layer, 724-fourth back passivation layer, 81-front fine gate electrode, 82-back fine gate electrode, 9-back main gate electrode. DETAILED DESCRIPTION

[0075] In the prior art, when preparing a passivation contact cell with a selective polysilicon layer, a processing technology that can form a selectively doped polysilicon layer is usually used. However, first of all, this type of laser patterning solution usually adopts a method of partially overlapping the laser spot path (in order to fully etch, so as to avoid that some areas are not etched), resulting in an area where two laser paths overlap. This part has undergone two laser scans, which brings greater damage to the silicon substrate of the battery than a single laser scan, and the battery Voc electrical performance will be reduced. Secondly, the existing laser patterning solution uses laser processing after avoiding the position of the fine grid lines on the back of the battery. The laser area accounts for 90% to 95% of the back surface area of ​​the battery. Such a solution can maximize the reduction of the parasitic absorption of light by polysilicon and increase the current density Jsc of the battery, but it will destroy the TOPCon characteristic passivation structure of the battery, resulting in a decrease in the passivation performance of the laser area, which is not conducive to the Voc of the battery. Finally, the laser patterning scheme of the prior art usually adopts uninterrupted scanning parallel to the fine grid. The heavily doped polysilicon layer in the laser scanning area is removed. The conductive properties of the heavily doped polysilicon layer are similar to those of metals, and the transmission resistance of carriers on it can be ignored. After the heavily doped polysilicon layer is removed, the resistance of carrier transmission in this area will increase rapidly. In addition, in the prior art, because the main grid slurry does not have the property of burning through SiNx, it will not directly contact the silicon substrate or phosphorus-doped polysilicon. When designing the laser pattern structure, whether the main grid part is avoided is ignored. Such a structural scheme causes the transmission distance of carriers in the laser scanning area to be longer, and the resistance loss is larger, which will cause the fill factor FF of the solar cell to decrease.

[0076] The main idea of ​​the present invention is that: the present invention adopts a new laser patterning scheme to form a new type of selective polysilicon passivation contact structure on the back of the TOPCon solar cell. In this scheme, each laser path is separated (the laser opening area is separated by the carrier transmission area), and there is no overlapping area of ​​the laser paths. In this way, there is no damage to the silicon substrate by the secondary laser, and the open circuit voltage Voc will be improved to a certain extent.

[0077] Secondly, in the design of the laser grooving pattern of this scheme, the laser grooving area is set to 40% to 80% of the total area of ​​the back of the battery, which is beneficial to balance the passivation performance of the battery while reducing the parasitic absorption of light by polysilicon.

[0078] Finally, in the present invention, each laser scanning line on the back of the Topcon solar cell is separated by a phosphorus heavily doped polysilicon layer in the middle, there is no overlap of the laser scanning path, and the partial phosphorus doped polysilicon layer structure in the area around the main grid is retained. This structural method helps to reduce the transmission distance of carriers in the laser ablation area, and the carriers can be collected by the fine grid more quickly. In the conventional solution, the ablation width formed by the overlap of multiple laser lines is W2, and the carriers in the central area need to transmit a distance of 1 / 2*W2 to reach the doped polysilicon layer (see Fig.13 ), in the present invention, the ablation width formed by the laser scanning line is W1, and the carriers in the central area need to transmit a distance of 1 / 2*W1 to reach the doped polysilicon layer (see Figure 8 ), and then transmitted to the fine gate line through the partially phosphorus heavily doped polysilicon layer in the area around the main gate. The heavily doped polysilicon layer has a conductive property similar to that of a metal, and the transmission resistance of carriers on it can be ignored. After the heavily doped polysilicon layer is removed, the resistance of carrier transmission in this area will increase rapidly. The width of W1 is much smaller than the width of W2. This solution can significantly reduce the transmission distance of carriers in the high-resistance area scanned by the laser, reduce the transmission loss of carriers, and help carriers to be collected by the fine gate more quickly, thereby improving the fill factor FF of the battery. Especially under special conditions such as broken gates, the solution of the present invention is more advantageous.

[0079] After the phosphorus expansion process, a specially designed laser grooving scheme is used on the back of the battery structure in the present invention to form a selective polysilicon passivation contact structure on the back surface of the solar cell; the laser pattern used in the present invention is parallel to the fine grid, the laser line spacing is greater than the width of a single spot, there is no overlapping part, and at the same time a part of the area near the main grid is avoided, and 40% to 80% of the entire back surface area of ​​the battery is laser processed. This polysilicon selective structure: ① There is no overlapping part of the laser, which avoids the damage of the secondary laser to the silicon substrate, which is beneficial to improving the passivation performance of the solar cell and improving the open circuit voltage Voc; ② The laser grooving area of ​​40% to 80% maintains a balance between reducing the parasitic absorption of light by polysilicon and the passivation performance of the battery; ③ The middle is separated by a phosphorus-heavy doped polysilicon layer, there is no overlap of the laser scanning line, and the partial phosphorus-doped polysilicon layer structure in the area around the main gate is retained. Such a structural method helps to reduce the transmission distance of carriers in the laser ablation area, and the carriers can be collected by the fine gate more quickly. In addition, the conductive properties of the heavily doped polysilicon layer are similar to those of metals, and the transmission resistance of carriers on it can be ignored. After the heavily doped polysilicon layer is removed, the resistance of carrier transmission in this area increases rapidly. Therefore, this solution can significantly reduce the transmission distance of carriers in the high resistance area of ​​laser scanning, reduce the transmission loss of carriers, help carriers to be collected by the fine gate more quickly, and improve the filling factor FF of the battery. Especially under special conditions such as broken gates, the solution of the present invention is more advantageous.

[0080] In the description of the present invention, it should be understood that the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third" and "fourth" may explicitly or implicitly include at least one of the features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0081] Based on this, the present invention provides a polycrystalline silicon passivated contact cell and a preparation method thereof.

[0082] Specifically, the following Figures 1 to 15 The method for preparing a polycrystalline silicon passivated contact cell of the present invention is further introduced. The method for preparing a polycrystalline silicon passivated contact cell comprises:

[0083] (1) Wet clean the N-type single crystal silicon wafer to remove the damaged layer on the surface of the silicon wafer, clean the metal impurities and oil on the surface and make a velvet surface. At a reaction temperature of 70±10℃, use a 10% volume fraction of sodium hydroxide solution to corrode the damaged layer on the surface of the silicon wafer caused by wire cutting. The etching thickness on both sides is about 10µm. Then, a wet chemical process of alkaline solution + velvet additive is used to produce a random pyramid surface texture, and a standard RCA wet cleaning is performed. The height of the random pyramid is about 0.5~2µm. See the schematic diagram of the structure after treatment. Figure 1 As shown, a pyramid-shaped velvet structure is obtained on both sides of the N-type silicon wafer.

[0084] (2) Perform double-sided boron diffusion on the N-type silicon wafer to form an emitter. The boron source used for the diffusion is boron tribromide or boron trichloride, and the peak temperature of the diffusion is 1000~1100℃. The square resistance of the bump-doped emitter 2 obtained after the boron diffusion is 100~250Ω / sq. See the schematic diagram of the structure after processing. Figure 2 As shown, a boron-doped emitter 2 is formed on both the front and back surfaces of the N-type silicon wafer.

[0085] (3) Wet polishing of the back surface. Use a 3% to 10% HF solution to remove the BSG layer on the back and edge of the silicon wafer after boron diffusion. Then use a wet additive + KOH / NaOH + water solution (the mass ratio of the three is 1:5:90) to polish the back surface of the silicon wafer. The reaction temperature is 60±10℃. The schematic diagram of the structure after treatment is shown in Figure 3 As shown, only the boron-doped emitter 2 on the front side is retained on the N-type silicon wafer.

[0086] (4) A tunneling oxide layer and an intrinsic amorphous silicon layer grow on the back surface of the battery; phosphorus diffuses to form a phosphorus-doped polysilicon structure. Low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) is used to make silane (SiH4) react and deposit an ultra-thin tunneling oxide layer and polysilicon layer on the back surface of the silicon wafer under low-pressure conditions. The structural material of the ultra-thin tunneling oxide layer is SiO2, the deposition reaction temperature is 400-600℃, the thickness is selected to be 0.5nm~2.5nm, the deposition reaction temperature of intrinsic amorphous silicon is 500-650℃, and the thickness is selected to be 60~200nm; in the process of phosphorus diffusion, under the condition of oxygen, phosphorus oxychloride (POCl3) decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5), and the generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms (P), and the phosphorus atoms enter the intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer. The structure formed is as follows Figure 4 As shown, a boron-doped emitter 2 is provided on the front surface of the N-type silicon wafer, and a tunneling oxide layer 3 and a phosphorus-doped polysilicon layer 4 are formed on the back surface of the N-type silicon wafer.

[0087] (5) Laser ablation to form a selective polysilicon layer. In the non-metallized area, the laser patterning scheme specially designed by the present invention is used to ablate the non-metallized area. The laser spot is a rectangular or square spot with a length of 100µm~500µm, a width of 100µm~500µm, and a line spacing of 200µm~600µm. There is no overlapping part between the spot lines. The main grid part also reserves a width of 100µm~500µm without laser treatment. In terms of laser, an ultraviolet picosecond or nanosecond laser with a wavelength of 200~600nm is used, preferably a 355nm purple laser or a 532nm green laser. The laser frequency is 50~300KHz, the laser scanning speed is 5~25m / s, and the energy density of the laser treatment is 0.1~5J / cm 2 Among them, the solutions of the prior art are as follows Figure 5 As shown, 5 is the laser opening area (first time), 6 is the secondary laser opening area, and the corresponding image after laser ablation on the silicon wafer is as follows Fig.16 As shown in FIG. 6 , it can be seen that the overlapping laser scanning at 6 locations will damage the silicon wafer body 1. Figure 6 As shown, the shaded portion 5 is the laser opening region. Since the two laser opening regions 5 are separated by the carrier transport region, the laser scanning will not overlap.

[0088] (6) Deposition of passivation anti-reflection film on the front and back surfaces. The passivation anti-reflection film on the front and back surfaces adopts a laminated film design, which is a combination of two materials such as aluminum oxide, silicon nitride, silicon dioxide, and silicon oxynitride. As a preferred method, a passivation anti-reflection film laminated design of aluminum oxide + silicon carbide is adopted, wherein the preferred thickness of aluminum oxide is 2 to 10 nm, the preferred thickness of silicon nitride is 20 to 50 nm, and the refractive index of silicon nitride is 2.1 to 2.2. The schematic diagram of the sample structure formed in this step is shown in the figure. Figure 7 shown.

[0089] (7) Printing and sintering of metal electrodes on the front and back surfaces. Print metallization patterns on the front and back surfaces (printing is done by screen printing or laser transfer, etc.). The metal grid lines can be made of silver paste, silver aluminum paste or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the metal fine grid lines on the front and back sides is 10-60µm, the height is 5-10µm, the fine grid spacing is 0.9-1.5mm, and the number is 150-250. The main grid line width is 30-100µm, the height is 2-8µm, the main grid spacing is 10-20mm, the number is 10-20, and the sintering temperature is 700-850℃; or use laser-assisted enhanced sintering process to enhance contact and reduce contact resistivity. The structural schematic diagram of the final battery is as follows: Figure 8-10 As shown. Among them, Figure 8 is a top view of the back surface of the battery. Fig. 9 for Figure 8 AA cross-section of the middle cell (perpendicular to the fine gate electrode and avoiding the main gate electrode part), Fig.10 for Figure 8 Cross-sectional view of the middle cell BB (a cross-sectional view passing through the main gate electrode and perpendicular to the main gate electrode).

[0090] The battery comprises a silicon wafer body 1 having a back surface and a back metal electrode, wherein the back metal electrode comprises a back main grid electrode 9 and a back fine grid electrode 82;

[0091] In the region of the back fine gate electrode 82, the back surface of the silicon wafer body 1 has a first tunneling oxide layer 31, a first doped polysilicon layer 41 and a first back passivation layer 721 in sequence;

[0092] Between two adjacent back fine gate electrodes 82, the opening region 5 has at least two (although Fig. 9 2 are shown in the figure, but the present invention is not limited to 2, and may be 3 or more opening areas 5), and each two adjacent opening areas 5 are separated by the interval of the laser path line to form a carrier transport area;

[0093] The opening area 5 includes a second back passivation layer 722 formed on the back side of the silicon wafer body 1;

[0094] The carrier transport region includes a second tunneling oxide layer 32, a second doped polysilicon layer 42 and a third back passivation layer 723 sequentially formed on the back side of the silicon wafer body;

[0095] The area where the back main gate electrode 9 is located includes a third tunneling oxide layer 33 , a third doped polysilicon layer 43 , and a fourth back passivation layer 724 which are sequentially formed on the back side of the silicon wafer body.

[0096] The processing area and cross-sectional structure of traditional batteries are as follows: Fig.11 , 12 As shown; the laser processing method of the prior art and the selective polysilicon cell structure formed are respectively as shown Figures 13-15 As shown (where Fig.14 for Fig.13 AA cross-section of the middle cell, Fig.15 for Fig.13 (BB cross-section of the middle cell).

[0097] By comparing three different laser patterning schemes and battery structures, the present invention has the following advantages: ① There is no overlapping part of the laser, which avoids the damage of the silicon substrate caused by the secondary laser (see Fig.15 As shown), it is beneficial to improve the passivation performance of solar cells and increase the open circuit voltage Voc; ②40% to 80% of the laser grooving area maintains a balance between reducing the parasitic absorption of light by polysilicon and the passivation performance of the battery; ③ Between parallel adjacent laser paths, the middle is separated by a phosphorus-heavy doped polysilicon layer, there is no overlap of laser scanning lines, and a portion of the phosphorus-doped polysilicon layer structure in the area around the main gate is retained. Such a structural method helps to reduce the transmission distance of carriers in the laser ablation area, and the carriers can be collected by the fine gate more quickly. In addition, the conductive properties of the heavily doped polysilicon layer are similar to those of metals, and the transmission resistance of carriers on it can be ignored. After the heavily doped polysilicon layer is removed, the resistance of carrier transmission in this area will increase rapidly. Therefore, the present invention can significantly reduce the transmission distance of carriers in the high resistance area of ​​laser scanning, reduce the transmission loss of carriers, help carriers to be collected by the fine gate more quickly, and improve the filling factor FF of the battery. Especially under special conditions such as broken gates, the scheme of the present invention is more advantageous.

[0098] The above scheme is further described below in conjunction with specific embodiments; it should be understood that these embodiments are used to illustrate the basic principles, main features and advantages of the present invention, and the present invention is not limited to the scope of the following embodiments; the implementation conditions adopted in the embodiments can be further adjusted according to specific requirements, and the implementation conditions not specified are usually the conditions in conventional experiments.

[0099] Unless otherwise specified in the following examples, all raw materials are commercially available or prepared by conventional methods in the art.

[0100] The embodiment is a polysilicon layer passivation structure formed by the laser patterning scheme designed by the present invention. Comparative Example 1 is a traditional TOPCon cell without a selective polysilicon structure on the back; Comparative Example 2 is a cell structure of an existing laser processing scheme, with partial overlap of the spot lines. Embodiment 1:

[0101] The above-mentioned specific preparation method is adopted, and the parameters are designed: the light spot adopts a square light spot of 250×250µm, and the solution of avoiding main grid line + laser path separation is adopted. The path line spacing is 300µm, and the laser path is scanned 3 times at each grid line interval. 300µm is reserved on one side of the main grid line without laser processing, the fine grid interval is 1000µm, the main grid interval is 10.8mm, and the laser opening area accounts for 70.8%. Embodiment 2:

[0102] The above-mentioned specific preparation method is adopted, and the parameters are designed: the light spot adopts a square light spot of 250×250µm, and the solution of avoiding main grid line + laser path separation is adopted. The path line spacing is 300µm, and the laser path is scanned twice for each grid line interval. 300µm is reserved on one side of the main grid line without laser processing, the fine grid interval is 1000µm, the main grid interval is 10.8mm, and the laser opening area accounts for 47.2%.

[0103] Comparative Example 1:

[0104] Basically the same as Example 1, but without the laser ablation step (5).

[0105] Comparative Example 2:

[0106] Basically the same as Example 1, but the parameters are designed as follows: the light spot adopts a square spot of 250×250µm, and the scheme of not avoiding the main grid line + laser path superposition is adopted. The line spacing of the laser path line is 220µm, and the laser path is scanned 4 times at each grid line interval. The overlapping width between the laser path lines is 30µm, the fine grid interval is 1000µm, the main grid interval is 10.8mm, and the laser opening area accounts for 91%.

[0107] Comparative Example 3:

[0108] It is basically the same as Example 1, but the parameters are designed as follows: the light spot uses a square spot of 708×708µm, the main grid lines are not avoided, the laser path is scanned only once between the fine grid lines, 300µm is reserved on one side of the main grid line without laser processing, the fine grid spacing is 1000µm, the main grid spacing is 10.8mm, and the laser opening area accounts for 70.8%, which is the same as Example 1.

[0109] Performance Testing:

[0110] The batteries obtained in the above-mentioned embodiments and comparative examples were subjected to the following performance tests, and the testing method was: using an IV tester to test the battery photoelectric conversion efficiency and related electrical performance parameters under standard light power under a simulated solar light source.

[0111] The specific test results are shown in Table 1 (Eta; conversion efficiency, Voc: open circuit voltage, Jsc: short circuit current density, FF: fill factor). The electrical performance data is the average value of 100Pcs batteries.

[0112]

[0113] It can be seen that compared with Comparative Example 1, the conversion efficiency and short-circuit current density of the battery in Example 1 are significantly improved (although the difference is small, in the field of solar cells, a change of 0.1% in conversion efficiency, such as improvement, is usually a huge improvement); compared with Comparative Example 2, the conversion efficiency of the battery in Example 1 is improved, and the open circuit voltage is also significantly improved; compared with Comparative Example 3, the conversion efficiency of the battery in Example 1 is improved, and the fill factor is also improved. The battery in Example 1 has excellent comprehensive performance.

[0114] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

[0115] The endpoints and any values ​​of the ranges disclosed in this article are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article.

Claims

1. A method for preparing a passivated contact battery, characterized in that: The preparation method comprises the following steps: providing a silicon wafer body, growing a tunneling oxide layer and a doped polysilicon layer on the back surface of the silicon wafer body; using a laser to ablate a first area on the back surface of the silicon wafer body, so that the tunneling oxide layer and the doped polysilicon layer in the first area are removed to form an opening area; the laser is continuously scanned to form a plurality of spaced laser path lines, and there is no overlapping part between the plurality of laser path lines; forming a back passivation layer on the entire area of ​​the back surface of the silicon wafer body; printing and sintering a back main gate electrode and a back fine gate electrode on the back surface of the silicon wafer body; the area where the back main gate electrode is located is located outside the first area; In the back fine gate electrode region, the back surface of the silicon wafer body has a first tunneling oxide layer, a first doped polysilicon layer and a first back passivation layer in sequence; There are at least two opening areas between two adjacent back fine gate electrodes, and each two adjacent opening areas are separated by a gap of a laser path line to form a carrier transport area; The opening area includes a second back passivation layer formed on the back side of the silicon wafer body; The carrier transport region includes a second tunneling oxide layer, a second doped polysilicon layer and a third back passivation layer sequentially formed on the back side of the silicon wafer body; The area where the back main gate electrode is located includes a third tunneling oxide layer, a third doped polysilicon layer, a fourth back passivation layer and a back main gate electrode which are sequentially formed on the back side of the silicon wafer body.

2. The method for preparing a passivated contact battery according to claim 1, characterized in that: The laser is a rectangular spot or a square spot, and the rectangular spot or the square spot is continuously scanned to form the laser path line.

3. The method for preparing a passivated contact battery according to claim 2, characterized in that: The rectangular light spot or the square light spot has a length of 100-500 μm and a width of 100-500 μm.

4. The method for preparing a passivated contact cell according to claim 2, characterized in that: The wavelength of the laser is 200-1200 nm, and the laser is at least one of a picosecond laser and a nanosecond laser.

5. The method for preparing a passivated contact cell according to claim 4, characterized in that: The laser is selected from 355nm ultraviolet laser, 532nm green laser, 650nm red laser, 820nm near-infrared laser or 1030nm infrared laser.

6. The method for preparing a passivated contact battery according to claim 1, characterized in that: The frequency of the laser is 50-300 KHz; and / or the scanning speed of the laser is 5-25 m / s; and / or the energy density of the laser is 0.1-5 J / cm 2 .

7. The method for preparing a passivated contact cell according to claim 1, characterized in that: The line spacing of the laser path lines is 200~600μm.

8. The method for preparing a passivated contact battery according to claim 1, characterized in that: When the laser is used for the ablation process, the laser does not ablate the area corresponding to the back main gate electrode, and the width of the area is 100~500μm.

9. The method for preparing a passivated contact battery according to claim 1, characterized in that: The preparation method also includes the steps of sequentially forming a boron-doped emitter and a front surface passivation layer on the front surface of the silicon wafer body, and printing and sintering a front surface metal electrode.

10. A passivated contact battery prepared by the method for preparing a passivated contact battery according to any one of claims 1 to 9, characterized in that: In the back fine gate electrode region, the back surface of the silicon wafer body has a first tunneling oxide layer, a first doped polysilicon layer and a first back passivation layer in sequence; There are at least two opening regions between two adjacent back fine gate electrodes, and each two adjacent opening regions are separated by the carrier transport region; The opening area includes a second back passivation layer formed on the back side of the silicon wafer body; The carrier transport region includes a second tunneling oxide layer, a second doped polysilicon layer and a third back passivation layer sequentially formed on the back side of the silicon wafer body; The area where the back main gate electrode is located includes a third tunneling oxide layer, a third doped polysilicon layer, a fourth back passivation layer and a back main gate electrode which are sequentially formed on the back side of the silicon wafer body.

11. The passivated contact cell according to claim 10, characterized in that: The cross-section of the opening region is selected from at least one of a rectangle, a square, a trapezoid or a rhombus; and / or the cross-section of the carrier transport region is selected from at least one of a rectangle, a square, a trapezoid or a rhombus.

12. The passivated contact cell according to claim 11, characterized in that: The width of each opening area is 100-500 μm.

13. The passivated contact cell according to claim 10, characterized in that: Between two adjacent back fine gate electrodes, the spacing between each two adjacent opening areas is equal.

14. The passivated contact cell according to claim 13, characterized in that: Between two adjacent back fine gate electrodes, the spacing between two adjacent opening areas is 200~600µm.

15. The passivated contact cell according to claim 10, characterized in that: Taking the total area of ​​the back surface of the silicon wafer body excluding the back main gate electrode and the back fine gate electrode as a reference, the total area of ​​the opening area accounts for 40% to 80% of it.

16. The passivated contact cell according to claim 10, characterized in that: In each carrier transport region, the second tunneling oxide layer and the second doped polysilicon layer have the same width.

17. The passivated contact cell according to claim 10, characterized in that: The first tunneling oxide layer, the second tunneling oxide layer, and the third tunneling oxide layer have the same thickness; and / or, the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer have the same thickness; and / or, the first back passivation layer, the second back passivation layer, the third back passivation layer, and the fourth back passivation layer have the same thickness.

18. The passivated contact cell according to claim 10, characterized in that: The doped polysilicon layer is a phosphorus-doped polysilicon layer.

19. The passivated contact cell according to claim 10, characterized in that: The line width of the back main gate electrode is 30-100µm, and the interval is 10-20mm; and / or, the line width of the back fine gate electrode is 10-60µm, and the interval is 0.9-1.5mm; and / or, the back main gate electrode and the back fine gate electrode are perpendicular to each other.

20. A photovoltaic module, characterized in that: The photovoltaic module comprises the passivated contact cell according to any one of claims 10-19.

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