A method for manufacturing a micro-nanopillar structure

Abstract

The application discloses a kind of micro-nanopillar structure production methods, it is related to LED technical field, including the following steps: after CaN wafer and target substrate are washed, buffer layer, N-CaN layer, MQWS layer, P-GaN layer on CaN wafer are integrally stripped from sapphire substrate, then P-GaN layer is welded on target substrate, again buffer layer is etched and removed, SiO2 buffer layer is deposited on N-CaN layer first, then metal mask layer is deposited, finally, first, second and third etching are carried out, to form micro-nanopillar structure;By stripping buffer layer on target wafer, N-CaN layer is exposed, then deposition and etching are carried out on N-CaN, N-CaN layer has significantly fewer defects compared to buffer layer, so N-CaN layer is used as processing layer, can avoid etching out sharp cone type or pyramid structure, and micro-nanopillar structure can be obtained.

Description

Technical Field

[0001] This invention relates to the field of LED technology, and specifically to a method for fabricating a micro / nano columnar structure. Background Technology

[0002] In LED devices, GaN is a commonly used material for wafers. Although GaN is widely used due to its excellent properties, the lack of single-crystal substrates means that most common GaN-based optoelectronic devices and high-frequency microwave devices are currently fabricated using heteroepitaxial growth on mature substrates such as sapphire single crystals and silicon carbide single crystals. Significant lattice and thermal mismatches exist between the substrate material and the epitaxially grown device, particularly due to the difference in thermal expansion coefficients. This results in substantial residual stress in devices grown at high temperatures. Furthermore, due to the mismatch, the lattice of the device epitaxially grown on the heterogeneous substrate easily generates dislocations to match the substrate lattice, which extend with growth, resulting in a high dislocation density in the device. Since dislocations in crystals act as non-radiative recombination centers and have the ability to trap charge carriers, the performance of devices epitaxially grown on heterogeneous substrates is significantly limited.

[0003] The presence of defects offers an advantage for some products requiring surface roughening. In LED devices, the epitaxial layers of a wafer can be simplified to a substrate, a buffer layer (U-CaN layer), an N-CaN layer, a quantum well layer, and a P-CaN layer. When growing U-GaN epitaxially on sapphire, defects are unavoidable in the early stages of growth due to lattice constant mismatch and edge effects during crystal nucleation. Material doping also introduces new point defects. As the epitaxial thickness increases, new epitaxial layers continue to grow on the U-GaN material, thus reducing defects. For pure GaN epitaxial wafers, the thickness exceeds 5µm, and the top layer achieves a near-perfect crystal structure. Therefore, for traditional LED epitaxial wafers, the top P-CaN layer already has relatively few defects. Thus, during dry etching, by adjusting the etching parameters, a columnar structure with low sidewall roughness can be etched anisotropically.

[0004] However, in order to increase the light-emitting area and improve electrical performance, some high-power or non-traditional LEDs are flip-chip. The U-CaN layer is first peeled off from the substrate to expose the undoped U-CaN layer, and then the P-CaN layer is rebonded to the new substrate. The U-CaN layer is a buffer layer for epitaxial growth, so it has a lot more defects. Therefore, whether wet or dry etching is performed, the structural shape will inevitably change due to the presence of defects, resulting in only the etching of conical or pyramidal structures, and it is difficult to obtain columnar structures. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating micro / nano columnar structures, thereby solving the following technical problems:

[0006] How to fabricate micro / nano pillar structures on a target wafer?

[0007] The objective of this invention can be achieved through the following technical solutions:

[0008] A method for fabricating micro / nano pillar structures includes the following steps:

[0009] S1: Clean the CaN wafer and the target substrate. The CaN wafer includes a sapphire substrate, a buffer layer, an N-CaN layer, an MQWS layer, and a P-GaN layer stacked sequentially from bottom to top. After cleaning, the buffer layer, N-CaN layer, MQWS layer, and P-GaN layer on the CaN wafer are integrally peeled off from the sapphire substrate. Then, the P-GaN layer in the peeled part is bonded to the target substrate by eutectic bonding to obtain the target wafer.

[0010] S2: The buffer layer on the target wafer is removed by inductively coupled plasma etching to expose the N-CaN layer.

[0011] S3: First deposit a SiO2 buffer layer on the N-CaN layer, and then deposit a metal mask layer on the SiO2 buffer layer;

[0012] S4: The first and second etching processes are performed sequentially on the deposited metal mask layer using reactive ion etching equipment, followed by a third etching process using inductively coupled plasma etching equipment. The first etching process removes the metal mask layer, exposing the SiO2 buffer layer. The second etching process removes the SiO2 buffer layer exposed by the first etching process, exposing the target wafer. The third etching process occurs on the target wafer exposed by the second etching process, forming a micro-nano pillar structure.

[0013] In a further embodiment of the present invention: in step S3, the deposition thickness of the SiO2 buffer layer is 620-640 nm;

[0014] Preferably, the SiO2 buffer layer has a deposition thickness of 630 nm.

[0015] In a further embodiment of the invention: the SiO2 buffer layer is deposited by plasma-enhanced chemical vapor deposition.

[0016] In a further embodiment of the present invention: in step S3, the deposition thickness of the metal mask layer is 160-180 nm;

[0017] Preferably, the deposition thickness of the metal mask layer is 170 nm.

[0018] In a further embodiment of the present invention: the metal material of the metal mask layer is one of aluminum, gold, silver, platinum, copper, chromium, titanium, and nickel.

[0019] In a further embodiment of the present invention: in step S4, the parameters for the first etching are: time 20-40 min; pressure 2-10 mtor r; power 340-440 W; and the gas composition is a combination of two or more of CHF3, SF6, CF4, and O2.

[0020] Preferably, the parameters for the first etching are: time 30 min; pressure 6 mtor r; power 400 W; and gas composition of CHF3 and SF6.

[0021] In a further embodiment of the present invention: in step S4, the parameters for the second etching are: time 15-20 min; pressure 2-100 mtor r; power 120-150 W; and the gas composition is a combination of two or more of CHF3, SF6, CF4, and O2.

[0022] Preferably, the parameters for the second etching are: time 18 min; pressure 50 mtorr; power 130 W; and gas composition of CHF3 and SF6.

[0023] In a further embodiment of the present invention: in step S4, the parameters for the third etching are: time 4-12 min; pressure 2-40 mtor r; ion concentration power 200-800 W; bias power supply 2-140 W; and the gas composition is a combination of two or more of Cl2, BCl2, Ar, and O2.

[0024] Preferably, the parameters for the third etching are: time 8 min; pressure 20 mtorr; ion concentration power 500 W; bias power supply 80 W; and gas composition of a combination of Cl2 and BCl2.

[0025] In a further embodiment of the present invention: in step S1, the target substrate is a silicon carbide plate, a silicon plate, or a glass plate;

[0026] Preferably, the target substrate is a silicon substrate.

[0027] The beneficial effects of this invention are:

[0028] In the fabrication method of the micro / nano pillar structure of the present invention, the buffer layer, N-CaN layer, MQWS layer and P-GaN layer on the CaN wafer are integrally peeled off from the sapphire substrate. Then, the P-GaN layer in the peeled part is bonded to the target substrate by eutectic bonding to obtain the target wafer. By peeling off the buffer layer on the target wafer, the N-CaN layer is exposed. Then, deposition and etching are performed on the N-CaN. The N-CaN layer has significantly fewer defects than the buffer layer. Therefore, by using the N-CaN layer as the processing layer, it is possible to avoid etching out the cone-shaped or pyramid-shaped structure and obtain the micro / nano pillar structure. Attached Figure Description

[0029] The invention will now be further described with reference to the accompanying drawings.

[0030] Figure 1 This is a flowchart of the method for fabricating the micro / nano columnar structure in this invention;

[0031] Figure 2 This is a top view of the column structure obtained in Example 1 of this invention;

[0032] Figure 3 This is a side view of the column structure obtained in Example 1 of this invention;

[0033] Figure 4 This is a top view of the column structure obtained in Example 2 of this invention;

[0034] Figure 5 This is a side view of the column structure obtained in Example 2 of this invention;

[0035] Figure 6 This is a top view of the column structure obtained in Example 3 of this invention;

[0036] Figure 7 This is a side view of the column structure obtained in Example 3 of this invention;

[0037] Figure 8 This is a top view of the column structure obtained in Comparative Example 1 of this invention.

[0038] Figure 9 This is a side view of the column structure obtained in Comparative Example 1 of this invention;

[0039] Figure 10 This is a side cross-sectional view of the column structure obtained in Comparative Example 1 of this invention. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Please see Figure 1 This invention discloses a method for fabricating micro / nano pillar structures, comprising the following steps:

[0042] Step 1: Clean the CaN wafer and the target substrate. The CaN wafer includes a sapphire substrate, a buffer layer, an N-CaN layer, an MQWS layer, and a P-GaN layer stacked sequentially from bottom to top. After cleaning, the buffer layer, N-CaN layer, MQWS layer, and P-GaN layer on the CaN wafer are integrally peeled off from the sapphire substrate. Then, the P-GaN layer in the peeled part is bonded to the target substrate by eutectic bonding to obtain the target wafer.

[0043] Step 2: Remove the buffer layer on the target wafer by inductively coupled plasma etching to expose the N-CaN layer;

[0044] Step 3: First, deposit a SiO2 buffer layer with a thickness of 620-640nm on the N-CaN layer using plasma-enhanced chemical vapor deposition. Then, deposit a metal mask layer with a thickness of 160-180nm on the SiO2 buffer layer using any one of the following metal materials: aluminum, gold, silver, platinum, copper, chromium, titanium, and nickel.

[0045] Step 4: Perform the first etching on the deposited metal mask layer using reactive ion etching (RIE) for 20-40 min; pressure 2-10 mtorr; power 340-440 W; gas composition of two or more of CHF3, SF6, CF4, and O2. Then perform the second etching for 15-20 min; pressure 2-100 mtorr; power 120-150 W; gas composition of two or more of CHF3, SF6, CF4, and O2. Finally, perform the third etching using inductively coupled plasma (ICP-COP) for 4-12 min; pressure 2-40 mtorr; ion concentration power 200-800 W; bias power 2-140 W; gas composition of two or more of Cl2, BCl2, Ar, and O2. The first etching removes the metal mask layer, exposing the SiO2 buffer layer; the second etching removes the Si exposed in the first etching. An O2 buffer layer is applied to expose the target wafer; a third etching is then applied to the target wafer exposed by the second etching, forming a micro-nano pillar structure.

[0046] Next, micro-nano pillar structures are fabricated using the fabrication method of the present invention, as detailed in Examples 1-3 below.

[0047] Example 1

[0048] Step 1: Clean the CaN wafer and silicon substrate. After cleaning, peel off the buffer layer, N-CaN layer, MQWS layer and P-GaN layer on the CaN wafer as a whole from the sapphire substrate. Then, the P-GaN layer in the peeled part is bonded to the silicon substrate by eutectic bonding to obtain the target wafer.

[0049] Step 2: Remove the buffer layer on the target wafer by inductively coupled plasma etching to expose the N-CaN layer;

[0050] Step 3: First, a SiO2 buffer layer with a thickness of 630 nm is deposited on the N-CaN layer using plasma-enhanced chemical vapor deposition. Then, a metal mask layer with a thickness of 170 nm is deposited on the SiO2 buffer layer using aluminum metal material.

[0051] Step 4: The deposited metal mask layer is etched sequentially using a reactive ion etching (RIE) apparatus for the first etching at a time of 30 min, a pressure of 6 mtorr, a power of 400 W, and a gas composition of CHF3 and SF6. A second etching is then performed at a time of 18 min, a pressure of 50 mtorr, a power of 130 W, and a gas composition of CHF3 and SF6. Finally, an inductively coupled plasma (ICP) etching apparatus is used for the third etching at a time of 8 min, a pressure of 20 mtorr, an ion concentration of 500 W, a bias power of 80 W, and a gas composition of Cl2 and BCl2, resulting in micro / nano structures.

[0052] The obtained micro- and nanostructures were analyzed to obtain results such as... Figure 4-5 The morphology diagram shown indicates that the obtained micro-nano structure is a micro-nano columnar structure.

[0053] Example 2

[0054] Step 1: Clean the CaN wafer and silicon substrate. After cleaning, peel off the buffer layer, N-CaN layer, MQWS layer and P-GaN layer on the CaN wafer as a whole from the sapphire substrate. Then, the P-GaN layer in the peeled part is bonded to the silicon substrate by eutectic bonding to obtain the target wafer.

[0055] Step 2: Remove the buffer layer on the target wafer by inductively coupled plasma etching to expose the N-CaN layer;

[0056] Step 3: First, a SiO2 buffer layer with a thickness of 620 nm is deposited on the N-CaN layer using plasma-enhanced chemical vapor deposition. Then, a metal mask layer with a thickness of 160 nm is deposited on the SiO2 buffer layer using aluminum metal.

[0057] Step 4: The deposited metal mask layer is etched sequentially using a reactive ion etching (RIE) apparatus for the first etching at a time of 20 min, a pressure of 10 mtorr, a power of 340 W, and a gas composition of CHF3 and SF6. A second etching is then performed at a time of 15 min, a pressure of 100 mtorr, a power of 120 W, and a gas composition of CHF3 and SF6. Finally, an inductively coupled plasma (ICP) etching apparatus is used for the third etching at a time of 4 min, a pressure of 40 mtorr, an ion concentration of 200 W, a bias power of 2 W, and a gas composition of Cl2 and BCl2, resulting in micro / nano structures.

[0058] The obtained micro- and nanostructures were analyzed to obtain results such as... Figure 2-3 The morphology diagram shown indicates that the obtained micro-nano structure is a micro-nano columnar structure.

[0059] Example 3

[0060] Step 1: Clean the CaN wafer and silicon substrate. After cleaning, peel off the buffer layer, N-CaN layer, MQWS layer and P-GaN layer on the CaN wafer as a whole from the sapphire substrate. Then, the P-GaN layer in the peeled part is bonded to the silicon substrate by eutectic bonding to obtain the target wafer.

[0061] Step 2: Remove the buffer layer on the target wafer by inductively coupled plasma etching to expose the N-CaN layer;

[0062] Step 3: First, a SiO2 buffer layer with a thickness of 640 nm is deposited on the N-CaN layer using plasma-enhanced chemical vapor deposition. Then, a metal mask layer with a thickness of 180 nm is deposited on the SiO2 buffer layer using aluminum metal.

[0063] Step 4: The deposited metal mask layer is etched sequentially using a reactive ion etching (RIE) apparatus for the first etching at a time of 40 min, a pressure of 2 mtorr, a power of 440 W, and a gas composition of CHF3 and SF6. A second etching is then performed at a time of 20 min, a pressure of 2 mtorr, a power of 150 W, and a gas composition of CHF3 and SF6. Finally, an inductively coupled plasma (ICP) etching apparatus is used for the third etching at a time of 12 min, a pressure of 2 mtorr, an ion concentration of 800 W, a bias power of 140 W, and a gas composition of Cl2 and BCl2, resulting in micro / nano structures.

[0064] The obtained micro- and nanostructures were analyzed to obtain results such as... Figure 6-7 The morphology diagram shown indicates that the obtained micro-nano structure is a micro-nano columnar structure.

[0065] Comparative Example 1

[0066] Step 1: It is exactly the same as Step 1 in Example 1.

[0067] Step 2: First, a SiO2 buffer layer with a thickness of 630nm is deposited on the buffer layer of the target wafer using plasma-enhanced chemical vapor deposition technology. Then, a metal mask layer with a thickness of 170nm is deposited on the SiO2 buffer layer using aluminum metal material.

[0068] Step 3: This is exactly the same as Step 4 in Example 1.

[0069] The obtained micro- and nanostructures were analyzed to obtain results such as... Figure 8-10 The morphology diagram shown indicates that the obtained micro-nano structure is a micro-nano cone structure.

[0070] pass Figure 2-10Analysis of the micro-nano structures prepared in Examples 1-3 and Comparative Example 1 reveals that the micro-nano structures prepared in Examples 1-3 are all columnar structures, while the micro-nano structures prepared in Comparative Example 1 are cone-shaped structures. This indicates that removing the buffer layer to expose the N-CaN layer during flip-chip fabrication can remove the defective parts, allowing the etching to fall on the N-CaN layer with fewer defects, thereby producing micro-nano columnar structures.

[0071] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the claims of this invention should still fall within the patent coverage of this invention.

Claims

1. A method for fabricating a micro / nano columnar structure, characterized in that, Includes the following steps: S1: Clean the CaN wafer and the target substrate. The CaN wafer includes a sapphire substrate, a buffer layer, an N-CaN layer, an MQWS layer, and a P-GaN layer stacked sequentially from bottom to top. After cleaning, the buffer layer, N-CaN layer, MQWS layer, and P-GaN layer on the CaN wafer are integrally peeled off from the sapphire substrate. Then, the P-GaN layer in the peeled part is bonded to the target substrate by eutectic bonding to obtain the target wafer. S2: The buffer layer on the target wafer is removed by inductively coupled plasma etching to expose the N-CaN layer. S3: First, deposit a SiO2 buffer layer on the N-CaN layer, and then deposit a metal mask layer on the SiO2 buffer layer; S4: The first and second etching processes are performed sequentially using reactive ion etching equipment on the deposited metal mask layer, followed by a third etching process using inductively coupled plasma etching equipment. The first etching process removes the metal mask layer, exposing the SiO2 buffer layer. The second etching process removes the SiO2 buffer layer exposed by the first etching process, exposing the target wafer. The third etching is applied to the target wafer exposed by the second etching, forming a micro-nano pillar structure.

2. The method for fabricating the micro / nano columnar structure according to claim 1, characterized in that, In step S3, the deposition thickness of the SiO2 buffer layer is 620-640 nm.

3. The method for fabricating the micro / nano pillar structure according to claim 2, characterized in that, The SiO2 buffer layer was deposited using plasma-enhanced chemical vapor deposition.

4. The method for fabricating the micro / nano pillar structure according to claim 1, characterized in that, In step S3, the deposition thickness of the metal mask layer is 160-180 nm.

5. The method for fabricating the micro / nano pillar structure according to claim 4, characterized in that, The metal material of the metal mask layer is one of aluminum, gold, silver, platinum, copper, chromium, titanium, and nickel.

6. The method for fabricating the micro / nano pillar structure according to claim 1, characterized in that, In step S4, the parameters for the first etching are: time 20-40 min; pressure 2-10 mtor r; power 340-440 W; and gas composition of two or more of CHF3, SF6, CF4, and O2.

7. The method for fabricating the micro / nano pillar structure according to claim 6, characterized in that, In step S4, the parameters for the second etching are: time 15-20 min; pressure 2-100 mtor r; power 120-150 W; and gas composition of two or more of CHF3, SF6, CF4, and O2.

8. The method for fabricating the micro / nano columnar structure according to claim 7, characterized in that, In step S4, the parameters for the third etching are: time 4-12 min; pressure 2-40 mtorr; ion concentration power 200-800 W; bias power supply 2-140 W; and gas composition consisting of two or more of Cl2, BCl2, Ar, and O2.

9. The method for fabricating the micro / nano columnar structure according to claim 1, characterized in that, In step S1, the target substrate is a silicon carbide plate, a silicon plate, or a glass plate.

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