Monitoring die-to-die connectivity with clock receiver

Abstract

An I / O sensor includes: a programmable delay line; a delayed sampling device having the following inputs: (a) a data signal also serving as an input to a reference clock receiver configured to sample the data signal received from an interconnect channel between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clock receiver; a comparison circuit configured to compare a data signal output of the delayed sampling device with a data signal output of the reference clock receiver; and a controller configured to estimate a connectivity quality between the two ICs on the interconnect channel based on a comparison result of the comparison circuit and an amount of delay resulting in the comparison result.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 18 / 089,541, filed on December 27, 2022, entitled “Monitoring Die-to-Die Connectivity with a Clock Receiver,” which claims priority to U.S. Provisional Patent Application No. 63 / 349,863, filed on June 7, 2022, entitled “Monitoring Die-to-Die Connectivity with a Clock Receiver,” and the contents of both patent applications are incorporated herein by reference. Background Art

[0003] Semiconductor integrated circuits (ICs) typically include analog and digital electronic circuits on a flat semiconductor substrate, such as a silicon wafer. Microscopic transistors are printed onto the substrate using photolithography techniques to produce complex circuits of billions of transistors in an extremely small area, making modern electronic circuit designs using ICs both low-cost and highly efficient. ICs are produced in assembly lines in factories, called foundries, which have commercialized the production of ICs such as complementary metal oxide semiconductor (CMOS) ICs.

[0004] Typically, ICs are mass-produced on a single wafer of electronic grade silicon (EGS) or other semiconductors such as GaAs. The wafer is cut (diced) into pieces, each containing a copy of the circuit. Each of these pieces is called a "die."

[0005] Digital ICs are typically packaged in metal, plastic, glass, or ceramic housings. The housing or "package" is connected to a circuit board, such as by using solder. Package types include lead frames (through-hole, surface mount, chip carrier, and / or the like), pin grid arrays, wafer-level packages, ball grid arrays, and / or the like to connect between the IC pads and the circuit board.

[0006] In fact, some modern ICs are modules composed of multiple interconnected ICs (sometimes called "chips" or "chiplets") configured to work together. A typical example is a logic IC interconnected with a memory IC, but there are many other types. There are also many die-to-die (i.e., IC-to-IC) connectivity technologies. One example is wafer-level integration characterized by high-density connectivity, which is based on redistribution layers (RDL) and integrated fan-out vias (TIVs), such as sold by Taiwan Semiconductor Manufacturing Co., Ltd. Another example is system-level integration, which is characterized by individual chips joined by micro-bumps on a silicon interposer, such as the Chip-on-Wafer-on-Substrate (CoWoS) technology sold by TSMC Corporation and the Embedded Interconnect Bridge (EMIB) technology sold by Intel Corporation. Both support high-bandwidth memory (HBM) subsystems. A third example is through silicon via (TSV) based three-dimensional (3D) wafer stacking technology, such as wafer-on-wafer (CoW) and wafer-on-wafer (WoW) technologies marketed by TSMC Corporation.

[0007] The foregoing examples of the related art and limitations associated therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those having ordinary knowledge in the art upon reading the specification and studying the drawings. Summary of the invention

[0008] The following specific examples and aspects thereof are described and illustrated in conjunction with systems, tools, and methods, which are intended to be illustrative and illustrative, but not limiting in scope.

[0009] One specific example is directed to an I / O sensor that includes: a programmable delay line; a delay sampling device having the following inputs: (a) a data signal that is also used as an input to a reference clock receiver that is configured to sample a data signal received from an interconnect channel between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal that is received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clock receiver; a comparison circuit that is configured to compare the data signal output of the delay sampling device with the data signal output of the reference clock receiver; and a controller that is configured to: (a) gradually adjust an amount of delay introduced by the programmable delay line, (b) receive a result of the comparison from the comparison circuit after each gradual adjustment of the delay, and (c) estimate a quality of connectivity between the two ICs on the interconnect channel based on at least one of the results and the amount of delay that caused the result.

[0010] In some specific examples, the programmable delay line includes a coarse delay line and a fine delay line connected in series; each delay step of the coarse delay line is longer than each delay step of the fine delay line; the length of each delay step of the coarse delay line is configured so that the rising edge of the delayed clock signal is close to the position where the result of the comparison may be reversed from "pass" to "fail" or from "fail" to "pass"; and the length of each delay step of the fine delay line is configured to detect the exact point where the result of the comparison may be reversed from "pass" to "fail" or from "fail" to "pass".

[0011] In some embodiments, the estimation of the connectivity quality includes calculation of eye diagram parameters of the data signal.

[0012] In some embodiments, the eye diagram parameters include an eye width calculated based on a time distance between inversion points of comparison results at a left side and a right side of a unit interval (UI) of the data signal.

[0013] In some embodiments, the controller is configured to operate the programmable delay line to scan the eye in one direction in order to detect a reversal point of the comparison result.

[0014] In some embodiments, the controller is configured to select between two eye scanning modes: a first eye scanning mode in which a first side of the eye is scanned by increasing or decreasing the amount of delay introduced by a programmable delay line; and a second eye scanning mode in which a second, opposite side of the eye is scanned by increasing or decreasing the amount of delay introduced by the programmable delay line.

[0015] In some specific examples, the clock signal that clocks the reference clock receiver is a multi-phase clock signal, and wherein: in a first eye scanning mode, one of the phases of the multi-phase clock signal experiences an increase or decrease in the amount of delay introduced by a programmable delay line; in a second eye scanning mode, a different one of the phases of the multi-phase clock signal experiences an increase or decrease in the amount of delay introduced by the programmable delay line; and in both the first and second eye scanning modes, a different one of the phases of the multi-phase clock signal is used to clock the reference clock receiver.

[0016] In some embodiments, the delayed sampling device is a clock receiver having a reference voltage as an additional input, which is also used as an input to the reference clock receiver. In some such embodiments, the reference voltage is a variable reference voltage; the eye diagram parameters further include eye height; and the controller is further configured to measure the eye height by gradually adjusting the variable reference voltage during each of the first and second eye scanning modes, thereby measuring the eye width at different voltage levels.

[0017] In some embodiments, the clock signal that clocks the reference clock receiver is a multi-phase clock signal; and the controller is further configured to detect duty cycle distortion of the multi-phase clock signal based on only one of the two eye scanning patterns.

[0018] In some embodiments, the clock signal for clocking the reference clock receiver has a multi-phase clock signal with a duty cycle of approximately 50%; and when calculating the eye width, the delayed clock signal received from the programmable delay line is only one phase of the multi-phase clock signal.

[0019] In some embodiments, the I / O sensor further includes a compensation delay element configured to apply a fixed amount of delay to the clock signal to compensate for an intrinsic delay of the programmable delay line.

[0020] In some embodiments, the I / O sensor further includes a compensation delay element configured to apply a fixed amount of delay to the data signal to compensate for an intrinsic delay of the programmable delay line.

[0021] In some embodiments, the I / O sensor further includes a compensation delay element configured to apply a fixed delay amount to at least one of the data signal and the clock signal to compensate for a distance between the reference clock receiver and the I / O sensor.

[0022] In some embodiments, the delayed sampling device is a flip-flop.

[0023] In some embodiments, the I / O sensor further includes a timing measurement circuit configured to measure the delay provided by the programmable delay line. In some embodiments, the timing measurement circuit includes a ring oscillator circuit selectively configured to include the programmable delay line.

[0024] Another specific example is directed to a method for estimating the quality of connectivity between two ICs interconnected by an interconnect channel, the method including operating the various elements of an I / O sensor as described above.

[0025] Another embodiment is directed to computer readable code of an I / O sensor that includes various elements of an I / O sensor as described above (or elsewhere herein). The computer readable code may be stored on a (non-transitory) computer readable medium.

[0026] In addition to the illustrative aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the figures and by study of the following detailed descriptions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Illustrative embodiments are described in the referenced drawings. The dimensions of components and features shown in the drawings are generally selected for convenience and clarity of presentation and are not necessarily shown to scale. The drawings are listed below.

[0028] FIG1 shows an exemplary die-to-die connection with a clock receiver;

[0029] Figure 2 A first version of an exemplary I / O sensor based on a clock receiver is shown;

[0030] Figure 3 To illustrate the use Figure 2 A timing diagram of the search mechanism of the I / O sensor to detect / measure the eye width (EW) of the input signal;

[0031] Figure 4 shows an exemplary die-to-die connectivity configuration utilizing multi-phase clocks;

[0032] Figure 5 To show Figure 4 A timing diagram of the timing of the clock phase;

[0033] Figure 6 Shows that there is Figure 4 Multi-phase clock configuration Figure 2 Implementation of I / O sensor;

[0034] Figure 7 A second version of an exemplary I / O sensor based on a clock receiver is shown;

[0035] Figure 8 A third version of an exemplary I / O sensor based on a clock receiver is shown;

[0036] Fig.9A A fourth version of an exemplary I / O sensor based on a clock receiver is shown;

[0037] Fig. 9B shows a variation of a fourth version of an exemplary I / O sensor based on flip-flop based sampling;

[0038] Fig. 9C A circuit for measuring a programmable delay line for accurate EW measurement using an I / O sensor is shown;

[0039] Fig.10 Shown for use Figure 7 , Figure 8 , Fig.9A or Fig. 9B A timing diagram of a search mechanism for detecting / measuring the eye width (EW) of an input data signal using an I / O sensor;

[0040] Fig.11 Shows the use of Figure 7 and Figure 8 An exemplary die-to-die connectivity configuration of an I / O sensor;

[0041] Fig. 12A Shows the use of Fig.9A Another exemplary die-to-die connectivity configuration of an I / O sensor;

[0042] Fig. 12B Shows the use of Fig. 9B Similar exemplary die-to-die connectivity configurations of I / O sensors;

[0043] Fig.13A Shows the use of Figure 2 and Figures 7 to 9B Another exemplary die-to-die connectivity configuration of an I / O sensor having the added capability of measuring eye height (EH);

[0044] Fig. 13B Shown is the Fig.13A Method for measuring eye height based on the configuration of

[0045] Fig.14 Shows the use of Figure 2 and Figures 7 to 9B Another exemplary die-to-die connectivity configuration of an I / O sensor having the additional capability of using a single I / O sensor for multiple clock receivers;

[0046] Fig.15A and Fig. 15B The timing diagrams of a normal multi-phase clock duty cycle and an abnormal (distorted) multi-phase clock duty cycle are shown respectively. DETAILED DESCRIPTION

[0047] Disclosed herein are circuits, devices, systems, and methods (often referred to as "I / O sensors" or "I / O sensing," respectively) for estimating and monitoring connectivity quality between ICs of a multi-IC module (sometimes referred to as a "multi-chip module") on an interconnect channel. The estimation may include, for example, measuring eye diagram parameters (such as eye width and / or eye height) of a signal received at one end of the interconnect channel, estimating degradation of connectivity quality over time, etc. Optionally, when the connectivity quality is insufficient, one or more actions may be taken, such as replacing a failed interconnect channel with a spare interconnect channel, reducing the transmission rate (also referred to as "data rate") on the failed interconnect channel, replacing a failed IC with a new IC (in the case where the low connectivity quality is the result of a failed IC rather than a failed interconnect channel), etc.

[0048] As referred to herein, the term "multi-IC module" may describe a group of interconnected ICs (sometimes referred to as "chiplets" or "dies") that are integrated and packaged together and configured to cooperate via this interconnection in order to achieve a specific joint functionality. The ICs in a module may communicate with each other, for example, via interconnection buses. The physical integration may be horizontal, vertical, or both.

[0049] The term "eye diagram" as referred to herein may describe a graph in which a digital signal from a receiver is repeatedly sampled and applied to the vertical input, while the data rate is used to trigger the horizontal scan. Eye diagrams help evaluate signal transmission quality, such as channel noise and various other phenomena that cause digital signal distortion. From a mathematical point of view, an eye diagram is a visualization of the probability density function (PDF) of a signal, modulo the unit interval (UI). In other words, it shows the probability of the signal being at each possible voltage within the duration of the UI. Common measurement parameters of an eye diagram are the eye width (EW) and the eye height (EH).

[0050] Multi-IC modules related to the present application may be constructed by any known or later introduced integration technology that provides direct connection between ICs, or indirect connection by an interposer such as an interposer, substrate, circuit board and / or the like. Multi-IC modules may also employ direct and indirect connectivity between pairs of their integrated ICs. Examples of current multi-IC module integration technologies include chip on wafer on substrate (CoWoS), chip on wafer (WoW), chip on wafer (CoW), and 3D IC. However, the specific examples of the present application are of course also beneficial for any other type of multi-IC module characterized by die-to-die (IC-to-IC) connectivity.

[0051] The disclosed I / O sensing includes die-to-die connectivity monitoring, specifically determining the quality of connectivity of high-speed die-to-die interconnects. Such interconnects may implement wide buses and / or low power (picojoules / bit). Quality issues may be the result of opens, shorts, bridge shorts (signal to signal), microbump resistance degradation at the receiver side, and / or microbump resistance degradation at the transmitter side. In this case, the signal timing at the receiver is expected to change, and the change can be detected by the disclosed monitoring techniques. The timing and power effects of this monitoring are minimal, if not negligible.

[0052] Embodiments of the present disclosure may be used, for example, in die-to-die connectivity schemes employing clock receivers (also known as "clock comparators" or "switch comparators"), which are common in today's high-speed die-to-die connections that provide transmission data rates of 4-32 GT / s (Gigatransfers / second) or higher.

[0053] Referring to FIG. 1 , an exemplary die-to-die connection according to the prior art is shown, with a transmitter (a first IC belonging to a multi-IC module) on the left and a receiver (a second IC belonging to a multi-IC module) on the right. The two ICs are interconnected using an interconnect channel; the physical connection between each IC and the channel is at a pad (typically a microbump, pin, etc.). This receiver is based on a clock receiver configuration (shown in an enlarged portion of the figure), in which a comparator is used to compare the input data to a reference voltage (V REF ) for comparison.

[0054] If the voltage difference (V in -V REF ) is greater than a certain value at the clock edge (depending on the implementation and design of the comparator, e.g. 1 to 20 mV), the data output D0 will be interpreted as V DD Otherwise, D0 will be interpreted as V SS .

[0055] According to the principles of the present disclosure, when monitoring the quality of connectivity of an interconnect channel that uses a clock receiver as a sampler, the monitoring circuit should implement the same type of receiver to produce reliable diagnostics. That is, by using a monitoring circuit that is a replica of the monitored circuit (referred to herein as an "I / O sensor"), it is generally ensured that any detected anomalies are real and not caused by the monitoring itself.

[0056] Thus, the disclosed I / O sensor for monitoring and characterizing a channel based on a clock receiver sampler also implements a clock receiver sampler. In the various I / O sensor versions described below, the principle is to use a delayed clock receiver in parallel with a reference clock receiver (the latter is essentially the same clock receiver that would be used in an IC even without an I / O sensor). Both of these clock receivers receive the same data signal (D) from the channel. in ) and the same reference voltage (V REF ), but are clocked differently: while the reference clock receiver is directly clocked by the original clock signal, the delayed clock receiver is clocked by a delayed version of the original clock signal. By comparing the data output (D_s_d) of the delayed clock receiver with the data output (D_s) of the reference clock receiver, it is possible to evaluate the interconnect quality of the channel, for example by measuring the data signal (D in) of the I / O sensor. The evaluation / measurement may be performed by a controller included in the I / O sensor, which controls the delay amount, receives the result of the comparison, and selects the input clock signal if necessary. The controller may further track the eye width over time (e.g., days, weeks, months, and years) to detect degradation of the channel; a decrease in eye width indicates degradation. The controller may further determine whether the eye width is less than a preset threshold value, and in response, trigger replacement of the failed channel with another spare channel.

[0057] Significantly, in all I / O sensor versions described below, the evaluation of interconnect quality and the measurement of eye diagram parameters can be advantageously performed while the channel is transmitting real data in "mission mode." It is not necessary to stop the normal operation of the channel to perform the evaluation and measurement because the I / O sensor operates in parallel with the sampling element (clock receiver) of the channel and does not interfere with the operation of that sampling element.

[0058] Figure 2 A first version of an exemplary I / O sensor based on a clock receiver is shown. in ) drives two clock receivers (two Rx elements shown) that are connected to the connectivity channel at one of their ports. The lower Rx ("reference clock receiver") can be a pre-existing receiver in the IC design, and the upper Rx ("delayed clock receiver") is a receiver added for monitoring purposes.

[0059] Voltage reference V REF Connected to the other port of each of the clock receivers and used as a in The comparison level.

[0060] The clock signal (clk) directly drives the lower clock receiver.

[0061] An inverted delayed version of the clock signal (clk_d_b) is generated by a programmable delay line. The delayed clock version (clk_b_d) is used to clock the upper clock receiver.

[0062] Therefore, the two clock receivers register the data (D) at different times. in ) is sampled and generates two outputs D_s and D_s_d.

[0063] The two outputs are then sampled by the two flip-flops (storage elements, indicated as FF1 and FF2) shown and compared by a comparison circuit (such as the "exclusive OR" gate shown). FF1 and FF2 are clocked by the inverted clock signal Clk_b. If D_s_d is equal to D_s, the "exclusive OR" output (X0) will be a logic 0 (indicating a 'pass'), and if D_s_d is different from D_s, the "exclusive OR" output will be a logic 1 (indicating a 'fail').

[0064] The last flip-flop (storage element, indicated as FF3) can be used to store the exclusive OR value when it first changes to logic 1, with the following configuration: FF3 is clocked by Clk_b; the data input to FF3 comes from the OR gate, whose first input is X0 and whose second input is the output of FF3. The last flip-flop is also considered as part of the comparison circuit as it stores the last change of the comparison result.

[0065] A controller embedded in the IC (not shown in this figure) can control the amount of incremental delay introduced by the programmable delay line and can also receive the output of FF3. Therefore, the controller knows the specific amount of delay that caused the first "failure" in X0 and can use this knowledge to calculate D in Eye width.

[0066] refer to Figure 3 Better understand Figure 2 The operation of I / O sensors, Figure 3 To illustrate the use of D in A timing diagram of a search mechanism (method) for detecting / measuring the eye width of an input signal.

[0067] In the figure, during communication (data transfer), the clock signal (clk) that clocks the lower clock receiver samples the value of the D1 data output at the middle of the unit interval (UI).

[0068] The Clk_b_d generated by the programmable delay line is used to scan the eye from left to right or right to left by clocking the upper clock receiver with a different delay level compared to the Clk signal (shown with a dashed line on the rising edge of the clock).

[0069] The outputs of the two clock receivers are sampled by two flip-flops (FF1 and FF2) at the falling edge of the clk signal and then compared by an exclusive OR.

[0070] If the flip-flops happen to sample different values, the "exclusive OR" output will be set to logic 1. The last flip-flop (FF2) will store this failure indication until it is reset by the controller in a subsequent scan sequence. Of course, the controller can be configured to store a record of all past failure indications in non-volatile memory on the IC along with the time at which each failure was indicated.

[0071] The scanning sequence (method) can be as follows:

[0072] Starting from the minimum delay of the programmable delay line, clk_b_d samples the value of the D0 data output. The clk signal samples D0.

[0073] Since D0 is not equal to D1, a failure (shown by the letter F) is expected.

[0074] The programmable delay line then increases its delay in small increments, and at the point (delay line position) where both clock receivers are sampling the same value, the detection is switched (inverted) to pass (shown by the letter P).

[0075] The delay line then continues to increase its delay value until the two clock receivers again sample different values. The comparison then indicates a failure (shown by the letter F).

[0076] Eye width can be measured as follows:

[0077] 1. Record the position of the programmable delay line at the first fail-pass (F→P) transition.

[0078] 2. Record the position of the programmable delay line at the first pass-fail (P→F) transition.

[0079] 3. Calculate the number of delay line increments (K) between the 1st fail-pass and the 1st pass-fail.

[0080] 4. Convert K to time (e.g., in picoseconds) by multiplying K by the delay line "tick" (d), which is the duration of each incremental step that the delay line is programmed to perform.

[0081] The disclosed I / O sensors can also be used with die-to-die connectivity configurations that utilize multi-phase clocks to increase data transfer bandwidth. In such configurations, a sampling clock frequency (e.g., 2.4 GHz) can span multiple clock phases (e.g., 8 phases) to produce a greater bandwidth (e.g., 2.4×8=19.2 GT / s).

[0082] Such exemplary configurations are Figure 4 , where there are eight clock receivers, each clock receiver is clocked by a different phase of the clock (Φ0 to Φ7), producing eight different data outputs (D0 to D7). Such a configuration may include a different number of clock phases, such as 2 to 32 phases or more.

[0083] Figure 5 It also explains Figure 4 4 shows a timing diagram of the eight clock phases of a clock receiver and the timing of the eight data outputs.

[0084] refer to Figure 6 , which illustrates the disclosed multi-phase clock configuration (such as Figure 4 In this embodiment, with Figure 2In comparison, I / O sensors can be configured with the following changes:

[0085] 1. Use one representative receiver for every eight receivers.

[0086] 2. The reference data (D_in) is generated by the channel receiver (D0).

[0087] 3. A delayed clock version (clko) is generated by the I / O sensor to drive an external clock receiver to generate delayed data D0_D (however, this clock receiver may also be included in the I / O sensor itself).

[0088] As an alternative to coupling the I / O sensor to only one representative clock receiver of a multi-phase clock configuration, it is possible to couple the I / O sensor to multiple clock receivers using a multiplexer that selects a different clock receiver each time. This alternative configuration is not shown in the figure.

[0089] refer to Figure 7 , which describes a second version of a clock receiver based I / O sensor; and reference Fig.10 , which explains the use of Figure 7 The operation of the second version of the I / O sensor is similar to that of the first version thereof, with certain differences being indicated below and described in Figure 7 Shown in.

[0090] The second I / O sensor version allows measuring the eye width by performing two measurements, each in a separate scan mode of operation selected by the multiplexer.

[0091] In the first measurement mode (M1, Mode-1), the rising edge of the clk signal is used as a reference for measuring the right timing shift of the EW. This is done by shifting the clk signal (adjusting its delay) by the delay line to find the lowest fail indication (assuming the delay line delay is shifted from its maximum value to its minimum value), or to find the highest pass indication (assuming the delay line is shifted from its minimum value to its maximum value).

[0092] In the second measurement (M2, Mode 2), the rising edge of the clk signal is used as a reference, while the rising edge of the clk_b signal (the inverse of clk) is delayed by the delay line to measure the left timing shift of the EW. This is done by shifting the clk_b signal by the delay line to find the highest fail indication (assuming the delay line is shifted from its minimum value to its maximum value), or to find the lowest pass indication (assuming the delay line is shifted from its maximum value to its minimum value).

[0093] Then, the minimum EW is calculated as: minimum EW = UI + M1 - M2. UI represents the data unit interval, that is, 1 / data rate (in GT / s). Each of M1 and M2 represents the delay provided by the delay line when FF3 first indicates "failure" in the respective mode.

[0094] The delay line may be composed of two parts, a coarse delay line and a fine delay line connected in series, such that the combination of their delays provides the total delay of the delay line. For example, each step length of the coarse delay line may increase the delay by a value between 1 / 2 and 6 / 8 of the UI length, while each step length of the fine delay line may increase the delay by a value between 1 / 8 and 1 / 4 of the UI length. In general, the ratio of the length of the step delay between the coarse delay line and the fine delay line may be 2:1 or greater.

[0095] The coarse delay line is a controlled delay element that enables the I / O sensor to operate at multiple / wide range of data rates (clock frequencies) simultaneously using the same variable (fine) delay line. The coarse delay line is configured based on the data rate to bring the edge of the scan clock to the fail region (i.e., to near where a transition from a "fail" to a "pass" or from a "pass" to a "fail" result will likely be detected). The fine delay line is then used for a finer scan to detect the exact point of transition from pass to fail or from fail to pass.

[0096] Both the coarse delay line and the fine delay line are controlled by the same controller (not shown), which is embedded in the IC and optionally part of the I / O sensor, which also receives the output of FF3 and controls the multiplexer.

[0097] refer to Figure 8 , which describes a third version of a clock receiver-based I / O sensor; and reference Fig.10 , which explains the use of Figure 8 The timing diagram of the search mechanism of the I / O sensor to detect / measure the eye width of the input signal (this timing diagram is the same as Figure 7 same as the I / O sensors of the

[0098] The third version of the I / O sensor is capable of operating at extremely high data rates (frequencies), such as 32GT / s and above, by using two input clocks of opposite phase (clk_phase_0 and clk_phase_1) that directly clock the delay line and the reference clock receiver that produces the D_s output. Due to such high data rates, two optional compensating delay elements may be included in this version of the I / O sensor: inA phase shifter that applies a fixed delay, and a compensating delay buffer that applies a fixed delay to the clk_phase_0 signal. It is also possible to include only one of these compensating delay elements. The fixed delay can be 3 to 12 picoseconds (or more if desired), which is roughly equivalent to the intrinsic delay of the programmable delay line. That intrinsic delay is the delay affected by the programmable delay line, even before it is set to apply any delay; its mere presence in a particular signal path causes any signal passing through it to be slightly slowed down. By slightly delaying D in , it can be ensured that each data signal arrives at the two clock receivers almost at the same time (for example, with a maximum variance of no more than 3 picoseconds); similarly, by slightly delaying the clk_phase_0 signal, it can be ensured that when the delay line is set to introduce a certain delay, the clk_phase_0 signal will arrive at the delayed clock receiver almost at the set delay (with a maximum variance of no more than 3 picoseconds, for example), and not much later than that delay. In general, these compensating delay elements help ensure an equal comparison - comparing the outputs of the two clock receivers under the same starting conditions.

[0099] The third I / O sensor version allows measuring the eye width by performing two measurements in two separate scan modes that can be selected using a multiplexer (similar to the second version). The EW is extracted using the same method as described above. Clk_phase_0 is used as the reference clock for both M1 and M2 measurements, clk_phase_0 is the delayed clock under M1 measurement, and clk_phase_1 is the delayed clock under M2 measurement.

[0100] In the first measurement (M1, Mode-1), the rising edge of the clk_phase_0 signal is used as a reference to measure the right timing shift of the EW. This is done by shifting the clk_phase_0 signal by the delay line to find the lowest fail indication (assuming the delay line is shifted from its maximum value to its minimum value), or to find the highest pass indication (assuming the delay line is shifted from its minimum value to its maximum value).

[0101] In the second measurement mode (M2, Mode-2), the rising edge of the clk_phase_0 signal is used as a reference to measure the left timing shift of the EW. This is done by shifting the clk_phase_1 signal by the delay line to find the highest fail indication (assuming the delay line is shifted from its minimum value to its maximum value), or to find the lowest pass indication (assuming the delay line is shifted from its maximum value to its minimum value).

[0102] Then, the minimum EW is calculated as: minimum EW = UI + M1 - M2.

[0103] Clk_phase_0 and clk_phase_1 represent two adjacent clock phases in a multi-clock phase system, with clk_phase_0 being the leading clock phase and clk_phase_1 being the lagging clock phase by UI. By connecting every two adjacent clock phases to an I / O sensor, a third I / O sensor version can be used to measure the EW of each data index (more than two) in a multi-clock phase system. For example, in a 4-clock phase system, the following clock phase pairs [lead, lag] can be measured: [clk_phase_1,clk_phase_0], [clk_phase_2,clk_phase_1], [clk_phase_3,clk_phase_2]. As will be readily appreciated by one of ordinary skill in the art, this can be implemented by adding an input selector (multiplexer).

[0104] Now refer to the following figures: Fig.9A , which illustrates a fourth version of a clock receiver based I / O sensor; Fig. 9B , which illustrates a fourth version of an I / O sensor based on flip-flop sampling (and also measuring quadrature phase clocks); and Fig.10 , which explains the use of Fig.9A or Fig. 9B The timing diagram of the search mechanism of the I / O sensor to detect / measure the eye width of the input signal (this timing diagram is for Figure 7 and Figure 8 The I / O sensors are the same).

[0105] The 4th edition I / O sensor is capable of measuring the eye width of each clock phase in multi-phase clock, wide frequency range systems. For example, such systems utilize multi-phase clocks to sample wide data rate transmissions (e.g., 4GT / s to 3.2GT / s) with multiple clock phases (e.g., 2 or 4). Fig.9A The I / O sensor can measure EW relative to each of the clock phases clke and clko. Fig. 9B The I / O sensor may measure EW with respect to each of the clock phases clk_phase_1, clk_phase_2, clk_phase_3, and clk_phase_4.

[0106] Fig.9A and Fig. 9B The main difference between Fig.9A A clock receiver is used to sample and Fig. 9B The flip-flop (temporary register) is used to sample the data. Specifically, Fig. 9BA first flip-flop (FF1) and a second flip-flop (FF2) are used to sample data using a delayed version of a reference clock and a non-delayed version of a reference clock, respectively. The other flip-flops in the I / O sensor are substantially the same. The use of a sampling flip-flop may facilitate simplified manufacturing or fabrication compared to a clock receiver. In this configuration, VREF also does not need to be provided to the I / O sensor, which may improve signal routing efficiency.

[0107] Fig.9A Two clock phases are shown, an even clock (clke) and an odd clock (clko). The phase between clke and clko is 180 degrees, so that clke samples data at even bits of the data stream, while clko samples data at odd bits of the data stream (for double data rate DDR operation). Other configurations contemplated herein may include different numbers of clock phases. Fig. 9B As shown, there may be four clock phases, with each clock phase having a 90 degree separation from the other two clock phases (for quadrature data rate, QDR operation). Even more clock phases may be used, and one of ordinary skill in the art will recognize the need to adapt these examples to facilitate that number of clock phases.

[0108] The fourth version of the I / O sensor implements two input multiplexers mux1 and mux2 to select each clock phase in the system to be used as the reference clock ( Fig.9A clke or clko in, or Fig. 9B The I / O sensor will measure the EW of each selected clock phase in the multi-mode measurement technique as described above.

[0109] for Fig.9A , To measure EW relative to clke: In mode 1, both mux1 and mux 2 select clke. In mode 2, mux1 selects clko, and mux2 selects clke. To measure EW relative to clko: In mode 1, both mux1 and mux2 select clko. In mode 2, mux1 selects clke, and mux2 selects clko.

[0110] refer to Fig. 9B , an input multiplexer is used to select two clock phases per measurement, as explained below.

[0111] To measure EW in DDR mode (where only two clock phases are used), the two clock phases should be selected in the following order. Eye-1 is measured by selecting clk_phase_1, clk_phase_2 (clk_f1, clk_f2). Eye-2 is measured by selecting clk_phase_2, clk_phase_1 (clk_f2, clk_f1). This can be achieved by making the following selections for mux2 (controlled by the prtn_io_sensor_cfg[10:9] signal) and mux1 (controlled by the prtn_io_sensor_cfg[12:11] signal).

[0112] To measure Eye-1 in DDR mode, select the following clock pairs:

[0113] prtn_io_sensor_cfg[10:9]=[0,0], prtn_io_sensor_cfg[12:11]=[0,0]→M1

[0114] prtn_io_sensor_cfg[10:9]=[0,0], prtn_io_sensor_cfg[12:11]=[0,1]→M2

[0115] To measure Eye-2 in DDR mode, the following clock pairs were selected:

[0116] prtn_io_sensor_cfg[10:9]=[0,1], prtn_io_sensor_cfg[12:11]=[0,1]→M1

[0117] prtn_io_sensor_cfg[10:9]=[0,1], prtn_io_sensor_cfg[12:11]=[0,0]→M2

[0118] To measure each EW in QDR mode, two of the four clock phases should be selected in the following order. Eye-1 is measured by selecting clk_phase_1, clk_phase_4 (clk_f1, clk_f4). Eye-2 is measured by selecting clk_phase_2, clk_phase_1 (clk_f2, clk_f1). Eye-3 is measured by selecting clk_phase_3, clk_phase_2 (clk_f3, clk_f2). Eye-4 is measured by selecting clk_phase_4, clk_phase_3 (clk_f4, clk_f3). This can be achieved by making the following selections for mux2 (controlled by the prtn_io_sensor_cfg[10:9] signal) and mux1 (controlled by the prtn_io_sensor_cfg[12:11] signal).

[0119] To measure Eye-1 in QDR mode, the following clock pairs are selected:

[0120] prtn_io_sensor_cfg[10:9]=[0,0], prtn_io_sensor_cfg[12:11]=[0,0]→M1

[0121] prtn_io_sensor_cfg[10:9]=[0,0], prtn_io_sensor_cfg[12:11]=[1,1]→M2.

[0122] To measure Eye-2 in QDR mode, the following clock pairs were selected:

[0123] prtn_io_sensor_cfg[10:9]=[0,1], prtn_io_sensor_cfg[12:11]=[0,1]→M1

[0124] prtn_io_sensor_cfg[10:9]=[0,1], prtn_io_sensor_cfg[12:11]=[0,0]→M2

[0125] To measure Eye-3 in QDR mode, the following clock pairs were selected:

[0126] prtn_io_sensor_cfg[10:9]=[1,0], prtn_io_sensor_cfg[12:11]=[1,0]→M1

[0127] prtn_io_sensor_cfg[10:9]=[1,0], prtn_io_sensor_cfg[12:11]=[0,1]→M2

[0128] To measure Eye-4 in QDR mode, the following clock pairs were selected:

[0129] prtn_io_sensor_cfg[10:9]=[1,1], prtn_io_sensor_cfg[12:11]=[1,1]→M1

[0130] prtn_io_sensor_cfg[10:9]=[1,1], prtn_io_sensor_cfg[12:11]=[1,0]→M2

[0131] refer to Fig. 9C , shows a circuit for using an I / O sensor to measure a programmable or adjustable delay line for accurate EW measurement. By coupling to an input multiplexer and a programmable delay line at the locations shown, this circuit can be used with, for example, Fig.9A or Fig. 9B I / O sensor interconnection.

[0132] In this design, a ring oscillator (ROSC) circuit is used to measure the delay. The ROSC circuit includes an extended delay line (EDL) and a ROSC inverter. The ROSC circuit is controlled by a ROSC channel gate and a ROSC selector, both of which are enabled by the ROSC enable signal osc_en. When osc_en = [1], the ROSC channel gate and the ROSC selector are enabled, and when osc_en = [0], the ROSC channel gate and the ROSC selector are disabled.

[0133] The output of the ROSC selector is controlled by the mode signal osc_mode. The ROSC circuit can operate in two modes. In the first mode (osc_mode = [1]), the ROSC circuit includes only an extended delay line and a ROSC inverter. In the second mode (osc_mode = [0]), the ROSC circuit includes a programmable delay line of an I / O sensor, an extended delay line, and a ROSC inverter. The output of the ROSC selector is provided to a frequency divider, including: a frequency divider flip-flop (FF); and an inverter. The output of the ROSC selector is provided to the frequency divider flip-flop (FF) as a clock input, and the inverter is coupled between the frequency divider flip-flop (FF) data output and the frequency divider flip-flop (FF) data input. Therefore, the signal at the frequency divider flip-flop (FF) data output is half the frequency of the output of the ROSC selector.

[0134] The output of the divider is provided to a buffer which provides an oscillator output signal osc_out. Advantageously, the oscillator output signal may be multiplexed with the measurement output of an I / O sensor (not shown). When programmable delay line measurements are being made, it is advantageous to disable normal I / O sensor measurements. For this purpose, the ROSC enable signal osc_en is also provided to an inverting control input (labeled Input_dis) on a multiplexer (mux) which supplies the delay line (e.g., Fig.9A and Fig. 9B Thus, when osc_en=[1], the inverting control input disables the multiplexer. In this way, the programmable delay line can be used for normal (EW) measurement or delay line measurement. In the latter case, the normal (EW) measurement mode is disabled.

[0135] The programmable delay line circuit produces a linear delay in fine steps. The delay provided by the programmable delay line (D) can be expressed by the following expression:

[0136] Where D0 is the intrinsic delay of the delay line, d is the fine step delay step size, and n is the number of steps minus 1 (since the initial value of k is 0), which may be 16 in the example case.

[0137] The ROSC circuit allows the fine delay line step size to be measured in picoseconds. As explained above, the ROSC circuit can be activated in two configuration modes. The first mode (osc_mode = [1]) is also called the fine delay line bypass mode, and in this configuration, the ROSC includes an EDL and a ROSC inverter. The oscillation frequency of the ROSC is then based on the EDL delay. The oscillation period Tosc is twice the EDL delay. The second mode (osc_mode = [0]) is also called the fine delay line no bypass mode. In this configuration, the ROSC includes an EDL and a programmable delay line. In this mode, the oscillation frequency of the ROSC corresponds to the delay of the EDL and the delay of the programmable fine delay line. In this case, the oscillation period Tosc is twice the sum of the EDL delay and the programmable delay line delay.

[0138] In a specific example (for illustration purposes only), the EDL delay may have a value of 0.5 ns, and the expected frequency of the ROSC in the first mode is then approximately The frequency divider (including the frequency divider flip-flop FF) divides the ROSC frequency by 2, so that the oscillator output signal osc_out is approximately 500 MHz in this example.

[0139] In operation, the first mode of the ROSC circuit is used to generate a baseline frequency (FB), which in the illustrative example above is 500 MHz. The cycle time can then be extracted: In this illustrative example, T B is 4 ns. Then, the second mode of the ROSC circuit is used with k=0. This is used to measure the frequency (F) corresponding to the sum of the EDL delay and the intrinsic delay (D0) of the programmable delay line. D ) and extract the corresponding cycle time (TD) from it:

[0140]

[0141] Finally, the second mode of the ROSC circuit is used, in which k is set to each of 1 to n (n=15 in the illustrative example discussed herein) to measure F D (k) and extract the fine delay line step duration d(k) according to the following expression:

[0142]

[0143] Typical example values ​​of d(k) may be 1 ps to 5 ps, depending on the delay line configuration.Timing measurements determined in this manner may then be used for accurate EW measurements.

[0144] In general, this circuit may be considered a timing measurement circuit configured to measure the delay provided by a programmable delay line. The timing measurement circuit may include a ring oscillator circuit that is selectively configured to include the programmable delay line. In this way, a comparison of the output frequency of the ring oscillator circuit without the programmable delay line and the output frequency of the ring oscillator circuit including the programmable delay line may indicate the delay introduced by the programmable delay line. Accurate EW measurement (up to picoseconds) may thereby be possible.

[0145] Reference now Fig.11 , which shows an exemplary die-to-die connectivity configuration utilizing any of the first, second, or third versions of an I / O sensor. This I / O sensor is positioned close to the channel sampling element (reference clock receiver (Rx)). The I / O sensor input signal is connected to the channel to receive the D in , and the Rx clock is also used to clock the I / O sensors. Rx V REF Also used as reference voltage for the I / O sensor's own (delayed) clock receiver.

[0146] Reference now Fig. 12A and Fig. 12B , which shows an exemplary die-to-die connectivity configuration utilizing a fourth I / O sensor version. Fig. 12A Using a fourth I / O sensor version based on a clock receiver with two clock phases, as for example in Fig.9A As shown in Fig. 12BUsing a fourth I / O sensor version based on a sampling flip-flop (or similar) with four clock phases, as in Fig. 9B In both cases, the I / O sensor is located close to the channel sampling element, the clock receiver (Rx). The I / O sensor input signal is connected to the channel to receive the D in , and the two clock phases of the respective Rx element are also used to clock the I / O sensor. Fig. 12A In, Rx V REF Used as reference voltage for the I / O sensor's own (delayed) clock receiver. When using a sampling flip-flop in the I / O sensor, it is not necessary to provide Rx V REF As a reference voltage to the I / O sensors, such as Fig. 12B as shown in .

[0147] Reference now Fig.13A , which shows an exemplary die-to-die connectivity configuration using any of the above-mentioned I / O sensor versions, using the variable V REF Additional capability to measure eye height (EH). To measure eye height, such as Fig. 13B As described in the above, the measured values ​​of M1 and M2 are compared with different V REF The values ​​are compared so that now according to different V REF The eye width can now be calculated based on the predefined minimum eye width (e.g., V REF + / -2dV) to calculate eye height.

[0148] Reference now Fig.14 , which shows an exemplary die-to-die connectivity configuration using any of the I / O sensor versions mentioned above, with the ability to use one I / O sensor per multiple reference clock receivers (Rx) (e.g., two). In this configuration, each of the reference clock receivers is connected to the I / O sensor so that its clock-to-data delay difference remains substantially constant regardless of the distance between the clock receivers. The delay inherent in that distance (i.e., the signal propagation time that is proportional to the distance of the path) can be compensated by the illustrated compensating delay buffer, which applies a fixed delay amount that is pre-calculated based on the relevant distance. Maintaining the same delay difference between the data signal and the clock signal at the input of the I / O sensor allows EW and EH to be measured based on M1+M2 measurements in a reliable manner; that is, the measured EW and EH will be equal to the EW and EH of the reference clock receivers themselves. The two multiplexers mux1 and mux2 shown in this figure can be implemented external to the I / O sensor, or as part of the I / O sensor.

[0149] In the third and fourth I / O sensor versions using multi-phase clocks, the duty cycle distortion of such clocks can be detected and / or measured using the techniques described below. This distortion manifests itself as different, non-matching periods of different clock phases. Fig.15A and Fig. 15B , the figures show timing diagrams of a normal multi-phase clock duty cycle and an abnormal (distorted) multi-phase clock duty cycle, respectively. A normal multi-phase clock exhibits a duty cycle of 50%, where the UI is consistent and the distances between the rising edges of each clock phase signal clko and clke are equal. However, in an abnormal multi-phase clock, there is no consistent UI. In the case of clko, its "phase low" (PL) period is longer than its "phase high" (PH) period, and the opposite phenomenon can be observed in clke. The distances between the rising edges of each of these clock phase signals are not equal. Duty cycles different from 50% are generally undesirable in multi-phase clock receivers.

[0150] In order to detect such duty cycle distortion, and optionally measure the distorted duty cycle, two measurements may be performed: a measurement in mode 1 using clke (M1e), and a measurement in mode 1 using clko (M1o). The distortion is then given by M1e to M1o. Alternatively, the two measurements may include a measurement in mode 2 using clke (M2e), and a measurement in mode 2 using clko (M2o). Here, the distortion is given by M2e to M2o.

[0151] Various methods for measuring the eye width (minimum EW) are described above in the context of versions of the I / O sensor using a multi-phase clock (second, third, and fourth versions). These methods require operating two scan modes. However, when the duty cycle of the multi-phase clock is known to be undistorted, a simpler method can be used to measure the eye width (either by measuring the distortion as described above, or by knowing by other tests that no distortion is expected). This method requires only a single scan mode, where the lowest and highest failures are determined for one clock phase (due to the 50% duty cycle assumption, the other clock phase does not need to be measured). The eye width is given by the following formula: UI+lowest failure-highest failure. That is, the duration of the UI plus the delay required to reach the lower failure minus the delay required to reach the highest failure.

[0152] It can be seen that when it is known in advance that the multi-phase reference clock receiver has a normal (50%) duty cycle (or close to a normal duty cycle, such as a 47-53% duty cycle), the third and fourth I / O sensor versions can be implemented without a multiplexer for mode selection; instead, only one clock phase can be used for connectivity quality estimation and eye width measurement. Similarly, the second I / O sensor version can be implemented without a clock inverter and a multiplexer following it, so that connectivity quality estimation and eye width measurement are performed only based on the original clock signal.

[0153] Further provided herein is a method of calculating eye width jitter. This may include taking a large number (e.g., 10,000 or more) of M1 or M2 measurements using the second, third, or fourth I / O sensor versions and calculating a statistical measure of the distribution of the measurements. An alternative method of calculating eye width jitter is to spread these M1 or M2 measurements over multiple interconnect channels (i.e., when the associated I / O sensor is connected to the reference clock receivers of multiple different channels) so that the calculated eye width jitter represents the jitter occurring over all of these channels.

[0154] In general, with respect to all versions of the I / O sensor, it will be appreciated that the I / O sensor may include a controller as briefly described above. The controller may be configured by appropriate circuitry it includes to control a programmable delay line, i.e., to gradually adjust the amount of delay introduced by the delay line according to any delay increment (or "step size") built into the delay line. This gradual adjustment may be according to the scanning method described above.

[0155] The controller may be further configured to control any of the mentioned multiplexers to achieve different measurement modes.

[0156] The controller may be further configured to receive the comparison result ("pass" or "fail", expressed as 0 or 1) from the comparison circuit (e.g., a mutex or gate) immediately after each comparison is performed, or only after the last flip-flop (e.g., Figure 7 After the value in FF3 in the figure and the equivalent flip-flops in other figures) changes from one value to another (for example, from "pass" to "fail", or from "fail" to "pass").

[0157] In addition, the controller can be configured to estimate the quality of connectivity between ICs connected on the interconnect channel based on the comparison result and the amount of delay that caused that result; that is, if the comparison result changes (reverses) from a previous "pass" to a "fail" in response to a certain amount of delay introduced by the delay line, the controller can infer that the connectivity quality is related to that certain amount of delay. Generally, the longer the delay, the better the connectivity quality, and vice versa. The quality estimate can constitute, for example, the measurement of eye diagram parameters of the signal received by the interconnect channel, such as eye width and / or eye height. To measure the eye height, the controller can be further configured to control the variable V REF , so as to gradually adjust V REF to the different levels required to obtain eye height measurements.

[0158] The quality estimation performed by the controller may also take the form of longer term monitoring, during which trends in "failure" results in varying amounts of delay (and respective eye diagram parameters) are detected and acted upon as appropriate. Whether the estimation is instantaneous or long term, when the quality of connectivity is insufficient (e.g., below a threshold, or when a degradation trend exceeds a certain slope), the controller may perform or trigger one or more actions, as discussed above.

[0159] The controller may be further configured to perform the aforementioned duty cycle distortion detection / measurement, and the aforementioned eye width jitter measurement.

[0160] The controller may be further configured to transmit the quality estimate (e.g., measured eye diagram parameters) to a computing device on which the multi-IC module is installed, and from there to a computerized server via a communication network as appropriate. The quality estimate may be further analyzed by the computing device or the computerized server, and each may issue an indication to a user regarding the results of the quality estimate and / or its further analysis.

[0161] Furthermore, in general, with respect to all versions of I / O sensors, if desired, the I / O sensor may include one or more compensating delay elements that are configured to compensate for intrinsic delays of elements of the I / O sensor and / or intrinsic delays of greater signal propagation distances required due to the location of the I / O sensor. Figure 8 The compensating delay buffer and phase shifter of are examples of such compensating delay elements, where a first compensating delay element delays a clock signal and a second compensating delay element delays a data signal. Fig.14 Further examples regarding the distance to an I / O sensor that requires timing compensation are given in . In general, the importance of such compensated delay elements in an I / O sensor may increase as the data rate of the interconnect channel being monitored increases; at high data rates, the sampling of the data signal must be precisely timed, and any uncompensated delay associated with the I / O sensor (its elements and / or its location) may reduce the reliability of the quality estimate, for example by producing inaccurate measurements of eye diagram parameters.

[0162] Advantages of the disclosed I / O sensor and I / O sensing method may include:

[0163] -Full data channel coverage.

[0164] - Comprehensive coverage of driver and receiver (comparator, level shifter) circuits.

[0165] -The impact on area and power is negligible.

[0166] -Used during testing and missions.

[0167] -Data analysis skills.

[0168] The disclosed I / O sensors and I / O sensing methods can be used, for example, to characterize IC designs prior to fabrication:

[0169] - Characterization of channel performance (eye width and jitter) under different PVT (process voltage temperature) ranges.

[0170] -Channel-to-channel skew and crosstalk characterization.

[0171] - Substrate design topology verification.

[0172] The disclosed I / O sensors and I / O sensing methods may also be useful, for example, after an IC has been fabricated:

[0173] - Outlier detection in assembled multi-IC modules.

[0174] - Alternative channels are started (if such channels are available).

[0175] -Yield monitoring and yield decline warning.

[0176] The disclosed I / O sensors and I / O sensing methods can also be used, for example, to monitor the reliability of multi-IC modules operating in the field, where die-to-die channels can degrade over time. If an impending failure is detected, predictive maintenance can be performed, such as activating a spare channel, module swapping, etc.

[0177] Another option is to perform I / O sensing at each IC before it is ultimately packaged with another IC to avoid packaging together ICs that have substantial performance differences (e.g., receivers with substantially different delays). To this end, one specific example may include a test device ("tester") configured to transmit data to an IC connected to the tester, where the IC includes the disclosed I / O sensors. Since it is assumed that the tester is transmitting data perfectly and is not the cause of any channel delay (not a substantial cause, anyway), any delay can be attributed to the IC under test. By testing each fabricated IC in this manner, "fast" ICs (ICs with low channel delays) can be interconnected and packaged together, and so can "slow" ICs. This prevents fast ICs from being packaged together with slow ICs (which would result in a die-to-die connection that is as slow as the slowest IC (the weakest link)).

[0178] A series of circuit designs and schematics are described herein. It will be appreciated that such circuit designs may be embodied in electronic (also "digital") representations (also "encoded") . The electronic representation may be stored in a computer-readable medium, particularly of a non-transitory nature. Suitable electronic representations may include representations of electronic computer-aided design (ECAD) software, also known as electronic design automation (EDA) software. In this case, portions of the representation may be stored across multiple electronic files or archives, possibly including one or more libraries of the ECAD software that provide details of the components of the circuit. The ECAD representation may provide instructions suitable for the manufacture (also "fabrication") of the circuit as represented in the design. Such electronic representations may be provided in accordance with the present application. Further consideration is given to methods of using an electronic representation of an electronic circuit as part of manufacturing the electronic circuit.

[0179] The flowcharts, circuits, and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of the systems, methods, and computer program products according to various specific examples of the present application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing a specified logical function. It should also be noted that each block in the block diagram and / or flowchart illustration, and combinations of blocks in the block diagram and / or flowchart illustration, may be implemented by a dedicated hardware-based system that performs the specified functions or actions or implements a combination of dedicated hardware and computer instruction files.

[0180] In the specification and claims, when describing a numerical value, the terms "substantially," "essentially," and their respective forms mean a deviation of up to 20% (i.e., ±20%) from that value. Similarly, when such terms describe a numerical range, they mean a broader range of up to 20%—10% above that explicit range and 10% below that range.

[0181] In the specification, any given numerical range shall be deemed to have specifically disclosed all possible sub-ranges and individual values ​​within that range, so that each such sub-range and individual value constitutes a specific example of the present application. Regardless of the breadth of the range, the above situation applies. For example, the description of integer ranges such as from 1 to 6 shall be deemed to be specifically disclosed such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 and individual values ​​within that range, such as 1, 4 and 6. Similarly, the description of the fractional range such as from 0.6 to 1.1 shall be deemed to be specifically disclosed such as from 0.6 to 0.9, from 0.7 to 1.1, from 0.9 to 1, from 0.8 to 0.9, from 0.6 to 1.1, from 1 to 1.1 and individual values ​​within that range, such as 0.7, 1 and 1.1.

[0182] The description of various embodiments of the present application is presented for the purpose of illustration and is not intended to be exhaustive or limited to the explicit description. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

[0183] In the description and claims of the present application, each of the terms "comprises," "includes," and "has," and forms thereof, are not necessarily limited to the components in the list with which the terms can be associated.

Claims

1. An I / O sensor, comprising: a programmable delay line; A delayed sampling device having the following inputs: a data signal which is also used as an input to a reference clock receiver configured to sample the data signal received from an interconnect channel between two integrated circuits (ICs) of a multi-IC module, and a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clock receiver; a comparison circuit configured to compare a data signal output of the delayed sampling device with a data signal output of the reference clock receiver; and A controller configured to: gradually adjusting a delay amount introduced by the programmable delay line, After each gradual adjustment of the delay amount, receiving the comparison result from the comparison circuit, and A connectivity quality between the two ICs on the interconnect channel is estimated based on at least one of the results and based on the amount of delay that caused the result.

2. The I / O sensor of claim 1, wherein: The programmable delay line comprises a coarse delay line and a fine delay line connected in series; Each delay step of the coarse delay line is longer than each delay step of the fine delay line; The length of each delay step of the coarse delay line is configured so that a rising edge of the delayed clock signal is close to the position where the result of the comparison is likely to flip from a pass to a fail or from a fail to a pass; and The length of each delay step of the fine delay line is configured to detect a precise point at which the result of the comparison may flip from a pass to a fail or vice versa.

3. The I / O sensor of claim 1 or claim 2, wherein the estimation of the connectivity quality comprises a calculation of an eye-view parameter of the data signal. 4 . The I / O sensor of claim 3 , wherein the eye diagram parameter comprises an eye width calculated based on a time distance between inversion points of comparison results at a left side and a right side of a unit interval (UI) of the data signal.

5. The I / O sensor of claim 4, wherein the controller is configured to operate the programmable delay line to scan the eye in one direction in order to detect the reversal point of the comparison result.

6. The I / O sensor of claim 4, wherein the controller is configured to select between two eye scanning modes: a first eye scanning mode in which a first side of the eye is scanned by increasing or decreasing the amount of delay introduced by the programmable delay line; and A second eye scanning mode in which a second opposite side of the eye is scanned by increasing or decreasing the amount of delay introduced by the programmable delay line.

7. The I / O sensor of claim 6, wherein the clock signal for clocking the reference clock receiver is a multi-phase clock signal, and wherein: In the first eye scanning mode, one of the phases of the multi-phase clock signal experiences the increase or the decrease in the amount of delay introduced by the programmable delay line; In the second eye scanning mode, a different one of the phases of the multi-phase clock signal experiences the increase or the decrease in the amount of delay introduced by the programmable delay line; and In both the first eye scan mode and the second eye scan mode, the different one of the phases of the multi-phase clock signal is used to clock the reference clock receiver.

8. The I / O sensor of claim 6 or claim 7, wherein: The delayed sampling device is a clock receiver having a reference voltage as an additional input, the reference voltage also serving as an input to the reference clock receiver; The reference voltage is a variable reference voltage; The eye diagram parameters further include an eye height; and The controller is further configured to measure the eye height by gradually adjusting the variable reference voltage during each of the first eye scanning mode and the second eye scanning mode to measure the eye width at different voltage levels.

9. The I / O sensor according to any one of claims 6 to 8, wherein: The clock signal for clocking the reference clock receiver is a multi-phase clock signal; and The controller is further configured to detect a duty cycle distortion of the multi-phase clock signal based on only one of the first eye scanning pattern and the second eye scanning pattern.

10. The I / O sensor according to any one of claims 4 to 9, wherein: The clock signal that clocks the reference clock receiver is a multi-phase clock signal having an approximately 50% duty cycle; and When calculating the eye width, the delayed clock signal received from the programmable delay line is only one phase of the multi-phase clock signal.

11. The I / O sensor of any one of claims 1 to 10, further comprising a compensation delay element configured to apply a fixed delay amount to the clock signal to compensate for an intrinsic delay of the programmable delay line.

12. The I / O sensor of any one of claims 1 to 11, further comprising a compensation delay element configured to apply a fixed delay amount to the data signal to compensate for an intrinsic delay of the programmable delay line.

13. The I / O sensor of any one of claims 1 to 12, further comprising a compensation delay element configured to apply a fixed delay amount to at least one of the data signal and the clock signal to compensate for a distance between the reference clock receiver and the I / O sensor.

14. An I / O sensor as claimed in any one of claims 1 to 13, wherein the delayed sampling device is a clock receiver having a reference voltage as an additional input, the reference voltage also serving as an input to the reference clock receiver.

15. The I / O sensor as claimed in any one of claims 1 to 13, wherein the delayed sampling device is a flip-flop.

16. The I / O sensor of any one of claims 1 to 15, further comprising: A timing measurement circuit is configured to measure a delay provided by the programmable delay line.

17. The I / O sensor of claim 16, wherein the timing measurement circuit comprises a ring oscillator circuit configured to selectively include the programmable delay line.

18. A non-transitory computer readable medium storing computer readable code for an I / O sensor, the computer readable code of the I / O sensor comprising: a programmable delay line; A delayed sampling device having the following inputs: a data signal which is also used as an input to a reference clock receiver configured to sample the data signal received from an interconnect channel between two integrated circuits (ICs) of a multi-IC module, and a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clock receiver; a comparison circuit configured to compare a data signal output of the delayed sampling device with a data signal output of the reference clock receiver; and A controller configured to: gradually adjusting a delay amount introduced by the programmable delay line, After each gradual adjustment of the delay amount, receiving the comparison result from the comparison circuit, and A connectivity quality between the two ICs on the interconnect channel is estimated based on at least one of the results and based on the amount of delay that caused the result.

19. The non-transitory computer-readable medium of claim 18, wherein the computer-readable code of the I / O sensor further comprises any one of the technical features of any one of claims 2 to 17.

Images