Latency and power efficient clock and data recovery in high speed single wire bidirectional buses

Abstract

A receive clock generated at a receiver coupled to a single wire bus is synchronized in each clock cycle, allowing for receiving infinite length data frames without clock overflow or underload. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in the output of the clock gating circuit. The clock gating circuit is disabled when the output of the counter indicates a pre-configured maximum count value. An edge synchronization circuit that synchronizes an edge in the basic clock signal with an edge in a data signal received through the single wire bus ignores the edge in the data signal when the counter output has a value less than the maximum count value, and resetting the counter in response to an edge detected in the data signal received through the single wire bus.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 861,886, filed on July 11, 2022, entitled “Latency And Power Efficient Clock And Data Recovery In A High-Speed ​​One-Wire Bidirectional Bus,” which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to serial communications, and more particularly to clock generation at a receiver coupled to a single-wire communications bus. Background Art

[0004] A mobile communication device may include various components including circuit boards, integrated circuit (IC) devices, and / or system-on-chip (SoC) devices. These components may include processing circuits, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus may operate according to a standardized protocol or a proprietary protocol. In one example, the serial bus operates according to an inter-integrated circuit (I2C bus or I2C) protocol. The I2C bus was developed to connect low-speed peripheral devices to a processor, wherein the I2C bus is configured as a multi-point bus. The two-wire I2C bus includes a serial data line (SDA) carrying a data signal and a serial clock line (SCL) carrying a clock signal. In another example, the improved inter-integrated circuit (I3C) protocol defined by the Mobile Industry Processor Interface (MIPI) Alliance derives certain specific implementation aspects from the I2C protocol including separate clock and data lines.

[0005] In another example, the radio frequency front end (RFFE) interface defined by the MIPI Alliance provides a communication interface for controlling various radio frequency (RF) front-end devices, including power amplifiers (PA), low noise amplifiers (LNA), antenna tuners, filters, sensors, power management devices, switches, etc. These devices can be co-located in a single IC device or provided in multiple IC devices. In another example, the system power management interface (SPMI) defined by the MIPI Alliance provides a hardware interface that can be implemented between a baseband or application processor and peripheral components. In some specific implementations, SPMI is deployed to support power management operations within the device.

[0006] Using a MIPI-defined serial bus instead of a parallel bus reduces the number of physical general-purpose input / output (GPIO) pins required to support communication between multiple devices. However, as device complexity increases, the demand for GPIO pins also increases, and there is a need for a more simplified bus architecture, including a bus architecture that supports communication through a single GPIO pin as well as through a single wire. Summary of the invention

[0007] Certain aspects of the present disclosure relate to systems, apparatus, methods, and techniques for implementing clock generation at a receiving device sufficient to support communication over a single-wire serial bus. The clock signal generated at the receiver is synchronized with each transition in a Manchester encoded signal that encodes the data bits. In some examples, the transmitter clock signal used to generate the Manchester encoded signal is reconstructed and can serve as a substitute for the clock signal originally sent over the two-wire serial bus. Phase and frequency errors can be accommodated, and accumulation of such errors is prevented. The single-wire link can format datagrams according to a protocol defined by RFFE, SPMI, or another standard.

[0008] In various aspects of the present disclosure, a clock and data recovery device includes an oscillator configured to generate a base clock signal having a base frequency; a clock gating circuit responsive to one or more control inputs and configured to output a gated base clock signal when the clock gating circuit is enabled; a first counter clocked by the gated base clock signal and configured to provide a counter output reflecting a count of positive edges and negative edges in the gated base clock signal; control logic coupled to a first control input of the clock gating circuit and configured to disable the clock gating circuit when the counter output corresponds to a maximum count value; and an edge synchronization circuit coupled to a single-wire bus. The edge synchronization circuit can be configured to ignore edges in a signal received from the single-wire bus when the counter output has a value less than the maximum count value, and reset the first counter in response to an edge detected in the signal received from the single-wire bus.

[0009] In various aspects of the present disclosure, a method of data communication includes configuring an oscillator to generate a base clock signal having a base frequency; configuring a clock gating circuit to output a gated base clock signal when the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs; configuring a first counter to provide a counter output reflecting a count of positive edges and negative edges in the gated base clock signal that clocks the first counter; configuring control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and configuring an edge synchronization circuit. The edge synchronization circuit may be configured to ignore edges in a signal received from a single-wire bus by the edge synchronization circuit when the counter output has a value less than the maximum count value, and to reset the first counter in response to an edge detected in the signal received from the single-wire bus.

[0010] In various aspects of the present disclosure, a data communication device includes a component for generating a basic clock signal having a basic frequency; a component for gating the basic clock signal, including a clock gating circuit responsive to one or more control inputs, the component for gating the basic clock signal being configured to output the gated basic clock signal when the clock gating circuit is enabled; a component for counting positive and negative edges in the gated basic clock signal, including a first counter clocked by the gated basic clock signal; a component for disabling the clock gating circuit, including control logic coupled to a first control input of the clock gating circuit, the component for disabling the clock gating circuit being configured to disable the clock gating circuit when the output of the first counter corresponds to a maximum count value; and a component for synchronizing the component for counting positive and negative edges in a signal received from a single-wire bus. The component for synchronizing may be configured to ignore edges in the signal received from the single-wire bus when the output of the first counter represents a value less than the maximum count value, and reset the first counter in response to an edge detected in the signal received from the single-wire bus.

[0011] In various aspects of the present disclosure, a computer readable medium stores code thereon, and the code, when executed by a processor in a processing circuit, causes the processing circuit to configure an oscillator to generate a base clock signal having a base frequency; configure a clock gating circuit to output a gated base clock signal when the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs; configure a first counter to provide a counter output reflecting a count of positive edges and negative edges in the gated base clock signal that clocks the first counter; configure control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and configure an edge synchronization circuit. The edge synchronization circuit may be configured to ignore edges in a signal received by the edge synchronization circuit from a single-wire bus when the counter output has a value less than the maximum count value, and further configured to reset the first counter in response to an edge detected in the signal received from the single-wire bus.

[0012] In one aspect, the signal received from the single-wire bus is Manchester encoded based on an encoding clock having a frequency four times the fundamental frequency of the fundamental clock signal. In one example, the encoding clock has a frequency of at least 52 MHz.

[0013] In one aspect, a clock and data recovery apparatus includes a flip-flop configured to capture a data bit from a single-wire bus in response to an edge detected in a signal received from the single-wire bus. A signal output by control logic that disables a clock gating circuit may be used to clock the flip-flop.

[0014] In one aspect, a signal output by control logic that disables the clock gating circuit is used to generate a write clock signal output by a clock and data recovery device.

[0015] In one aspect, the clock and data recovery device includes a second counter timed by a signal received from the single-wire bus. The second counter can be configured to drive a second control input of the clock gating circuit. The second counter can remain in a reset state when the single-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the single-wire bus. The second counter can be configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus. The clock gating circuit can be disabled until the second counter stops counting. The second counter can be reset when the output of the control logic that disables the clock gating circuit is used to generate a write clock signal output by the clock and data recovery device.

[0016] In one aspect, signals received from the single-wire bus carry datagrams configured according to a radio frequency front end (RFFE) protocol and encoded using Manchester encoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 An apparatus is illustrated that employs a data link between IC devices that selectively operates according to one of a plurality of available standards.

[0018] Figure 2 A first example of an apparatus employing a data link that may be used to communicatively couple two or more devices is illustrated.

[0019] Figure 3 A second example of an apparatus employing a data link that may be used to communicatively couple two or more devices including various radio frequency front end devices is illustrated.

[0020] Figure 4 Included is a timing diagram illustrating the signaling sent to delineate the boundaries of RFFE and SPMI datagrams.

[0021] Figure 5 Certain aspects relating to the timing of RFFE transactions performed over a data communications link are illustrated.

[0022] Figure 6 A system is illustrated in which a bus master device communicates with one or more single-wire slave devices in accordance with certain aspects disclosed herein.

[0023] Figure 7 An example of a single-wire serial interface that may be configured according to certain aspects of the present disclosure is illustrated.

[0024] Figure 8 Certain aspects of Manchester encoding and control signaling that may be used to exchange data between a bus master and a single-wire slave device in accordance with certain aspects of the present disclosure are illustrated.

[0025] Fig. 9 Included are timing diagrams illustrating arbitration transactions conducted on a single-wire serial bus configured or adapted according to certain aspects of the present disclosure.

[0026] Fig.10 A write transaction performed on a single-wire serial bus configured according to certain aspects disclosed herein is illustrated.

[0027] Fig.11 A read transaction performed on a single-wire serial bus configured according to certain aspects disclosed herein is illustrated.

[0028] Fig.12 A Manchester decoder that may be configured according to certain aspects disclosed herein is illustrated.

[0029] Fig.13 A data read transaction in a receiver equipped with a Manchester decoder configured according to certain aspects disclosed herein is illustrated.

[0030] Fig.14 A comparison of phase matched data read transactions and phase mismatched data read transactions using a Manchester decoder configured according to certain aspects disclosed herein is provided.

[0031] Fig.15 A first example of a clock and data recovery circuit that may be used to generate a receive clock and decode data in a Manchester decoder configured according to certain aspects of the present disclosure is illustrated.

[0032] Fig.16 Illustrated Fig.15 Certain aspects of the operation of the clock and data recovery circuit illustrated in FIG.

[0033] Fig.17 Certain aspects of a second example of a clock and data recovery circuit that may be used to generate a receive clock and decode data in a Manchester decoder configured according to certain aspects of the present disclosure are illustrated.

[0034] Fig.18 Certain aspects of examples of clock generators that may be used in clock and data recovery circuits configured according to certain aspects of the present disclosure are illustrated.

[0035] Fig.19 One example of an oscillator that may be implemented in an IC device according to certain aspects of the present disclosure is illustrated.

[0036] Fig. 20 An RFFE interface is illustrated where a conventional two-wire RFFE interface can be coupled to a single-wire serial bus.

[0037] Fig.21 One example of an apparatus employing processing circuitry that may be adapted according to certain aspects disclosed herein is illustrated.

[0038] Fig. 22 is a flow chart illustrating a method for communicating data at a bus master according to certain aspects disclosed herein.

[0039] Fig.23 Examples of hardware implementations for apparatus adapted according to certain aspects disclosed herein are illustrated. DETAILED DESCRIPTION

[0040] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations with which the concepts described herein can be practiced. In order to provide a thorough understanding of the various concepts, the specific embodiments include specific details. However, it is obvious to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid blurring such concepts, known structures and components are shown in block diagram form.

[0041] Several aspects of the present invention will now be described with reference to various devices and methods. These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0042] Certain aspects of the present disclosure relate to the communication of digital signals including transitions between two or more signaling states. For the purposes of this description, a transition between two signaling states in a digital signal may be referred to as an edge. A transition from a low voltage signaling state to a higher voltage signaling state may be referred to as a positive edge, a positive transition, a rising edge, a rising transition, or a positive transition edge. A transition from a higher voltage signaling state to a low voltage signaling state may be referred to as a negative edge, a negative transition, a falling edge, a falling transition, or a negative transition edge.

[0043] Certain aspects of the present disclosure relate to serial bus configurations in which multiple devices can communicate at various times. The described serial bus is generally operated in a hierarchical manner because one device controls the communication during a transaction. The control device may be referred to as a host device, a bus master, a management device, or another term supported by a standard that defines the protocol implemented by the control device. In some serial bus configurations, a single control device manages or controls the communication during all transactions performed by the serial bus. In other serial bus configurations, for each transaction performed by the serial bus, multiple devices may operate as control devices, and one device is used as a control device. The control device may provide a common clock signal sent through a conventional two-wire serial bus. The control device may provide control signaling that identifies the type of transaction to be performed through a conventional two-wire serial bus. During certain transactions, the control device may use address information provided in or with the command to send commands directed to one or more receiving devices. The receiving device may be referred to as a client device, a slave device, an accessory device, a peripheral device, or another term supported by a standard that defines the protocol implemented by the control device. For the purposes of this disclosure, the control device will be referred to as a bus master, and the associated receiving device will be referred to as a slave device.

[0044] Overview

[0045] Devices including multiple SoCs and other IC devices typically employ a shared communication interface that may include a serial bus or other data communication link to connect the processor to a modem and other peripherals. The serial bus or other data communication link may operate according to multiple standards or protocols. For example, the serial bus may operate according to I2C, I3C, SPMI, and / or RFFE protocols or another protocol that may be configured for half-duplex operation. The increased functionality and complexity of the operations involving devices coupled to the serial bus, as well as the tighter timing constraints imposed to support applications, peripherals, and sensors may result in greater demands on GPIO pins and communication link throughput.

[0046] Certain aspects of the present disclosure relate to techniques for communicating over a single-wire bus using Manchester encoding and synchronization signaling that can be distinguished by devices coupled to the single-wire bus. The synchronization signaling can be configured to enable a receiving device to synchronize a clock signal generated in a device currently transmitting over the single-wire bus. In one aspect, the bus master device can be adapted to format datagrams according to an RFFE or SPMI protocol. A clock generation circuit is described herein that can be used in a slave device to generate a receive clock from certain transitions in a Manchester encoded signal. The receive clock can be resynchronized in each bit transmission interval, thereby eliminating the possibility of cumulative effects of transmission errors on the phase and frequency of the Manchester encoded signal or on the receive clock.

[0047] According to certain aspects of the present disclosure, a receive clock generated at a receiver coupled to a single-wire bus is synchronized in each clock cycle, thereby allowing the reception of data frames of unlimited length without clock overflow or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in the output of the clock gating circuit. When the output of the counter indicates a preconfigured maximum count value, the clock gating circuit is disabled. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received via the single-wire bus ignores edges in the data signal when the counter output has a value less than the maximum count value, and resets the counter in response to an edge detected in a signal received from the single-wire bus. The edge synchronization circuit can synchronize edges in the base clock signal with edges that first appear in the data signal after the counter output reaches the maximum count value.

[0048] Certain aspects disclosed herein provide protocols that can replace or supplement serial bus protocols, such as I2C, I3C, SPMI, and / or RFFE protocols. Certain aspects are applicable to serial buses operating in half-duplex mode or full-duplex mode.

[0049] Example of a device using a serial data link

[0050] According to certain aspects of the present disclosure, a serial data link may be used to interconnect electronic devices that are subcomponents of devices such as: a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a Global Positioning System (GPS) device, a smart home device, smart lighting, a multimedia device, a video device, a digital audio player (e.g., an MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multi-rotor helicopter, or any other similarly functional device.

[0051] Figure 1 An example of an apparatus 100 that may employ a data communication bus is illustrated. The apparatus 100 may include a processing circuit 102 having a plurality of circuits or devices 104, 106, and / or 108, which may be implemented in a SoC or one or more ASICs. In one example, the apparatus 100 may be a communication device, and the processing circuit 102 may include a processing device provided in an ASIC 104, one or more peripheral devices 106, and a transceiver 108 that enables the apparatus to communicate with a radio access network, a core access network, the Internet, and / or another network via an antenna 124.

[0052] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuit 116, and / or other logic circuits or functions. Processing circuit 102 may be controlled by an operating system, which may provide an application programming interface (API) layer that enables one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage 122 provided on processing circuit 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage 122. ASIC 104 may access its onboard memory 114, processor-readable storage 122, and / or storage devices external to processing circuit 102. Onboard memory 114, processor-readable storage 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that may be used in processing systems and computing platforms. The processing circuit 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating the device 100 and / or the processing circuit 102. The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disk or hard disk, etc. The processing circuit 102 may also be operatively coupled to external devices such as an antenna 124, a display 126, operator controls (such as switches or buttons 128, 130 and / or an integrated or external keyboard 132), and other components. The user interface module may be configured to operate with the display 126, external keyboard 132, etc., through a dedicated communication link or through one or more serial data interconnects.

[0053] The processing circuit 102 may provide one or more buses 118a, 118b, 120 that enable certain devices 104, 106, and / or 108 to communicate. In one example, the ASIC 104 may include a bus interface circuit 116 that includes a combination of circuits, counters, timers, control logic, and other configurable circuits or modules. In one example, the bus interface circuit 116 may be configured to operate according to a communication specification or protocol. The processing circuit 102 may include or control power management functions that configure and manage the operation of the apparatus 100.

[0054] Figure 2 A first example of an apparatus 200 employing a data link that can be used to communicatively couple two or more devices is illustrated. Here, the apparatus 200 includes a plurality of devices 202 and 2220-222 coupled to a two-wire serial bus 220. N . Devices 202 and 2220-222 NThe devices 202 and 2220-222 may be implemented in one or more semiconductor IC devices such as application processors, SoCs, or ASICs. N Some of the devices in the embodiment may include, support, or operate as a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, and / or other such components or devices. In some examples, one or more devices 2220-222 may be used. N To control, manage or monitor the sensor device. Devices 202 and 2220-222 N Communications between the serial bus 220 are controlled by a bus master 202. Some types of buses may support multiple bus masters 202.

[0055] In one example, the bus master 202 may include an interface controller 204 that manages access to the serial bus, configures a dynamic address for the slave device, and / or generates a clock signal 228 to be sent on the clock line 218 of the serial bus 220. The bus master 202 may include a configuration register 206 or other storage device 224 and other control logic 212 configured to process protocols and / or higher-level functions. The control logic 212 may include processing circuits such as a state machine, a sequencer, a signal processor, or a general-purpose processor. The bus master 202 includes a transceiver 210 and line drivers / receivers 214a and 214b. The transceiver 210 may include a receiver, a transmitter, and a common circuit, wherein the common circuit may include timing, logic, and storage circuits and / or devices. In one example, the transmitter encodes and sends data based on the timing in the clock signal 228 provided by the clock generation circuit 208. The control logic 212 and other functions, circuits, or modules may use other timing clocks 226.

[0056] One or more devices 2220-222 NIt can be configured to operate as a slave device. In some examples, the slave device may include circuits and modules that support displays, image sensors, and / or control one or more sensors that measure environmental conditions and communicate with them. In one example, the device 2220 configured to operate as a slave device may provide a control function, module or circuit 232, which includes circuits and modules for supporting displays, image sensors, and / or control one or more sensors that measure environmental conditions and communicate with them. In this example, the device 2220 may include a configuration register 234 or other storage device 236, a control logic 242, a transceiver 240, and line drivers / receivers 244a and 244b. The control logic 242 may include processing circuits such as a state machine, a sequencer, a signal processor, or a general processor. The transceiver 240 may include a receiver, a transmitter, and a common circuit, wherein the common circuit may include timing, logic, and storage circuits and / or devices. In one example, the transmitter encodes and sends data based on the timing in the clock signal 248 provided by the clock generation and / or recovery circuit 246. In some examples, clock signal 248 may be derived from a signal received from clock line 218. Other timing clocks 238 may be used by control logic 242 and other functions, circuits, or modules.

[0057] The serial bus 220 may operate according to RFFE, I2C, I3C, SPMI, or other protocols. Devices 202 and 2220-222 N At least one of the devices 202 and 2220-222 may be configured to operate as a bus master and a slave on the serial bus 220. N Two or more of the two-wire serial bus 220 may be configured to operate as a bus master on the serial bus 220. The protocol selected for controlling the operation of the serial bus 220 may define direct current (DC) characteristics that affect certain signal levels associated with the serial bus 220, and / or alternating current (AC) characteristics that affect certain timing aspects of signals sent on the serial bus 220. In various examples, the two-wire serial bus 220 sends data on the data line 216 and sends a clock signal on the clock line 218. In some instances, the data may be encoded in the signaling states, or transitions in the signaling states of the data line 216 and the clock line 218.

[0058] Figure 3A second example of an apparatus 300 employing a data link that can be used to communicatively couple two or more devices is illustrated. In this example, a chipset or device 302 employs multiple RFFE buses 330, 332, 334 to couple various RF front-end devices 318, 320, 322, 324, 326, 328. A modem 304 includes an RFFE interface 308 that couples the modem 304 to a first RFFE bus 330. The modem 304 can communicate with a baseband processor 306 and a radio frequency IC (RFIC 312) via one or more communication links 310, 336. The illustrated device 302 can be embodied in one or more of a mobile communication device, a mobile phone, a mobile computing system, a laptop, a tablet computing device, a media player, a gaming device, a wearable computing device, and / or a communication device, an appliance, and the like.

[0059] In various examples, the device 302 may be implemented with one or more baseband processors 306, a modem 304, an RFIC 312, multiple communication links 310, 336, multiple RFFE buses 330, 332, 334, and / or other types of buses. The device 302 may include other processors, circuits, modules, and may be configured for various operations and / or different functions. Figure 3 In the illustrated example, the modem is coupled to the RF tuner 318 via its RFFE interface 308 and a first RFFE bus 330. The RFIC 312 may include one or more RFFE interfaces 314, 316, controllers, state machines, and / or processors that configure and control certain aspects of the RF front end. The RFIC 312 may communicate with the PA 320 and the power tracking module 322 via a first RFFE interface and a second RFFE bus 332 in its RFFE interface 314. The RFIC 312 may communicate with the switch 324 and one or more LNAs 326, 328 via a second RFFE interface and a third RFFE bus 334 in its RFFE interface 316.

[0060] Bus latency may affect the ability of a serial bus to handle high priority, real-time, and / or other time-constrained messages. Low latency messages or messages requiring low bus latency may involve sensor states, real-time events generated by devices, and virtualized GPIO states. In one example, bus latency may be measured as the time elapsed between the time a message becomes available for transmission and the delivery of the message or the start of the transmission of the message in some instances. Other measurements of bus latency may be used. Bus latency typically includes delays incurred when sending higher priority messages, interrupt processing, the time required to terminate a datagram in a process on a serial bus, the time to send a command that turns the bus between a transmit mode and a receive mode, bus arbitration, and / or the transmission of commands specified by a protocol.

[0061] In some examples, the latency sensitive messages may include coexistence messages. Coexistence messages are sent in a multi-system platform to prevent or reduce situations where certain types of devices conflict with each other, including, for example, switches 324, LNAs 326, 328, PAs 320, and other types of devices operating concurrently in a manner that may generate inter-device interference or may potentially cause damage to one or more devices. Devices that may interfere with each other may exchange coexistence management (CxM) messages to permit each device to signal an impending action that may cause interference or conflict. CxM messages may be used to manage the operation of shared components including switches 324, LNAs 326, 328, PAs 320, and / or antennas.

[0062] Multi-point interfaces (such as RFFE, SPMI, I3C, etc.) can reduce the number of physical input / output (I / O) pins used to communicate between multiple devices. Protocols that support communication over a multi-point serial bus define datagram structures for sending command, control, and data payloads. The datagram structures for different protocols define certain common features, including addressing, clock generation and management, interrupt handling, and device priority for selecting a device to receive or send data. In the present disclosure, the example of the RFFE protocol may be used to illustrate certain aspects disclosed herein. However, the concepts disclosed herein are applicable to other serial bus protocols and standards.

[0063] Figure 4 406. The RFFE protocol includes timing diagrams 400, 420 illustrating signaling sent to delineate the boundaries of a datagram sent in accordance with the RFFE protocol. The timing diagrams 400, 420 show the relative timing of signals sent on a two-wire serial bus that provides a clock signal on SCLK 402 and provides data exchange over SDATA 404. The first timing diagram 400 illustrates the timing of a sequence start condition (SSC 408) that is sent to signal the start of a transaction, such as the transmission of a datagram 410. The SSC 408 is sent when the serial bus is in an idle state 406. In the idle state 406, the SCLK 402 is driven at full strength by the bus master, while slave devices coupled to the serial bus present a high impedance to the SCLK 402. The SCLK 402 is held in a low signaling state (here, zero volts) by the bus master. In the idle state 406, SDATA 404 is driven weakly by the bus master or is held in a weakly driven low signaling state 412 using a keeper circuit or a weak pull-down circuit. For example, when the bus master has put its line driver into a high impedance state, and when no other device is driving SDATA 404, the keeper circuit or weak pull-down circuit can maintain the signaling state of SDATA 404. The weakly driven low signaling state 412 can be easily overcome by another line driver that can drive SDATA 404 at full strength.

[0064] In the master driven SSC 408, the bus master begins transmission of the SSC 408 at a first point in time 414 when the bus master begins driving the SDATA 404, which is initially in a low signaling state, at full strength. The bus master then provides a pulse 416 on the SDATA 404 while continuing to drive the SCLK 402 to a low signaling state. The pulse 416 has a duration of at least one cycle of the clock signal provided on the SCLK 402 during the transmission of the datagram 410. At a second point in time 418, the bus master begins to send clock pulses on the SCLK 402, thereby providing a clock signal for controlling or indicating the timing of the datagram 410 sent on the SDATA 404.

[0065] For example, the second timing diagram 420 illustrates the timing of a bus park cycle (BPC 424) that may be sent to signal the termination of a datagram 422. The BPC 424 is sent by providing a falling edge 428 on SDATA 404 when SCLK 402 is in a high signaling state 430. By the protocol, transitions on SDATA 404 during the transmission of a datagram 422 are permitted only when the clock signal is in a low signaling state, and the falling edge 428 that occurs when SCLK 402 is in a high signaling state 430 is interpreted as control signaling (i.e., BPC 424). The falling edge 428 is provided by the bus master driving SDATA 404 low at full strength. The bus master then drives SCLK 402 low and continues to drive SCLK 402 at full strength through subsequent bus idle intervals 426, 436. After driving SCLK 402 low, the bus master initiates a bus idle interval 436 at time 432 when it puts its line drivers into a high impedance state. When no other device is driving SDATA 404, SDATA 404 remains in a weakly driven low signaling state 434. BPC 424 is terminated and the serial bus enters a bus idle interval 426 until the next datagram is ready to be sent.

[0066] Figure 5Certain aspects related to the timing of an RFFE transaction 500 performed over a data communication link are illustrated. The transaction 500 begins at time 508 with a bus arbitration procedure 512 in which the initiating device indicates a desire to write or read data over the data communication link by driving SDATA 504. The bus arbitration procedure 512 is performed to determine the highest priority device seeking to use the data communication link. Device priority may be determined based on a device identifier, and the highest priority device participating in the bus arbitration procedure 512 is typically granted control of the data communication link. Initially, SDATA 504 is weakly driven by the bus master or maintained in a weakly driven low signaling state using a keeper circuit or a weak pull-down circuit. For example, when the bus master has put its line driver into a high impedance state, and when no other device is driving SDATA 504, the keeper circuit or weak pull-down circuit may maintain the signaling state of SDATA 504. The weakly driven low signaling state may be easily overcome by another line driver that is capable of driving SDATA 504 at full strength.

[0067] At time point 508, the initiating device initiates a first pulse 510 on SDATA 504. Consistent with the RFFE protocol, the current bus master provides a clock signal on SCLK 502 after detecting a rising edge 520, and the initiating device releases SDATA 504 during the first clock cycle. The bus master then drives SDATA 504 to provide a falling edge 522 of the first pulse 510 before configuring its line driver for high impedance mode and re-entering SDATA 504 into a weakly driven low signaling state. Devices seeking control of the data communication link then attempt to send their respective addresses. Upon detecting a higher priority address, the participating devices exit from the bus arbitration procedure 512. The device that successfully sends its entire address wins the bus arbitration procedure 512. In the illustrated example, a sequence start condition (SSC 514) is sent after completing the bus arbitration procedure 512 to start a transaction 516 involving the winning device. According to some protocols, the winning device may take control of the transaction 516 and provide the SSC 514 by sending a second pulse 524 on SDATA 504 while the clock signal on SCLK 502 is held in a low signaling state.

[0068] In response to the continuous demand for improved performance and capabilities, wireless communication devices continue to use an increasing number of RF interfaces to provide more functions, which has led to increased circuit complexity. With the introduction of newer process technologies to meet the demand for higher operating frequencies, the physical size of IC circuits has been decreasing. The reduction in the size of IC devices and the increase in the number of RF front-end circuits and other types of interfaces have created an insatiable demand for input / output (I / O) pins for interconnecting IC devices. It is generally expected that the serial bus will be reduced to a single-line operation by eliminating the transmission of clock signals between devices coupled to the serial bus. In the example of RF front-end devices, the elimination of the clock line may be difficult to achieve without compromising data throughput.

[0069] Conventional single-wire interfaces typically operate at limited speeds, with throughput in the range of 32kHz to 4MHz. These single-wire interfaces may send data without any clock information, or may use techniques that limit the available data rate or transaction size to send data with embedded clock information. For example, due to phase shift, frequency mismatch, noise, and other interference, the derived receive clock signal may lose synchronization with the transmitter clock after a certain number of clock cycles.

[0070] In one example, a simple UART-based interface does not use a separate clock line and does not embed clock information in the transmitted data. The transmitting and receiving sides rely on a priori knowledge of the bit rate and use a local oversampled clock to encode and decode the data bits. This approach is limited in speed due to the inherent clock phase and frequency mismatch between the two sides and imposes a limit on the number of bits that can be packed between the start and stop bit intervals.

[0071] The throughput limitation can be improved by using clock generation circuits that employ delay locked loops (DLLs), phase locked loops (PLLs), or synchronization circuits. However, these synchronization circuits are often too complex and power consuming for many mobile communication applications, which require clock generation circuits that consume no more than 1uA-2uA in standby mode and can transition from standby mode to a stable full rate mode with a delay of no more than 150ns. Conventional clock generator circuits that meet these criteria are not available for use in mobile communication devices.

[0072] Certain aspects disclosed herein relate to a low-cost, low-complexity clock generator circuit that employs robust phase synchronization to derive a receive clock for high-speed serial bus operations. The currently disclosed clock generator circuit can be used to implement a single-wire serial bus based on I2C, I3C, SPI, SPMI, RFFE, or other standard-defined or proprietary protocols. Full high-speed data rates can be achieved without using a separate clock line. The clock generator circuit disclosed in the present invention can ensure a high degree of robustness (10 kHz to 40 kHz) under very high clock variations from the nominal frequency (+ / - 5% to 15%). -9 The clock generator circuit disclosed in the present invention can minimize power consumption and IC die area occupation.

[0073] According to certain aspects disclosed herein, a protocol for controlling single-wire serial bus operation may be adapted from a protocol defined for two-wire operation. Certain aspects of a serial multi-drop protocol selected for controlling and managing transmissions over a single-wire serial bus may be adapted, configured, or modified to support arbitration, line turnaround, and transmissions performed without an explicit clock reference (such as a clock signal sent on a dedicated clock line).

[0074] In various examples provided herein, examples of single-wire serial buses are described in which data and commands are configured according to the RFFE protocol. However, these concepts are not limited to the RFFE protocol, and various aspects of the present disclosure are equally applicable to I2C, I3C, SPI, SPMI, and other standard-defined or proprietary protocols. The single wire of the single-wire serial bus is used as a data line for bidirectional transmission of control and data signaling. According to certain aspects of the present disclosure, timing for communication between single-wire slave devices coupled to the serial bus can be embedded in the data transmission, and control signaling can be provided to synchronize clock signals at the transmitter and receiver.

[0075] Figure 6 1-604 according to certain aspects disclosed herein wherein a bus master device 602 and one or more single-line slave devices 6041-604 N The system 600 of the present invention is a system for communication. A bus master 602 may be provided in an RFIC, a modem, an application processor, or another type of device. The bus master 602 may be adapted to communicate with single-line slave devices 6041-604 via a single line. N To exchange data, this single line is referred to in the illustrated system 600 as an SDATA line 606. The data is encoded in a signal sent over the SDATA line 606, where the signal includes embedded clock information that can be used by a receiving device to decode the data from the signal.

[0076] Bus master device 602 and single-wire slave devices 6041-604 NTypically includes corresponding protocol controllers 608, 6101-610 N . Protocol controller 608, 6101-610 N The bus master 602 may include a processor, controller, state machine, or other logic circuit configured to support one or more protocols. The protocol controller 608 in the bus master 602 may be further configured to manage communications over the SDATA line 606. In some examples, the protocol controller 608 performs some of the functions of the bus master. In some implementations, the protocol controller 608 in the bus master 602 may be used to configure the single-wire slave devices 6041-604 N The bus master device 602 may determine the single-wire slave devices 6041-604 as the designated recipients of the data to be sent via the SDATA line 606. N The configuration and can enable the protocol controller 608 to send and address to the single-wire slave devices 6041-604 through the SDATA line 606 N The signal pair is intended for use by the receiving single-wire slave device 6041-604 N Encode the data.

[0077] The bus master 602 may include a transmit clock generator 612 that may be used to define the timing of transmissions over the SDATA line 606. N Each of the local clock generation circuits 6141-614 N , which provides corresponding protocol controllers 6101-610 N The timing of the local clock generation circuit 6141-614 N A sync pulse may be used which is sent by the bus master 602 after the SSC, or by the bus master 602 or by the single-line slaves 6041-604 after a line turnaround. N According to certain aspects of the present disclosure, the local clock generation circuits 6141-614 N Transitions in the Manchester encoded command and data payload sent over the SDATA line 606 may be used for synchronization. Local clock generation circuits 6141-614 N A ring oscillator or a delay locked loop may be included. In some implementations, the local clock generation circuits 6141-614 N An injection locked oscillator is included that responds to synchronization pulses and / or transitions in Manchester encoded command and data payload transmissions.

[0078] The keeper circuit 616 can be coupled to the SDATA line 606 to facilitate line turnaround, in-band interrupt requests, or arbitration procedures according to certain aspects disclosed herein. In one example, the keeper circuit 616 can be configured as a positive feedback circuit that drives the SDATA line 606 through a high impedance output and receives feedback from the SDATA line 606 through a low impedance input. The keeper circuit 616 can be configured to maintain the last asserted signaling state or voltage on the SDATA line 606. The keeper circuit 616 can be used by the bus master device 602 or the single-line slave devices 6041-604 N The active line driver in one of the two is easily overcome.

[0079] Conventional implementations of single-wire bidirectional communication buses are hampered by restrictively slow data rates. Many conventional single-wire bidirectional communication buses are limited to less than megahertz (MHz) signaling rates and are not suitable for high-speed RF front-end control applications that may require clock rates of 52 MHz or higher. Some conventional single-wire bidirectional communication buses attempt to increase data rates by using pulse width modulation and other data encoding schemes. However, for example, due to various limitations of PWM signaling, these latter communication buses are generally unable to achieve signaling rates greater than 4 MHz.

[0080] A single-wire bidirectional communication bus implemented according to certain aspects of the present disclosure can achieve a data rate of at least 52 MHz. In some examples, a signaling scheme provided for communication over a single-wire communication bus uses a combination of RFFE protocol, Manchester encoding, and modified control signaling that can indicate and distinguish various types of transactions.

[0081] According to certain aspects of the present disclosure, clock phase and frequency synchronization at a receiver coupled to a single-wire serial bus is obtained and maintained by using Manchester encoding. Manchester encoding embeds clock information in each bit sent through the single-wire serial bus by requiring each bit to include a transition in the middle of a bit transmission interval. According to one aspect of the present disclosure, a receive clock signal can be resynchronized for each bit of Manchester encoding received in a data stream. Synchronization implemented at the bit transmission rate can eliminate the cumulative effects of phase and frequency changes, and can ensure error-free data recovery with an unlimited data frame length.

[0082] In one aspect, higher power efficiency can be achieved by using Manchester encoding. State transitions of the interface can be detected and used to disable or enable an oscillator in the receive clock generation circuit. For example, the oscillator can be enabled when the start of frame (SoF) is detected, and can be disabled when the end of frame (EoF) is detected, thereby saving energy by avoiding the need for a normally open free-running oscillator.

[0083] In some implementations, a clock stability delay interval can be defined or configured to define a delay between the SoF and the transmission of the first data bit. The programmable clock stability delay interval can be configured and / or calibrated to minimize the delay imposed in achieving phase synchronization of the receive clock.

[0084] In some implementations, one or more programmable clock phase synchronization (CPS) pulses may be sent to serve as edge-sensitive phase synchronization triggers. In one example, a CPS pulse is sent after the SoF is sent and before the data bits are sent. In another example, the first CPS pulse sent serves as the SoF and may be followed by one or more additional CPS pulses before the sending of the data bits. In some instances, each CPS pulse is sent in a single clock cycle and both edges of the pulse are used for synchronization. In some instances, each CPS pulse is sent in two clock cycles and one edge of the pulse is used for synchronization.

[0085] In some implementations, the receive clock generation circuit is a bit rate sensitive independent clock and can be programmed or configured. In one example, the receive clock generation circuit can be enabled or disabled based on the state of the single-wire serial bus. In some instances, an out-of-loop control circuit can be used to configure the frequency of the receive clock generation circuit. Frequency control can be implemented to adapt to variable operating conditions, including conditions affected by process, voltage, temperature (PVT) variations or corners.

[0086] In one example, the receive clock generation circuit includes a flip-flop chain configured as a clock divider. One or more flip-flops in the flip-flop chain can be configured to define edge triggering modes, reset or preload values ​​and options, and clock gating functions. The flip-flop chain can be configured to reduce the frequency of the output clock signal by integer division of the input or master clock signal. The flip-flop chain can be configured to control the duty cycle and phase of its output clock signal.

[0087] Figure 7 1 illustrates an example of a single-wire serial interface 700 that may be configured according to certain aspects of the present disclosure. In this example, a bus master device 602 and a single-wire slave device 604 are illustrated. N (See Figure 6 ). The bus master device 602 includes a protocol controller 702. The protocol controller 702 may be implemented using a processor, a microcontroller, or a finite state machine, and may be used to control the transmit and receive functions of the bus master device 602. The protocol controller 702 may include or be coupled to a signal generating circuit 704 that generates a signal when coupling the bus master device 602 to one or more slave devices 604. NThe signal generation circuit 704 can be configured to generate different types of SSC to initiate arbitration, initiate data transmission, or abandon arbitration. The signal generation circuit 704 can be configured to generate a synchronization pulse that is used to enable the slave device 604 to N The clock signal generated at is synchronized with the transmit clock signal generated in the bus master device 602.

[0088] The protocol controller 702 may be configured to selectively activate the Manchester encoder 706 and the Manchester decoder 708 based on the operating mode of the single-wire serial interface 700. The Manchester decoder 708 may extract data and clock information from the signal received from the SDATA line 720. The protocol controller 702 may be further configured to format a datagram for transmission over the SDATA line 720. The protocol controller 702 may be further configured to generate commands to be transmitted over the SDATA line 720.

[0089] In the illustrated example, the single-wire slave device 604 N The protocol controller 722 is included. The protocol controller 722 can be implemented using a processor, a microcontroller, or a finite state machine and can be used to control the single-wire slave device 604. N The protocol controller 722 may include or be coupled to a signal generating circuit 724, which generates a signal when the single-line slave device 604 N The protocol controller 722 may further be configured to cause the signal generation circuit 724 to drive the SDATA line 720 to initiate the SSC in an in-band interrupt procedure, and may further be configured to cause the signal generation circuit 724 to drive the SDATA line during an arbitration procedure. The synchronization pulse generated by the signal generation circuit 704 may be configured to synchronize the clock signal generated at the bus master device 602 with the clock signal generated at the slave device 604. N Synchronize with the transmit clock signal generated in .

[0090] The protocol controller 722 may be configured to selectively activate the Manchester encoder 726 and the Manchester decoder 728 based on the operating mode of the single-wire serial interface 700. The Manchester decoder 728 may extract data and clock information from the signal received from the SDATA line 720. The protocol controller 722 may be further configured to format a datagram for transmission over the SDATA line 720. The protocol controller 722 may be further configured to decompose the datagram and / or respond to commands received from the SDATA line 720.

[0091] The protocol controller 702 may be configured to manage and control the operation of the line driver 712 and the line receiver 710. The protocol controller 722 may be configured to manage and control the operation of the line driver 732 and the line receiver 730. When not activated or disabled, the line drivers 712, 732 may present a high impedance to the SDATA line 720. For example, when the single-wire slave device 604 N When configured or expected to send data or control signals via the SDATA line 720, the output of the line driver 712 in the bus master 602 may present a high impedance to the SDATA line 720. When the bus master 602 is driving the SDATA line 720, the single-line slave device 604 N The output of the line driver 732 in is normally in a high impedance state.

[0092] The keeper circuit 740 coupled to the SDATA line 720 facilitates line turnaround, in-band interrupt requests, and arbitration procedures in a bidirectional single-wire serial bus. It is often desirable to maintain the state of the SDATA line 720 when all devices are in high impedance mode, during line turnaround, or in arbitration procedures. Line turnaround occurs when the bus master device 602 transitions from transmit to receive or from receive to transmit. During arbitration procedures, when a single-wire slave device 604 N The bus master 602 may enter a high impedance mode when it has the option to transmit and the line driver in the bus master 602 may present a high impedance to the SDATA line 720 to avoid contention. A keeper circuit 740 may be used to maintain the state of the SDATA line 720. In one example, the keeper circuit 740 may be configured as a positive feedback circuit that drives the SDATA line 720 through a high impedance output and receives feedback from the SDATA line 720 through a low impedance input. The keeper circuit 740 may be configured to maintain the last asserted voltage on the SDATA line 720. The keeper circuit 740 may be respectively controlled by the bus master 602 and the single-line slave 604. N The line drivers 712, 732 in FIG.

[0093] Figure 8 606 (see Figure 6 ) between the bus master device 602 and the single-line slave devices 6041-604 N800. As shown in the first timing diagram 800, Manchester encoding encodes data based on the direction of the transition that occurs in the middle of the bit transmission interval 802. For example, the signal line may initially be in a low state and the transition 804 to the high state indicates a '0' value bit. The signal line may initially be in a high state and the transition 806 to the low state indicates a '1' value bit. Clock information is embedded in the data signal in the transition that occurs within each bit transmission interval 802.

[0094] The second timing diagram 810 illustrates five bit transmission intervals 814a-814e in the signal carried on SDATA 812. The bit sequence {0,0,1,1,0} is transmitted in the five bit transmission intervals 814a-814e, and transitions within each of the five bit transmission intervals 814a-814e are illustrated. It will be observed that transitions may occur at some boundaries between the bit transmission intervals 814a-814e, and no transitions occur at other boundaries between the bit transmission intervals 814a-814e.

[0095] The third timing diagram 820 illustrates certain aspects of the timing associated with the transmission of an 8-bit data frame 822 through a single-line serial bus. The data frame 822 may be serialized and provided to a Manchester encoder in a data signal 824. In some implementations, the Manchester encoder receives parallel data for encoding, or accesses a data frame stored in a transmit buffer. The Manchester encoder may encode data according to the timing provided by a transmit clock signal 826. In one example, the frequency of the transmit clock signal 826 may be 52 MHz. The Manchester encoder generates a Manchester encoded signal 828 for transmission through a single-line serial bus.

[0096] At the receiving device, the Manchester encoded signal 828 is provided to a Manchester decoder. The Manchester decoder may include or be coupled to a clock generation circuit configured to generate a receive clock signal 830 to be used to decode data from the Manchester encoded signal 828. The clock generation circuit may include one or more oscillators, one or more frequency dividers, and a phase synchronization circuit. The phase synchronization circuit may be configured to synchronize the receive clock signal 830 based on timing information derived from the Manchester encoded signal 828. The timing information includes a transition 834 of the Manchester encoded signal 828 at the center of each bit transmission interval 832.

[0097] In the illustrated example, each falling edge 838 in the receive clock signal 830 is delayed relative to the corresponding falling edge 836 in the transmit clock signal 826. The delay 840 between the associated falling edges 836, 838 can be configured to provide sufficient setup and hold time for sampling circuits in the receiver device. The delay 840 between the associated falling edges 836, 838 can be configured to provide tolerance for phase offsets between the transmit clock signal 826 and the receive clock signal 830, including transient phase offsets caused by noise affecting the single-wire serial bus and phases caused by loss of synchronization or incomplete synchronization.

[0098] According to certain aspects of the present disclosure, a single-wire serial bus may be configured, managed, controlled and / or monitored according to a standard-defined or proprietary protocol. For the purposes of this description, an example of an RFFE protocol will be illustrated. However, these concepts are not limited to the RFFE protocol, and various aspects of the present disclosure are equally applicable to I2C, I3C, SPI, SPMI, and other standard-defined or proprietary protocols. For example, other protocols employ or may be adapted to use similar arbitration schemes, SoF and EoF signaling, command structures, and datagram or data frame configurations. In some instances, a protocol defined for use with a two-wire serial bus may be adapted to implement features such as line turnaround for controlling a single-wire serial bus.

[0099] Fig. 9 A timing diagram 900 is included to illustrate arbitration transactions 904 performed on a single-wire serial bus configured or adapted according to certain aspects of the present disclosure. The single-wire serial bus has an interconnect or line (SDATA 902) configured to carry bidirectional data between two or more devices. The bus master manages the operation of the single-wire serial bus by providing control signaling, which can indicate, for example, the beginning of a datagram, the end of a datagram, the beginning of an interruptible transaction, and the abandonment of an interruption processing (arbitration) procedure. The bus master also uses a signaling and encoding technique configured to realize clock synchronization from a device and realize data exchange during read and write operations. In one example, control signaling based on the SSC length can be used to adapt to interruptions, and / or to abandon interrupt signaling to support the processing of a higher priority message newly received.

[0100] In the illustrated example, the duration of SSC 906 can be controlled by the bus master. Initially, SDATA 902 is in an idle state, driven weakly low by the bus master, or using, for example, Figure 6 and Figure 7The keeper circuit 616 or 740 or the weak pull-down circuit illustrated in FIG. 6A is maintained in a weakly driven low signaling state. For example, when the bus master has put its line driver into a high impedance state and when no other device is driving SDATA 902, the keeper circuit or the weak pull-down circuit can maintain the signaling state of SDATA 902. The weakly driven low signaling state can be easily overcome by an active line driver that can drive SDATA 902 at full strength, such as the line driver 712 in the bus master 602 or the single-line slave 604. N A line driver 732 in one of the.

[0101] The bus master may initiate the SSC 906, or one or more slave devices may drive the SDATA 902 to initiate the SSC 906 by driving the SDATA 902 high during a bus idle cycle. In the case where the SSC 906 is initiated by a slave device, the slave device may initiate the SSC 906 after the SDATA 902 has been idle for a minimum period of time defined by the protocol and / or preconfigured during system initialization. It is expected that the slave device releases the SDATA 902 by causing its line driver coupled to the SDATA 902 to present a high impedance to the SDATA 902 within one clock cycle of an internally generated clock signal. The signaling of the SDATA 902 may be maintained by a keeper circuit after the line driver in the slave device has entered a high impedance mode. The bus master is configured to activate its line driver coupled to the SDATA 902 after approximately one clock cycle of the clock signal it sends. The bus master may terminate the SSC 906 by driving the SDATA 902 low to indicate the type of transaction to be performed. In some examples, the bus master terminates SSC 906 after two cycles of the send clock to indicate that no bus arbitration procedures are to be performed and / or to indicate that a read or write transaction will be initiated by the bus master. For example, the arbitration procedures may be suppressed when the bus master determines that a higher priority message is available for transmission, when the bus master determines that subsequent transmission of an arbitration procedure or datagram will interfere with a scheduled message or command, or for other reasons defined by an application or system configuration. In the illustrated example, the bus master terminates SSC 906 after 4 cycles of the send clock to indicate that an arbitration procedure will be performed.

[0102] The bus master device can send one or more synchronization pulses after terminating SSC 906. The number of synchronization pulses sent can be selected based on the capabilities of the receiving device. In the illustrated example, the bus master device sends two synchronization pulses 910 after terminating SSC 906. The receiving device can use the synchronization pulse 910 to synchronize the local clock generation circuit. In one example, the local clock generation circuit includes a ring oscillator. In another example, the local clock generation circuit includes a delay locked loop. The clock pulse can be provided to the injection locking circuit of the local clock generation circuit. The number of pulses in the synchronization pulse 910 can be configured during manufacturing, system integration or configuration, and / or configured by the application or bus master device.

[0103] The synchronization pulse 910 may precede the arbitration cycle 912. In some instances, the arbitration cycle 912 provides a two-cycle time slot for each slave address registered at the bus master or coupled to the single-wire serial bus. In one example, the arbitration cycle 912 accommodates 8 devices and has a duration of 16 cycles of the transmit clock used by the bus master. The bus master may cause its line driver to enter a high impedance state at the beginning of each time slot in the arbitration cycle 912, and the signaling state of SDATA 902 is maintained by a keeper circuit or a weak pull-down circuit until the line driver coupled to SDATA 902 begins to actively drive SDATA 902.

[0104] A slave device may participate in bus arbitration by driving SDATA 902 high during the first cycle of its corresponding time slot in arbitration cycle 912. Then, the participating slave device causes its line driver to enter a high impedance state before the end of the first cycle of the time slot. SDATA 902 is maintained in a high state due to the operation of the keeper circuit or due to the bus master device activating its line driver to maintain SDATA 902 in a high state for a complete first cycle. The bus master device drives SDATA 902 low in the second cycle of the time slot to allow the next slave device to clearly signal participation in arbitration. The bus master device identifies each device that drives SDATA 902 high during its corresponding time slot in arbitration cycle 912 as a device seeking service. Then, the bus master device can schedule the service of the participating slave device in an order determined by the priority or sequence configured for the system. In the case where the bus master device abandons the arbitration process by sending an 8-cycle SSC, the bus master device can retain information identifying the participating slave device in the arbitration cycle 912, and can schedule services based on the identification information.

[0105] The bus master may idle SDATA 902 for a period of time 914 after the arbitration cycle 912 and before initiating the next transaction 916. SDATA 902 may be idled when the bus master puts its line drivers into a high impedance state. In the illustrated example, the next transaction 916 begins with a 2-cycle SSC 918 to indicate that arbitration is not enabled. The transaction 916 continues to send a synchronization pulse 920, which the receiving device may use to synchronize its local clock generation circuit.

[0106] According to certain aspects of the present disclosure, the control signaling provided by the bus master may indicate the beginning of a datagram, the end of a datagram, the beginning of an interruptible transaction, and the abandonment of an interrupt handling procedure. A datagram may also be referred to as a frame, or may be provided within a frame including an arbitration or other datagram. The control signaling provided by the bus master may indicate a start of frame (SoF) or an end of frame (EoF). Signaling and encoding techniques may be configured to implement clock synchronization and data exchange for read and write operations. Control signaling based on the SSC length may be used to adapt interrupts as an integrated support feature of the bus architecture, and to abandon interrupt signaling in order to support the processing of newly received higher priority messages.

[0107] Fig.10 A write transaction 1000 is illustrated as being performed on a single-wire serial bus configured according to certain aspects disclosed herein. The write transaction 1000 may begin with the transmission of an SSC 1002. In the illustrated example, the SSC 1002 has a duration of three transmit clock cycles. In some implementations, arbitration may optionally follow the SSC 1002. The write transaction 1000 continues with the transmission of a synchronization pulse 1004, which the receiving device may use to synchronize its local clock generation circuit. A write command 1006 is transmitted. The write command 1006 may have a structure and content that is compatible or consistent with one or more commands defined by the RFFE protocol. The write command 1006 may be encoded using Manchester encoding. The bus master then transmits a payload 1008 directed to the device identified in the write command 1006. The payload 1008 may be encoded using Manchester encoding. The write transaction 1000 is terminated by an EoF 1010. In some instances, EoF 1010 may be indicated by SDATA being idle for a number of cycles. In one example, EoF 1010 is indicated when SDATA is idle for 7 cycles of the transmit clock.

[0108] The illustrated write transaction 1000 includes additional overhead relative to a corresponding write transaction conducted over a conventional two-wire serial bus operating in accordance with the RFFE protocol. The additional overhead may be attributed to the transmission of the sync pulse 1004 and the EoF 1010. In the illustrated example, the additional overhead associated with the SSC 1002 and the sync pulse 1004 may be calculated as 5 cycles of the transmit clock. The additional overhead may be attributed to the transmission of the EoF 1010.

[0109] Fig.11 A read transaction 1100 is illustrated as being performed on a single-wire serial bus configured according to certain aspects disclosed herein. The read transaction 1100 may begin with the transmission of an SSC 1102. In the illustrated example, the SSC 1102 has a duration of three transmit clock cycles. The read transaction 1100 continues with the transmission of a synchronization pulse 1104, which the receiving device may use to synchronize its local clock generation circuitry. A read command 1106 is transmitted. The read command 1106 may have a structure and content that is compatible or consistent with one or more commands defined by the RFFE protocol. The read command 1106 may be encoded using Manchester encoding.

[0110] The bus master provides a turnaround cycle during which the bus master puts its line driver into a high impedance state and activates its line driver from the device addressed by the read command 1106. The bus master is configured to disable its line driver and the addressed slave device enables its line driver. The slave device sends a synchronization pulse 1108, which the bus master can use to synchronize its receive clock generation circuit. In one example, the slave device uses two cycles of its transmit clock signal to send the synchronization pulse 1108. The slave device then sends a payload 1110. Manchester encoding can be used to encode the payload 1110. The read transaction 1100 is terminated by EoF 1112. In some instances, EoF 1112 can be indicated by SDATA being idle for several cycles. In one example, EoF 1112 is indicated when SDATA is idle for 7 cycles of the transmit clock.

[0111] The illustrated read transaction 1100 includes additional overhead relative to a corresponding read transaction conducted over a conventional two-wire serial bus operating according to the RFFE protocol. The additional overhead may be attributed to the transmission of the SSC 1102, sync pulses 1104, 1108, and EoF 1112. In the illustrated example, the additional overhead associated with the SSC 1102, sync pulse 1104 may be calculated as 7 cycles of the transmit clock.

[0112] Fig.12A Manchester decoder 1200 that may be configured according to certain aspects disclosed herein is illustrated. The Manchester decoder 1200 is coupled to an SDA 1210 (single wire serial bus) and is operable to produce an output 1220 representing data encoded in a signal transmitted via the SDA 1210.

[0113] The Manchester decoder 1200 includes a clock generator 1206, which can be configured to provide a plurality of clock signals 1216. The clock generator 1206 can include or be coupled to a programmable oscillator. In one example, the programmable oscillator can be configured to generate a basic clock signal having a frequency that is four times (4x) the frequency of a clock signal used by the transmitter to encode data for transmission via the SDA 1210. In some implementations, the programmable oscillator can be implemented using a programmable ring oscillator circuit. The clock generator 1206 can include a frequency divider, a delay circuit, a phase shifter, an inverter, and other circuits that can modify the frequency or phase of a clock signal. In the illustrated example, the clock generator 1206 outputs one or more clock signals 1216, including a sampling signal 1218, which is half the frequency of the basic clock signal and twice the frequency of the clock signal used by the transmitter during encoding. The sampling signal 1218 clocks the flip-flop 1208 coupled to the SDA 1210 so that the flip-flop can capture data from the SDA 1210 when enabled.

[0114] The synchronization circuit 1204 may be used to control the frequency and phase of the clock signal 1216. The synchronization circuit 1204 may be configured to align edges in the clock signal 1216 with transitions in the SDA 1210. The synchronization circuit 1204 may configure the control signal 1214 to enable and disable the flip-flop 1208 based on the current state of the Manchester decoder 1200. The synchronization circuit 1204 may be configured to enable and disable the oscillator in the clock generator 1206 based on the current state of the SDA 1210. In one example, the state monitoring circuit 1202 determines when a SoF has been received, when the SDA 1210 is active and carrying a data signal, and when an EoF has been received. The synchronization circuit 1204 can be configured to enable the oscillator in response to a control signal 1222 received from the state monitoring circuit 1202 indicating detection of the SoF, align the clock signal 1216 in frequency and phase during the transmission of the synchronization pulse, and use edges detected in the data signal received from the SDA 1210 during the active transmission to continuously adjust the frequency and phase synchronization clock signal 1216. In some implementations, the synchronization circuit 1204 uses the control and status signal 1212 to manage the operation of the clock generator 1206.

[0115] Fig.131300 is illustrated in a data read transaction in a receiver configured according to certain aspects disclosed herein. For example, a receiver may be equipped with Fig.12 13. Manchester decoder 1200 illustrated in FIG. 13. In the illustrated example, an encoder in a transmitter receives a serialized data signal 1304. The encoder encodes the data signal 1304 according to the timing provided by a transmit clock signal 1302 to produce a Manchester encoded signal 1306. In one example, the period of the transmit clock signal 1302 defines a bit transmission interval 1310 (T) corresponding to a transmit clock frequency of 52 MHz. The encoded signal is transmitted via SDA 1210. Fig.13 It is concerned with maintaining clock synchronization during datagram transmission, and the transmission of SoF, EoF or synchronization pulses is not shown.

[0116] The Manchester decoder 1200 operates using a clock signal 1216 provided by a clock generator 1206. The clock generator 1206 includes a programmable oscillator that can be configured to generate an oscillator base signal 1308 at four times (4x) the frequency of the transmit clock signal 1302. The frequency of the receive clock signal 1218 is twice (2x) the frequency of the transmit clock signal 1302 and can be obtained by dividing the oscillator base signal 1308 by two. The synchronization circuit 1204 can be configured to adjust the phase and / or frequency of the oscillator base signal 1308 to obtain a rising edge 1316 in the receive clock signal 1218 that is phase-aligned with a falling edge 1314 in the transmit clock signal 1302. The falling edge 1314 in the transmit clock signal 1302 corresponds to the center of the bit transmission interval 1310, and thus corresponds to a guaranteed transition of the Manchester encoded signal 1306.

[0117] The Manchester decoder 1200 typically does not directly access the transmit clock signal 1302, and therefore synchronizes its clock signal 1216 with the edges in the Manchester encoded signal 1306. The Manchester decoder 1200 can reliably decode data from the Manchester encoded signal 1306 as long as the transition at the edge of the bit transmission interval 1310 is not interpreted as a transition at the center of the bit transmission interval 1310. In some examples, successful decoding of the data can be guaranteed when the combined phase and frequency error is limited to 10%. The synchronization circuit 1204 can be configured to adjust the phase of the oscillator base signal 1308 in each bit transmission interval 1310 in which a phase shift is detected. In some instances, the phase is adjusted by adjusting a delay circuit used to determine the frequency of the oscillator base signal 1308. Adjusting the phase of the oscillator base signal 1308 can also cause the frequency of the oscillator base signal 1308 to change.

[0118] In one aspect of the present disclosure, the ability to adjust the phase of the oscillator base signal 1308 in each bit transmission interval 1310 produces the expectation that the SDA 1210 can be reliably captured or sampled regardless of the number of bits in the data transmission because phase and / or frequency errors do not accumulate. In the illustrated example, the SDA 1210 is captured using a flip-flop 1208. Each data bit can be captured at a falling edge 1318 of the receive clock signal 1218 immediately after the center of the bit transmission interval 1310, as represented by a rising edge 1316 in the receive clock signal 1218, which nominally occurs after a 0.75T delay 1312 from the beginning of the bit transmission interval 1310.

[0119] Fig.14 A comparison of a phase-matched data read transaction 1400 and a phase-mismatched data read transaction 1420 in a receiver equipped with a Manchester decoder 1200 configured according to certain aspects disclosed herein is provided. In the illustrated example, an encoder in a transmitter generates a Manchester encoded signal 1404 according to the timing provided by a transmit clock signal 1402. In one example, the period of the transmit clock signal 1402 defines a bit transmission interval 1410 (T) corresponding to a transmit clock frequency of 52 MHz. The encoded signal is transmitted via the SDA 1210.

[0120] The Manchester decoder 1200 operates using a receive clock signal 1408 provided by a clock generator 1206 located in the receiver. The clock generator 1206 includes a programmable oscillator that can be configured to generate an oscillator base signal 1406 at four times (4x) the frequency of the transmit clock signal 1402. The frequency of the receive clock signal 1408 is twice (2x) the frequency of the transmit clock signal 1402 and can be obtained by dividing the oscillator base signal 1406 by two.

[0121] Referring to the phase matching data read transaction 1400, the synchronization circuit 1204 can control the phase and / or frequency of the oscillator base signal 1406 so that the rising edge 1414 in the receive clock signal 1408 is phase aligned with the falling edge 1412 in the transmit clock signal 1402. In the illustrated example, the falling edge 1412 in the transmit clock signal 1402 corresponds to the center of the bit transmission interval 1410, and thus corresponds to a guaranteed transition in the Manchester encoded signal 1404.

[0122] The Manchester decoder 1200 does not directly access the transmit clock signal 1402, and therefore synchronizes its clock signal 1216 with the edges in the Manchester encoded signal 1404. In a phase matched data read transaction 1400, the Manchester decoder 1200 can reliably decode data from the Manchester encoded signal 1404.

[0123] Phase mismatch data read transaction 1420 relates to situations where the phase and / or frequency of oscillator base signal 1406 may drift due to channel noise or PVT variations. Phase mismatch may be caused by a frequency or phase error that causes a rising edge 1424 in the receive clock signal 1408 to be out of phase with a corresponding falling edge 1422 in the transmit clock signal 1402. In the illustrated example, the rising edge 1424 in the receive clock signal 1408 is delayed by a certain duration 1428 and causes misalignment with the falling edge 1422 in the transmit clock signal 1402.

[0124] The falling edge 1422 in the transmit clock signal 1402 may mark the center of the bit transmission interval 1410 and the corresponding edge transition of the Manchester encoded signal 1404. In some instances, the phase misalignment may be attributed to other sources of PVT variations or oscillator drift. In some instances, the relationship between the falling edge 1422 in the transmit clock signal 1402 and the corresponding edge transition of the Manchester encoded signal 1404 may drift due to channel noise. In either case, the receive clock signal 1408 and the transmit clock signal 1402 may be out of synchronization. The implementation of synchronization for each bit transmission interval generally limits the duration 1428 of the delay between the falling edge 1422 in the transmit clock signal 1402 and the rising edge 1424 in the receive clock signal 1408, so that the Manchester decoder 1200 can reliably decode data from the Manchester encoded signal 1404 in the presence of a phase shift.

[0125] The synchronization circuit 1204 can be configured to detect the duration 1428 of the delay and accordingly adjust the phase of the oscillator base signal 1406. In some examples, the phase is adjusted by adjusting a delay circuit used to determine the frequency of the oscillator base signal 1406. In some examples, adjusting the phase of the oscillator base signal 1406 can cause the frequency of the oscillator base signal 1406 to be adjusted.

[0126] In one aspect of the present disclosure, the ability to adjust the phase of the oscillator base signal 1406 in each bit transmission interval 1410 limits the phase shift per bit transmission interval 1410 and can support the expectation that data can be reliably captured or sampled from the SDA 1210 regardless of the number of bits in the data transmission because phase and / or frequency errors do not accumulate when using the decoder disclosed in the present invention. In the illustrated example, the signaling state of the SDA 1210 is captured using a flip-flop 1208. Each data bit can be captured at the falling edge 1416, 1426 of the receive clock signal 1218 immediately after the center of the bit transmission interval 1410, as represented by the transition detected in the Manchester encoded signal 1404.

[0127] Fig.15A first example of a clock and data recovery circuit 1500 that may be used to generate a receive clock and decode data in a Manchester decoder configured according to certain aspects of the present disclosure is illustrated. Fig.15 The circuits shown and in other figures are provided as examples. These figures include certain edge-sensitive devices that are sensitive to positive edges, sensitive to negative edges, or sensitive to both positive and negative edges. These edge-sensitive devices are tailored to the requirements of the illustrated circuits, which are provided to facilitate description of certain aspects of the present disclosure. Other circuit designs are contemplated, including Fig.15 Some of the devices illustrated in the and other figures may be sensitive to transitions different from those depicted. For example, Fig.15 The sync bit counter 1504 in FIG. 1 is depicted as responsive to a negative edge, but in other implementations, the sync bit counter 1504 may be responsive to a positive edge. It is contemplated that the flip-flops, counters, registers, and other circuits discussed or depicted in the present disclosure may be implemented using positive edges, negative edges, or both edges as required by a particular design implementation.

[0128] The illustrated clock and data recovery circuit 1500 includes a state monitor 1502 configured to monitor and respond to an activity or change in activity on a single-wire serial bus (SDA 1522). For example, the state monitor 1502 may be configured to detect the occurrence of an EoF condition in a SSC and a signal received from the SDA 1522. The state monitor 1502 may determine that an SSC has been received after an idle period on the SDA 1522. The SSC may be identified based on its configuration and duration. The state monitor 1502 may assert a control signal (SSC_det signal 1534) to indicate that a valid SSC has been received. In the illustrated example, the SSC_det signal 1534 is provided to a local oscillator 1510 and an edge synchronization circuit 1508.

[0129] When asserted, the SSC_det signal 1534 indicates that an SSC has been detected and the local oscillator 1510 is enabled or activated. The local oscillator 1510 may be configured to generate a signal having a fundamental frequency (f base ) of the base clock signal 1520. In one example, f base =4×52MHz=208MHz. In another example, f base >208MHz. In some instances, f base In the illustrated example, the base clock signal 1520 is provided to the modulo-7 counter 1512 via a base clock AND gate 1506 that is responsive to various control signals 1534 , 1538 indicative of state information associated with the clock and data recovery circuit 1500 .

[0130] In the illustrated example, the base clock AND gate 1506 blocks the base clock signal 1520 until a necessary or preconfigured number of synchronization pulses have been received. In the illustrated example, each synchronization pulse corresponds to a zero-valued bit of Manchester encoding. The delay provided between the SSC and the synchronization pulse can be configured to provide sufficient time for the local oscillator 1510 to obtain oscillation stability.

[0131] In the illustrated example, the synchronization bit counter 1504 is enabled after the SSC has been received or detected. The synchronization bit counter 1504 is configured to count the midpoint transitions in the Manchester coded signal received from the SDA 1522. In one example, the synchronization pulse includes a negative transition at the midpoint of its corresponding bit transmission interval. In another example, the synchronization pulse includes a positive transition at the midpoint of its corresponding bit transmission interval. In another example, the synchronization pulse includes a combination of positive and negative transitions at the midpoint of its corresponding bit transmission interval. The synchronization bit counter 1504 can synchronize the receiving circuit in the clock and data recovery circuit 1500 based on the timing of the midpoint transition in the synchronization pulse. The synchronization bit counter 1504 can be configured to stop counting at a predefined or preconfigured count value corresponding to the number of expected synchronization pulses. In the illustrated example, the protocol specifies that two synchronization pulses will be expected. In one example, the synchronization bit counter 1504 can be self-gated, whereby the logic circuit included operates to stop counting after the expected number of synchronization pulses has been detected and counted. In other examples, the sync bit counter 1504 may be coupled to logic circuitry that disables counting after an expected number of sync pulses have been detected and counted.

[0132] The output of the sync bit counter 1504 may continue to indicate the count value reached before the count was stopped until the sync bit counter 1504 is reset. In some examples, the sync bit counter 1504 is reset when the EoF_det signal 1518 is asserted by the state monitor 1502 after an EoF is detected in the signal received via the SDA 1522. The sync signal 1524 may be provided by the sync bit counter 1504 or by a logic circuit associated with the sync bit counter 1504. The sync signal 1524 may be used to indicate that a sync pulse has been detected. In the illustrated example, the sync signal 1524 is driven high when asserted and is connected to the input of the base clock AND gate 1506. In some implementations, the sync signal 1524 is driven directly by the sync bit counter 1504 using a counter output bit representing a binary weighted value. In some implementations, the sync signal 1524 is generated by a combinational logic coupled to the output of the sync bit counter 1504. In some implementations, the sync bit counter 1504 is set to a non-zero value during reset and the sync signal 1524 indicates a counter overflow condition.

[0133] The third input to the base clock AND gate 1506 is controlled by the output of the gate control logic 1516. The gate control logic 1516 is controlled by the output of the modulo 7 counter 1512 (M7 输出 Signal 1528) indicates count value M7 输出 <6, drives its output (SDA_mask signal 1538) high, and 输出 Signal 1528 indicates count value M7 输出 = 6, its output is driven low. Therefore, when M7 输出 <6, the third input to the base clock AND gate 1506 is high.

[0134] In some implementations, the edge synchronization circuit 1508 drives an M7_Reset signal 1536 that is used to reset the modulo-7 counter 1512 when asserted. The edge synchronization circuit 1508 can be responsive to the state of the SDA 1522 as indicated by the SSC_det signal 1534 and the sync signal 1524 and to an edge in the Manchester encoded signal sent via the SDA 1522. The M7_Reset signal 1536 can be initially asserted and remain asserted until the sync signal 1524 is asserted. The sync signal 1524 is asserted on the falling edge of the last sync pulse received after the SSC has been detected or after a line turnaround. When the M7_Reset signal 1536 is deasserted after the sync signal 1524 is asserted, the modulo-7 counter 1512 begins counting.

[0135] The modulo-7 counter 1512 is configured to count both positive and negative transition edges in the gated base clock signal 1526 output by the base clock AND gate 1506. The modulo-7 counter 1512 actively counts after the SSC and sync pulses have been received. The SDA_mask signal 1538 is in a high logic state when the modulo-7 counter 1512 is reset and remains high until the modulo-7 counter 1512 reaches a count value of 6, corresponding to six edges of the gated base clock signal 1526. The six edges of the gated base clock signal 1526 cover 75% of the bit interval or clock cycle used to encode the data bits in the Manchester encoded signal. When the SDA_mask signal 1538 transitions to low, the base clock signal 1520 is blocked and the counting of the modulo-7 counter 1512 is stopped.

[0136] The SDA_mask signal 1538 is used to gate the input of the edge synchronization circuit 1508 that receives the Manchester encoded signal transmitted via SDA 1522. When the SDA_mask signal 1538 is high, the Manchester encoded signal is blocked at the input of the edge synchronization circuit 1508. When the SDA_mask signal 1538 is low, the Manchester encoded signal is passed to the logic circuit within the edge synchronization circuit 1508, and the next edge in the Manchester encoded signal causes the M7_Reset signal 1536 to be asserted. The configuration of the modulo 7 counter 1512 causes the edge synchronization circuit 1508 to ignore transitions that may occur at the boundaries of the bit transmission interval in the Manchester encoded signal. After reaching a count value of 6, the modulo 7 counter 1512 is reset by the next occurring edge in the Manchester encoded signal, which corresponds to a transition at the center of the bit transmission interval. The modulo 7 counter 1512 may respond to early or late transitions in the Manchester encoded signal occurring within the last 25% of the bit transmission interval.

[0137] The edge synchronization circuit 1508 can account for phase errors. The modulo-7 counter 1512 is reset by a transition at the center of each bit transmission interval in the Manchester encoded signal and prevents accumulation of phase errors. In some implementations, phase information can be provided to the local oscillator 1510 by the edge synchronization circuit 1508. When similar magnitude phase errors are observed in multiple consecutive bit transmission intervals in the Manchester encoded signal, the feedback information can be used to adjust the frequency of the base clock signal 1520.

[0138] The write clock signal 1530 may be derived from the SDA_mask signal 1538 output by the gate control logic 1516. The write clock signal 1530 may be used to write the data output 1532 of the clock and data recovery circuit 1500 to an external flip-flop, shift register, or other storage device. In the illustrated example, the write clock signal 1530 is a buffered version of the SDA_mask signal 1538. In some examples, the write clock signal 1530 is driven directly by the gate control logic 1516. In other examples, the SDA_mask signal 1538 is an inverted or delayed version of the SDA_mask signal 1538. For example, the SDA_mask signal 1538 may be inverted or delayed to control the time from edge detection on the SDA 1522 until data is captured from the SDA 1522. The SDA_mask signal 1538 may be divided, inverted, phase shifted, and / or delayed in order to generate a signal that emulates a bus clock signal (eg, SCLK) expected by conventional two-wire bus interface circuits.

[0139] In the illustrated example, the SDA_mask signal 1538 is used to clock the data latch 1514. In other examples, the data latch 1514 is clocked by a signal generated by combinatorial logic coupled to the output of the modulo-7 counter 1512 or by a signal representing one or more bits output by the modulo-7 counter 1512. In the illustrated example, the data latch 1514 provides the data output 1532 of the clock and data recovery circuit 1500.

[0140] Fig.16 Illustrated Fig.15 16. Certain aspects of the operation of the clock and data recovery circuit 1500 illustrated in FIG. 16. The timing diagram 1600 relates to signaling associated with the start of the clock and data recovery circuit 1500 coupled to the SDA 1522 of the single-wire bus. The start of the transmission can be indicated by the SSC 1602. The state monitor 1502 can identify a pulse of a predefined or preconfigured minimum length as a valid SSC and can assert the SSC_det signal 1534. In the illustrated example, the SSC_det signal 1534 is asserted at the rising edge 1612 of the SSC 1602 to maximize the available time 1610 to obtain oscillator stability. The minimum time to achieve oscillator stability defined for the single-wire interface can be met as a combination of the duration of the SSC 1602 and the delay 1604 before receiving the synchronization bit 1606. The local oscillator 1510 responds to the assertion of the SSC_det signal 1534 by enabling the generation of the basic clock signal 1520.

[0141] The sync bit counter 1504 is enabled after the SSC has been detected and verified. In the illustrated example, the sync bit counter 1504 is configured to count transitions 1614, 1616 in each of the sync bits 1606 that are negative transitions. By protocol or configuration, the transitions 1614, 1616 in the sync bits 1606 are expected to occur at the midpoint of the bit transmission intervals 1608a, 1608b. The illustrated transitions 1614, 1616 in the sync bits 1606 provide a timing reference that can be used to begin decoding data from the Manchester encoded signal to be transmitted via the SDA 1522.

[0142] The sync bit counter 1504 is configured to stop counting when the count value corresponds to the number of expected sync bits 1606 (here, 2 sync bits 1606 are expected). The sync bit counter 1504 or a logic circuit coupled to the output of the sync bit counter 1504 is configured to assert a logical true (here, a high signaling state) on the sync signal 1524, which indicates that two sync bits 1606 have been received. In some implementations, the protocol defines a different number of expected sync bits 1606, and the sync signal 1524 indicates that a full complement of sync bits 1606 has been received. The sync bit counter 1504 or a logic circuit coupled to the output of the sync bit counter 1504 is configured to continue asserting a logical true on the sync signal 1524 after an EoF is detected on the SDA 1522 until the state monitor 1502 asserts the EoF_det signal 1518. When logic true is asserted in synchronization signal 1524 , certain circuits in clock and data recovery circuit 1500 are enabled and each bit synchronization may be performed on subsequent bits received from SDA 1522 .

[0143] Timing diagram 1620 relates to signaling associated with each bit synchronization on the data bits received in the Manchester encoded signal transmitted via SDA 1522. Edge synchronization circuit 1508 is configured to transmit a signal at each bit transmission interval (T n-1 -T n+4 )'s center 1622 n-1 -1622 n+4 The modulo-7 counter 1512 is reset at 1508. When the modulo-7 counter 1512 is in the reset state, the SDA_mask signal 1538 is in the high signaling state. The modulo-7 counter 1512 counts six edges of the base clock signal 1520 before causing the SDA_mask signal 1538 to be driven to the low signaling state. When the SDA_mask signal 1538 is in the high signaling state, the Manchester encoded signal sent via SDA 1522 is blocked at the input of the edge synchronization circuit 1508, and the edge synchronization circuit 1508 effectively ignores the transition in the Manchester encoded signal. When the SDA_mask signal 1538 is in the low signaling state, the edge synchronization circuit 1508 responds to the next transition in the Manchester encoded signal by resetting the modulo-7 counter 1512, thereby returning the SDA_mask signal 1538 to the high signaling state.

[0144] In the illustrated example, the SDA_mask signal 1538 is driven high at the center of the bit transmission interval of the Manchester encoded signal, and remains in a high signaling state within a duration 1626 equivalent to three-quarters of the bit transmission interval. The SDA_mask signal 1538 is in a high signaling state at the boundary between each pair of consecutive transmission intervals, and ignores any edge in the Manchester encoded signal at these boundaries. In the illustrated example, the rising edge 1624 in the SDA_mask signal 1538 can be used to capture data bits from the Manchester encoded signal. In some instances, the rising edge 1624 in the SDA_mask signal 1538 is substantially consistent with the edge of the Manchester encoded signal at the center of the bit transmission interval. In these instances, the SDA_mask signal 1538 can be delayed to provide a write clock that satisfies the minimum data setup and hold time defined for the data latch 1514.

[0145] Fig.17 Certain aspects of a second example of a clock and data recovery circuit 1700 that can be used to generate a receive clock and decode data in a Manchester decoder configured according to certain aspects of the present disclosure are illustrated. In this example, monitoring of the state of SDA 1722 can be handled by a monitoring circuit or can be implemented using various functional elements and / or logic circuits provided in the clock and data recovery circuit 1700.

[0146] The clock and data recovery circuit 1700 includes an edge synchronization circuit 1702 configured to monitor and respond to activity or changes in activity on a single-wire serial bus (SDA 1722) and control the operation of a local oscillator 1710 and a synchronization bit counter 1704. The edge synchronization circuit 1702 can determine that an SSC has been received in a Manchester encoded signal transmitted via the SDA 1722. The SSC can be identified or verified based on its duration. Once the SSC is detected, the local oscillator 1710 can be enabled.

[0147] The local oscillator 1710 may be configured to generate a signal having a fundamental frequency (f base ) of the base clock signal 1720. In one example, f base =4×52MHz=208MHz. In another example, f base >208MHz. In some instances, f base <208 MHz. In the illustrated example, a base clock signal 1720 is provided to a modulo-7 counter 1712 via a base clock AND gate 1706 that is responsive to various status information.

[0148] In the illustrated example, the base clock AND gate 1706 blocks the base clock signal 1720 until the synchronization pulse sequence has been received. In some instances, the final synchronization pulse in the synchronization pulse sequence corresponds to a Manchester coded bit having a value of "1". A delay may be provided between the SSC and the synchronization pulse to provide sufficient time for the local oscillator 1710 to obtain oscillation stability.

[0149] In the illustrated example, the synchronization bit counter 1704 is enabled after the SSC has been received or detected. The synchronization bit counter 1704 is configured to count negative transitions and positive transitions. The synchronization pulse sequence corresponds to a zero bit, followed by a non-zero bit, as encoded by the transition direction at the midpoint of their corresponding bit transmission intervals. The synchronization bit counter 1704 is operable to synchronize certain circuits in the clock and data recovery circuit 1700 based on the timing of the positive transition in the final synchronization pulse. The synchronization bit counter 1704 can be configured to stop counting at a predefined or preconfigured count value corresponding to the number of expected synchronization pulses. In the illustrated example, the protocol specifies that two synchronization pulses will be expected. In some specific implementations, the synchronization bit counter 1704 is self-gated, including a logic circuit that stops counting after the expected number of synchronization pulses has been detected and counted. In other examples, the synchronization bit counter 1704 is coupled to a logic circuit that disables counting after the expected number of synchronization pulses has been detected and counted.

[0150] The output of the synchronization bit counter 1704 may maintain the control signal 1724 in a state indicating that the expected count value has been reached and / or synchronization has been completed. The control signal 1724 may continue to indicate that synchronization has been completed until the synchronization bit counter 1704 is reset. In some examples, when EoF is detected on SDA 1722, the synchronization bit counter 1704 is reset. The control signal 1724 may be coupled to the input of the basic clock and gate 1706 and / or driven high. In some specific implementations, the input of the basic clock and gate 1706 is directly driven by the synchronization bit counter 1704 using the counter output bit representing the binary weighted value. In some specific implementations, the input of the basic clock and gate 1706 is driven by a combinational logic coupled to the output of the synchronization bit counter 1704.

[0151] The third input to the base clock AND gate 1706 is controlled by the output of the gate logic module 1716. The gate logic module 1716 is connected to the output 1736 (M7) of the modulo 7 counter 1712. 输出 ) indicates the count value M7 输出 =7, and drives its output 1734 low, and drives its output high when edge synchronization circuit 1702 detects an edge on SDA 1722. Therefore, the third input to base clock AND gate 1706 is high until M7输出 reaches the value 7.

[0152] In one aspect of the disclosure, when the output 1734 of the gate logic module 1716 is in a high state, transitions on the SDA 1722 are blocked from the edge synchronization circuit 1702. In another aspect of the disclosure, when the output 1734 of the gate logic module 1716 is in a high state, the base clock signal 1720 is blocked by the base clock AND gate 1706.

[0153] The clock and data recovery circuit 1700 includes a group of flip-flops 1708 configured as a loop, wherein the input of each flip-flop is coupled to the output of another flip-flop. The output of the flip-flops in the group of flip-flops 1708 is assigned a specific value when reset, wherein the assigned values ​​are {0, 1, 1, 0} in sequence. Each flip-flop in the group of flip-flops 1708 is clocked by both the negative edge and the positive edge in the gated basic clock signal 1726 output by the basic clock and gate 1706. In the free-running mode, the first clock signal 1728 output by the group of flip-flops 1708 is substantially a square wave signal, and its frequency is half the frequency of the gated basic clock signal 1726. The first clock signal 1728 is synchronized with the transition at the center of the bit transmission interval in the Manchester coded signal. In some specific implementations, the number of flip-flops in the group of flip-flops 1708 can be increased to obtain different frequency divisors. The first clock signal 1728 can be further processed to act as a bus clock signal, such as SCLK. In one example, the conditioning circuit 1714 can provide a second clock signal 1730 having a frequency that is half the frequency of the first clock signal 1728. In some instances, the conditioning circuit 1714 can invert or phase shift the first clock signal 1728 to obtain the second clock signal 1730. After each bit is sampled, the clock signals 1728, 1730 are automatically recalibrated to the timing of the Manchester encoded signal. Each bit recalibration can prevent accumulation of clock errors and can allow sampling accuracy to be maintained regardless of the datagram size.

[0154] Fig.18 Certain aspects of an example of a clock generator 1800 that may be used in a clock and data recovery circuit configured according to certain aspects of the present disclosure are illustrated. The operation of a programmable oscillator 1810 in the clock generator 1800 may be dynamically controlled by bit settings in one or more control registers 1808, 1814. The programmable oscillator 1810 may be enabled and disabled, and the frequency of a clock signal 1820 generated by the programmable oscillator 1810 may be adjusted.

[0155] In one aspect, the oscillator on / off control circuit 1812 can be configured to selectively turn on and off the output clock signal 1820. In some implementations, the oscillator on / off control circuit 1812 can respond to programmed control by selectively turning on or off the differential amplifier 1802 at the core of the programmable oscillator 1810. In some implementations, the oscillator on / off control circuit 1812 can be configured to reduce the power consumption of the differential amplifier 1802 without completely powering down the differential amplifier 1802. In one example, the oscillation frequency can be reduced by several orders of magnitude to reduce power consumption.

[0156] According to certain aspects of the present disclosure, the oscillator on / off control circuit 1812 may be responsive to a command that causes the oscillator on event to be synchronized or triggered by one or both types of edges in a signal received from a single-wire bus. The on event may be programmed to be sensitive to a positive edge, a negative edge, or any type of edge. Default options for on sensitivity may be predefined or configured. For example, a default edge sensitivity may be selected at design time. In certain implementations described herein, the positive edge sensitivity may be defined as a default setting.

[0157] According to certain aspects of the present disclosure, the oscillator on / off control circuit 1812 can respond to the inactivity of the single-wire bus by causing the programmable oscillator 1810 to enter a power-down state. In one example, the programmable oscillator 1810 can be powered down after a period of inactivity on the single-wire bus. The duration of the idle time before initiating the power down can be predefined or configured. For example, a default minimum duration of the idle time can be selected at design time. The minimum duration of the idle time can be defined or configured to ensure that the sequence of encoded data bits, control signaling, and other purposeful signaling (e.g., the delay between the SSC and the synchronization bit) is not misinterpreted as bus inactivity. The minimum duration of the idle time can be expressed according to the number of clock signal cycles generated.

[0158] In some implementations, power down can be initiated in response to a command generated by an application or a power management system. In one example, an application can choose to force power down the programmable oscillator 1810 for battery management reasons. In another example, an application can force power down the programmable oscillator 1810 after disabling an RF interface or other functionality in the mobile communication device.

[0159] In some implementations, the oscillator on / off control circuit 1812 can be configured via one or more programmable control registers 1814. The oscillator on / off control circuit 1812 can read configuration information from the programmable control register 1814 after power-up, in response to a command, and / or as part of a control cycle. Certain information in the programmable control register 1814 can be transferred to the frequency control register 1808 directly or through the operation of the oscillator on / off control circuit 1812.

[0160] The frequency control register 1808 may be used to control the frequency of the clock signal 1820 generated by the programmable oscillator 1810. The frequency control register 1808 may be configured with a default value that defines the operating frequency to be used after system power-up, after a system reset, or after system initialization. The frequency control register 1808 may override or overwrite the default value to modify or tune the frequency of the clock signal 1820. Some bits in the frequency control register 1808 may control the capacitance of the variable capacitor 1804. Other bits in the frequency control register 1808 may control the resistance of the variable resistor 1806. In some implementations, more than one variable capacitor 1804 and / or more than one variable resistor 1806 may be controlled by the frequency control register 1808. In the illustrated example, the variable capacitor 1804 provides coarse control of the frequency of the clock signal 1820 generated by the programmable oscillator 1810, while the variable resistor 1806 provides coarse control of the frequency of the clock signal 1820.

[0161] In some implementations, dynamic frequency control is managed by an application or by a power management system. In some instances, dynamic frequency control can be managed by a datagram received from a single-wire serial bus. The datagram can carry information to be written to the frequency control register 1808. In some implementations, the frequency control register 1808 can be configured with a plurality of frequency control settings that can be selected in response to commands received from a control entity.

[0162] Fig.19 An example of an oscillator 1900 that may be implemented in an IC device according to certain aspects of the present disclosure is illustrated. The oscillator 1900 may correspond at least in part to Fig.18 The programmable oscillator 1810 illustrated in FIG.

[0163] According to certain aspects of the present disclosure, oscillator 1900 may be configured to generate a clock signal having a frequency that is four times (4x) the frequency of a data encoding clock signal at the transmitter. In one example, the transmitter encodes data using 52 MHz, and oscillator 1900 may be configured to generate a clock signal having a frequency that is four times (4x) the frequency of a data encoding clock signal at the transmitter. base=4×52 MHz=208 MHz. Generates the base clock signal. Oscillator 1900 can be expected to accommodate a combined phase and frequency error of 10%.

[0164] Fig.18 and Fig.19 is provided as an example of an oscillator that may be used in a clock and data recovery circuit that operates according to certain aspects of the present disclosure. Other types of oscillators may be used, including ring oscillators and metastable oscillators. A ring oscillator may be implemented using a set of inverters, with the output of each inverter connected to the next inverter in the ring. The output of the last inverter in the set is coupled to the input of the first inverter in the set to close the ring or loop. A ring oscillator may provide outputs at multiple different phases.

[0165] Fig. 20 An RFFE interface 2000 is illustrated where a conventional two-wire RFFE interface may be coupled to a single-wire serial bus. When a single-wire serial bus is used for RFFE communications, SCLK 2006 is not received from the transmitting device, and a conventional RFFE core 2004 in the slave device will not have a timing reference to decode information from the data signal. A clock recovery module 2002 configured in accordance with certain aspects of the present disclosure may generate a receive clock signal that conforms to the bus clock signal expected by the conventional RFFE core 2004. In one example, Fig.17 The clock and data recovery circuit 1700 illustrated in the example generates a second clock signal 1730 having the same frequency and phase as the expected bus clock signal. In the illustrated example, the clock recovery module 2002 may send the clock signal to the RFFE core 2004 via SCLK 2006 that complies with or is compatible with the RFFE protocol. In other specific implementations, the clock recovery module 2002 may provide a bus clock signal that complies with or complies with a different bus protocol supported by a conventional interface.

[0166] Examples of Processing Circuits and Methods

[0167] Fig.212100. In some examples, the device 2100 may perform one or more functions disclosed herein. According to various aspects of the present disclosure, the processing circuit 2102 may be used to implement any combination of elements, any part of elements, or elements disclosed herein. The processing circuit 2102 may include one or more processors 2104 controlled by a certain combination of hardware modules and software modules. Examples of processors 2104 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other appropriate hardware configured to perform various functionalities described throughout the present disclosure. One or more processors 2104 may include special-purpose processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 2116. One or more processors 2104 may be configured by a combination of software modules 2116 loaded during initialization, and may also be configured by loading or unloading one or more software modules 2116 during operation.

[0168] In the illustrated example, the processing circuit 2102 may be implemented with a bus architecture, which is generally represented by a bus 2110. Depending on the specific application of the processing circuit 2102 and the overall design constraints, the bus 2110 may include any number of interconnecting buses and bridges. The bus 2110 links various circuits (including one or more processors 2104 and storage devices 2106) together. The storage device 2106 may include a memory device and a mass storage device, and may be referred to as a computer-readable medium and / or a processor-readable medium in this article. The bus 2110 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuits. The bus interface 2108 may provide an interface between the bus 2110 and one or more transceivers 2112a, 2112b. Transceivers 2112a, 2112b may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all circuits or processing modules found in transceivers 2112a, 2112b. Each transceiver 2112a, 2112b provides a component for communicating with various other devices through a transmission medium. In one example, the transceiver 2112a can be used to couple the device 2100 to a multi-line bus. In another example, the transceiver 2112b can be used to connect the device 2100 to a radio access network. Depending on the nature of the device 2100, a user interface 2118 (e.g., a keypad, a display, a speaker, a microphone, a joystick) may also be provided and the user interface may be communicatively coupled to the bus 2110 directly or via the bus interface 2108.

[0169] The processor 2104 may be responsible for managing the bus 2110 and for general processing, which may include executing software stored in a computer-readable medium, which may include a storage device 2106. In this regard, the processing circuit 2102 (including the processor 2104) may be used to implement any of the methods, functions, and techniques disclosed herein. The storage device 2106 may be used to store data that is manipulated by the processor 2104 when executing the software, and the software may be configured to implement any of the methods disclosed herein.

[0170] One or more processors 2104 in the processing circuit 2102 may execute software. Software should be interpreted broadly to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in a computer-readable form within the storage device 2106 or in an external computer-readable medium. The external computer-readable medium and / or the storage device 2106 may include a non-transitory computer-readable medium. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. The computer-readable medium and / or storage device 2106 may also include, for example, carrier waves, transmission lines, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. The computer-readable medium and / or storage device 2106 may reside in the processing circuit 2102, in the processor 2104, external to the processing circuit 2102, or distributed across multiple entities including the processing circuit 2102. The computer-readable medium and / or storage device 2106 may be embodied as a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[0171] The storage device 2106 may maintain software maintained and / or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules 2116. Each of the software modules 2116 may include instructions and data that, when installed or loaded into the processing circuit 2102 and executed by the one or more processors 2104, contribute to a runtime image 2114 that controls the operation of the one or more processors 2104. Certain instructions, when executed, may cause the processing circuit 2102 to perform functions according to certain methods, algorithms, and processes described herein.

[0172] Some of the software modules 2116 may be loaded during initialization of the processing circuit 2102, and these software modules 2116 may configure the processing circuit 2102 to enable the various functions disclosed herein to be performed. For example, some of the software modules 2116 may configure the internal devices and / or logic circuits 2122 of the processor 2104, and may manage access to external devices such as transceivers 2112a, 2112b, bus interface 2108, user interface 2118, timers, math coprocessors, etc. The software modules 2116 may include a control program and / or operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by the processing circuit 2102. Resources may include memory, processing time, access to transceivers 2112a, 2112b, user interface 2118, etc.

[0173] One or more processors 2104 of the processing circuit 2102 can be multifunctional, whereby some of the software modules 2116 are loaded and configured to perform different functions or different instances of the same function. One or more processors 2104 can be additionally adapted to manage background tasks initiated in response to inputs such as from a user interface 2118, transceivers 2112a, 2112b, and device drivers. In order to support the execution of multiple functions, one or more processors 2104 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks served by one or more processors 2104 as needed or desired. In one example, a time sharing program 2120 that transfers control of the processor 2104 between different tasks can be used to implement a multitasking environment, whereby each task returns control of the one or more processors 2104 to the time sharing program 2120 when any pending operation is completed and / or in response to inputs such as interrupts. When a task controls one or more processors 2104, the processing circuit is effectively specialized for the purpose of being solved by the function associated with the control task. The time sharing program 2120 may include an operating system, a main loop that transmits control on a cycle basis, functions that allocate control of one or more processors 2104 based on the priority of the functions, and / or an interrupt-driven main loop that responds to external events by providing control of one or more processors 2104 to processing functions.

[0174] The processing circuit 2102 may be configured to perform one or more of the functions disclosed herein. For example, the processing circuit 2102 may be configured to operate as a master device coupled to a serial bus. The processing circuit 2102 may be configured to initiate a pulse on a line coupling the processing circuit 2102 to a slave device, present a high impedance to the line after initiating the pulse, and determine whether the slave device has terminated the pulse in advance, thereby indicating a first coded value. When the slave device has not terminated the pulse, the processing circuit 2102 may be configured to terminate the pulse after a duration sufficient to indicate a second coded value. In one example, the first coded value is assigned a binary 1 and the second coded value is assigned a binary 0. In another example, the first coded value is assigned a binary 0 and the second coded value is assigned a binary 1. The processing circuit 2102 may be configured to determine the coded value or may employ a separate PWM decoder.

[0175] Fig. 22 2200 is a flow chart of a method of data communication that can be performed at a slave device coupled to a single-wire serial bus. One or more slave devices can be coupled to the single-wire serial bus. A bus master can exchange Manchester-encoded data with the slave device. The bus master can send Manchester-encoded data and commands to the slave device via the single-wire serial bus.

[0176] At box 2202, an oscillator may be configured to generate a basic clock signal with a basic frequency from a device. At box 2204, a clock gating circuit may be configured to output a gated basic clock signal when the clock gating circuit is enabled from a device. The clock gating circuit may be responsive to one or more control inputs. At box 2206, a first counter may be configured to provide a counter output reflecting the count of positive and negative edges in the gated basic clock signal that is timed to the first counter from a device. At box 2208, a control logic may be configured to disable the clock gating circuit from a device when the counter output corresponds to a maximum count value. At box 2210, an edge synchronization circuit may be configured to ignore an edge in a signal received from a single-wire bus by an edge synchronization circuit when the counter output has a value less than the maximum count value from a device, and reset the first counter in response to an edge detected in a signal received from the single-wire bus. The maximum count value may be a preconfigured or reconfigurable value.

[0177] In some examples, the signal received from the single-wire bus is Manchester encoded based on an encoding clock having a frequency four times that of the base clock signal. The encoding clock may have a frequency of at least 52 MHz.

[0178] In some examples, the flip-flop is configured to capture a data bit from the single-wire bus in response to an edge detected in a signal received from the single-wire bus.A signal output by the control logic that disables the clock gating circuit may be used to clock the flip-flop.

[0179] In some examples, the output signal may be generated using a signal output by control logic that disables the clock gating circuit.The output signal may be configured to provide timing for writing data captured from the single-wire bus.

[0180] In some examples, the method includes configuring a second counter to drive a second control input of the clock gating circuit. The second counter can be timed by a signal received from the single-wire bus. The second counter can remain in a reset state when the single-wire bus is idle and until an SSC is detected in the signal received from the single-wire bus. The second counter can be configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus. The clock gating circuit can be disabled until the second counter stops counting. The second counter can be reset when the output of the control logic that disables the clock gating circuit is used to generate a write clock signal output by the clock and data recovery device.

[0181] In some examples, signals received from the single-wire bus carry datagrams configured according to the RFFE protocol and encoded using Manchester encoding.

[0182] Fig.232302 is a diagram illustrating an example of a hardware implementation for an apparatus 2300 employing a processing circuit 2302. The processing circuit typically has a controller or processor 2316 that may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. The processing circuit 2302 may be implemented with a bus architecture, which is generally represented by a bus 2320. Depending on the specific application of the processing circuit 2302 and the overall design constraints, the bus 2320 may include any number of interconnecting buses and bridges. The bus 2320 links together various circuits including one or more processors and / or hardware modules represented by the controller or processor 2316, modules or circuits 2304, 2306, 2308, and 2310, and a processor-readable storage medium 2318. One or more physical layer circuits and / or modules 2314 may be provided to support communications over a communication link implemented using a multi-wire bus 2312, through an antenna or antenna array 2322 (e.g., to a radio access network), etc. The bus 2320 may also link various other circuits, such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0183] The processor 2316 is responsible for general processing, including executing software, code, and / or instructions stored on the processor readable storage medium 2318. The processor readable storage medium 2318 may include a non-transitory storage medium. The software, when executed by the processor 2316, causes the processing circuit 2302 to perform various functions described herein and described for any particular device. The processor readable storage medium 2318 may be used to store data manipulated by the processor 2316 when executing the software. The processing circuit 2302 also includes at least one of the modules 2304, 2306, 2308, and 2310. The modules 2304, 2306, 2308, and 2310 may be software modules running in the processor 2316, resident / stored in the processor readable storage medium 2318, one or more hardware modules coupled to the processor 2316, or some combination thereof. The modules 2304, 2306, 2308, and 2310 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0184] In one configuration, the apparatus 2300 includes modules and / or circuits 2304 adapted to monitor the single-wire bus for activity, inactivity, and control signaling. The apparatus 2300 also includes modules and / or circuits 2306 adapted to generate one or more internal clock signals for decoding signals received over the single-wire bus. The apparatus 2300 also includes modules and / or circuits 2308 configured to synchronize the internal clock signals with edges in the signals received over the single-wire bus. The apparatus 2300 also includes modules and / or circuits 2310 adapted to capture and decode data from the signals received over the single-wire bus.

[0185] In one example, the device 2300 includes a physical layer circuit and / or module 2314 that implements an interface circuit having at least one line receiver, and the at least one line driver is adapted or configured to couple the device 2300 to a single-line serial bus. The device 2300 may have a processor 2316 or a protocol controller. The device 2300 may include a keeper circuit or be coupled to a keeper circuit via a single-line serial bus. The keeper circuit is operable to maintain the single-line serial bus in a constant signaling state after the line drivers in the bus master and slave devices present a high impedance to the single-line serial bus.

[0186] The device 2300 may be configured to operate as a clock and data recovery device and include an oscillator configured to generate a base clock signal having a base frequency; a clock gating circuit responsive to one or more control inputs and configured to output a gated base clock signal when the clock gating circuit is enabled; a first counter clocked by the gated base clock signal and configured to provide a counter output reflecting a count of positive edges and negative edges in the gated base clock signal; control logic coupled to a first control input of the clock gating circuit and configured to disable the clock gating circuit when the counter output corresponds to a maximum count value; and an edge synchronization circuit coupled to the single-wire bus. The edge synchronization circuit may be configured to ignore edges in a signal received from the single-wire bus when the counter output has a value less than the maximum count value, and to reset the first counter in response to an edge detected in the signal received from the single-wire bus.

[0187] In various examples, a signal received from a single-wire bus is Manchester encoded based on an encoding clock having a frequency that is four times the fundamental frequency of a fundamental clock signal. In one example, the encoding clock has a frequency of at least 52 MHz. The clock and data recovery device may include a flip-flop configured to capture a data bit from the single-wire bus in response to an edge detected in a signal received from the single-wire bus. A signal output by control logic of a disabled clock gating circuit may be used to clock the flip-flop. A signal output by control logic of a disabled clock gating circuit is used to generate a write clock signal output by the clock and data recovery device.

[0188] In some examples, the clock and data recovery device includes a second counter timed by a signal received from the single-wire bus. The second counter may be configured to drive a second control input of the clock gating circuit. The second counter may remain in a reset state when the single-wire bus is idle and until an SSC is detected in the signal received from the single-wire bus. The second counter may be configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus. The clock gating circuit may be disabled until the second counter stops counting. The second counter may be reset when the output of the control logic that disables the clock gating circuit is used to generate a write clock signal output by the clock and data recovery device. The signal received from the single-wire bus may carry a datagram configured according to the RFFE protocol and encoded using Manchester encoding.

[0189] The processor-readable storage medium 2318 stores code and data. The code may be executed by the processor 2316, a state machine, or a sequencer. The code, when executed by the processor 2316, causes the processing circuit 2302 to configure the oscillator to generate a base clock signal having a base frequency; configure the clock gating circuit to output a gated base clock signal when the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs; configure the first counter to provide a counter output reflecting a count of positive edges and negative edges in the gated base clock signal that clocks the first counter; configure the control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and configure the edge synchronization circuit. The edge synchronization circuit may be configured to ignore edges in a signal received by the edge synchronization circuit from a single-wire bus when the counter output has a value less than the maximum count value, and further configured to reset the first counter in response to an edge detected in the signal received from the single-wire bus.

[0190] In some examples, the signal received from the single-wire bus carries a Manchester-encoded datagram configured according to the RFFE protocol. The datagram can be encoded using an encoding clock having a frequency that is four times the fundamental frequency of the fundamental clock signal.

[0191] In some examples, the processor readable storage medium 2318 stores code that, when executed by the processor 2316, causes the processing circuit 2302 to configure the second counter to drive the second control input of the clock gating circuit. The second counter can be timed by a signal received from the single-wire bus. When the single-wire bus is idle and until an SSC is detected in the signal received from the single-wire bus, the second counter can remain in a reset state. The second counter can be configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus. The clock gating circuit can be disabled until the second counter stops counting.

[0192] Some specific implementation examples are described in the following numbered clauses:

[0193] 1. A clock and data recovery device, comprising: an oscillator configured to generate a base clock signal having a base frequency; a clock gating circuit responsive to one or more control inputs and configured to output a gated base clock signal when the clock gating circuit is enabled; a first counter clocked by the gated base clock signal and configured to provide a counter output reflecting a count of positive edges and negative edges in the gated base clock signal; control logic coupled to a first control input of the clock gating circuit and configured to disable the clock gating circuit when the counter output corresponds to a maximum count value; and an edge synchronization circuit coupled to a single-wire bus and configured to: ignore edges in a signal received from the single-wire bus when the counter output has a value less than the maximum count value; and reset the first counter in response to an edge detected in the signal received from the single-wire bus.

[0194] 2. A clock and data recovery apparatus according to clause 1, wherein the signal received from the single-wire bus is Manchester encoded based on an encoding clock having a frequency four times the fundamental frequency of the fundamental clock signal.

[0195] 3. A clock and data recovery apparatus according to clause 2, wherein the encoding clock has a frequency of at least 52 MHz.

[0196] 4. A clock and data recovery apparatus according to any one of clauses 1 to 3, further comprising: a flip-flop configured to capture a data bit from the single-wire bus in response to an edge detected in the signal received from the single-wire bus.

[0197] 5. The clock and data recovery apparatus of clause 4, wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flip-flop.

[0198] 6. A clock and data recovery apparatus according to any one of clauses 1 to 5, wherein a signal output by the control logic that disables the clock gating circuit is used to generate a write clock signal output by the clock and data recovery apparatus.

[0199] 7. A clock and data recovery device according to any one of clauses 1 to 6, further comprising: a second counter, the second counter being timed by the signal received from the single-wire bus and being configured to drive a second control input of the clock gating circuit, wherein the second counter remains in a reset state when the single-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the single-wire bus, wherein the second counter is configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus, and wherein the clock gating circuit is disabled until the second counter stops counting.

[0200] 8. The clock and data recovery apparatus of clause 7, wherein the second counter is reset when an output of the control logic of the clock gating circuit is disabled for generating a write clock signal output by the clock and data recovery apparatus.

[0201] 9. A clock and data recovery apparatus according to any one of clauses 1 to 8, wherein the signal received from the single wire bus carries a datagram configured according to a Radio Frequency Front End (RFFE) protocol and encoded using Manchester encoding.

[0202] 10. A data communication method, comprising: configuring an oscillator to generate a base clock signal having a base frequency; configuring a clock gating circuit to output a gated base clock signal when the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs; configuring a first counter to provide a counter output reflecting a count of positive edges and negative edges in the gated base clock signal that clocks the first counter; configuring control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and configuring an edge synchronization circuit to: ignore edges in a signal received by the edge synchronization circuit from a single-wire bus when the counter output has a value less than the maximum count value; and responsive to an edge synchronization circuit being received from the single-wire bus

[0203] The first counter is reset by an edge detected in the signal received by the single-wire bus.

[0204] 11. The method of clause 10, wherein the signal received from the single-wire bus is Manchester encoded based on an encoding clock having a frequency four times the fundamental frequency of the fundamental clock signal.

[0205] 12. The method of clause 11, wherein the encoding clock has a frequency of at least 52 MHz.

[0206] 13. The method of any of clauses 10 to 12, further comprising configuring a flip-flop to capture a data bit from the single-wire bus in response to an edge detected in the signal received from the single-wire bus.

[0207] 14. The method of clause 13, wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flip-flop.

[0208] 15. The method of any of clauses 10 to 14, further comprising: using a signal output by the control logic that disables the clock gating circuit to generate an output signal configured to provide timing for writing data captured from the single-wire bus.

[0209] 16. The method according to any one of clauses 10 to 15, further comprising: configuring a second counter to drive a control input of the clock gating circuit, the second counter being timed by the signal received from the single-wire bus, wherein the second counter remains in a reset state when the single-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the single-wire bus, wherein the second counter is configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus, and wherein the clock gating circuit is disabled until the second counter stops counting.

[0210] 17. The method of clause 16, wherein the second counter is reset when an output of the control logic that disables the clock gating circuit is used to generate an output signal configured to provide timing for writing data captured from the single-wire bus.

[0211] 18. A method according to any of clauses 10 to 17, wherein the signal received from the single wire bus carries a datagram configured according to a Radio Frequency Front End (RFFE) protocol and encoded using Manchester encoding.

[0212] 19. A data communication device, comprising: a component for generating a basic clock signal having a basic frequency; a component for gating the basic clock signal, comprising a clock gating circuit responsive to one or more control inputs, the component for gating the basic clock signal being configured to output a gated basic clock signal when the clock gating circuit is enabled; a component for counting positive and negative edges in the gated basic clock signal, comprising a first counter timed by the gated basic clock signal; a component for disabling the clock gating circuit, comprising a first control circuit coupled to the clock gating circuit a control logic input to a control input, the component for disabling the clock gating circuit being configured to disable the clock gating circuit when the output of the first counter corresponds to a maximum count value; and a component for synchronizing the component for counting positive and negative edges in the signal received from the single-wire bus, the component for synchronizing being configured to: ignore edges in the signal received from the single-wire bus when the output of the first counter represents a value less than the maximum count value; and reset the first counter in response to an edge detected in the signal received from the single-wire bus.

[0213] 20. The data communication device of clause 19, wherein the signal received from the single-wire bus is Manchester encoded based on an encoding clock having a frequency four times the fundamental frequency of the fundamental clock signal.

[0214] 21. The data communication device of clause 20, wherein the encoding clock has a frequency of at least 52 MHz.

[0215] 22. A data communications apparatus according to any of clauses 19 to 21, further comprising means for capturing data bits from the single-wire bus in response to edges detected in the signal received from the single-wire bus.

[0216] 23. The data communications device of clause 22, wherein the means for capturing data bits from the single-wire bus comprises a flip-flop, and wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flip-flop.

[0217] 24. A data communications device according to any of clauses 19 to 23, wherein a signal output by the control logic that disables the clock gating circuit is used to generate a write clock signal output by the data communications device.

[0218] 25. A data communication device according to any one of clauses 19 to 24, further comprising: a component for counting synchronization pulses, comprising a second counter timed by the signal received from the single-wire bus, the component for counting synchronization pulses being configured to drive a second control input of the clock gating circuit, wherein the second counter remains in a reset state when the single-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the single-wire bus, wherein the component for counting synchronization pulses is configured to stop the second counter when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus, and wherein the clock gating circuit is disabled until the second counter stops counting.

[0219] 26. The data communications device of clause 25, wherein the second counter is reset when an output of the control logic of the clock gating circuit is disabled for use in generating a write clock signal output by the data communications device.

[0220] 27. A data communications device according to any of clauses 19 to 26, wherein the signal received from the single wire bus carries a datagram configured according to a Radio Frequency Front End (RFFE) protocol and encoded using Manchester encoding.

[0221] 28. A processor-readable storage medium having code stored thereon, the code, when executed by a processor in a processing circuit, causes the processing circuit to: configure an oscillator to generate a basic clock signal having a basic frequency; configure a clock gating circuit to output a gated basic clock signal when the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs; configure a first counter to provide a counter output reflecting a count of positive edges and negative edges in the gated basic clock signal that clocks the first counter; configure control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and configure an edge synchronization circuit to: ignore edges in a signal received by the edge synchronization circuit from a single-wire bus when the counter output has a value less than the maximum count value; and reset the first counter in response to an edge detected in the signal received from the single-wire bus.

[0222] 29. A processor-readable storage medium according to clause 28, wherein the signal received from the single-wire bus carries a Manchester encoded datagram configured according to a radio frequency front end (RFFE) protocol and encoded using an encoding clock, the frequency of which is four times the base frequency of the base clock signal.

[0223] 30. A processor-readable storage medium according to clause 28 or clause 29, wherein the code further causes the processing circuit to: configure a second counter to drive a control input of the clock gating circuit, the second counter being timed by the signal received from the single-wire bus, wherein the second counter remains in a reset state when the single-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the single-wire bus, wherein the second counter is configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus, and wherein the clock gating circuit is disabled until the second counter stops counting.

[0224] It should be understood that the specific order or hierarchy of steps in the disclosed processes is an illustration of an exemplary method. It should be understood that the specific order or hierarchy of steps in these processes can be rearranged according to design preferences. In addition, some steps can be combined or omitted. The attached method claims present the elements of multiple steps in a sample order and are not meant to be limited to the specific order or hierarchy presented.

[0225] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the claims, wherein unless otherwise specified, references to elements in the singular are not intended to mean "one and only one", but "one or more". Unless otherwise specified, the term "some" refers to one or more. All structural and functional equivalents of the elements of the various aspects described throughout the present disclosure that are known or will be known later to a person of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. Any claim element cannot be interpreted as a component plus function unless the element is explicitly stated using the phrase "component for..."

Claims

1. A clock and data recovery device, comprising: an oscillator configured to generate a base clock signal having a base frequency; a clock gating circuit responsive to one or more control inputs and configured to output a gated base clock signal when the clock gating circuit is enabled; a first counter clocked by the gated base clock signal and configured to provide a counter output reflecting a count of positive and negative edges in the gated base clock signal; control logic coupled to a first control input of the clock gating circuit and configured to disable the clock gating circuit when the counter output corresponds to a maximum count value; and An edge synchronization circuit is coupled to the single-wire bus and is configured to: ignoring edges in a signal received from the single-wire bus when the counter output has a value less than the maximum count value; as well as The first counter is reset in response to an edge detected in the signal received from the single-wire bus.

2. The clock and data recovery apparatus according to claim 1, wherein the signal received from the single-wire bus is Manchester encoded based on an encoding clock whose frequency is four times the fundamental frequency of the fundamental clock signal.

3. The clock and data recovery apparatus of claim 2, wherein the encoding clock has a frequency of at least 52 MHz.

4. The clock and data recovery device according to claim 1, further comprising: A flip-flop is configured to capture a data bit from the single-wire bus in response to an edge detected in the signal received from the single-wire bus.

5. The clock and data recovery apparatus of claim 4, wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flip-flop.

6. The clock and data recovery apparatus of claim 1, wherein a signal output by the control logic that disables the clock gating circuit is used to generate a write clock signal output by the clock and data recovery apparatus.

7. The clock and data recovery device according to claim 1, further comprising: a second counter clocked by the signal received from the single-wire bus and configured to drive a second control input of the clock gating circuit, wherein the second counter remains in a reset state when the single-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the single-wire bus, Wherein the second counter is configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus, and wherein the clock gating circuit is disabled until the second counter stops counting.

8. The clock and data recovery apparatus of claim 7, wherein the second counter is reset when the output of the control logic of the clock gating circuit is disabled for generating a write clock signal output by the clock and data recovery apparatus.

9. The clock and data recovery apparatus of claim 1, wherein the signal received from the single-wire bus carries a datagram configured according to a radio frequency front end (RFFE) protocol and encoded using Manchester encoding.

10. A method of data communication, comprising: configuring the oscillator to generate a base clock signal having a base frequency; configuring a clock gating circuit to output a gated base clock signal when the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs; configuring a first counter to provide a counter output reflecting a count of positive and negative edges in the gated base clock signal that clocks the first counter; configuring control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; as well as Configure the edge synchronous circuit as: ignoring edges in a signal received by the edge synchronization circuit from a single-wire bus when the counter output has a value less than the maximum count value; and The first counter is reset in response to an edge detected in the signal received from the single-wire bus.

11. The method of claim 10, wherein the signal received from the single-wire bus is Manchester encoded based on an encoding clock having a frequency four times the fundamental frequency of the fundamental clock signal.

12. The method of claim 11, wherein the encoding clock has a frequency of at least 52 MHz.

13. The method according to claim 10, further comprising: A flip-flop is configured to capture a data bit from the single-wire bus in response to an edge detected in the signal received from the single-wire bus.

14. The method of claim 13, wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flip-flop.

15. The method according to claim 10, further comprising: An output signal configured to provide timing for writing data captured from the single-wire bus is generated using a signal output by the control logic that disables the clock gating circuit.

16. The method according to claim 10, further comprising: configuring a second counter to drive a control input of the clock gating circuit, the second counter being clocked by the signal received from the single-wire bus, wherein the second counter remains in a reset state when the single-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the single-wire bus, Wherein the second counter is configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus, and wherein the clock gating circuit is disabled until the second counter stops counting.

17. The method of claim 16, wherein the second counter is reset when an output of the control logic that disables the clock gating circuit is used to generate an output signal configured to provide timing for writing data captured from the single-wire bus.

18. The method of claim 10, wherein the signal received from the single-wire bus carries a datagram configured according to a radio frequency front end (RFFE) protocol and encoded using Manchester encoding.

19. A data communication device, comprising: means for generating a basic clock signal having a basic frequency; means for gating the base clock signal, comprising a clock gating circuit responsive to one or more control inputs, the means for gating the base clock signal being configured to output a gated base clock signal when the clock gating circuit is enabled; means for counting positive edges and negative edges in the gated base clock signal, comprising a first counter timed by the gated base clock signal; means for disabling the clock gating circuit, comprising control logic coupled to a first control input of the clock gating circuit, the means for disabling the clock gating circuit being configured to disable the clock gating circuit when an output of the first counter corresponds to a maximum count value; and means for synchronizing said means for counting positive and negative edges in said signal received from a single-wire bus, said means for synchronizing being configured to: ignoring edges in the signal received from the single-wire bus when the output of the first counter represents a value less than the maximum count value; as well as The first counter is reset in response to an edge detected in the signal received from the single-wire bus.

20. The data communication device of claim 19, wherein the signal received from the single-wire bus is Manchester-encoded based on an encoding clock having a frequency four times the basic frequency of the basic clock signal.

21. The data communication device of claim 20, wherein the encoding clock has a frequency of at least 52 MHz.

22. The data communication device according to claim 19, further comprising: Means for capturing data bits from the single-wire bus in response to edges detected in the signal received from the single-wire bus.

23. The data communications apparatus of claim 22, wherein the means for capturing data bits from the single-wire bus comprises a flip-flop, and wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flip-flop.

24. The data communication device of claim 19, wherein a signal output by the control logic that disables the clock gating circuit is used to generate a write clock signal output by the data communication device.

25. The data communication device according to claim 19, further comprising: means for counting synchronization pulses, comprising a second counter clocked by the signal received from the single-wire bus, the means for counting synchronization pulses being configured to drive a second control input of the clock gating circuit, wherein the second counter remains in a reset state when the single-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the single-wire bus, wherein the means for counting synchronization pulses is configured to stop the second counter when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus, and The clock gating circuit is disabled until the second counter stops counting.

26. The data communication device of claim 25, wherein the second counter is reset when an output of the control logic of the clock gating circuit is disabled for generating a write clock signal output by the data communication device.

27. The data communication device of claim 19, wherein the signal received from the single-wire bus carries a datagram configured according to a radio frequency front end (RFFE) protocol and encoded using Manchester encoding.

28. A processor-readable storage medium having stored thereon code which, when executed by a processor in a processing circuit, causes the processing circuit to: configuring the oscillator to generate a base clock signal having a base frequency; configuring a clock gating circuit to output a gated base clock signal when the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs; configuring a first counter to provide a counter output reflecting a count of positive and negative edges in the gated base clock signal that clocks the first counter; configuring control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; as well as Configure the edge synchronous circuit as: ignoring edges in a signal received by the edge synchronization circuit from a single-wire bus when the counter output has a value less than the maximum count value; and The first counter is reset in response to an edge detected in the signal received from the single-wire bus.

29. A processor-readable storage medium according to claim 28, wherein the signal received from the single-wire bus carries a Manchester encoded datagram configured according to a radio frequency front end (RFFE) protocol and encoded using an encoding clock, the frequency of which is four times the base frequency of the base clock signal.

30. The processor-readable storage medium of claim 28, wherein the code further causes the processing circuit to: configuring a second counter to drive a control input of the clock gating circuit, the second counter being clocked by the signal received from the single-wire bus, wherein the second counter remains in a reset state when the single-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the single-wire bus, Wherein the second counter is configured to stop counting when an expected number of synchronization pulses has been counted in the signal received from the single-wire bus, and wherein the clock gating circuit is disabled until the second counter stops counting.

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