Adaptive digital predistortion

Abstract

Aspects of the present disclosure generally relate to wireless communications. In some aspects, an apparatus may receive, from a plurality of digital pre-distortion (DPD) cores, an indication of a selected DPD core. The apparatus may store a plurality of envelope values associated with samples of an in-phase / quadrature (I / Q) signal and select a subset of envelope values based at least in part on the selected DPD kernel. The apparatus may generate an envelope calculated value using the subset of envelope values and a lookup table (LUT) component. The apparatus may store a plurality of calculated values associated with the sample and select at least one subset of calculated values based at least in part on the selected DPD kernel. The device may generate an output sample including a DPD based at least in part on combining the envelope calculated value with the at least one subset of calculated values. Numerous other aspects are described.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. non-provisional patent application No. 17 / 812,611, entitled “ADAPTIVE DIGITAL PRE-DISTORTION,” filed on July 14, 2022, which is hereby expressly incorporated herein by reference. Technical Field

[0003] Aspects of the present disclosure relate generally to wireless communications, and to techniques and apparatus for adaptive digital predistortion. Background Art

[0004] Wireless communication systems are widely deployed to provide a variety of telecommunication services, such as telephony, video, data, messaging, and broadcasting. Typical wireless communication systems may employ multiple access technologies that can support communication with multiple users by sharing available system resources (e.g., bandwidth, transmit power, etc.). Examples of such multiple access technologies include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single carrier frequency division multiple access (SC-FDMA) systems, time division synchronous code division multiple access (TD-SCDMA) systems, and long term evolution (LTE). LTE / LTE-Advanced is a set of enhancements to the Universal Mobile Telecommunications System (UMTS) mobile standard promulgated by the Third Generation Partnership Project (3GPP).

[0005] A wireless network may include one or more network nodes that support communications for wireless communication devices, such as user equipment (UE) or multiple UEs. A UE may communicate with a network node via downlink communications and uplink communications. A "downlink" (or "DL") refers to a communication link from a network node to a UE, and an "uplink" (or "UL") refers to a communication link from a UE to a network node. Some wireless networks may support device-to-device communications, such as via a local link (e.g., a side link (SL), a wireless local area network (WLAN) link, and / or a wireless personal area network (WPAN) link, etc.).

[0006] The above-mentioned multiple access technologies have been adopted in various telecommunication standards to provide a common protocol that enables different UEs to communicate at a city, country, region and / or global level. New Radio (NR), which may be referred to as 5G, is a set of enhancements to the LTE mobile standard promulgated by 3GPP. NR is designed to better support mobile broadband Internet access by improving spectrum efficiency, reducing costs, improving services, utilizing new spectrum, and using orthogonal frequency division multiplexing (OFDM) with cyclic prefix (CP) (CP-OFDM) on the downlink, using CP-OFDM and / or single carrier frequency division multiplexing (SC-FDM) (also known as discrete Fourier transform spread OFDM (DFT-s-OFDM)) on the uplink to better integrate with other open standards, as well as supporting beamforming, multiple input multiple output (MIMO) antenna technology and carrier aggregation. As the demand for mobile broadband access continues to increase, further improvements in LTE, NR and other radio access technologies remain useful. Summary of the invention

[0007] Some aspects described herein relate to an apparatus for wireless communication at a device. The apparatus may include a first input mechanism configured to receive an indication of a selected digital predistortion (DPD) kernel from a plurality of DPD kernels. Alternatively or additionally, the apparatus may include an envelope delay line component, the envelope delay line component including an envelope storage component configured to store an input envelope value as one of a plurality of envelope values ​​associated with a plurality of samples sampled within a time duration. The apparatus may include an envelope selection component configured to select an envelope value subset from the plurality of envelope values ​​based at least in part on the selected DPD kernel. In some aspects, the apparatus may include at least one lookup table (LUT) component coupled to the envelope selection component. The at least one LUT component may include: a second input mechanism configured to receive the envelope value subset; an output component configured to output an envelope calculation value based at least in part on the envelope value subset. The device may include a computational delay line component, the computational delay line component including a computational storage component. The computational storage component of the computational delay line component may be configured to store at least the following items: a first plurality of computational values, the first plurality of computational values ​​being based at least in part on a first computation applied to each of the plurality of samples; a second plurality of computational values, the second plurality of computational values ​​being based at least in part on a second computation applied to each of the plurality of samples; and the plurality of samples, the plurality of samples spanning the time duration. In some aspects, the device may include at least one computational selection component, the at least one computational selection component being coupled to the computational delay line component and being configured to select at least a subset of the computational values ​​stored by the computational storage component based at least in part on the selected DPD kernel. Alternatively or additionally, the device may include at least one combiner component, the at least one combiner component being coupled to the at least one computational selection component and the at least one LUT component. The at least one combiner component may be configured to generate an output sample based at least in part on combining the envelope computational value with the at least one computational value subset.

[0008] Some aspects described herein relate to a method performed by an apparatus. The method may include receiving an indication of a selected DPD kernel from a plurality of DPD kernels. The method may include storing an envelope value associated with a sample of an I / Q signal based at least in part on an envelope delay line component, the storing including storing the envelope value as one of a plurality of envelope values ​​across a time duration, the plurality of envelope values ​​being based at least in part on a plurality of samples associated with the I / Q signal. The method may include storing at least the following based at least in part on a computation storage component: a first computation value as one of a first plurality of computation values, the first plurality of computation values ​​being based at least in part on the plurality of samples, the first computation value being based at least in part on a first computation applied to the sample; and a second computation value as one of a second plurality of computation values, the second plurality of computation values ​​being based at least in part on the plurality of samples, the second computation value being based at least in part on a second computation applied to the sample. The method may include selecting an envelope value subset from the plurality of envelope values ​​based at least in part on the selected DPD kernel. The method may include generating an envelope calculation value based at least in part on the subset of envelope values, at least one LUT component, and the selected DPD kernel. The method may include selecting at least one calculation value subset stored by the calculation storage component based at least in part on the selected DPD kernel. The method may include generating output samples including digital predistortion based at least in part on combining the envelope calculation value with the at least one calculation value subset.

[0009] Some aspects described herein relate to a non-transitory computer-readable medium storing an instruction set for wireless communication by a device. The instruction set, when executed by one or more processors of the device, may cause the device to receive an indication of a selected DPD kernel from a plurality of DPD kernels. The instruction set, when executed by one or more processors of the device, may cause the device to store an envelope value associated with a sample of an I / Q signal based at least in part on an envelope delay line component, the storing comprising storing the envelope value as one of a plurality of envelope values ​​across a time duration, the plurality of envelope values ​​being based at least in part on a plurality of samples associated with the I / Q signal. In some aspects, the instruction set, when executed by one or more processors of the device, may cause the device to store at least the following items based at least in part on a computation storage component: a first computation value as one of a first plurality of computation values, the first plurality of computation values ​​being based at least in part on the plurality of samples, the first computation value being based at least in part on a first computation applied to the sample. Alternatively or additionally, the instruction set, when executed by one or more processors of the device, may cause the device to store the following items based at least in part on the computational storage component: a second computational value as one of the second plurality of computational values, the second plurality of computational values ​​being based at least in part on the plurality of samples, the second computational value being based at least in part on a second computation applied to the samples. In some aspects, the instruction set, when executed by one or more processors of the device, may cause the device to store the plurality of samples based at least in part on the computational storage component. The instruction set, when executed by one or more processors of the device, may cause the device to select a subset of envelope values ​​from the plurality of envelope values ​​based at least in part on the selected DPD kernel. The instruction set, when executed by one or more processors of the device, may cause the device to generate an envelope computational value based at least in part on the subset of envelope values, the selected DPD kernel, and at least one LUT component. The instruction set, when executed by one or more processors of the device, may cause the device to select at least one subset of computational values ​​stored by the computational storage component based at least in part on the selected DPD kernel. The set of instructions, when executed by one or more processors of the apparatus, may cause the apparatus to generate output samples including digital predistortion based at least in part on combining the envelope calculation value with the at least one calculation value subset.

[0010] Some aspects described herein relate to an apparatus for wireless communication. The apparatus may include means for receiving an indication of a selected DPD kernel from a plurality of DPD kernels. The apparatus may include means for storing an envelope value associated with a sample of an I / Q signal based at least in part on an envelope delay line component, the storing comprising storing the envelope value as one of a plurality of envelope values ​​across a time duration, the plurality of envelope values ​​being based at least in part on a plurality of samples associated with the I / Q signal. The apparatus may include means for storing at least the following items based at least in part on a computation storage component: a first computation value as one of a first plurality of computation values, the first plurality of computation values ​​being based at least in part on the plurality of samples, the first computation value being based at least in part on a first computation applied to the sample; and a second computation value as one of a second plurality of computation values, the second plurality of computation values ​​being based at least in part on the plurality of samples, the second computation value being based at least in part on a second computation applied to the sample. The apparatus may include means for selecting a subset of envelope values ​​from the plurality of envelope values ​​based at least in part on the selected DPD kernel. The apparatus may include means for generating an envelope calculation value based at least in part on the subset of envelope values, at least one LUT component, and the selected DPD kernel. The apparatus may include means for selecting at least one subset of calculation values ​​stored by the calculation storage component based at least in part on the selected DPD kernel. The apparatus may include means for generating output samples including digital predistortion based at least in part on combining the envelope calculation value with the at least one subset of calculation values.

[0011] Some aspects described herein relate to an apparatus for wireless communication at a device. The apparatus may include: a power amplifier; a digital-to-analog converter (DAC) coupled to the power amplifier; and an adaptive DPD device coupled to the DAC. The adaptive DPD device includes an envelope delay line component, the envelope delay line component including an envelope storage component, the envelope storage component configured to store a plurality of envelope values ​​associated with a plurality of samples of an I / Q signal. Alternatively or additionally, the adaptive DPD device may include: an envelope selection component, the envelope selection component configured to select a subset of envelope values ​​from the plurality of envelope values; and at least one LUT component, the at least one LUT component coupled to the envelope selection component. The at least one LUT component may include an output mechanism, the output mechanism configured to output an envelope calculation value, the envelope calculation value being based at least in part on the subset of envelope values. The adaptive DPD device may include a calculation delay line component, the calculation delay line component including a calculation storage component, the calculation storage component configured to store a plurality of calculation values, the plurality of calculation values ​​being based at least in part on the plurality of samples. The adaptive DPD device may include at least one calculation selection component coupled to the calculation delay line component and configured to select at least one calculation value subset stored by the calculation storage component based at least in part on a selected DPD kernel from a plurality of DPD kernels. In some aspects, the adaptive DPD device includes at least one combiner component coupled to the at least one calculation selection component and the at least one LUT component. The at least one combiner component may be configured to generate an output sample based at least in part on combining the envelope calculation value with the at least one calculation value subset.

[0012] The various aspects generally include methods, apparatus, systems, computer program products, non-transitory computer-readable media, user equipment, base stations, network entities, network nodes, wireless communication devices and / or processing systems as fully described herein with reference to the drawings and description and as illustrated in the drawings and description.

[0013] The features and technical advantages of examples according to the present disclosure have been outlined quite broadly above so that the following specific embodiments may be better understood. Additional features and advantages will be described below. The disclosed concepts and specific examples may be easily used as a basis for modifying or designing other structures for achieving the same purpose of the present disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein, both in terms of their organization and method of operation, and the associated advantages will be better understood by considering the following description in conjunction with the accompanying drawings. Each of the figures in the accompanying drawings is provided for the purpose of illustration and description, and not as a definition of the limitations of the claims.

[0014] Although various aspects are described in the present disclosure by illustrating some examples, it will be understood by those skilled in the art that such aspects can be implemented in many different arrangements and scenarios. The technology described herein can be implemented using different platform types, devices, systems, shapes, sizes and / or packaging arrangements. For example, some aspects can be implemented via integrated chip implementations or other devices based on non-module components (e.g., end-user devices, vehicles, communication equipment, computing equipment, industrial equipment, retail / shopping equipment, medical equipment and / or artificial intelligence devices). Various aspects can be implemented in chip-level components, modular components, non-modular components, non-chip-level components, device-level components and / or system-level components. The equipment incorporating the various aspects and features described may include additional components and features for implementing and practicing the various aspects claimed and described. For example, the transmission and reception of wireless signals may include one or more components for analog and digital purposes (e.g., hardware components, including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders and / or summers). The various aspects described herein are intended to be practiced in various devices, components, systems, distributed arrangements and / or end-user devices of various sizes, shapes and configurations. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to fully understand the above-mentioned features of the present disclosure, a more specific description of the invention briefly summarized above can be obtained by referring to various aspects (some of which are illustrated in the accompanying drawings). However, it should be noted that the accompanying drawings only illustrate certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit other equally effective aspects. The same reference numerals in different drawings may identify the same or similar elements.

[0016] Figure 1 is a diagram illustrating an example of a wireless network according to the present disclosure.

[0017] Figure 2 is a diagram illustrating an example of communication between a network node and a user equipment (UE) in a wireless network according to the present disclosure.

[0018] Figure 3 is a diagram illustrating an example of a wireless transceiver that may be used by a device to communicate in a wireless network in accordance with the present disclosure.

[0019] Figure 4 is a diagram illustrating an example decomposed base station architecture according to the present disclosure.

[0020] Figure 5 is a diagram illustrating an example including a transmitter that may include a digital pre-distortion (DPD) capability and a receiver that may include a digital post-distortion (DPoD) capability according to the present disclosure.

[0021] Figure 6 is a diagram illustrating an example of a table specifying calculations and / or values ​​that may be used in a generalized DPD kernel according to the present disclosure.

[0022] Figure 7 is a diagram illustrating an example of an adaptive DPD apparatus according to the present disclosure.

[0023] Figure 8 is a diagram of an example including a delay line multiplexer selection component according to the present disclosure.

[0024] Fig. 9A and Fig. 9B is a diagram illustrating an example process performed, for example, by a device according to the present disclosure. DETAILED DESCRIPTION

[0025] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. Instead, these aspects are provided so that the present disclosure will be thorough and complete, and the protection scope of the present disclosure will be fully conveyed to those skilled in the art. It will be appreciated by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods implemented using other structures, functionality, or structures and functionality in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the present invention.

[0026] Several aspects of telecommunication systems will now be presented with reference to various devices and techniques. These devices and techniques will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using hardware, software, or a combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0027] Although various aspects may be described herein using terms generally associated with 5G or new radio (NR) radio access technology (RAT), various aspects of the present disclosure may be applied to other RATs, such as 3G RAT, 4G RAT and / or RATs beyond 5G (e.g., 6G).

[0028] Figure 11 is a diagram illustrating an example of a wireless network 100 according to the present disclosure. The wireless network 100 may be a 5G (e.g., NR) network and / or a 4G (e.g., Long Term Evolution (LTE)) network, or may include elements of a 5G (e.g., NR) network and / or elements of a 4G (e.g., Long Term Evolution (LTE)) network, as well as other examples. The wireless network 100 may include one or more network nodes 110 (shown as network node 110a, network node 110b, network node 110c, and network node 110d), user equipment (UE) 120 or multiple UEs 120 (shown as UE 120a, UE 120b, UE 120c, UE 120d, and UE 120e), and / or other entities. The network node 110 is a network node that communicates with the UE 120. As shown in the figure, the network node 110 may include one or more network nodes. For example, the network node 110 may be a converged network node, which means that the converged network node is configured to utilize a radio protocol stack that is physically or logically integrated within a single radio access network (RAN) node (e.g., within a single device or unit). For another example, the network node 110 may be a decomposed network node (sometimes referred to as a decomposed base station), which means that the network node 110 is configured to utilize a protocol stack that is physically or logically distributed between two or more nodes (such as one or more central units (CUs), one or more distributed units (DUs), or one or more radio units (RUs)).

[0029] In some examples, the network node 110 is or includes a network node (such as an RU) that communicates with the UE 120 via a radio access link. In some examples, the network node 110 is or includes a network node (such as a DU) that communicates with other network nodes 110 via a fronthaul link or a midhaul link. In some examples, the network node 110 is or includes a network node (such as a CU) that communicates with other network nodes 110 via a midhaul link or communicates with the core network via a backhaul link. In some examples, the network node 110 (such as an aggregated network node 110 or a decomposed network node 110) may include multiple network nodes, such as one or more RUs, one or more CUs, and / or one or more DUs. For example, the network node 110 may include an NR base station, an LTE base station, a Node B, an eNB (e.g., in 4G), a gNB (e.g., in 5G), an access point, a transmit receive point (TRP), a DU, a RU, a CU, a mobility element of a network, a core network node, a network element, a network equipment, a RAN node, or a combination thereof. In some examples, network nodes 110 may be interconnected to each other or to one or more other network nodes 110 in wireless network 100 via various types of fronthaul, midhaul, and / or backhaul interfaces, such as direct physical connections, air interfaces, or virtual networks, using any suitable transport network.

[0030] In some examples, the network node 110 may provide communication coverage for a particular geographic area. In the Third Generation Partnership Project (3GPP), the term "cell" may refer to the coverage area of ​​the network node 110 and / or the network node subsystem serving the coverage area, depending on the context in which the term is used. The network node 110 may provide communication coverage for a macro cell, a pico cell, a femto cell, and / or another type of cell. A macro cell may cover a relatively large geographic area (e.g., a radius of several kilometers) and may allow unrestricted access by a UE 120 with a service subscription. A pico cell may cover a relatively small geographic area and may allow unrestricted access by a UE 120 with a service subscription. A femto cell may cover a relatively small geographic area (e.g., a home) and may allow restricted access by a UE 120 associated with the femto cell (e.g., a UE 120 in a closed subscriber group (CSG)). A network node 110 for a macro cell may be referred to as a macro network node. A network node 110 for a pico cell may be referred to as a pico network node. The network node 110 for a femto cell may be referred to as a femto network node or a home network node. Figure 1 In the example shown, network node 110a may be a macro network node for macro cell 102a, network node 110b may be a pico network node for pico cell 102b, and network node 110c may be a femto network node for femto cell 102c. The network node may support one or more (e.g., three) cells. In some examples, the cells may not necessarily be stationary, and the geographic area of ​​the cells may move according to the location of the mobile network node 110 (e.g., a mobile network node).

[0031] In some aspects, the term "base station" or "network node" may refer to a converged base station, a decomposed base station, an integrated access and backhaul (IAB) node, a relay node, or one or more components thereof. For example, in some aspects, a "base station" or "network node" may refer to a CU, a DU, a RU, a near real-time (near RT) RAN intelligent controller (RIC), or a non-real-time (non-RT) RIC, or a combination thereof. In some aspects, the term "base station" or "network node" may refer to a device configured to perform one or more functions (such as those described herein in conjunction with the network node 110). In some aspects, the term "base station" or "network node" may refer to a plurality of devices configured to perform one or more functions. For example, in some distributed systems, each of a number of different devices (which may be located in the same geographic location or in different geographic locations) may be configured to perform at least a portion of a function, or to repeat the execution of at least a portion of the function, and the term "base station" or "network node" may refer to any one or more of these different devices. In some aspects, the term "base station" or "network node" may refer to one or more virtual base stations or one or more virtual base station functions. For example, in some aspects, two or more base station functions may be instantiated on a single device. In some aspects, the term "base station" or "network node" may refer to one of the base station functions but not another base station function. In this way, a single device may include more than one base station.

[0032] The wireless network 100 may include one or more relay stations. A relay station is a network node that can receive transmissions of data from an upstream node (e.g., a network node 110 or a UE 120) and transmit transmissions of data to a downstream node (e.g., a UE 120 or a network node 110). A relay station may be a UE 120 that can relay transmissions for other UEs 120. Figure 1 In the example shown, a network node 110d (e.g., a relay network node) may communicate with a network node 110a (e.g., a macro network node) and a UE 120d to facilitate communications between the network node 110a and the UE 120d. A network node 110 that relays communications may be referred to as a relay station, a relay base station, a relay network node, a relay node, a relay, etc.

[0033] The wireless network 100 may be a heterogeneous network that includes different types of network nodes 110, such as macro network nodes, pico network nodes, femto network nodes, relay network nodes, etc. These different types of network nodes 110 may have different transmit power levels, different coverage areas, and / or different impacts on interference in the wireless network 100. For example, a macro network node may have a high transmit power level (e.g., 5 watts to 40 watts), while a pico network node, a femto network node, and a relay network node may have a lower transmit power level (e.g., 0.1 watt to 2 watts).

[0034] The network controller 130 may be coupled to or in communication with a set of network nodes 110 and may provide coordination and control for the network nodes 110. The network controller 130 may communicate with the network nodes 110 via a backhaul communication link or a midhaul communication link. The network nodes 110 may also communicate directly with each other or indirectly via a wireless backhaul link or a wired backhaul link. In some aspects, the network controller 130 may be or may include a CU or a core network device.

[0035] UE 120 may be dispersed throughout the wireless network 100, and each UE 120 may be stationary or mobile. UE 120 may include, for example, an access terminal, a terminal, a mobile station, and / or a subscriber unit. UE 120 may be a cellular phone (e.g., a smart phone), a personal digital assistant (PDA), a wireless modem, a wireless communication device, a handheld device, a laptop computer, a cordless phone, a wireless local loop (WLL) station, a tablet computer, a camera, a gaming device, a netbook, a smartbook, an ultrabook, a medical device, a biometric device, a wearable device (e.g., a smart watch, smart clothing, smart glasses, a smart wristband, smart jewelry (e.g., a smart ring or a smart bracelet)), an entertainment device (e.g., a music device, a video device, and / or a satellite radio), a vehicle component or sensor, a smart meter / sensor, an industrial manufacturing equipment, a global positioning system device, a UE function of a network node, and / or any other suitable device configured to communicate via a wireless or wired medium.

[0036] Some UEs 120 may be considered as machine type communication (MTC) or evolved or enhanced machine type communication (eMTC) UEs. MTC UEs and / or eMTC UEs may include, for example, robots, drones, remote devices, sensors, meters, monitors, and / or location tags that may communicate with a network node, another device (e.g., a remote device), or some other entity. Some UEs 120 may be considered as Internet of Things (IoT) devices and / or may be implemented as NB-IoT (narrowband IoT) devices. Some UEs 120 may be considered as customer premises equipment. UE 120 may be included in a housing that houses components of UE 120, such as a processor component and / or a memory component. In some examples, the processor component and the memory component may be coupled together. For example, a processor component (e.g., one or more processors) and a memory component (e.g., a memory) may be operationally coupled, communicatively coupled, electronically coupled, and / or electrically coupled.

[0037] Generally speaking, any number of wireless networks 100 may be deployed in a given geographic area. Each wireless network 100 may support a specific RAT and may operate on one or more frequencies. RAT may be referred to as a radio technology, air interface, etc. Frequency may be referred to as a carrier, frequency channel, etc. Each frequency may support a single RAT in a given geographic area to avoid interference between wireless networks of different RATs. In some cases, NR or 5G RAT networks may be deployed.

[0038] In some examples, two or more UEs 120 (e.g., shown as UE 120a and UE 120e) may communicate directly (e.g., without using network node 110 as an intermediary to communicate with each other) using one or more side link channels. For example, UE 120 may communicate using peer-to-peer (P2P) communication, device-to-device (D2D) communication, vehicle-to-everything (V2X) protocols (e.g., which may include vehicle-to-vehicle (V2V) protocols, vehicle-to-infrastructure (V2I) protocols, or vehicle-to-pedestrian (V2P) protocols), and / or mesh networks. In such examples, UE 120 may perform scheduling operations, resource selection operations, and / or other operations described elsewhere herein as being performed by network node 110.

[0039] The devices of the wireless network 100 may communicate using an electromagnetic spectrum, which may be subdivided into various categories, bands, channels, etc., according to frequency or wavelength. For example, the devices of the wireless network 100 may communicate using one or more operating bands. In 5G NR, two initial operating bands have been identified as frequency ranges designated FR1 (510 MHz–7.125 GHz) and FR2 (24.25 GHz–52.6 GHz). It should be understood that, although a portion of FR1 is greater than 6 GHz, FR1 is often (interchangeably) referred to as a “below 6 GHz” band in various documents and articles. A similar naming problem sometimes occurs with respect to FR2, which is often (interchangeably) referred to as a “millimeter wave” band in documents and articles, although it is different from the extremely high frequency (EHF) band (30 GHz–300 GHz) identified as a “millimeter wave” band by the International Telecommunication Union (ITU).

[0040] Frequencies between FR1 and FR2 are generally referred to as mid-band frequencies. Recent 5G NR research has identified the operating bands for these mid-band frequencies as frequency range designation FR3 (7.125 GHz–24.25 GHz). The bands falling within FR3 can inherit FR1 characteristics and / or FR2 characteristics, and thus the features of FR1 and / or FR2 can be effectively extended to mid-band frequencies. In addition, higher frequency bands are currently being explored to extend 5G NR operations to more than 52.6 GHz. For example, three higher operating bands have been identified as frequency range designations FR4a or FR4-1 (52.6 GHz–71 GHz), FR4 (52.6 GHz–114.25 GHz), and FR5 (114.25 GHz–300 GHz). Each of these higher frequency bands falls within the EHF band.

[0041] Considering the above examples, unless otherwise explicitly stated, it should be understood that if the term "below 6 GHz" or the like is used herein, the term may broadly refer to frequencies that may be lower than 6 GHz, may be within FR1, or may include mid-band frequencies. In addition, unless otherwise explicitly stated, it should be understood that if the term "millimeter wave" or the like is used herein, the term may broadly refer to frequencies that may include mid-band frequencies, may be within FR2, FR4, FR4-a or FR4-1, and / or FR5, or may be within the EHF band. It is contemplated that the frequencies included in these operating bands (e.g., FR1, FR2, FR3, FR4, FR4-a, FR4-1, and / or FR5) may be modified, and the techniques described herein are applicable to those modified frequency ranges.

[0042] As indicated above, Figure 1 are provided as examples. Other examples can be found in the Figure 1 Different than described.

[0043] Figure 2 2 is a diagram illustrating an example 200 of a network node 110 communicating with a UE 120 in a wireless network 100 according to the present disclosure. The network node 110 may be equipped with a set of antennas 234a to 234t, such as T antennas (T≥1). The UE 120 may be equipped with a set of antennas 252a to 252r, such as R antennas (R≥1). The network node 110 of example 200 includes one or more radio frequency components, such as an antenna 234 and a modem 254. In some examples, the network node 110 may include an interface, a communication component, or another component that facilitates communication with the UE 120 or another network node. Some network nodes 110 may not include a radio frequency component that facilitates direct communication with the UE 120, such as one or more CUs or one or more DUs.

[0044] At the network node 110, the transmit processor 220 may receive data intended for the UE 120 (or a set of UEs 120) from the data source 212. The transmit processor 220 may select one or more modulation and coding schemes (MCS) for the UE 120 based at least in part on one or more channel quality indicators (CQI) received from the UE 120. The network node 110 may process (e.g., encode and modulate) the data for the UE 120 based at least in part on the MCS selected for the UE 120, and provide data symbols for the UE 120. The transmit processor 220 may process system information (e.g., for semi-static resource partitioning information (SRPI)) and control information (e.g., CQI requests, grants, and / or upper layer signaling), and provide overhead symbols and control symbols. The transmit processor 220 may generate reference symbols for reference signals (e.g., cell-specific reference signals (CRS) or demodulation reference signals (DMRS)) and synchronization signals (e.g., primary synchronization signals (PSS) or secondary synchronization signals (SSS)). The transmit (TX) multiple-input multiple-output (MIMO) processor 230 may perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, overhead symbols, and / or reference symbols, where applicable, and may provide a set of output symbol streams (e.g., T output symbol streams) to a corresponding set of modems 232 (e.g., T modems) (shown as modems 232a to 232t). For example, each output symbol stream may be provided to a modulator component (shown as MOD) of the modem 232. Each modem 232 may process a corresponding output symbol stream (e.g., for OFDM) using a corresponding modulator component to obtain an output sample stream. Each modem 232 may further process (e.g., convert to analog, amplify, filter, and / or up-convert) the output sample stream using a corresponding modulator component to obtain a downlink signal. The modems 232a to 232t may transmit a set of downlink signals (e.g., T downlink signals) via a corresponding set of antennas 234 (e.g., T antennas) (shown as antennas 234a to 234t).

[0045] At the UE 120, a set of antennas 252 (shown as antennas 252a to 252r) may receive downlink signals from the network node 110 and / or other network nodes 110 and may provide a set of received signals (e.g., R received signals) to a set of modems 254 (e.g., R modems) (shown as modems 254a to 254r). For example, each received signal may be provided to a demodulator component (shown as DEMOD) of the modem 254. Each modem 254 may use a corresponding demodulator component to condition (e.g., filter, amplify, downconvert, and / or digitize) the received signal to obtain input samples. Each modem 254 may use a demodulator component to further process the input samples (e.g., for OFDM) to obtain received symbols. A MIMO detector 256 may obtain received symbols from the modem 254, may perform MIMO detection on the received symbols where applicable, and may provide detected symbols. The receive processor 258 may process (e.g., demodulate and decode) detected symbols, may provide decoded data for the UE 120 to the data sink 260, and may provide decoded control information and system information to the controller / processor 280. The term "controller / processor" may refer to one or more controllers, one or more processors, or a combination thereof. The channel processor may determine a reference signal received power (RSRP) parameter, a received signal strength indicator (RSSI) parameter, a reference signal received quality (RSRQ) parameter, and / or a CQI parameter, among other things. In some examples, one or more components of the UE 120 may be included in the housing 284.

[0046] The network controller 130 may include a communication unit 294, a controller / processor 290, and a memory 292. The network controller 130 may include, for example, one or more devices in a core network. The network controller 130 may communicate with the network node 110 via the communication unit 294.

[0047] One or more antennas (e.g., antennas 234a to 234t and / or antennas 252a to 252r) may include or be included within one or more antenna panels, one or more antenna groups, one or more sets of antenna elements, and / or one or more antenna arrays, etc. Antenna panels, antenna groups, sets of antenna elements, and / or antenna arrays may include one or more antenna elements (in a single housing or multiple housings), sets of coplanar antenna elements, sets of non-coplanar antenna elements, and / or coupled to one or more transmit and / or receive components (such as, Figure 2 One or more antenna elements of one or more components in.

[0048] On the uplink, at the UE 120, the transmit processor 264 may receive and process data from the data source 262 and control information from the controller / processor 280 (e.g., for reports including RSRP, RSSI, RSRQ, and / or CQI). The transmit processor 264 may generate reference symbols for one or more reference signals. The symbols from the transmit processor 264 may be pre-decoded by the TX MIMO processor 266, where applicable, further processed by the modem 254 (e.g., for DFT-s-OFDM or CP-OFDM), and transmitted to the network node 110. In some examples, the modem 254 of the UE 120 may include a modulator and a demodulator. In some examples, the UE 120 includes a transceiver. The transceiver may include any combination of an antenna 252, a modem 254, a MIMO detector 256, a receive processor 258, a transmit processor 264, and / or a TX MIMO processor 266. The transceiver may be used by a processor (eg, controller / processor 280) and memory 282 to perform aspects of any of the methods described herein (eg, with reference to Figures 5 to 9B ).

[0049] At the network node 110, uplink signals from the UE 120 and / or other UEs may be received by the antenna 234, processed by the modem 232 (e.g., a demodulator component of the modem 232 shown as DEMOD), detected by the MIMO detector 236 (where applicable), and further processed by the receive processor 238 to obtain decoded data and control information transmitted by the UE 120. The receive processor 238 may provide the decoded data to the data sink 239 and the decoded control information to the controller / processor 240. The network node 110 may include a communication unit 244 and may communicate with the network controller 130 via the communication unit 244. The network node 110 may include a scheduler 246 to schedule one or more UEs 120 for downlink and / or uplink communications. In some examples, the modem 232 of the network node 110 may include a modulator and a demodulator. In some examples, the network node 110 includes a transceiver. The transceiver may include any combination of antenna 234, modem 232, MIMO detector 236, receive processor 238, transmit processor 220, and / or TX MIMO processor 230. The transceiver may be used by a processor (e.g., controller / processor 240) and memory 242 to perform aspects of any of the methods described herein (e.g., reference 20 to FIG. 1 ). Figures 5 to 9B ).

[0050] The controller / processor 240 of the network node 110, the controller / processor 280 of the UE 120, and / or Figure 2 Any other component of the controller / processor 240 of the network node 110, the controller / processor 280 of the UE 120, and / or Figure 2 Any other component of the Fig. 9A and Fig. 9B Alternatively or additionally, and as with respect to Figure 3 and Figure 5 As further described, the network node 110 and / or the UE 120 may include an adaptive DPD device (eg, as described in reference to FIG. 9 ) that performs or directs the operation of the process 900. Figure 7 10 and 110). The memory 242 and the memory 282 may store data and program codes for the network node 110 and the UE 120, respectively. In some examples, the memory 242 and / or the memory 282 may include a non-transitory computer-readable medium that stores one or more instructions (e.g., code and / or program code) for wireless communication. For example, when the one or more instructions are executed by one or more processors of the network node 110 and / or the UE 120 (e.g., directly executed, or executed after compilation, conversion and / or interpretation), the one or more instructions may cause the one or more processors, the UE 120 and / or the network node 110 to perform or direct, for example, Fig. 9A and Fig. 9B The process 900 and / or operations of other processes as described herein. In some examples, executing instructions may include running instructions, converting instructions, compiling instructions, and / or interpreting instructions, etc.

[0051] In some aspects, the apparatus 702 includes means for receiving an indication of a selected DPD kernel from a plurality of DPD kernels and / or means for storing envelope values ​​associated with samples of the I / Q signal based at least in part on an envelope delay line component. In some aspects, the means for storing may include means for storing the envelope value as one of a plurality of envelope values ​​across a duration of time, wherein the plurality of envelope values ​​may be based at least in part on a plurality of samples associated with the I / Q signal. The apparatus 702 may include means for storing at least the following based at least in part on a computation storage component: a first computation value as one of a first plurality of computation values, the first plurality of computation values ​​being based at least in part on a plurality of samples, the first computation value being based at least in part on a first computation applied to the sample; a second computation value as one of a second plurality of computation values, the second plurality of computation values ​​being based at least in part on a plurality of samples, the second computation value being based at least in part on a second computation applied to the sample; and / or a plurality of samples. Alternatively or additionally, the device 702 includes means for selecting a subset of envelope values ​​from a plurality of envelope values ​​based at least in part on the selected DPD kernel. In some aspects, the device 702 includes means for generating an envelope calculation value based at least in part on the subset of envelope values ​​and at least one LUT component. The device 702 may include means for selecting at least one subset of calculation values ​​stored by the calculation storage component based at least in part on the selected DPD kernel, and / or means for generating output samples including DPD (e.g., output samples generated based at least in part on applying digital predistortion to input samples) based at least in part on combining the envelope calculation value with the at least one subset of calculation values. In some aspects, means for the apparatus to perform the operations described herein may include, for example, one or more of the following: an envelope delay line component 710, an envelope selection component 712, a LUT component 714, a LUT selection component 716, one or more computational delay line components 718, one or more computational selection components 720 and / or 722, one or more combiner components 724 and / or 726, and / or one or more value selection components 728, as described with respect to Figure 7 Further described.

[0052] Although Figure 2 The blocks in the 200 and 210 are illustrated as distinct components, but the functionality described above for these blocks may be implemented in a single hardware, software, or combined component or in various combinations of components. For example, the functionality described for the transmit processor 264, the receive processor 258, and / or the TX MIMO processor 266 may be performed by or under the control of the controller / processor 280.

[0053] As indicated above, Figure 2 are provided as examples. Other examples can be found in the Figure 2 Different than described.

[0054] Figure 3 300 is a diagram illustrating an example of a wireless transceiver 302 that can be used by a device to communicate in a wireless network according to the present disclosure. In some aspects, the wireless transceiver 302 may include Figure 2 For example, one or more components of the wireless transceiver 302 may be coupled to and / or included in the modem 232 (e.g., one or more of the modems 232a to 232t) and / or the modem 254 (e.g., one or more of the modems 254a to 254r).

[0055] The wireless transceiver 302 may include a transmitter 304 (shown in dashed lines) and / or a receiver 306 (shown in dashed lines). As shown in example 300, the transmitter 304 may be coupled to at least a first antenna 308, and the receiver 306 may be coupled to at least a second antenna 310. However, in other examples, the transmitter 304 and the receiver 306 may be coupled to the same antenna via a switch and / or a duplexer. In some aspects, the transmitter 304 may generate and transmit an outgoing RF signal 312, and the receiver 306 may receive and process an incoming RF signal 314.

[0056] As shown in example 300, transmitter 304 may include a digital-to-analog converter 316 (DAC 316), a first mixer 318-1, a first amplifier 320 (e.g., a power amplifier), and a first filter 322-1 (e.g., a surface acoustic wave (SAW) filter). The first mixer 318-1 may be coupled to a local oscillator (LO) 324. In some aspects, DAC 316 may be coupled to an application processor or another processor associated with wireless transceiver 302 (e.g., modem 232 or modem 254). Other examples of transmitters may include multiple DACs, multiple mixers, multiple amplifiers, and / or multiple filters not shown in example 300.

[0057] Receiver 306 may include a second filter 322-2 (e.g., a SAW filter), a second amplifier 326 (e.g., a low noise amplifier), a second mixer 318-2, and an analog-to-digital converter 328 (ADC 328). Second mixer 318-2 may be coupled to LO 324. Alternatively or additionally, ADC 328 may be coupled to an application processor or another processor associated with wireless transceiver 302 (e.g., modem 232 or modem 254). Other examples of receivers may include multiple filters, multiple amplifiers, multiple mixers, and / or multiple ADCs not shown in example 300.

[0058] In some aspects, the wireless transceiver 302 may be implemented using multiple circuits, such as multiple integrated circuits (ICs). For illustration, the wireless transceiver 302 may include a transceiver circuit 330 and a radio frequency front end (RFFE) circuit 332. Thus, components used to form the transmitter 304 and the receiver 306 may be distributed across multiple circuits. As an example, the transceiver circuit 330 and the RFFE circuit 332 may each include at least some of the components forming the transmitter 304 and / or at least some of the components forming the receiver 306. For illustration, and with respect to the transmitter 304, the transceiver circuit 330 may include a DAC 316 and a first mixer 318-1 of the transmitter 304, and the RFFE circuit 332 may include a first amplifier 320 and a first filter 322-2 of the transmitter 304. Alternatively or additionally, and with respect to receiver 306, transceiver circuitry 330 may include second mixer 318-2 and ADC 328 of receiver 306, and RFFE circuitry 332 may include second filter 322-2 and second amplifier 326 of receiver 306. In some aspects, DAC 316 and / or ADC 328 may be implemented on circuitry separate from transceiver circuitry 330, such as modem 232 or modem 254.

[0059] In some aspects, the transmitter 304 may generate the outgoing RF signal 312 based at least in part on one or more digital samples 334. A "digital sample" (which may alternatively be referred to as a sample) may represent a representation of an analog signal, such as a representation of the amplitude of an analog signal at a point in time. Each sample in a set of samples spanning a time duration may represent an analog signal at a different point in time within the time duration. For illustration, a first sample may represent a signal at a first point in time, a second sample may represent a signal at a second, different point in time, up to an nth sample which may represent a signal at an nth point in time, where n is an integer and the points in time across the time duration may be evenly spaced in time. In some aspects, a sample may capture an in-phase / quadrature (I / Q) signal. For example, a sample may include an in-phase component (I component) value associated with the I / Q signal at the time point and a quadrature component (Q component) value at the time point. A sample associated with an I / Q signal (e.g., which includes an I component and a Q component) may alternatively or additionally be referred to as a complex sample.

[0060] In some aspects, the DAC 316 can receive one or more samples associated with a pre-upconverted signal (e.g., a baseband signal or an intermediate frequency (IF) signal) as digital samples 334. In some aspects, the DAC 316 can receive one or more samples including digital predistortion (DPD), such as with respect to Figure 5 For illustration, the DAC 316 may receive one or more samples from an adaptive DPD device, such as Figure 7Using digital samples 334, DAC 316 may generate analog pre-upconverted signal 336 as an output.

[0061] The first mixer 318-1 may receive the analog pre-upconverted signal 336 as an input and generate a pre-filtered upconverted signal 338 as an output using an LO signal 340-1 provided by the LO 324. The pre-filtered upconverted signal 338 may be an RF signal and / or may include some noise and / or unwanted frequencies, such as harmonic frequencies. The first amplifier 320 may receive the pre-filtered upconverted signal 338 and generate an amplified pre-filtered signal 342.

[0062] The first filter 322-2 may receive the amplified pre-filtered signal 342 as an input and filter the amplified pre-filtered transmit signal 342 to generate a filtered transmit signal 344. As part of the filtering process, the first filter 322-2 may attenuate noise or unwanted frequencies included in the pre-filtered up-converted signal 338 and / or the amplified pre-filtered signal 342. The transmitter 304 may provide the filtered transmit signal 344 to the first antenna 308 for transmission as the outgoing RF signal 312.

[0063] In some aspects, the receiver 306 can receive the incoming RF signal 314 using the second antenna 310. As shown in the example 300, the second antenna 310 can generate a pre-filtered receive signal 346. The second antenna 310 can be coupled to the second filter 322-2 so that the second filter 322-2 receives the pre-filtered receive signal 346 and filters it to remove noise and / or unwanted frequencies. Thus, the second filter 322-2 can generate a filtered receive signal 348.

[0064] The second amplifier 326 may receive and amplify the filtered received signal 348 to generate an amplified filtered received signal 350. Based at least in part on being coupled to the second amplifier 326, the second mixer 318-2 may receive the amplified filtered received signal 350 and downconvert the amplified filtered received signal 350 using the LO signal 324-2 (e.g., from the LO 340) to generate a downconverted received signal 352, which may be a baseband signal or an IF signal. The ADC 328 may receive the downconverted received signal 352 and generate a digital signal by generating one or more digital samples 354 as an output. The one or more digital samples 354 may be processed by a processor associated with the wireless transceiver 302 and / or another processor (such as a processor associated with the modem 232 or the modem 254).

[0065] As indicated above, Figure 3 are provided as examples. Other examples can be found in the Figure 3As an example, the wireless transceiver 302 may include one or more feedback mechanisms, such as providing feedback associated with the output from the first amplifier 320 to the DPD device (e.g., as described with respect to Figure 7 A feedback path (eg, a feedback receiver) of an adaptive DPD device) further described.

[0066] The deployment of a communication system (such as a 5G NR system) may be arranged with various components or components in a variety of ways. In a 5GNR system or network, a network node, a network entity, a mobility element of a network, a RAN node, a core network node, a network element, a base station or network equipment may be implemented in an aggregated or decomposed architecture. For example, a base station (such as a node B (NB), an evolved NB (eNB), an NR BS, a 5G NB, an access point (AP), a TRP or a cell, etc.) or one or more units (or one or more components) performing base station functionality may be implemented as an aggregated base station (also referred to as an independent base station or a monolithic base station) or a decomposed base station. A "network entity" or a "network node" may refer to a decomposed base station or one or more units of a decomposed base station (such as one or more CUs, one or more DUs, one or more RUs or a combination thereof).

[0067] An aggregated base station (e.g., an aggregated network node) can be configured to utilize a radio protocol stack that is physically or logically integrated within a single RAN node (e.g., within a single device or unit). A decomposed base station (e.g., a decomposed network node) can be configured to utilize a protocol stack that is physically or logically distributed between two or more units (such as one or more CUs, one or more DUs, or one or more RUs). In some examples, the CU can be implemented within a network node, and one or more DUs can be co-located with the CU, or alternatively, can be geographically or virtually distributed across one or more other network nodes. The DU can be implemented to communicate with one or more RUs. Each of the CU, DU, and RU can also be implemented as a virtual unit, such as a virtual central unit (VCU), a virtual distributed unit (VDU), or a virtual radio unit (VRU), and the like.

[0068] Base station type operations or network designs may take into account the aggregated nature of base station functionality. For example, a decomposed base station may be utilized in an IAB network, an open radio access network (O-RAN (such as a network configuration initiated by the O-RAN Alliance)), or a virtualized radio access network (vRAN, also known as a cloud radio access network (C-RAN)) to facilitate the scaling of a communication system by separating base station functionality into one or more units that can be deployed separately. A decomposed base station may include functionality implemented across two or more units at various physical locations, as well as functionality implemented virtually for at least one unit, which may enable flexibility in network design. Individual units of a decomposed base station may be configured for wired or wireless communication with at least one other unit of the decomposed base station.

[0069] Figure 4 4 is a diagram illustrating an example disaggregated base station architecture 400 according to the present disclosure. The disaggregated base station architecture 400 may include a CU 410 that may communicate directly with a core network 420 via a backhaul link, or indirectly with the core network 420 through one or more disaggregated control units, such as a near-RT RIC 425 via an E2 link, or a non-RT RIC 415 associated with a service management and orchestration (SMO) framework 405, or both. The CU 410 may communicate with one or more DUs 430 via respective midhaul links, such as via an F1 interface. Each of the DUs 430 may communicate with one or more RUs 440 via respective fronthaul links. Each of the RUs 440 may communicate with one or more UEs 120 via respective radio frequency (RF) access links. In some implementations, a UE 120 may be served simultaneously by multiple RUs 440.

[0070] Each of the units (including CU 410, DU 430, RU 440) and the near-RT RIC 425, non-RT RIC 415, and SMO framework 405 may include or be coupled to one or more interfaces configured to receive or transmit signals, data, or information (collectively referred to as signals) via a wired or wireless transmission medium. Each of the units or an associated processor or controller that provides instructions to one or more communication interfaces of the corresponding unit may be configured to communicate with one or more of the other units via a transmission medium. In some examples, each of the units may include a wired interface and a wireless interface, the wired interface being configured to receive signals or transmit signals to one or more of the other units via a wired transmission medium, and the wireless interface being configured to receive signals or transmit signals to one or more of the other units via a wired transmission medium, or both.

[0071] In some aspects, CU 410 may host one or more higher layer control functions. Such control functions may include radio resource control (RRC) functions, packet data convergence protocol (PDCP) functions, or service data adaptation protocol (SDAP) functions, etc. Each control function may be implemented using an interface that is configured to communicate signals with other control functions hosted by CU 410. CU 410 may be configured to handle user plane functionality (e.g., central unit-user plane (CU-UP) functionality), control plane functionality (e.g., central unit-control plane (CU-CP) functionality), or a combination thereof. In some specific implementations, CU 410 may be logically split into one or more CU-UP units and one or more CU-CP units. When implemented in an O-RAN configuration, the CU-UP unit may communicate bidirectionally with the CU-CP unit via an interface such as an E1 interface. As needed, CU 410 may be implemented to communicate with DU 430 for network control and signaling.

[0072] Each DU 430 may correspond to a logical unit including one or more base station functions for controlling the operation of one or more RUs 440. In some aspects, the DU 430 may host one or more of a radio link control (RLC) layer, a MAC layer, and one or more high physical (PHY) layers, at least in part, according to a functional partition such as that defined by 3GPP. In some aspects, one or more high PHY layers may be implemented by one or more modules for forward error correction (FEC) encoding and decoding, scrambling, modulation and demodulation, etc. In some aspects, the DU 430 may also host one or more low PHY layers, such as one or more modules for fast Fourier transform (FFT), inverse FFT (iFFT), digital beamforming or physical random access channel (PRACH) extraction and filtering, etc. Each layer (which may also be referred to as a module) may be implemented using an interface that is configured to communicate signals with other layers (and modules) hosted by the DU 430 or with control functions hosted by the CU 410.

[0073] Each RU 440 may implement lower layer functionality. In some deployments, the RU 440 controlled by the DU 430 may correspond to a logical node that hosts RF processing functions based on functional splits (e.g., functional splits defined by 3GPP) such as lower layer functional splits, or low PHY layer functions such as performing FFT, performing iFFT, digital beamforming, or PRACH extraction and filtering, etc. In this architecture, each RU 440 may be operated to handle over-the-air (OTA) communications with one or more UEs 120. In some specific implementations, real-time and non-real-time aspects of control plane and user plane communications with the RU 440 may be controlled by the corresponding DU 430. In some scenarios, this configuration may enable each DU 430 and CU 410 to be implemented in a cloud-based RAN architecture such as a vRAN architecture.

[0074] The SMO framework 405 may be configured to support RAN deployment and provisioning of non-virtualized network elements and virtualized network elements. For non-virtualized network elements, the SMO framework 405 may be configured to support the deployment of dedicated physical resources for RAN coverage requirements, which may be managed via an operation and maintenance interface (such as an O1 interface). For virtualized network elements, the SMO framework 405 may be configured to interact with a cloud computing platform (such as an open cloud (O-Cloud) platform 490) to perform network element lifecycle management (such as instantiating virtualized network elements) via a cloud computing platform interface (such as an O2 interface). Such virtualized network elements may include, but are not limited to, CU 410, DU 430, RU 440, non-RT RIC 415, and near-RT RIC 425. In some specific implementations, the SMO framework 405 may communicate with hardware aspects of the 4G RAN (such as an open eNB (O-eNB) 411) via the O1 interface. Additionally, in some implementations, the SMO framework 405 can communicate directly with each of the one or more RUs 440 via a corresponding O1 interface. The SMO framework 405 can also include a non-RT RIC 415 configured to support the functionality of the SMO framework 405.

[0075] The non-RT RIC 415 may be configured to include logic functions that enable non-real-time control and optimization of RAN elements and resources, artificial intelligence / machine learning (AI / ML) workflows including model training and updating, or policy-based guidance of applications / features in the near-RT RIC 425. The non-RT RIC 415 may be coupled to or in communication with the near-RT RIC 425 (such as via an A1 interface). The near-RT RIC 425 may be configured to include logic functions that enable near-real-time control and optimization of RAN elements and resources via data collection and actions through an interface (such as via an E2 interface) that connects one or more CUs 410, one or more DUs 430, or both, and the O-eNB with the near-RT RIC 425.

[0076] In some implementations, in order to generate an AI / ML model to be deployed in the near-RT RIC 425, the non-RT RIC 415 may receive parameters or external enrichment information from an external server. Such information may be utilized by the near-RT RIC 425 and may be received from a non-network data source or from a network function at the SMO framework 405 or the non-RT RIC 415. In some examples, the non-RT RIC 415 or the near-RT RIC 425 may be configured to tune RAN behavior or performance. For example, the non-RT RIC 415 may monitor long-term trends and patterns of performance and employ AI / ML models to perform corrective actions through the SMO framework 405 (such as via reconfiguration of the O1 interface) or via the creation of RAN management policies (such as A1 interface policies).

[0077] As indicated above, Figure 4 are provided as examples. Other examples can be found in the Figure 4 Different than described.

[0078] Figure 5 is a diagram illustrating an example 500 including a transmitter 505 that may include digital pre-distortion (DPD) capability and a receiver 510 that may include digital post-distortion (DPoD) capability according to the present disclosure. Figure 5 As shown, the transmitter 505 may communicate with the receiver 510 using wireless signals 515. In some aspects, the network node 110 (e.g., any network node described with respect to the decomposed base station architecture 400) may include the transmitter 505, and the UE 120 may include the receiver 510. Alternatively or additionally, the UE 120 may include the transmitter 505, and the network node 110 may include the receiver 510. For purposes of discussion, the block diagram associated with the transmitter 505 and the receiver 510 shown in the example 500 is simplified. Other examples may include alternative or additional features that are omitted for clarity. For example, the transmitter 505 may include information about Figure 3 Alternatively or additionally, the transmitter 304 may include one or more components of the transmitter 505. As another example, the receiver 510 may include one or more components of the transmitter 304 described above. Figure 3 One or more components of the receiver 306 (or vice versa) as described.

[0079] As shown in example 500, transmitter 505 can communicate with receiver 510 based at least in part on sending signal 515 to receiver 510. Signal 515 can be pre-processed by transmitter 505 to reduce a power back-off value associated with sending signal 515 to receiver 510, among other benefits.

[0080] To illustrate, in some communication systems, the transmitter 505 may transmit a signal with increased nonlinearity based at least in part on the power increase. For example, the transmitter 505 may include a power amplifier (PA) 520 (which may be a high power amplifier in some aspects) having a limited dynamic range that may distort the transmitted signal due to a relatively high peak-to-average power ratio (PAPR). In some aspects, the PA 520 may be considered to be the first amplifier 320, as described with respect to FIG. Figure 3 Described. Nonlinear distortion can be in-band distortion, which affects link performance related to mutual information and / or error vector magnitude (EVM) quantities, or out-of-band distortion, which causes adjacent channel interference (ACI) and / or leads to a high adjacent channel leakage ratio (ACLR) (e.g., the transmitted signal interferes with other signals on adjacent frequency bands, where the ACI and / or ACLR indicate the degree to which the adjacent channel is contaminated by the main transmission). To avoid nonlinear distortion and the accompanying interference, the transmitter 505 can apply a power back-off value to reduce the transmit power, thereby reducing nonlinearity.

[0081] In some aspects, applying a power backoff value may result in reduced power efficiency (e.g., using less available transmit power to transmit in a channel, thereby reducing range, signal-to-interference-and-noise ratio, etc.). For example, based at least in part on applying the power backoff value, the transmitter 505 may transmit a signal 515 with less power in the channel and may dissipate more power in the form of heat, which may result in reduced power efficiency. Therefore, the transmitter 505 may use one or more pre-transmit signal processing techniques to reduce the power backoff value. For example, the transmitter may utilize crest factor reduction (CFR) processing and / or digital predistortion (DPD) processing. CFR processing may reduce the dynamic range of the signal, while DPD processing may reduce nonlinear distortion to less than a threshold level by reducing the power backoff level, thereby increasing power efficiency relative to avoiding nonlinear distortion using only power backoff. As Figure 5As shown, the transmitter 505 may include a CFR component 525 for performing CFR processing on the signal 515 (eg, to reduce the PAPR in the signal 515 as much as possible and thus reduce the power backoff value). Figure 5 The transmitter 505 is shown to include a CFR component 525, but other transmitter implementations may exclude the CFR component 525, which is further indicated by the use of dashed lines. Alternatively or additionally, the transmitter 505 may include a DPD component 530 for performing DPD processing on the signal 515 (e.g., to linearize the response of the power amplifier). As an example, the DPD component 530 may perform DPD processing on the digital signal such that Figure 3 The digital sample 334 has been modified to include DPD. For illustration, as shown in FIG. Figure 3 The depicted transmitter 304 may include a DPD component 530 prior to the DAC 316 .

[0082] However, CFR processing consumes additional resources (e.g., bandwidth resources, power resources, computing resources, etc.), and in some cases, CFR processing may introduce in-band distortion (e.g., EVM distortion) and / or out-of-band distortion (e.g., ACI distortion). In addition, although DPD processing can correct nonlinear effects within the dynamic range, nonlinearity may still cause clipping effects (e.g., caused by limited dynamic range). Therefore, the effectiveness and / or power efficiency benefits of CFR processing and DPD processing are limited.

[0083] To address the limitations of CFR and / or DPD processing, the receiver 510 may apply DPoD processing to the signal 515. The DPoD processing may be similar to the DPD processing, but is performed in the receiver 510 instead of in the transmitter 505, and may be directed to processing only for EVM instead of processing for both EVM and ACI. More specifically, the DPoD processing may be performed by a DPoD component 535 at the receiver 510, which may include hardware and / or software configured to implement an algorithm configured to remove nonlinear noise (e.g., PA clipping) generated by a known model. Thus, the DPoD processing may reduce the power back-off value and improve power efficiency.

[0084] Different RATs may utilize different frequency bands and / or have different performance requirements. As an example, a first communication standard associated with LTE may specify a first carrier frequency, a first bandwidth, and / or a first power level for LTE communications that is different from a second carrier frequency, a second bandwidth, and / or a second power level specified by a second communication standard associated with 5G. Thus, the device may use a first carrier frequency that is lower than a second higher carrier frequency associated with sending 5G communications to send LTE communications. Alternatively or additionally, the device may send LTE communications based at least in part on a first power level, a first frequency band, and / or a first bandwidth that is different from a second power level, a second frequency band, and / or a second bandwidth associated with sending 5G communications. In some aspects, the device may send LTE communications based at least in part on compliance with a first error vector magnitude (EVM) requirement and / or a first adjacent channel leakage ratio (ACLR) requirement (e.g., specified by an LTE communication standard), the first adjacent channel leakage ratio (ACLR) requirement being different from a second EVM requirement and / or a second ACLR requirement associated with sending 5G communications.

[0085] Differences in carrier frequency, frequency band, bandwidth and / or power level may affect the way the PA distorts the signal. For example, a first signal having a first bandwidth amplified by a PA may produce different distortions relative to a second signal amplified by the same PA, wherein the second signal has a second different bandwidth (e.g., wider or narrower than the first bandwidth). In some wireless communication devices, the DPD processing performed by the DPD component may implement a single DPD algorithm and / or a single DPD kernel. That is, the DPD component may not switch between DPD algorithms or kernels. A single DPD algorithm and / or DPD kernel may cause inaccurate DPD applied to some signals that change signal parameters. For illustration, a single DPD algorithm and / or DPD kernel may model the PA distortion associated with the PA and / or the inverse of the PA distortion (e.g., inverse PA distortion for correction) for a first signal at a first carrier frequency with a first bandwidth within an accuracy threshold. However, a single DPD algorithm and / or DPD kernel may fail to model the PA distortion (and / or inverse PA distortion) of a second signal at a second different carrier frequency with a second different bandwidth within an accuracy threshold. Alternatively or additionally, different PAs may introduce different nonlinear distortions such that a single DPD algorithm and / or DPD core may fail to mitigate PA distortion and / or inverse PA distortion of some PAs within an accuracy threshold. A "DPD core" may refer to a core processing algorithm that performs digital predistortion processing using a single DPD algorithm. For example, an architecture associated with a DPD core and / or calculations performed by the DPD core may be based at least in part on a single DPD algorithm.

[0086] Failure to mitigate distortion introduced by the PA within an accuracy threshold may cause the device to fail to meet the performance requirements of the transmission. Alternatively or additionally, failure to meet the performance requirements may introduce errors in the transmitted signal and / or the observed signal at the receiver. For example, failure to mitigate distortion within an accuracy threshold may result in (unmitigated) PA noise (which results in increased recovery errors at the receiver) and / or clipped signals (which results in recovery errors at the receiver). In some aspects, failure to mitigate distortion within an accuracy threshold may result in interference with other signals in the wireless network and increase recovery errors at other devices. Increased recovery errors may reduce data throughput in the wireless network, increase resource consumption, and / or increase data transmission latency.

[0087] Some techniques and devices described herein provide an adaptive digital predistortion kernel. In some aspects, a device (e.g., an adaptive DPD device) may include hardware that implements multiple DPD kernels based at least in part on a generalized DPD kernel, as further described below. A "generalized DPD kernel" may refer to a configurable DPD kernel that can implement different DPD kernels using a single architecture by modifying one or more characteristics associated with the generalized DPD kernel, such as a timing advance characteristic of an envelope value used by the generalized DPD kernel, a timing delay characteristic of an envelope value used by the generalized DPD kernel, and / or a series summation calculation used by the generalized DPD kernel.

[0088] The adaptive DPD device may enable a transmitting device to dynamically change a DPD kernel used to apply digital predistortion to an input signal. As the frequency bandwidth, carrier frequency, and / or power level of the input signal changes, the transmitting device may select a DPD kernel (e.g., without changing hardware and using an adaptive DPD device) that models the behavior of a nonlinearity of distortion, an inverse nonlinearity of distortion, and / or a nonlinearity of predistortion associated with mitigating distortion within an accuracy threshold. Alternatively or additionally, the transmitting device may select a DPD kernel based at least in part on the type of PA being used to process the input signal (e.g., a Doherty power amplifier, a laterally diffused metal oxide semiconductor (LDMOS) power amplifier, and / or a gallium nitride (GaN) power amplifier). For illustration, the transmitting device may select a DPD kernel based at least in part on nonlinear distortion associated with the type of PA being used to process the input signal (and / or predistortion applied by the DPD kernel to mitigate PA distortion).

[0089] The ability to change the DPD kernel improves the way a transmitting device mitigates PA distortion in a signal relative to using other DPD kernels. For example, a transmitting device may switch from using a first DPD kernel that fails to mitigate PA distortion within an accuracy threshold to using a second DPD kernel that mitigates PA distortion within an accuracy threshold (e.g., by selecting a DPD kernel that better models the behavior of PA distortion, inverse PA distortion, and / or pre-distortion that mitigates PA distortion). Mitigating PA distortion within an accuracy threshold enables a device to meet performance requirements, reduce recovery errors at a receiver, improve data throughput, and / or improve data transmission latency. An adaptive DPD device enables a device to use the same hardware to mitigate PA distortion associated with multiple transmit configurations and / or multiple PA types. Using the same hardware (e.g., a single adaptable DPD device) may simplify the hardware design of a transmitting device, reduce the cost of building a transmitting device, and / or reduce testing time and cost.

[0090] As indicated above, Figure 5 Other examples may differ from the examples described above.

[0091] In some aspects, the Volterra-based DPD kernel may be based at least in part on a generalized memory polynomial (GMP) series and / or a dynamic deviation reduction (DDR) series that models nonlinear distortion associated with a PA and / or a behavior of a nonlinear predistortion that mitigates the nonlinear distortion of the PA. The GMP series and / or the DDR series may be collectively referred to as a generalized DDR (GDDR) series. Based at least in part on one or more mathematical substitutions associated with assumptions about the nonlinear system modeled by the series, a first generalized DDR (GDDR1) series may be represented as at least one of the following:

[0092] GDDR1 Type 1:

[0093] or

[0094] GDDR1 Type 2: where x n represents the nth input sample (e.g., of a signal without predistortion), y n represents the nth output sample (e.g., of the signal with predistortion applied), M1 and M2 each represent a respective memory depth or length (e.g., time duration) of the respective series and / or model, L1 and L2 each represent a respective lag (e.g., time lag) cross-term index of the respective series and / or model, K1 and K2 each represent a respective nonlinear order associated with the respective series and / or model, and c mlk Represents the coefficient value, where k, l, m, and n are integers.

[0095] In a similar manner, and based at least in part on one or more mathematical substitutions associated with assumptions about the nonlinear system modeled by the series, a second generalized DDR (GDDR2) series may be represented as at least one of the following:

[0096] GDDR2 Type 1:

[0097] or

[0098] GDDR2 Type 2:

[0099] or

[0100] GDDR2 Type 3:

[0101] where x n represents the nth input sample, y n represents the nth output sample, M3, M4, and M5 each represent the corresponding memory depth or length of the corresponding series and / or model, L3, L4, and L5 each represent the corresponding lag (e.g., time lag) cross-term index, K3, K4, and K5 each represent the nonlinear order of the corresponding series and / or model, and c mlk Represents the coefficient value, where k, l, m, and n are integers.

[0102] Based at least in part on one or more mathematical substitutions associated with assumptions about the nonlinear system modeled by the series, the third generalized DDR (GDDR3) series may be represented as at least one of the following:

[0103] GDDR3 Type 1:

[0104] or

[0105] GDDR3 Type 2:

[0106] or

[0107] GDDR3 Type 3:

[0108] where x n represents the nth input sample, y n represents the nth output, M6, M7, and M8 each represent the corresponding memory depth or length of the corresponding series and / or model, L6, L7, and L8 each represent the corresponding lag (e.g., time lag) cross-term index, K6, K7, and K8 each represent the nonlinear order of the corresponding series and / or model, and c mlk Represents the coefficient value, where k, l, m, and n are integers.

[0109] The series and / or models shown by equations (1) to (8) can be simplified and collectively expressed as:

[0110] y n =q n-j ∑ m∈M p n-m ∑ l∈L ∑ k∈K c jmlk |x n-l | k (9)

[0111] where x n represents the nth input sample, y n represents the nth output, k represents the power of the envelope, j, l, and m represent the lead or lag relative to n (e.g., timing advance or timing delay), and c is a coefficient. In some aspects, j may be equal to "0". Each of equations (1) to (8) may be derived from equation (9) based at least in part on using calculations and / or values ​​associated with samples from a calculation set (e.g., 1, sample value, complex conjugate calculation, absolute value calculation, square calculation, complex conjugate square calculation, absolute value square calculation, complex conjugate cube calculation, absolute value square multiplied by sample calculation, and / or absolute value square multiplied by complex conjugate) as q and p, respectively, the calculation set being defined as follows:

[0112] {1,x m ,x m * ,|x m |,x m 2 ,x m *2 ,|x m | 2 ,x m 3 ,x m *3 ,|x m | 2 x m ,|x m | 2 x* m} (10)

[0113] As about Figure 7 Further describing, the LUT may store envelope calculation values ​​associated with equation (9), such as envelope power sum values. For example, the LUT may store envelope power sum values ​​and / or calculations ∑ approximating equation (9) k∈K c jmlk |x n-l | k An approximation of the summed envelope power.

[0114] As shown in Equation (11) below, the output samples (e.g., y n ) can be expressed as the sum of different kernels:

[0115]

[0116] where y n represents the output sample at index n, Q represents a set of different types of computations that can be used as q (e.g., and associated delays or advances), M represents a set of different types of computations that can be used as p (e.g., and associated delays or advances), c represents a coefficient, and x n represents the input sample at index n, L represents a set of calculations (e.g., associated delays or advances) that are utilized based at least in part on the achieved q, and K represents a set of calculations that may be utilized based at least in part on the achieved q. For illustration, the different calculations and / or values ​​used may be based at least in part on which of equations (1)-(8) maps to equation (11). Based at least in part on using a LUT, equation (11) may be expressed as:

[0117]

[0118] Figure 6 is a diagram illustrating an example 600 of a table 602 that specifies calculations and / or values ​​(e.g., associated with sample x) that may be used in a generalized DPD kernel according to the present disclosure. As shown in example 600, table 602 maps one or more calculations to q j and p m To map each of equations (1)-(8) to equation (11). Table 602 includes a first column 604 indicating any of equations (1)-(8), a column indicating the relationship between q j The second column 606 of the first calculation associated with p m The third column 608 of the associated second calculation. The calculations specified by the second column 606 and the third column 608 may include constant values ​​and / or sample values ​​(eg, calculations that may be implemented without performing the calculations).

[0119] As an example, row 610 of table 602 may be associated with equation (1) as described above. In some aspects, equation (1) may be solved by using q as indicated in second column 606. j A constant value (e.g., 1) and p as indicated in the third column 608 m The sample is multiplied by 1 (for example, x m ) is represented by equation (12). As another example, row 612 of table 602 may be associated with equation (8). Equation (8) may be represented by q as indicated in second column 606. jThe square of x0 (for example, x0 2 ) and using p as indicated in the third column 608 m The absolute value squared multiplied by the complex conjugate is calculated (for example, |x m | 2 x m *) is expressed by equation (11).

[0120] In some aspects, alternative or additional Volterra-based DPD kernel stages other than the GMP and GDDR classes described above may be mapped to equation (11), as generally indicated by reference numeral 614. As non-limiting examples, equation (11) may be mapped to a memory polynomial (MP) stage and / or a DDR stage. However, other DPD kernels not described herein may also be based at least in part on using a p m The first calculation (or constant) of q j A second calculation (or constant) of and / or an approximation stored in the LUT component based at least in part on the number of stages associated with the DPD kernel is represented by equation (11).

[0121] As indicated above, Figure 6 Other examples may differ from the examples described above.

[0122] In some aspects, the DPD kernel may be based at least in part on a decomposition vector rotation (DVR) series that models the behavior of nonlinear distortion associated with a PA (and / or a nonlinear predistortion that mitigates the nonlinear distortion of the PA) based at least in part on a piecewise linear function that is based at least in part on an envelope of a signal (e.g., a piecewise linear envelope function). For illustration, a first-order basic DVR series may be represented as:

[0123]

[0124] where x n represents the nth input sample, y n represents the nth output sample, M represents the memory depth or length of the corresponding series, K represents the resolution of the piecewise linear function, β k represents the boundary of the piecewise linear envelope function, and c mk represents the coefficient value, where k and m are integers. By replacing:

[0125]

[0126] The first-order basic DVR level can be expressed as:

[0127]

[0128] As follows about Figure 7 To further describe, the LUT may store envelope calculation values ​​associated with equation (15). For example, the LUT may store envelope calculation values ​​and / or calculations approximating equation (15). An approximation of the envelope calculation value of .

[0129] As another example, a first-order base DVR level may be represented as:

[0130]

[0131] As about Figure 7 Further describing, the LUT may store envelope calculation values ​​associated with equation (16). For example, the LUT may store envelope calculation values ​​and / or calculations approximating equation (16) An approximation of the envelope calculation value of .

[0132] As another example, the second-order base DVR level may be expressed as at least one of the following:

[0133]

[0134] or

[0135]

[0136] As about Figure 7 To further describe, the LUT may store envelope calculation values ​​associated with equation (17) and / or equation (18). For example, the LUT may store envelope power summation values ​​and / or calculations approximating equation (17) and equation (18) An approximation of the summed envelope power.

[0137] In some aspects, the DVR level may be represented as:

[0138] y n =∑ m∈M x m-m ∑ l∈L ∑ k∈K c mlk ||x n-l |-β k | (19)

[0139] As about Figure 7 Further describing, the LUT may store envelope calculation values ​​associated with equation (19). For example, the LUT may store envelope calculation values ​​and / or calculations ∑ approximating equation (19) k∈K c mlk ||x n-l |-β k | is an approximation of the envelope calculation value.

[0140] The DVR levels described with respect to equations (13), (15), (16), (17), (18) and (19) and other DVR levels not described above may be expressed as:

[0141]

[0142] or

[0143]

[0144] The LUT can store the calculation ∑ associated with equation (20) k∈K c jmlk ||x n-l |-β k | or the equivalent equation (21) The associated envelope calculation value and / or the approximation of the envelope calculation value may be used to represent the calculation performed by a particular DVR stage, as described above (e.g., a first LUT may store a first set of envelope calculation values ​​based at least in part on equation (13), a second LUT may store a second set of envelope calculation values ​​based at least in part on equation (17), and / or a third LUT may store a third set of envelope calculation values ​​based at least in part on equation (19)). Thus, the q value of the DVR stage may be based at least in part on the calculation x 2 And the p-value of the DVR level can be based at least in part on the calculation So equation (20) can be further expressed as:

[0145]

[0146] The ability to model a nonlinear system (e.g., distortion and / or predistortion) using a series (such as any combination of a Volterra series, a DVR series, a GMP series, an MP series, and / or a DDR series) can enable a transmitting device to mitigate distortion and mitigate recovery errors at a receiving device by applying predistortion to an input signal. For illustration and as further described above, the Volterra series, the DVR series, the GMP series, the MP series, and / or the DDR series can be calculated based at least in part on equation (21) using q and p calculations associated with the corresponding series as described above and a LUT storing envelope calculation values ​​associated with the corresponding series. Because the first model can more accurately represent the nonlinear system relative to the second model, the ability to change the model (such as through an adaptive DPD device) improves the manner in which the transmitting device mitigates PA distortion in the signal, resulting in improved signal quality. The improved signal quality reduces recovery errors at the receiver, improves data throughput in the wireless network, and / or reduces data transmission latency in the wireless network relative to other signal qualities.

[0147] Figure 7 is a diagram illustrating an example 700 of an adaptive DPD device 702 according to the present disclosure. In some aspects, the adaptive DPD device may be implemented using one or more integrated circuits (ICs) and / or one or more systems on chips (SOCs), as further described below. The adaptive DPD device 702 may be included in a network node (e.g., a Figure 1 The network node 110 described above and / or any network node described with respect to the decomposed base station architecture 400) and / or a UE (e.g., with respect to Figure 1 The wireless transceiver may be in (and / or coupled to) a wireless transceiver of a UE 120 described herein.

[0148] As shown in example 700, the adaptive DPD device 702 includes a first input mechanism 704 configured to receive an indication of the selected DPD core. As an example, the first input mechanism 704 may include one or more input lines connected to an input (such as a pin) of an IC and / or SoC. In some aspects, the first input mechanism 704 may include a receiving logic gate circuit (e.g., digital logic) and / or a clock to receive one or more bits serially and / or in parallel via one or more input lines. Alternatively or additionally, the adaptive DPD device may include a mapping logic gate circuit that maps one or more bits to an index value and / or identifier (ID) associated with one of the multiple DPD cores supported and / or implemented by the adaptive DPD device 702. The first input mechanism 704 is coupled to one or more communication circuits included in the adaptive DPD device 702, wherein the communication circuit communicates and / or forwards the indication of the selected DPD core to one or more configurable components, as further described below.

[0149] The adaptive DPD device 702 includes a second input mechanism 706 configured to receive samples (e.g., digital samples) of a signal. For example, the second input mechanism 706 may include one or more input lines for receiving complex samples x ( Figure 7 In some aspects, the second input mechanism 706 may be coupled to one or more computing circuits ( Figure 7 As an example, the second input mechanism 706 may be coupled to: a first computing circuit that generates an envelope value (e.g., an absolute value) based at least in part on the received samples (e.g., an absolute value) (e.g., an absolute value) based at least in part on the received samples. Figure 7 a second computation circuit that generates a cube value (in Figure 7 Indicated as "x 3 ”); a third computing circuit that generates a square value (in Figure 7 Indicated as "x 2 ”); and / or a fourth computing circuit that generates an absolute value square value (in Figure 7 is shown as “|x| 2”). Other examples of computational circuitry may include logic to generate a complex conjugate computation value, a complex conjugate square computation value, an absolute value square computation value, a complex conjugate cube computation value, an absolute value square multiplied by a sample computation value, and / or an absolute value square multiplied by a complex conjugate value. In some aspects, the computational circuitry may store a value without performing a computation, such as a “1” value or a sample value.

[0150] In some aspects, the adaptive DPD device 702 is configured to receive a calculation indication specifying the enabling and / or disabling of one or more calculation circuits, such as an indication to enable a complex conjugate calculation circuit, an indication to disable an absolute value square calculation circuit, and / or an indication to enable a constant value (e.g., 1), via the first input mechanism 704. Thus, the calculation values ​​generated and / or stored by the adaptive DPD device 702 may be configured via the first input mechanism 704 and / or the one or more calculation circuits.

[0151] As shown in example 700, the adaptive DPD device 702 includes an output mechanism 708 configured to output one or more modified samples (e.g., input samples x modified with predistortion). As an example, the output mechanism 708 may include one or more output lines coupled to a clock and / or one or more output logic gates to output the modified samples. For illustration, the output mechanism 708 may output the modified samples (e.g., represented by one or more bits) serially and / or in parallel via one or more output lines.

[0152] In some aspects, the adaptive DPD device 702 includes one or more envelope delay line components 710 configured to store one or more envelope values. As an example, the envelope delay line component 710 may include an envelope storage component having storage capacity associated with storing an input envelope value (e.g., |x|) as one of a plurality of envelope values ​​across a time duration. For example, the envelope storage component may include a memory or a shift register. In some aspects, the envelope storage component may be configured to store a plurality of envelope values ​​associated with a plurality of samples of the same I / Q signal, wherein each envelope value may be associated with a respective sample of the I / Q signal at a respective point in time in the time duration. For illustration, when the envelope delay line component 710 receives a new input envelope value, the envelope storage component includes one or more logic gate circuits (e.g., AND gates, OR gates, NAND gates, NOR gates, XOR gates, XNOR gates, buffer gates, and / or inverters) to remove the envelope value associated with the oldest time point and replace the removed envelope value with the new input envelope value (e.g., a circular buffer). Alternatively or additionally, the envelope storage component may include shift logic that shifts the plurality of envelope values ​​by one position so that the second oldest envelope value is shifted from a current position in the memory to a new position in the memory associated with the (removed) oldest envelope value.

[0153] The one or more envelope delay line components 710 are coupled to one or more envelope selection components 712, which include selection logic configured to select a subset of envelope values ​​from a plurality of envelope values ​​stored by the envelope delay line component 710. As an example, the envelope selection component 712 may include one or more multiplexers that select the subset of envelope values ​​based at least in part on the selected DPD kernel. In some aspects, the envelope selection component 712 may be configured to select the subset of envelope values ​​based at least in part on a timing advance and / or timing delay relative to a computation time reference (e.g., a current sample being processed using DPD). As a non-limiting example, the envelope selection component 712 may be configured to select the subset of envelope values ​​(e.g., x) based at least in part on a sample index as shown in equation (10) n-l Thus, the envelope selection component 712 can be configured to select any envelope value from the envelope delay line component 710 and subsequently select an envelope value having any timing advance and / or timing delay (e.g., relative to the nth sample) stored in the envelope delay line component 710 at a discrete time within the time duration. In some aspects, the envelope value delay line component 710 and one or more envelope selection components 712 can be implemented as a delay line multiplexer component, such as with respect to Figure 8 Further described.

[0154] In the example of the adaptive DPD device 702, the envelope selection component 712 is coupled to one or more LUT components, shown as LUT component 714-1, LUT component 714-2, LUT component 714-3 until LUT component 714-m, where m represents an integer. Therefore, although the example 700 illustrates four LUT components, other examples may include more or fewer LUT components. The LUT components may be collectively referred to as LUT components 714 (e.g., without sub-indicators). The LUT components may include one or more input mechanisms (e.g., one or more input lines), one or more storage components (e.g., memories), and one or more output mechanisms (e.g., one or more output lines). In some aspects, the LUT components may store multiple envelope calculation values ​​associated with calculation results based at least in part on one or more envelope values ​​in one or more storage components, such as the envelope power sum calculation value described with respect to equation (9) or the alternative envelope calculation value described with respect to equation (20) and / or equation (21). For illustration, the LUT component may store calculations of values ​​associated with approximations of the piecewise linear envelope function as described in the equations discussed above. Alternatively or additionally, the LUT component may store cross-reference information associated with each envelope calculation value in one or more storage components, such that the LUT component may receive a subset of envelope values ​​(e.g., via an input mechanism) and identify the envelope calculation value associated with the subset of envelope values. Alternatively or additionally, the cross-reference information may include an indication of a DPD kernel associated with the envelope calculation value.

[0155] In the example of the adaptive DPD device 702, the LUT component 714 is connected to the LUT selection component 716. The LUT selection component 716 receives m envelope calculation values ​​as input and outputs one or more envelope calculation values ​​based at least in part on the selected DPD kernel. As an example, the LUT selection component includes one or more crossbar (XBAR) multiplexers that select one or more envelope calculation values ​​based at least in part on the selected DPD kernel. Alternatively or additionally, the XBAR multiplexer routes the selected envelope calculation values ​​to one or more inputs of the combiner component, as further described below. The ability to select and route envelope calculation values ​​(e.g., through the LUT selection component 716) based at least in part on the selected DPD enables the adaptive DPD device 702 to dynamically change which envelope calculation values ​​are input to the combiner component and subsequently change the type of DPD kernel implemented by the adaptive DPD device. As a non-limiting example, the LUT selection component 716 can first select and route the envelope power summation value from the first LUT component based at least in part on the selected DPD core being a GMP core. Subsequently, the LUT selection component 716 can be configured to select a different envelope calculation value from the second LUT component based at least in part on the selected DPD core being changed to a DVR core. However, other envelope calculation values ​​associated with other types of cores can be stored by the LUT components and selected by the LUT selection component.

[0156] In some aspects, the adaptive DPD device 702 includes one or more computational delay line components 718 that store a plurality of computational values. For illustration, and in a manner similar to that described with respect to the envelope delay line component 710, the computational delay line component 718 may include one or more input mechanisms for receiving one or more computational values ​​(e.g., generated by computational circuitry), one or more computational storage components having storage capacity for storing the plurality of computational values, and one or more output mechanisms for outputting the one or more stored computational values.

[0157] As shown in example 700, the computation delay line component 718 may include a plurality of computation delay lines, such as a plurality of computation delay lines for storing a plurality of computation values ​​associated with a first computation (eg, x 3 ) and a storage device having a first calculation delay line (shown as a x3 delay line) and a plurality of values ​​(e.g., x3) associated with a second calculation applied to each sample in the plurality of samples. 2 ) of a storage device. The computation delay line component 718 may alternatively or additionally include a storage device having a plurality of values ​​associated with a third computation applied to each sample in the plurality of samples (e.g., |x 2|) and / or a fourth delay line (a sample delay line, shown as an IQ delay line) having a storage device for storing a plurality of samples. Although example 700 shows four computational delay lines, other examples may include more or fewer computational delay lines. The computational values ​​stored by the computational delay line component 718 may be configurable based at least in part on the first input mechanism 704 and the selection of one or more computational circuits, as further described above. Alternatively, the type of computational value stored by the computational delay line component 718 (e.g., based at least in part on the type of computation applied to the sample) may be fixed.

[0158] The computation delay line component 718 is coupled to one or more computation selection components. For illustration, and as shown in example 700, the computation delay line component 718 is coupled to a first computation selection component set and / or layer, which is shown as a first computation selection component 720-1 to a dth computation selection component 720-d, where d is an integer. The first computation selection component set may be collectively referred to as the computation selection component 720 (e.g., without a sub-indicator). The computation delay line component 718 is also coupled to a second computation delay line component set and / or layer, which is shown as a single computation selection component 722 for simplicity, but other examples may include multiple computation selection components in the second computation component set. The first computation selection component set and / or the second computation selection component set may be configured to select any computation value from any computation delay line component 718, and then select the computation value stored in the computation delay line component 718 with any timing advance and / or timing delay (e.g., relative to the nth sample) at a discrete time within the time duration.

[0159] In some aspects, each compute selection component may include one or more selection logic gates configured to select one or more subsets of compute values ​​stored by the compute storage component of the compute delay line component 718. For illustration, each compute selection component may include one or more multiplexers that select the subset of compute values ​​based at least in part on the selected DPD core. As an example, each compute selection component may be coupled to a mapping logic gate that receives an indication of the selected DPD core, wherein the compute selection component may configure the one or more multiplexers to select the subset of compute values ​​based at least in part on the selected DPD core. As a non-limiting example, each compute selection component may be configured to select a subset of compute values ​​(e.g., compute values ​​for q and / or p) based at least in part on the selected DPD core and a mapping specified by table 602. For illustration, a first set of compute selection components (e.g., compute selection component 720-1 and compute selection component 720-d) may be based at least in part on p with the selected DPD core.m The second set of computation selection components (e.g., computation selection components 722) may be dynamically configured (e.g., via input mechanism 704) based at least in part on the q associated with the selected DPD kernel. j Alternatively or additionally, the calculation selection component can be configured to select one or more samples (e.g., from the IQ sample delay line) (and include the one or more samples in the calculation value subset) based at least in part on the selected DPD kernel. In some aspects, the calculation selection component can be configured to select one or more samples (e.g., from the IQ sample delay line) based at least in part on the selected DPD kernel (and include the one or more samples in the calculation value subset). n-j and / or n-m ) associated timing advance or timing delay to select calculated values ​​and / or samples.

[0160] For clarity, compute selection component 720-1, compute selection component 720-d, and compute selection component 722 are each illustrated as separate components in example 700. However, in alternative or additional examples, compute selection component 720-1, compute selection component 720-d, and / or compute selection component 722 may be included in the same (single) component coupled to one or more compute delay line components in compute delay line component 718, such as a single multiplexer component and / or delay line multiplexer selection component as further described below.

[0161] As shown in example 700, the adaptive DPD device 702 includes one or more combiner components coupled to one or more computation components. As an example, a first combiner component 724-1 is coupled to a first computation selection component 720-1 until a d-th combiner component 724-d (collectively referred to as combiner components 724) coupled to a d-th computation selection component 720-d. The combiner components 724 are also coupled to the LUT selection component 716, such that each of the combiner components 724 receives at least a first input from the LUT selection component 716 and at least a second input from the corresponding computation selection component.

[0162] As also shown in example 700 , combiner component 726 is coupled to compute selection component 722 and value selection component 728 (described further below) such that combiner component 726 receives at least a first input from compute selection component 722 and at least a second input from value selection component 728 .

[0163] Each combiner component includes a circuit configured as one or more logic gates that generate an output based at least in part on combining one or more envelope calculation values ​​with a subset of calculation values. As an example, the combiner component may include a multiplier circuit that combines the values ​​using at least a multiplication operation and / or an adder circuit that combines the values ​​using at least a summation operation. For illustration, the adder circuit of the combiner component (e.g., combiner component 724-1) is coupled to a LUT selection component (e.g., LUT selection component 716) and combines the (approximate) envelope calculation values ​​selected and routed by the LUT selection component. As another example, the multiplier circuit of the combiner component is coupled to one or more calculation selection components (e.g., calculation selection component 720-1) and combines a subset of calculation values ​​with the (added) envelope calculation value.

[0164] The value selection component 728 includes logic gate circuits that select one or more combined values ​​generated by one or more combiner components (e.g., combiner component 724) based at least in part on the selected DPD core and output the selected combined value. For illustration, the value selection component 728 may include one or more multiplexers and / or one or more XBAR multiplexers that select (and / or route) combined values ​​based at least in part on the selected DPD core. The ability to select and route different combined values ​​generated by the combiner components based at least in part on the selected DPD enables the adaptive DPD device 702 to dynamically change which combined value is input to the combiner component (e.g., combiner component 726) and subsequently change the type of DPD core implemented by the adaptive DPD device 702.

[0165] In some aspects, the adaptive DPD component may be implemented at least in part as an IC device and / or a SoC device. An IC device may include an electronic circuit formed on a semiconductor substrate (such as silicon). Example types of IC devices include memory IC devices (e.g., dynamic random access memory devices or flash memory devices, etc.), processing IC devices (e.g., microprocessors, digital signal processors or microcontrollers, computing circuits, etc.), transceiver IC devices (e.g., RF or mixed signal transceivers, etc.), or power amplifier IC devices (e.g., operational amplifier devices, etc.). An SoC device (e.g., an SoC IC device) may include a combination of one or more types of IC devices.

[0166] The structures of IC devices (e.g., transistors, memory cells, logic gates, or interconnects, etc.) can be manufactured using semiconductor manufacturing processes, which include the use of deposition, photolithography, and etching techniques. Deposition techniques can form a dielectric or conductive material layer on or over a semiconductor substrate, and then photolithography and etching techniques can form a pattern of the structure (e.g., forming a transistor, memory cell, logic gate, or interconnect) from the dielectric or conductive material layer.

[0167] As indicated above, Figure 7 Other examples may differ from the examples described above.

[0168] Figure 8 is a diagram of an example 800 including a delay line multiplexer selection component 802 according to the present disclosure.

[0169] about Figure 7 The described adaptive DPD device 702 includes a variety of selection components configured to receive J values ​​as input and output a subset of K values ​​based on a selected DPD kernel, where J and K are integers and J>=K. For illustration, the envelope selection component 712 selects a subset of envelope values ​​stored by the envelope delay line component 710 based at least in part on the selected DPD kernel. Alternatively or additionally, the LUT selection component 716, the calculation selection component 720, and / or the value selection component 728 each selects a subset of values ​​(e.g., a subset of LUT output values, a subset of calculation values, and / or a subset of combined values, respectively) based at least in part on the selected DPD kernel. For illustration, the envelope selection component 712, the LUT selection component 716, the calculation selection component 720, and / or the value selection component 728 may include one or more multiplexer components configured to select a corresponding subset of values ​​based at least in part on the selected DPD kernel.

[0170] The complexity of a multiplexer component (e.g., power consumption, size factor, number of routing lines, and / or number of digital logic gates) can be at least partially based on the selection and / or reduction factor performed by the multiplexer component. For example, a first multiplexer component configured to perform a 16-to-1 reduction (e.g., receive 16 input values and output 1 value) may consume less power, use less space, include fewer routing lines, and / or include fewer digital logic gates (e.g., "AND" gates, "OR" gates, and / or inverters) compared to a second multiplexer component configured to perform a 64-to-1 reduction. Thus, increasing the reduction factor performed by a multiplexer component can also increase the number of digital logic gates included in the multiplexer component, such that the amount of power consumed and / or the size occupied by the multiplexer component exceeds some implementations that have constraints on power consumption and / or size. In contrast, a delay-line multiplexer selection component (such as delay-line multiplexer component 802) can utilize less power consumption, have a reduced size factor, use fewer routing lines, and / or use fewer digital logic gates compared to a single multiplexer. Thus, a delay-line multiplexer component can meet the power consumption and / or size constraints of more implementations compared to a single multiplexer configured with the same reduction factor.

[0171] In example 800, delay-line multiplexer selection component 802 is coupled to a first delay-line component 804 that stores L values, where L represents an integer and is shown in example 800 as having a value of 256. As an example, the first delay-line component 804 stores L envelope values or L computed values that are at least partially based on L samples of an I / Q signal. In some aspects, delay-line multiplexer selection component 802 performs an L-to-M reduction, where M is an integer. As a non-limiting example, delay-line multiplexer selection component performs a 256-to-1 reduction, where L = 256 and M = 1.

[0172] As shown by reference numeral 806, delay-line multiplexer selection component 802 receives a first subset of the values stored by first delay-line component 804. By way of illustration, delay-line multiplexer selection component 802 includes a first multiplexer component 808 that receives N input values from first delay-line component 804, where N is an integer and N < M. In some aspects, the N input values are evenly spaced from each other by an offset 810. As a non-limiting example, and as shown in example 800, first multiplexer component 808 of delay-line multiplexer selection component 802 receives a subset of N = 32 input values of L = 256 stored by first delay-line component 804, where each received input value is offset from an adjacent received value by an offset = 8 (e.g., in the storage device at first delay-line component 804 and / or in discrete time units).

[0173] The first multiplexer component 808 performs an N to P reduction factor such that the first multiplexer component 808 selects and outputs P values out of one or more of the N received input values, where P is an integer and P < N. As a non-limiting example, the first multiplexer component 808 may be configured to perform a 32 to 1 reduction factor that selects and outputs the value associated with connection 812 at least in part based on the selected DPD kernel, as described above. For illustration, the first multiplexer component 808 may be configured to select the value associated with position D + 16 of the first delay line component 804.

[0174] As shown in example 800, the first multiplexer component 808 is coupled to a second delay line component 814 that includes a storage component (e.g., a circular buffer and / or a shift register) configured to store R values, where R is an integer equivalent to the offset 810 (shown as having a value of 8 in example 800). Thus, when the first multiplexer component 808 outputs a new value, the second delay line component 814 stores the new value such as by replacing the oldest value with the new (received) value and / or by shifting the R - 1 values one position such that the second oldest value is shifted from its current position in the memory to the new position in the memory associated with the (removed) oldest value. Thus, after the first multiplexer component 808 makes R selections during initialization, the second delay line component 814 stores R values that are temporally contiguous and updates the R values at least in part based on receiving the new value output by the first multiplexer component 808. For illustration, and with respect to the above example where the first multiplexer component 808 selects and outputs the value associated with the D + 16 value stored by the first delay line component, the second delay line component 814 stores R samples, each of which represents the D + 16 value at a corresponding discrete time point.

[0175] The second delay line component 814 includes R outputs that are coupled to R inputs of a second multiplexer component 816, and the second multiplexer component 816 selects and outputs S values, where S is an integer and is shown as having a value of 1 in example 800. For illustration, the second multiplexer component 816 may select one value out of the R values stored by the second delay line component 814 at least in part based on the selected DPD kernel and / or the discrete time associated with the selected value (e.g., select one value out of the 8 stored D + 16 values). The second multiplexer component 816 may output the selected value, as shown by reference numeral 818.

[0176] Based at least in part on the first multiplexer component 808, the second delay line component 814, and the second multiplexer component 816, the delay line multiplexer selection component 802 can perform L to M reduction (e.g., 256 to 1 reduction) with reduced complexity (e.g., fewer digital logic gates, fewer routing lines) relative to a single multiplexer component that performs L to M reduction. The reduced complexity can cause the delay line multiplexer selection component 802 to consume less power and / or have a smaller form factor relative to a single multiplexer component that performs the same reduction factor.

[0177] As indicated above, Figure 8 Other examples may differ from the examples described above.

[0178] Fig. 9A and Fig. 9B is a diagram illustrating an example process 900, for example, performed by an apparatus according to the present disclosure. The example process 900 is an example in which an apparatus (eg, adaptive DPD apparatus 702) performs operations associated with adaptive digital pre-distortion.

[0179] like Fig. 9A As shown, in some aspects, process 900 may include receiving an indication of a selected digital predistortion (e.g., using Figure 7 ), may receive an indication of a selected DPD kernel from a plurality of DPD kernels, as described above.

[0180] like Fig. 9A As further shown, in some aspects, process 900 may include storing an envelope value associated with a sample of the I / Q signal based at least in part on the envelope delay line component. The storing may include storing the envelope value as one of a plurality of envelope values ​​across a time duration, wherein the plurality of envelope values ​​may be based at least in part on a plurality of samples associated with the I / Q signal (block 920). For example, an apparatus (e.g., using Figure 7 710) may store envelope values ​​associated with samples of the I / Q signal based at least in part on the envelope delay line component. The storing may include storing the envelope value as one of a plurality of envelope values ​​across a time duration, the plurality of envelope values ​​being based at least in part on a plurality of samples associated with the I / Q signal, as described above.

[0181] like Fig. 9AAs further shown, in some aspects, process 900 may include storing at least the following items based at least in part on a computational storage component: a first computational value as one of a first plurality of computational values, the first plurality of computational values ​​being based at least in part on a plurality of samples, the first computational value being based at least in part on a first computation applied to the samples. Alternatively or additionally, the storing may include storing the following items based at least in part on the computational storage component: a second computational value as one of a second plurality of computational values, the second plurality of computational values ​​being based at least in part on a plurality of samples, the second computational value being based at least in part on a second computation applied to the samples. The storing may include storing the plurality of samples based at least in part on the computational storage component (block 930). For example, the device (e.g., using Figure 7 The computational delay line component 718 depicted in the figure may store at least the following items based at least in part on a computational storage component: a first computational value as one of a first plurality of computational values ​​(e.g., where the first plurality of computational values ​​is at least partially based on a plurality of samples, and / or the first computational value is at least partially based on a first computation applied to the samples); a second computational value as one of a second plurality of computational values ​​(e.g., where the second plurality of computational values ​​is at least partially based on a plurality of samples and / or the second computational value is at least partially based on a second computation applied to the samples); and a plurality of samples, as described above.

[0182] like Fig. 9B As further shown, in some aspects, process 900 may include selecting a subset of envelope values ​​from a plurality of envelope values ​​based at least in part on the selected DPD kernel (block 940). Figure 7 An envelope selection component 712 depicted in FIG. 7 may select a subset of envelope values ​​from a plurality of envelope values ​​based at least in part on a selected DPD kernel, as described above.

[0183] like Fig. 9B As further shown, in some aspects, process 900 may include generating an envelope calculation value based at least in part on the subset of envelope values, at least one LUT component, and the selected DPD kernel (block 950). For example, the apparatus may generate an envelope calculation value based at least in part on the subset of envelope values, at least one LUT component (e.g., using Figure 7 The LUT component 714-1, LUT component 714-2, LUT component 714-3 and / or LUT component 714-m) depicted in FIG. 1 and the selected DPD kernel are used to generate envelope calculation values, as described above.

[0184] like Fig. 9B As further shown, in some aspects, process 900 may include selecting at least one subset of computed values ​​stored by a compute storage component based at least in part on the selected DPD kernel (block 960). Figure 7The compute selection component 720-1, compute selection component 720-d and / or compute selection component 722 depicted in FIG. 1 may select at least one subset of compute values ​​stored by the compute storage component based at least in part on the selected DPD kernel, as described above.

[0185] like Fig. 9B As further shown, in some aspects, process 900 may include generating output samples including digital predistortion based at least in part on combining the envelope calculation value with the at least one calculation value subset (block 970). Figure 7 The combiner component 724-1, combiner component 724-d, combiner component 726, LUT selection component 716 and / or value selection component 728 depicted in the figure can generate output samples including digital predistortion based at least in part on combining the envelope calculation value with at least one subset of calculation values, as described above.

[0186] Process 900 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other processes described elsewhere herein.

[0187] In a first aspect, at least one LUT component includes a plurality of LUT components, and wherein the method further comprises: selecting a subset of LUT outputs from the plurality of LUT components using a LUT selection component based at least in part on a selected DPD core; and inputting the subset of LUT outputs to at least one combiner component configured to generate at least one combined value based at least in part on the subset of LUT outputs and at least one subset of calculated values.

[0188] In a second aspect, either alone or in combination with the first aspect, at least one combiner component comprises a plurality of combiner components, wherein at least one combined value comprises a plurality of combined values, and wherein generating an output sample comprises: selecting, using at least one value selection component coupled to the plurality of combiner components, a subset of combined values ​​output from at least some of the plurality of combiner components based at least in part on a selected DPD kernel; and generating the output sample based at least in part on the subset of combined values.

[0189] In a third aspect, alone or in combination with one or more of the first and second aspects, selecting the subset of envelope values ​​includes selecting the subset of envelope values ​​based at least in part on using a delay line multiplexer selection component.

[0190] In a fourth aspect, alone or in combination with one or more of the first to third aspects, a delay line multiplexer selection component includes: a delay line component; a first multiplexer component coupled to at least one input portion of the delay line component; and a second multiplexer component coupled to at least one output portion of the delay line component.

[0191] In a fifth aspect, either alone or in combination with one or more of the first to fourth aspects, process 900 includes obtaining, from at least one LUT component, at least one of: a first envelope calculation value based at least in part on a piecewise linear envelope function associated with a distortion model; or a second envelope calculation value based at least in part on an approximate envelope power summation calculation.

[0192] In a sixth aspect, alone or in combination with one or more of the first to fifth aspects, a piecewise linear envelope function is associated with the DPD kernel.

[0193] In a seventh aspect, either alone or in combination with one or more of aspects 1 to 6, process 900 includes storing, based at least in part on a computational storage component, a third computational value as one of a third plurality of computational values ​​based at least in part on a plurality of samples, the third computational value being based at least in part on a third computation applied to the sample, wherein the first computation, the second computation, and the third computation are different from one another.

[0194] In the eighth aspect, alone or in combination with one or more of the first to seventh aspects, x m represents the mth sample in the plurality of samples, wherein the first calculation, the second calculation, or the third calculation comprises at least one of the following: m 、x m *、|x m |、x 2 m 、x m * 2 、|x m | 2 、x m 3 、x m * 3 、|x m | 2 x m or |x m | 2 x m *.

[0195] In a ninth aspect, alone or in combination with one or more of the first to eighth aspects, process 900 includes calculating a first calculated value or a second calculated value.

[0196] In a tenth aspect, alone or in combination with one or more of the first to ninth aspects, process 900 includes receiving as input the first calculated value or the second calculated value.

[0197] In an eleventh aspect, alone or in combination with one or more of the first to tenth aspects, at least one LUT component stores an envelope power summation value associated with a Volterra-based kernel as the envelope calculation value.

[0198] In a twelfth aspect, alone or in combination with one or more of the first to eleventh aspects, the plurality of DPD cores include at least one of a DDR DPD core, a GDDR DPD core, a GMP DPD core, or a DVR DPD core.

[0199] In a thirteenth aspect, either alone or in combination with one or more of aspects one to twelfth, selecting at least one subset of envelope values ​​comprises selecting at least one subset of envelope values ​​based at least in part on: a timing advance relative to a calculation time reference, or a timing delay relative to a calculation time reference.

[0200] In the fourteenth aspect, either alone or in combination with one or more of the first to thirteenth aspects, storing the first calculated value or the second calculated value further comprises: storing the first calculated value based at least in part on the first calculation delay line; or storing the second calculated value based at least in part on the second calculation delay line.

[0201] In a fifteenth aspect, either alone or in combination with one or more of aspects one to fourteen, process 900 includes storing a third calculated value in a third calculation delay line as one of a third plurality of calculated values, the third plurality of calculated values ​​being based at least in part on a third calculation applied to each sample of a plurality of samples.

[0202] In a sixteenth aspect, alone or in combination with one or more of the first to fifteenth aspects, process 900 includes storing a plurality of samples in a sample delay line.

[0203] In a seventeenth aspect, either alone or in combination with one or more of the first to sixteenth aspects, selecting at least one subset of calculated values ​​further comprises: selecting at least one sample from a plurality of samples as part of the subset of calculated values ​​based at least in part on the selected DPD kernel.

[0204] In an eighteenth aspect, either alone or in combination with one or more of the first to seventeenth aspects, each sample of the plurality of samples is a complex sample comprising an I component associated with the I / Q signal and a Q component associated with the I / Q signal.

[0205] In a nineteenth aspect, alone or in combination with one or more of the first to eighteenth aspects, the sample is a first sample, wherein the indication is a first indication, wherein the selected DPD kernel is a first selected DPD kernel, and the method further comprises: applying digital predistortion to the first sample based at least in part on the first selected DPD kernel; receiving a second indication of a second selected DPD kernel among a plurality of DPD kernels; and reconfiguring the apparatus to apply digital predistortion to the second sample based at least in part on the second selected DPD kernel.

[0206] Although Figure 9 shows example blocks of process 900, in some aspects, process 900 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently than those depicted in Figure 9. Additionally or alternatively, two or more of the blocks of process 900 may be performed in parallel.

[0207] The following provides an overview of some aspects of the disclosure:

[0208] Aspect 1: An apparatus, comprising: a first input mechanism, the first input mechanism being configured to receive an indication of a selected DPD kernel from a plurality of digital predistortion (DPD) kernels; an envelope delay line component, the envelope delay line component comprising an envelope storage component, the envelope storage component being configured to store an input envelope value as one of a plurality of envelope values ​​associated with a plurality of samples sampled over a time duration; an envelope selection component, the envelope selection component being configured to select an envelope value subset from the plurality of envelope values ​​based at least in part on the selected DPD kernel; at least one lookup table (LUT) component, the at least one LUT component being coupled to the envelope selection component, the at least one LUT component being configured to: output an envelope calculation value, the envelope calculation value being based at least in part on the envelope value subset and the selected DPD kernel; a computational delay line component, the computational delay line component comprising a computational storage component, The computation storage component is configured to store at least the following items: a first plurality of computation values, the first plurality of computation values ​​being based at least in part on a first computation applied to each of the plurality of samples; a second plurality of computation values, the second plurality of computation values ​​being based at least in part on a second computation applied to each of the plurality of samples; and the plurality of samples, the plurality of samples spanning the time duration; at least one computation selection component, the at least one computation selection component being coupled to the computation delay line component and being configured to select at least one subset of computation values ​​stored by the computation storage component based at least in part on a selected DPD core; and at least one combiner component, the at least one combiner component being coupled to the at least one computation selection component and the at least one LUT component, the at least one combiner component being configured to generate an output sample based at least in part on combining the envelope computation value with the at least one subset of computation values.

[0209] Aspect 2: An apparatus according to Aspect 1, wherein the at least one LUT component includes a plurality of LUT components, and wherein the apparatus further comprises: at least one LUT selection component, the at least one LUT selection component coupling the plurality of LUT components to the at least one combiner component, the at least one LUT selection component being configured to: select a subset of LUT outputs from the plurality of LUT components based at least in part on the selected DPD core; and input the subset of LUT outputs to the at least one combiner component.

[0210] Aspect 3: An apparatus according to Aspect 1 or Aspect 2, wherein the at least one combiner component includes a first set of combiner components and a second combiner component, and wherein the apparatus further includes: at least one value selection component, the at least one value selection component coupling the first set of combiner components to the second combiner component, the at least one value selection component being configured to: select a subset of combined values ​​output from the first set of combiner components based at least in part on the selected DPD kernel; and input the subset of combined values ​​to the second combiner component.

[0211] Aspect 4: The apparatus according to any one of aspects 1 to 3, wherein the envelope selection component comprises a delay line multiplexer selection component.

[0212] Aspect 5: An apparatus according to Aspect 4, wherein the delay line multiplexer selection component comprises: a delay line component; a first multiplexer component, the first multiplexer component being coupled to at least one input portion of the delay line component; and a second multiplexer component, the second multiplexer component being coupled to at least one output portion of the delay line component.

[0213] Aspect 6: An apparatus according to any one of aspects 1 to 5, wherein the at least one LUT component stores at least one envelope calculation value, the at least one envelope calculation value being based at least in part on a piecewise linear envelope function associated with a distortion model.

[0214] Aspect 7: An apparatus according to any one of Aspects 1 to 6, wherein the at least one LUT component stores at least one approximate envelope power summation value, and the at least one approximate envelope power summation value is at least partially based on an approximation of a signal envelope summation function.

[0215] Aspect 8: An apparatus according to any one of Aspects 1 to 7, wherein the computational storage component includes additional capacity to store at least the following items: a third plurality of computational values, the third plurality of computational values ​​being based at least in part on a third computation applied to each sample in the plurality of samples.

[0216] Aspect 9: The apparatus of any one of aspects 1 to 8, wherein the plurality of samples is based at least in part on an in-phase / quadrature (I / Q) signal.

[0217] Aspect 10: The apparatus of aspect 9, wherein each sample of the plurality of samples comprises a complex sample, the complex sample comprising an I component associated with the I / Q signal and a Q component associated with the I / Q signal.

[0218] Aspect 11: The apparatus according to any one of aspects 1 to 10, wherein the envelope selection component comprises one or more multiplexers.

[0219] Aspect 12: The apparatus according to any one of aspects 1 to 12, wherein the at least one computation selection component comprises one or more multiplexers.

[0220] Aspect 13: A device according to any one of Aspects 1 to 12, wherein the multiple DPD kernels include at least one of the following: a dynamic deviation reduction (DDR) DPD kernel, a generalized DDR (GDDR) DPD kernel, a generalized memory polynomial (GMP) DPD kernel, or a factorized vector rotation (DVR) DPD kernel.

[0221] Aspect 14: The apparatus according to any one of aspects 1 to 13, wherein the envelope calculation value comprises an envelope power summation value associated with a Volterra-based DPD kernel.

[0222] Aspect 15: The apparatus according to any one of aspects 1 to 15, wherein the envelope calculation value is based at least in part on a piecewise linear envelope function associated with a decomposition vector rotation (DVR) DPD kernel.

[0223] Aspect 16: An apparatus according to any one of Aspects 1 to 16, wherein the envelope selection component includes a selection circuit, which is configured to select the subset of envelope values ​​based at least in part on at least one of the following: a timing advance relative to a calculation time reference, or a timing delay relative to the calculation time reference.

[0224] Aspect 17: An apparatus according to any one of Aspects 1 to 16, wherein the computational storage component comprises: a first computational delay line, the first computational delay line being used to store the first plurality of computational values; and a second computational delay line, the second computational delay line being used to store the second plurality of computational values.

[0225] Aspect 18: An apparatus according to any one of Aspects 1 to 17, wherein the computational storage component includes: a third computational delay line, the third computational delay line being used to store a third plurality of computational values, the third plurality of computational values ​​being based at least in part on a third computation applied to each sample of the plurality of samples.

[0226] Aspect 19: The apparatus according to aspect 18, wherein the computational storage component comprises: a sample delay line for storing the plurality of samples.

[0227] Aspect 20: The apparatus of aspect 19, wherein the plurality of samples comprises a plurality of in-phase / quadrature (I / Q) samples.

[0228] Aspect 21: The apparatus of any one of aspects 1 to 20, wherein the at least one combiner component comprises at least one of: an adder circuit or a multiplier circuit.

[0229] Aspect 22: The apparatus of any one of aspects 1 to 21, wherein the at least one combiner component comprises an adder circuit coupling the at least one combiner component to the at least one LUT component.

[0230] Aspect 23: The apparatus of any one of aspects 1 to 22, wherein the at least one combiner component comprises a multiplier circuit coupling the at least one combiner component to the at least one computation selection component.

[0231] Aspect 24: An apparatus according to any one of Aspects 1 to 23, wherein the computational selection component comprises a selection logic gate circuit, the selection logic gate circuit being configured to select one or more samples from the plurality of samples, and wherein the at least one combiner component is configured to generate the output sample based at least in part on the selected one or more samples.

[0232] Aspect 25: An apparatus according to any one of aspects 1 to 24, wherein the combiner component includes a logic gate circuit configured to combine the envelope calculation value with the at least one calculation value subset based at least in part on a summation calculation.

[0233] Aspect 26: A method performed by an apparatus, the method comprising: receiving an indication of a selected digital predistortion (DPD) kernel from a plurality of DPD kernels; storing an envelope value associated with a sample of an in-phase / quadrature (I / Q) signal based at least in part on an envelope delay line component, the storing comprising storing the envelope value as one of a plurality of envelope values ​​across a time duration, the plurality of envelope values ​​being based at least in part on a plurality of samples associated with the I / Q signal; storing at least the following items based at least in part on a computation storage component: a first computed value as one of a first plurality of computed values, the first plurality of computed values ​​being based at least in part on the plurality of samples, the first computed value being based at least in part on a first computation applied to the sample a second calculated value as one of a second plurality of calculated values, the second plurality of calculated values ​​being based at least in part on the plurality of samples, the second calculated value being based at least in part on a second calculation applied to the samples; and the plurality of samples; selecting a subset of envelope values ​​from the plurality of envelope values ​​based at least in part on the selected DPD kernel; generating an envelope calculated value based at least in part on the subset of envelope values, at least one lookup table (LUT) component, and the selected DPD kernel; selecting at least one subset of calculated values ​​stored by the calculation storage component based at least in part on the selected DPD kernel; and generating output samples including digital predistortion based at least in part on combining the envelope calculated value with the at least one subset of calculated values.

[0234] Aspect 27: A method according to Aspect 26, wherein the at least one LUT component includes multiple LUT components, and wherein the method further includes: using a LUT selection component to select a LUT output subset from the multiple LUT components based at least in part on the selected DPD core; and inputting the LUT output subset to at least one combiner component, the at least one combiner component being configured to generate at least one combined value based at least in part on the LUT output subset and the at least one calculated value subset.

[0235] Aspect 28: A method according to Aspect 27, wherein the at least one combiner component includes multiple combiner components, wherein the at least one combined value includes multiple combined values, and wherein generating the output sample includes: using at least one value selection component coupled to the multiple combiner components to select a subset of combined values ​​output from at least some of the multiple combiner components based at least in part on the selected DPD core; and generating the output sample based at least in part on the subset of combined values.

[0236] Aspect 29: The method of any one of aspects 26 to 28, wherein selecting the subset of envelope values ​​comprises selecting the subset of envelope values ​​based at least in part on using a delay line multiplexer selection component.

[0237] Aspect 30: A method according to Aspect 29, wherein the delay line multiplexer selection component includes: a delay line component; a first multiplexer component, the first multiplexer component is coupled to at least one input section of the delay line component; and a second multiplexer component, the second multiplexer component is coupled to at least one output section of the delay line component.

[0238] Aspect 31: A method according to any one of Aspects 26 to 30, wherein generating the envelope calculation value includes: obtaining at least one of the following from the at least one LUT component: a first envelope calculation value, the first envelope calculation value being at least partially based on a piecewise linear envelope function associated with a distortion model; or a second envelope calculation value, the second envelope calculation value being at least partially based on an approximate envelope power summation calculation.

[0239] Aspect 32: The method according to aspect 31, wherein the piecewise linear envelope function is associated with a decomposed vector rotation (DVR) DPD kernel.

[0240] Aspect 33: According to the method described in any one of Aspects 26 to 32, the method also includes: storing a third calculated value as one of a third plurality of calculated values ​​based at least in part on the multiple samples based at least in part on the calculation storage component, the third calculated value being based at least in part on a third calculation applied to the sample, wherein the first calculation, the second calculation, and the third calculation are different from each other.

[0241] Aspect 34: The method according to Aspect 33, wherein x m represents the mth sample in the plurality of samples, wherein the first calculation, the second calculation, or the third calculation comprises at least one of the following: m 、x* m 、|x m |、x 2 m 、x* 2 m 、|x m | 2 、x 3 m 、x* 3 m 、|x m | 2 x m or |x m | 2 x* m .

[0242] Aspect 35: According to the method according to any one of Aspects 26 to 34, the method also includes: calculating the first calculated value or the second calculated value.

[0243] Aspect 36: The method according to any one of Aspects 26 to 35, further comprising: receiving the first calculated value or the second calculated value as input.

[0244] Aspect 37: The method according to any one of Aspects 26 to 36, wherein the at least one LUT component stores an envelope power summation value associated with a Volterra-based DPD kernel as the envelope calculation value.

[0245] Aspect 38: A method according to any one of Aspects 26 to 37, wherein the multiple DPD kernels include at least one of the following: a dynamic deviation reduction (DDR) DPD kernel, a generalized DDR (GDDR) DPD kernel, a generalized memory polynomial (GMP) DPD kernel, or a factorized vector rotation (DVR) DPD kernel.

[0246] Aspect 39: A method according to any one of Aspects 26 to 38, wherein selecting the at least one subset of envelope values ​​includes: selecting the at least one subset of envelope values ​​based at least in part on: a timing advance relative to a calculation time reference, or a timing delay relative to the calculation time reference.

[0247] Aspect 40: A method according to any one of Aspects 26 to 39, wherein storing the first calculated value or the second calculated value further comprises: storing the first calculated value based at least in part on a first calculation delay line; or storing the second calculated value based at least in part on a second calculation delay line.

[0248] Aspect 41: The method according to Aspect 40, further comprising: storing a third calculated value in a third calculation delay line as one of a third plurality of calculated values, the third plurality of calculated values ​​being based at least in part on a third calculation applied to each sample of the plurality of samples.

[0249] Aspect 42: The apparatus according to aspect 41, the apparatus further comprising: storing the plurality of samples in a sample delay line.

[0250] Aspect 43: The method according to any one of Aspects 26 to 42, wherein selecting the at least one subset of calculated values ​​further comprises: selecting at least one sample from the plurality of samples as part of the subset of calculated values ​​based at least in part on the selected DPD kernel.

[0251] Aspect 44: The method according to any one of Aspects 26 to 43, wherein each sample of the plurality of samples is a complex sample, the complex sample comprising an I component associated with the I / Q signal and a Q component associated with the I / Q signal.

[0252] Aspect 45: A method according to any one of Aspects 26 to 44, wherein the sample is a first sample, wherein the indication is a first indication, wherein the selected DPD kernel is a first selected DPD kernel, and the method further includes: applying digital predistortion to the first sample based at least in part on the first selected DPD kernel; receiving a second indication of a second selected DPD kernel among the multiple DPD kernels; and reconfiguring the device to apply digital predistortion to the second sample based at least in part on the second selected DPD kernel.

[0253] Aspect 46: A transceiver device, the transceiver device comprising: a power amplifier; a digital-to-analog converter (DAC), the digital-to-analog converter (DAC) coupled to the power amplifier; and an adaptive digital predistortion (DPD) device, the adaptive digital predistortion (DPD) device coupled to the DAC, the adaptive DPD device comprising: an envelope delay line component, the envelope delay line component comprising an envelope storage component, the envelope storage component being configured to store a plurality of envelope values ​​associated with a plurality of samples of an in-phase / quadrature (I / Q) signal; an envelope selection component, the envelope selection component being configured to select a subset of envelope values ​​from the plurality of envelope values; at least one lookup table (LUT) component, the at least one LUT component being coupled to the envelope selection component, the at least one LUT component comprising an output mechanism, the output mechanism being configured to an output envelope calculation value, the envelope calculation value being based at least in part on the subset of envelope values; a calculation delay line component, the calculation delay line component including a calculation storage component, the calculation storage component being configured to store a plurality of calculation values, the plurality of calculation values ​​being based at least in part on the plurality of samples; at least one calculation selection component, the at least one calculation selection component being coupled to the calculation delay line component and being configured to select at least one calculation value subset stored by the calculation storage component based at least in part on a selected DPD core from a plurality of DPD cores; and at least one combiner component, the at least one combiner component being coupled to the at least one calculation selection component and the at least one LUT component, the at least one combiner component being configured to generate an output sample based at least in part on combining the envelope calculation value with the at least one calculation value subset.

[0254] Aspect 47: An apparatus for performing wireless communications at a device, the apparatus comprising: a processor; a memory coupled to the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to perform one or more of the methods described in Aspects 26 to 45.

[0255] Aspect 48: An apparatus for wireless communication, the apparatus comprising a memory and one or more processors coupled to the memory, the one or more processors configured to perform the method according to one or more of aspects 26 to 45.

[0256] Aspect 49: An apparatus for wireless communication, the apparatus comprising at least one means for performing the method according to one or more of aspects 26 to 45.

[0257] Aspect 50: A non-transitory computer-readable medium storing code for wireless communication, the code comprising instructions executable by a processor to perform the method according to one or more of aspects 26 to 45.

[0258] While the foregoing disclosure provides illustration and description, it is not intended to be exhaustive or to limit the aspects to the precise forms disclosed. Modifications and variations are possible in light of the above disclosure or may be acquired from practice of these aspects.

[0259] As used herein, the term "component" is intended to be broadly interpreted as a combination of hardware and / or hardware and software. Whether referred to as software, firmware, middleware, microcode, hardware description language or other names, "software" should be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads, processes and / or functions implemented, etc. As used herein, a "processor" is implemented in a combination of hardware and / or hardware and software. It will be clear that the systems and / or methods described herein can be implemented by a combination of hardware and / or hardware and software in different forms. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit various aspects. Therefore, the operation and behavior of the system and / or method are not described herein with reference to specific software codes, because those skilled in the art will understand that software and hardware can be designed to implement the system and / or method based at least in part on the description herein.

[0260] As used herein, "satisfying a threshold" may refer to a value being greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc., depending on the context.

[0261] Although specific combinations of features are set forth in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various aspects. Many of these features can be combined in a manner that is not specifically described in the claims and / or is not disclosed in the specification. The disclosure of various aspects includes each dependent claim combined with each other claim in the claim set. As used herein, the phrase "at least one of" the list of items refers to any combination of these items (which includes a single member). As an example, "at least one of a, b or c" is intended to cover a, b, c, a+b, a+c, b+c and a+b+c, and any combination with multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c and c+c+c, or any other ordering of a, b and c).

[0262] Any element, action or instruction used herein should not be interpreted as key or necessary, unless clearly stated so. In addition, as used herein, the articles "one" and "a kind of" are intended to include one or more items, and can be used interchangeably with "one or more". In addition, as used herein, the article "said" is intended to include one or more items connected with the article "said", and can be used interchangeably with "one or more". In addition, as used herein, the terms "set" and "group" are intended to include one or more items, and can be used interchangeably with "one or more". If only one project is intended to be referred to, the phrase "only one" or similar terms are used. Moreover, as used herein, the terms "have", "have" etc. are intended to be open terms, which do not limit the elements they modify (for example, "elements with" A can also have B). In addition, the phrase "based on" is intended to represent "based at least in part on", unless otherwise explicitly stated. Furthermore, as used herein, the term "or" when used in a series is intended to be open-ended and may be used interchangeably with "and / or" unless expressly stated otherwise (eg, if used in conjunction with "either" or "only one of").

Claims

1. A device, comprising: a first input mechanism configured to receive an indication of a selected digital predistortion (DPD) core from a plurality of DPD cores; an envelope delay line component, the envelope delay line component comprising an envelope storage component configured to store an input envelope value as one of a plurality of envelope values ​​associated with a plurality of samples sampled over a time duration; an envelope selection component configured to select a subset of envelope values ​​from the plurality of envelope values ​​based at least in part on the selected DPD kernel; at least one look-up table (LUT) component, the at least one LUT component coupled to the envelope selection component, the at least one LUT component configured to: receiving the subset of envelope values, and outputting an envelope calculation value based at least in part on the subset of envelope values ​​and the selected DPD kernel; A computational delay line component, the computational delay line component comprising a computational storage component, the computational storage component being configured to store at least the following items: a first plurality of calculated values ​​based at least in part on a first calculation applied to each sample in the plurality of samples; a second plurality of calculated values ​​based at least in part on a second calculation applied to each sample in the plurality of samples; and the plurality of samples, the plurality of samples spanning the duration of time; at least one compute selection component coupled to the compute delay line component and configured to select at least one subset of compute values ​​stored by the compute storage component based at least in part on the selected DPD core; and At least one combiner component is coupled to the at least one calculation selection component and the at least one LUT component, the at least one combiner component being configured to generate output samples based at least in part on combining the envelope calculation value with the at least one calculation value subset.

2. The apparatus of claim 1 , wherein the at least one LUT component comprises a plurality of LUT components, and wherein the apparatus further comprises: at least one LUT selection component, the at least one LUT selection component coupling the plurality of LUT components to the at least one combiner component, the at least one LUT selection component being configured to: selecting a subset of LUT outputs from the plurality of LUT components based at least in part on the selected DPD core; and The LUT output subset is input to the at least one combiner component.

3. The apparatus of claim 1 , wherein the at least one combiner component comprises a first set of combiner components and a second combiner component, and wherein the apparatus further comprises: at least one value selection component coupling the first set of combiner components to the second combiner component, the at least one value selection component being configured to: selecting a subset of combined values ​​output from the first set of combiner components based at least in part on the selected DPD kernel; as well as The combined value subset is input to the second combiner component.

4. The apparatus of claim 1, wherein the envelope selection component comprises a delay line multiplexer selection component.

5. The apparatus of claim 4, wherein the delay line multiplexer selection component comprises: Delay line components; a first multiplexer component coupled to at least one input of the delay line component; and A second multiplexer component is coupled to at least one output of the delay line component.

6. The apparatus of claim 1, wherein the at least one LUT component stores at least one envelope calculation value based at least in part on a piecewise linear envelope function associated with a distortion model.

7. The apparatus of claim 1, wherein the at least one LUT component stores at least one approximate envelope power summation value, the at least one approximate envelope power summation value being based at least in part on an approximation of a signal envelope summation function.

8. The apparatus of claim 1, wherein the plurality of DPD kernels comprises at least one of: Dynamic Skew Reduction (DDR) DPD core, Generalized DDR (GDDR) DPD core, Generalized Memory Polynomial (GMP) DPD kernel, or Decomposition Vector Rotation (DVR) DPD kernel.

9. The apparatus of claim 1, wherein the envelope calculation value comprises an envelope power summation value associated with a Volterra-based DPD kernel.

10. The apparatus of claim 1, wherein the envelope calculation value is based at least in part on a piecewise linear envelope function associated with a Decomposition Vector Rotation (DVR) (DPD) kernel.

11. The apparatus of claim 1 , wherein the envelope selection component comprises a selection circuit configured to select the subset of envelope values ​​based at least in part on at least one of: the timing advance relative to the computation time reference, or The timing delay relative to the computation time reference.

12. The apparatus of claim 1, wherein the computational storage component comprises: a first calculation delay line, the first calculation delay line being used to store the first plurality of calculation values; and A second calculation delay line is provided, wherein the second calculation delay line is configured to store the second plurality of calculation values.

13. The apparatus of claim 1 , wherein the computational selection component comprises a selection logic gate circuit configured to select one or more samples from the plurality of samples, and Wherein the at least one combiner component is configured to generate the output sample based at least in part on the one or more samples.

14. The apparatus of claim 1, wherein the at least one combiner component comprises logic gate circuitry configured to combine the envelope calculation value with the at least one calculation value subset based at least in part on a summation calculation.

15. A method performed by an apparatus, the method comprising: receiving an indication of a selected digital predistortion (DPD) core from a plurality of DPD cores; storing an envelope value associated with samples of an in-phase / quadrature (I / Q) signal based at least in part on an envelope delay line component, the storing comprising storing the envelope value as one of a plurality of envelope values ​​across a duration of time, the plurality of envelope values ​​based at least in part on a plurality of samples associated with the I / Q signal; Based at least in part on the computational storage component, at least the following items are stored: a first calculated value as one of a first plurality of calculated values, the first plurality of calculated values ​​being based at least in part on the plurality of samples, the first calculated value being based at least in part on a first calculation applied to the samples; a second calculated value as one of a second plurality of calculated values, the second plurality of calculated values ​​being based at least in part on the plurality of samples, the second calculated value being based at least in part on a second calculation applied to the samples; and the plurality of samples; selecting a subset of envelope values ​​from the plurality of envelope values ​​based at least in part on the selected DPD kernel; generating an envelope calculation value based at least in part on the subset of envelope values, at least one lookup table (LUT) component, and the selected DPD kernel; selecting at least one subset of computed values ​​stored by the compute storage component based at least in part on the selected DPD kernel; as well as Output samples including digital predistortion are generated based at least in part on combining the envelope calculation value with the at least one subset of calculation values.

16. The method of claim 15, wherein the at least one LUT component comprises a plurality of LUT components, and wherein the method further comprises: selecting, using a LUT selection component, a subset of LUT outputs from the plurality of LUT components based at least in part on the selected DPD core; as well as The LUT output subset is input to at least one combiner component configured to generate at least one combined value based at least in part on the LUT output subset and the at least one calculated value subset.

17. The method of claim 16, wherein the at least one combiner component comprises a plurality of combiner components, wherein the at least one combined value comprises a plurality of combined values, and The generating of the output sample comprises: selecting, using at least one value selection component coupled to the plurality of combiner components, a subset of combined values ​​output from at least some of the plurality of combiner components based at least in part on the selected DPD kernel; as well as The output samples are generated based at least in part on the subset of combined values.

18. The method of claim 15, wherein selecting the subset of envelope values ​​comprises: The subset of envelope values ​​is selected based at least in part on using a delay line multiplexer selection component.

19. The method of claim 18, wherein the delay line multiplexer selection component comprises: Delay line components; a first multiplexer component coupled to at least one input of the delay line component; and A second multiplexer component is coupled to at least one output of the delay line component.

20. The method of claim 15, wherein generating the envelope calculation value comprises: Obtaining from the at least one LUT component at least one of the following: a first envelope calculation value based at least in part on a piecewise linear envelope function associated with a distortion model; or A second envelope calculated value is based at least in part on an approximate envelope power summation calculation.

21. The method of claim 20, wherein the piecewise linear envelope function is associated with a Decomposed Vector Rotation (DVR) (DPD) kernel.

22. The method according to claim 15, further comprising: storing, based at least in part on the calculation storage component, a third calculation value as one of a third plurality of calculation values ​​based at least in part on the plurality of samples, the third calculation value being based at least in part on a third calculation applied to the samples, The first calculation, the second calculation and the third calculation are different from each other.

23. The method of claim 22, wherein x m represents an mth sample in the plurality of samples, wherein the first calculation, the second calculation, or the third calculation comprises at least one of the following: x m ， x* m ， |x m |， x 2 m ， x* 2 m ， |x m | 2 ， x 3 m ， x* 3 m ， |x m | 2 x m ,or |x m | 2 x* m 。 24. The method of claim 15, wherein the at least one LUT component stores an envelope power summation value associated with a Volterra-based DPD kernel as the envelope calculation value.

25. The method of claim 15, wherein the plurality of DPD cores comprises at least one of: Dynamic Skew Reduction (DDR) DPD core, Generalized DDR (GDDR) DPD core, Generalized Memory Polynomial (GMP) DPD kernel, or Decomposition Vector Rotation (DVR) DPD kernel.

26. The method of claim 15, wherein storing the first calculated value or the second calculated value further comprises: storing the first calculated value based at least in part on a first calculation delay line; or The second calculated value is stored based at least in part on a second calculation delay line.

27. The method of claim 15, wherein selecting the at least one subset of calculated values ​​further comprises: At least one sample is selected from the plurality of samples as part of the subset of calculated values ​​based at least in part on the selected DPD kernel.

28. The method of claim 15, wherein the sample is a first sample, wherein the indication is a first indication, wherein the selected DPD kernel is a first selected DPD kernel, and the method further comprises: applying digital predistortion to the first samples based at least in part on the first selected DPD kernel; receiving a second indication of a second selected DPD kernel among the plurality of DPD kernels; as well as The apparatus is reconfigured to apply digital predistortion to second samples based at least in part on the second selected DPD kernel.

29. A transceiver device, the transceiver device comprising: Power amplifier; a digital-to-analog converter (DAC) coupled to the power amplifier; and an adaptive digital predistortion (DPD) device, the adaptive digital predistortion (DPD) device being coupled to the DAC, the adaptive DPD device comprising: an envelope delay line component, the envelope delay line component comprising an envelope storage component configured to store a plurality of envelope values ​​associated with a plurality of samples of an in-phase / quadrature (I / Q) signal; an envelope selection component configured to select a subset of envelope values ​​from the plurality of envelope values; at least one look-up table (LUT) component coupled to the envelope selection component, the at least one LUT component comprising an output mechanism configured to output an envelope calculation value based at least in part on the subset of envelope values; a computational delay line component, the computational delay line component comprising a computational storage component configured to store a plurality of computational values ​​based at least in part on the plurality of samples; at least one compute selection component coupled to the compute delay line component and configured to select at least one subset of compute values ​​stored by the compute storage component based at least in part on a selected DPD core from a plurality of DPD cores; and At least one combiner component is coupled to the at least one calculation selection component and the at least one LUT component, the at least one combiner component being configured to generate output samples based at least in part on combining the envelope calculation value with the at least one calculation value subset.

30. An apparatus, comprising: Memory; and one or more processors coupled to the memory and configured to: receiving an indication of a selected digital predistortion (DPD) core from a plurality of DPD cores; storing an envelope value associated with samples of an in-phase / quadrature (I / Q) signal based at least in part on an envelope delay line component, the storing comprising storing the envelope value as one of a plurality of envelope values ​​across a duration of time, the plurality of envelope values ​​based at least in part on a plurality of samples associated with the I / Q signal; Based at least in part on the computational storage component, at least the following items are stored: a first calculated value as one of a first plurality of calculated values, the first plurality of calculated values ​​being based at least in part on the plurality of samples, the first calculated value being based at least in part on a first calculation applied to the samples; a second calculated value as one of a second plurality of calculated values ​​based at least in part on the plurality of samples, the second calculated value being based at least in part on a second calculation applied to the samples; and the plurality of samples; selecting a subset of envelope values ​​from the plurality of envelope values ​​based at least in part on the selected DPD kernel; generating an envelope calculation value based at least in part on the subset of envelope values, at least one lookup table (LUT) component, and the selected DPD kernel; selecting at least one subset of computed values ​​stored by the compute storage component based at least in part on the selected DPD kernel; as well as Output samples including digital predistortion are generated based at least in part on combining the envelope calculation value with the at least one subset of calculation values.

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