Partial chain reconfiguration for reduced test time

Abstract

The invention relates to partial chain reconfiguration for reducing test time. According to an embodiment, a first aspect relates to a method for testing a scan chain. The method comprises the following steps: segmenting a scan chain into two or more sections; adding a respective multiplexer at the endpoint of each segment, wherein each pair of sequential segments share a common multiplexer therebetween; asserting a selection signal at a selection terminal of the multiplexer such that the relative positions of the two or more segments are positionally rearranged in the rearranged scan chain; generating a test pattern to be transmitted to the input terminals of the rearranged scan chain, the test results being observed at the output of the rearranged scan chain; and determining a fault condition in the rearranged scan chain based on comparing the test result with the expected result.

Description

Technical Field

[0001] The present disclosure relates generally to design for testing (DFT), and in particular embodiments, to partial scan chain reconfiguration for reducing test time. Background Art

[0002] Design for test (DFT) is used in digital logic design to ensure that integrated circuits (ICs) can be effectively tested for functionality and manufacturing defects. DFT techniques are designed to simplify and enhance the testability of ICs, reducing the time and resources required for testing.

[0003] Scan chains are a widely used DFT technique that enables efficient testing of integrated circuits. In a scan chain, additional flip-flops, called scan flip-flops, are inserted into the sequential elements of the design. These scan flip-flops form a shift register that allows the internal state of the design to be captured and observed. Scan chains enable efficient testing of complex sequential circuits by serially shifting in the test pattern and observing the corresponding outputs. This technique improves testability by providing controllability and observability of internal nodes, allowing faulty components to be identified more easily.

[0004] Scan compression technology reduces the test data required to test large, complex designs. As IC complexity increases, the amount of test data required to achieve high fault coverage increases significantly, resulting in longer test times and higher costs. Scan compression technology addresses this challenge by compressing test data and reducing storage and bandwidth requirements during testing.

[0005] Figure 1 An example of a conventional scan compression architecture 100 is illustrated. In the scan compression architecture, decompression circuitry 102 (i.e., decompressor) and compression circuitry 108 (i.e., compressor) work together to reduce the test data required during testing and then expand it back to its original form for analysis. By using decompression circuitry 102 and compression circuitry 108, the amount of test data required to test large and complex designs is significantly reduced. This reduction in test data size results in faster test times, reduced storage requirements, and improved fault detection efficiency without sacrificing fault coverage.

[0006] Decompression circuit 102 receives test input data from limited primary inputs 104. Decompression circuit 102 expands the test input data to be fed to scan chain 106 of the integrated circuit. Compression circuit 108 reduces the size of the output data by encoding the test pattern in a more compact representation. Compression circuit 108 receives the resulting output from scan chain 106 and compresses the data to be observed at limited externally accessible pins 110.

[0007] A "care" bit or "control" bit is a bit or signal whose value is critical to the correct operation of the circuit under test. It represents a signal that needs to be properly propagated and processed for the circuit under test to function as expected. During fault detection, the care bit creates the appropriate conditions to trigger a fault in the faulty circuit and enables it to be observed and monitored.

[0008] On the other hand, a "no-care" bit is a bit or signal whose value is not important to the correct operation of the circuit. It represents a signal that can have any value or don't care value without affecting the overall functionality of the circuit. Don't care bits are often used to reduce the complexity of the testing process by allowing flexibility in the values ​​they can take during testing.

[0009] During fault detection, don't care bits are typically excluded from the fault detection process. Because their values ​​do not affect the behavior of the circuit, potential faults associated with these bits are considered unimportant and do not need to be investigated. Ignoring testing of don't care bits helps simplify the test process and reduce the number of test patterns required to achieve high fault coverage.

[0010] Identifying care and don't care bits is typically performed during the test generation phase, where algorithms and techniques are used to analyze the circuit and determine the importance of each bit or signal. This information is then used during the fault detection phase to focus the test effort on the important parts of the circuit and ignore the unimportant parts.

[0011] In general, the decompression circuit 102 utilizes mathematical formulas, such as linear feedback shift registers (LFSRs), as part of its functionality. LFSRs are commonly used in scan compression architectures to generate and manipulate compressed test patterns. Mathematical formulas, and in particular LFSRs, provide a deterministic and efficient method for generating and manipulating compressed and uncompressed test patterns. By carefully configuring the LFSRs and coordinating their operation within the decompression circuit 102, the original test patterns can be accurately reconstructed, enabling proper testing and fault detection of the circuit under test.

[0012] In some cases, the bits of interest are clustered within several flip-flops in the same or adjacent cycles, which may become challenging for the decompression circuit 102. In other words, the clustering of the bits of interest within several flip-flops may complicate the mathematical equation to be solved by the decompression circuit 102. If the equations to be solved become inefficient, the test tool may discard certain faults from testing or generate inefficient test patterns, resulting in test pattern inflation or a significant increase in test patterns. Therefore, it is desirable to have an improved scan compression architecture that is not subject to the drawbacks of conventional solutions. Summary of the invention

[0013] Generally, technical advantages are achieved by embodiments of the present disclosure, which describe partial scan chain reconfiguration for reducing test time.

[0014] According to an embodiment, a first aspect relates to a method for testing a scan chain. The method includes: segmenting the scan chain into two or more sections; adding a corresponding multiplexer at the end of each section, wherein each pair of sequential sections shares a common multiplexer between; asserting a selection signal at a selection terminal of the multiplexer so that the relative positions of the two or more sections are rearranged in position in a rearranged scan chain; generating a test pattern to be transmitted to an input terminal of the rearranged scan chain, and observing a test result at an output of the rearranged scan chain; and determining a fault condition in the rearranged scan chain based on comparing the test result with an expected result.

[0015] A second aspect relates to a scan chain comprising a plurality of sequential segments and a plurality of multiplexers. Each multiplexer is arranged at an end point of each segment. Each pair of sequential segments shares a common multiplexer between them. Each multiplexer is configured to receive a selection signal so that the relative position of each sequential segment is rearranged in position in a rearranged scan chain. A test pattern is fed to an input terminal of the rearranged scan chain, and a test result is observed at an output end of the rearranged scan chain. A fault condition in the rearranged scan chain is determined based on a comparison between the test result and an expected result.

[0016] A third aspect relates to a test system. The test system includes multiple scan chains. Each alternating scan chain in the multiple scan chains includes multiple sequential segments and multiple multiplexers. Each multiplexer is arranged at the endpoint of each segment. Each pair of sequential segments shares a common multiplexer between them. Each multiplexer is configured to receive a selection signal so that the relative position of each sequential segment is rearranged in position in the rearranged scan chain. A test pattern is fed to the input terminal of the rearranged scan chain, and a test result is observed at the output end of the rearranged scan chain. Based on the comparison between the test result and the expected result, a fault condition in the rearranged scan chain is determined.

[0017] Embodiments may be implemented in hardware, software, or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is an example of a conventional scan-compression architecture;

[0020] Figure 2 is an example of cycle-by-cycle operation of multiple scan chains coupled to common combinational logic;

[0021] Figure 3 is an example of cycle-by-cycle operation of multiple scan chains coupled to a common combinational logic with time domain spacing;

[0022] Figure 4 is an example of cycle-by-cycle operation of a number N of scan chains coupled to a common combinational logic with and without time domain spacing;

[0023] Figure 5 is a block diagram of an embodiment of a reconfigurable scan chain;

[0024] Figure 6 is a block diagram of a first scan chain and a second scan chain compressed into a single output;

[0025] Figure 7 is a block diagram of a first scan chain compressed to a single output and a reconfigured second scan chain;

[0026] Figure 8 is a block diagram of an embodiment corresponding to dynamic reconfiguration of a scan chain with a common test point register;

[0027] Fig. 9 is a block diagram of an embodiment corresponding to dynamic reconfiguration of a scan chain having multiple test point registers; and

[0028] Fig.10 is a flow chart of an embodiment method for implementing a reconfigured scan chain as disclosed herein. DETAILED DESCRIPTION

[0029] The present disclosure provides many applicable inventive concepts that can be implemented in a variety of broad specific contexts. The specific embodiments are merely illustrative to illustrate specific configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments can be combined to form further embodiments.

[0030] The changes or modifications described in one of the embodiments may also be applied to other embodiments. In addition, various changes, substitutions and replacements may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0031] Although the inventive aspects are primarily described in the context of design for test (DFT), it should also be understood that these inventive aspects may also be applied to other aspects of circuit design. Embodiments of the present disclosure are applicable to combined compression and timing compression, and may be applicable to factory testing using, for example, an automatic test pattern generation (ATPG) tool, or to in-field testing using, for example, a logic built-in self-test (LBIST) controller.

[0032] In an embodiment, a system and method are presented that allow a compression tool to resolve controllability and observability formulas while minimizing overhead and increasing design flexibility. Advantageously, the number of test patterns is reduced, test coverage is improved, and test time is reduced. In addition, no intrusive test point insertion is required to implement the disclosed embodiments. In an embodiment, a subset of scan chains with common decompression and compression circuits are reconfigured by distributing care bits across the time domain. These and other details are further detailed below.

[0033] Figure 2 An example of cycle-by-cycle operation of multiple scan chains 202, 204, 206 coupled to a common combinational logic 208 is shown. As shown, Figure 2 Only three scan chains are shown in FIG. 2 : a first scan chain 202, a second scan chain 204, and a third scan chain 206. It should be understood that the number of scan chains is non-limiting.

[0034] Combinatorial logic 208 represents a logic circuit that produces an output based on the current input. Unlike sequential logic, which depends on the current input and past states, combinatorial logic 208 has no memory or feedback, making its behavior completely determined by the current input values.

[0035] Combinatorial logic 208 can be constructed by interconnecting basic logic gates to perform more complex operations. Combinatorial logic 208 may include one or more logic gates, such as AND, OR, NOT, NAND, NOR, and XOR. These gates receive one or more input signals and generate a single output signal based on the logic operation specified by the gate. Combinatorial logic 208 can be used in a variety of digital systems, including arithmetic circuits (e.g., adders, subtractors), multiplexers, demultiplexers, encoders, decoders, and many other applications.

[0036] When the circuit is in scan mode, the functional operation of the design is suspended, the scan chain is activated, and the test pattern is applied. During the shift cycle, the test pattern bits are serially shifted into the scan chain, loading the test pattern into the internal trigger. Typically, after the shift-in process, the circuit switches back to "functional mode", in which the test pattern propagates through, for example, combinational logic 208 and sequential elements. In order to observe the response of the circuit to the test pattern, the circuit switches to "scan mode" again during the shift cycle. The output response is then serially shifted out of the scan chain for analysis. At each cycle of the shift cycle 210, the complete test pattern is shifted in or out of each scan chain 202, 204, 206. The number of shift cycles depends on the length of the scan chain 202, 204, 206, which in turn depends on the number of triggers inserted in the design for scan testing each scan chain 202, 204, 206.

[0037] Depending on the operation of the scan chains, during various shift cycles 210, the flip-flops of the scan chains 202, 204, 206 may provide inputs to the combinatorial logic 208. Figure 2 In FIG. 2 , the shift cycles of a representative scan chain providing input to the combinatorial logic 208 are represented as hashed scan units. Figure 2 In the example of , the first scan chain 202 provides inputs at shift cycles three, five and fourteen to drive the combinational logic 208, the second scan chain 204 provides inputs at shift cycles three and seventeen to drive the combinational logic 208, and the scan chain 206 provides inputs at shift cycles one and fifteen to drive the combinational logic 208.

[0038] Therefore, in Figure 2 In the example of FIG. 1 , the first scan chain 202 and the second scan chain 204 drive the combinational logic 208 at the same third shift cycle, and the first scan chain 202 and the third scan chain 206 drive the combinational logic 208 at adjacent fourteenth and fifteenth shift cycles.

[0039] Here, "combinatorial depth" refers to the longest path of logic gates that a signal must pass through within a combinatorial logic circuit from its input to its output. The combinatorial depth determines the maximum propagation delay of the circuit and affects its overall performance. In general, the combinatorial depth directly affects the speed of the circuit, representing the worst-case time delay for a signal to propagate through the combinatorial logic and produce an output. In embodiments where the combinatorial logic 208 has a high combinatorial depth, test coverage may be affected; particularly when scan chains drive the combinatorial logic 208 in the same or adjacent shift cycles.

[0040] exist Figure 2 In the example of FIG. 2 , the first scan chain 202 , the second scan chain 204 , and the third scan chain 26 drive the same combinatorial logic 208 , and are configured as three adjacent scan chains.

[0041] Generally speaking, in conventional scan splicing, the test tool places the related flip-flops driving the same combinational logic into a single scan chain or two or three adjacent scan chains, depending on the associated combinational depth. The bits of interest of these adjacent scan chains are located at similar positions, so they drive the same combinational logic 208 in the same shift cycle.

[0042] Aspects of the present disclosure advantageously address this problem by dispersing the bits of interest across the time domain. In an embodiment, one or more bits of interest are rearranged by rearranging scan chains using time domain spacing. In some embodiments, alternative scan chains are reconfigured to disperse the bits of interest. In an embodiment, test patterns are generated for the original and modified scan chain configurations. Combining these test patterns improves test coverage for hard-to-detect faults while reducing the number of overall test patterns.

[0043] Advantageously, the direction of test pattern insertion remains the same (i.e., the scan direction is preserved) and is not reversed. Also, in the disclosed embodiments, the scan chain length is not modified. The shift order is reconfigured in several scan chains to reduce test time and minimize test patterns. Furthermore, no additional compression engine is required when implementing the disclosed embodiments (e.g., different scan chains are not reconfigured with different compression ratios).

[0044] The embodiments of the present disclosure do not affect functional paths, require minimal routing changes, reduce the number of test patterns, improve test scan coverage, reduce test time, and can be extended to any compressed design or LBIST design.

[0045] Figure 3 An example of cycle-by-cycle operation of multiple scan chains 202, 304, 206 coupled to a common combinatorial logic 208 with time domain spacing is shown. The first scan chain 202 and the third scan chain 206 are maintained as Figure 2 The original arrangement shown in FIG. 1 is shown in FIG. 2 , and the second scan chain 304 is Figure 2 The reconfigured scan chain arrangement of the second scan chain 204 in FIG.

[0046] In some embodiments where the number of scan chains is equal to N, each odd scan chain remains unchanged while each even scan chain is reconfigured. In some embodiments, each odd scan chain is reconfigured while each even scan chain remains unchanged. It should be noted that the selection of scan chains to be reconfigured is non-limiting and any arrangement is contemplated in embodiments.

[0047] Selective (non-universal) reconfiguration of scan chains (e.g., alternating scan chain selection) allows the relative positioning of the care bits to be spread across the scan chains; otherwise, the relative positioning may cause the care bits to remain the same relative to each other (e.g., reconfiguring both the first scan chain 202 and the second scan chain 204).

[0048] In an embodiment, the second scan chain 204 is first divided into a first section 308 and a second section 310. In an embodiment, the first section 308 and the second section 310 are sequential. In an embodiment, the first section 308 and the second section 310 cover the entire scan chain of the second scan chain 204.

[0049] The second scan chain 304 is a rearrangement of the second scan chain 204, wherein the placement of the first segment 308 is switched (i.e., swapped) with the placement of the second segment 310. Thus, where the second scan chain 204 includes the first segment 308 followed by the second segment 310, the second scan chain 304 includes the second segment 310 followed by the first segment 308. Likewise, where more than three scan chains are used, the scan chains selected to be reconfigured are rearranged by segmenting the scan chains into first segments and second segments and rearranging the positions of the segments.

[0050] The rearrangement of the second scan chain 304 relative to the second chain 204 (i.e., segmentation and swapping the positions of the segments) corresponds to the change of the positions of the triggers in the second scan chain 304 and the diffusion of the concerned bits across the time domain. Therefore, before this, the first scan chain 202 and the second scan chain 204 drive the combinational logic 208 at the same third shift cycle, while in the rearranged second scan chain 304, the first scan chain 202 and the second scan chain 304 drive the combinational logic 208 at different shift cycles (i.e., for different scan chains, the concerned bits are not in the same cycle), which helps the test tool to effectively generate test patterns.

[0051] In an embodiment, the first segment 308 and the second segment 310 are arranged to have the same number of triggers (i.e., halfway points). In other embodiments, the first segment 308 and the second segment 310 are arranged to have different numbers of triggers (i.e., the points for segmentation are skewed toward the start or end of the scan chain).

[0052] Figure 4 An example of cycle-by-cycle operation of a number N of scan chains coupled to a common combinatorial logic 208 with and without time domain spacing is shown. A first group of scan chains 400 includes a number N of scan chains 402a, 402b, 402c, ..., and 402n. A second group of scan chains 450 includes a number N of scan chains 402a, 452b, 402c, ..., and 402n - where N is assumed to be an odd number.

[0053] exist Figure 4 In the example of FIG. 4 , the second set of scan chains 450 includes a reconfigured arrangement (e.g., scan chain 452 b is a re-arranged scan chain 402 b) that is a subset of the first set of scan chains 400. In the second scan chains 450, each alternating scan chain (here, an even number) in the first scan chain 400 is (i) segmented into a first segment and a second segment, and (ii) swapped in position (i.e., the first segment is placed after the second segment).

[0054] In other embodiments, each odd scan chain in the first scan chain 400 is rearranged. Therefore, the rearrangement of the scan chain subset in the first scan chain 400 is non-limiting. In addition, segmenting the reconfigured scan chain into more than two segments is similarly considered in other embodiments. For example, the scan chain subset in the scan chain 400 can be segmented into M segments (where M is equal to or greater than two), which can be rearranged based on a predetermined or adjustable basis to reach the second scan chain 450.

[0055] Figure 5 1 shows a block diagram of an embodiment of a reconfigurable scan chain 500. The scan chain 500 includes a first segment 502, a second segment 504, a start multiplexer 506, a second multiplexer 508, and an end multiplexer 510, which may or may not be arranged as shown. In an embodiment, each alternating scan chain is reconfigured, such as Figure 5 In an embodiment, the multiplexer is arranged at a segment boundary (eg, the beginning, the end, etc.).

[0056] In an embodiment, the scan chain 500 is segmented into two sections: (i) a first section 502 and (ii) a second section 504, wherein the second section 504 is a sequential section of the first section 502. A start multiplexer 506 is arranged at the test scan entrance, an end multiplexer 510 is arranged at the detection scan exit, and a second multiplexer 508 is arranged at the end of the first section 502 and the start of the second section 504.

[0057] The "scan in" signal (SCAN_IN) is an input signal that loads a test pattern into the scan chain 500. The "scan in" signal is used to shift a test pattern or test data into the scan chain 500 during the test process. Normal operation is suspended to test the circuit, and the circuit is placed in "scan mode". In this mode, the scan chain 500 is activated and the scan in signal is applied. The test pattern is serially loaded into the scan chain 500 one bit at a time by shifting the data through the scan flip-flop. Each test pattern represents a specific group of input conditions, which is designed to run various functionalities and paths in the circuit to ensure comprehensive testing. Once the test pattern is loaded into the scan chain, the circuit switches back to "functional mode" for testing. The test pattern propagates through the combinational logic and sequential elements, and the corresponding output is shifted out of the scan chain using the "scan out" signal (SCAN_OUT) for analysis and comparison with the expected results.

[0058] A first terminal of the start multiplexer 506 and a first terminal of the second multiplexer 508 are coupled to a scan input signal (SCAN_IN). A second terminal of the start multiplexer 506 is coupled to the output of the second segment 504. A second terminal of the second multiplexer 508 is coupled to the output of the first segment 502. A first terminal of the end multiplexer 510 is coupled to the output of the first segment 502. A second terminal of the end multiplexer 510 is coupled to the output of the second segment 504.

[0059] Each of the starting multiplexer 506, the second multiplexer 508, and the end multiplexer 510 includes a selection terminal coupled to a selection line 512, which receives a selection signal from a common test point register 514. The test point register 514 is accessible by a test tool. It allows the test tool to forward the value at the first terminal or the second terminal of each of the starting multiplexer 506, the second multiplexer 508, and the end multiplexer 510 to its corresponding output terminal according to the value of the selection signal. It should be understood that the use of the common test point register 514 is non-limiting, and in other embodiments, additional test point registers may be used.

[0060] In the default configuration (indicated as solid lines between components), the test tool sets the select signal to forward the test pattern to the first section 502. The output of the first section 502 is then forwarded to the input of the second section 504. Finally, the resulting output from the second section 504 is observed at the output of the scan chain 500.

[0061] In a reconfigured configuration (e.g., scan chain 452b) (represented as dashed lines between components), the test tool sets the select signal so that the test pattern is first forwarded to the second section 504. Then, the output of the second section 504 is forwarded to the input of the first section 502. Finally, the resulting output of the first section 502 is observed at the output of the scan chain 500.

[0062] It should be noted that although the scan chain 500 is shown as having two sections, in other embodiments, the number of sections may be equal to M, where M is an integer greater than one. In such an embodiment, the scan chain will include a start multiplexer, an end multiplexer, and a corresponding multiplexer at the end of each section (count M-1). The test tool is then configured to provide a select signal to the M+1 multiplexer to arrange the scan chain 500 in the appropriate reconfigured arrangement.

[0063] Figure 6 A block diagram of a first scan chain 602 and a second scan chain 604 compressed to a single output is shown. In some cases, it is known a priori that when observing or capturing the response of a test pattern forwarded through a flip-flop in a scan chain in a circuit, the response is uncertain. This uncertain response may be the result of a timing violation, etc. The uncertain response is often referred to as an "X", meaning that we cannot state with certainty that the value is "0" or "1". Typically, when the test pattern is generated, this uncertain response is known, and the test tool knows that it does not need to compare the response of the corresponding cycle with the expected result.

[0064] A common problem occurs when the outputs of multiple scan chains are compressed or XORed into a single pin by the compression circuit 108. In this case, valid data may be captured on the second scan chain 604 while X-type data may be captured on the first scan chain 602. The output of the compression or XOR operation is X-type because one of the inputs to the XOR logic gate 606 is uncertain. Unfortunately, the valid data captured on the second scan chain 604 is therefore masked due to the uncertain data on the first scan chain 602.

[0065] Figure 7A block diagram of a first scan chain 602 compressed to a single output and a reconfigured second scan chain 704 is shown. Advantageously, the second scan chain 704 is reconfigured by (i) first segmenting the second scan chain 604 and (ii) swapping segments of the second scan chain 604 to form the second scan chain 704, whereby the position of the X-type data relative to the second chain 604 is rearranged. Therefore, the period in which the output of the first scan chain 602 is indeterminate is no longer in the same period as the valid output of the second chain 604. Advantageously, the valid data captured on the second scan chain 704 is therefore available at the output of the XOR logic gate 706.

[0066] Advantageously, by segmenting the scan chains and swapping the positions of the segments relative to each other, we benefit from (i) preventing different scan chains from driving common combinational logic (i.e., improved controllability) and (ii) preventing masking of valid data from another scan chain when one scan chain has an uncertain result (i.e., improved observability).

[0067] Figure 8 A block diagram of an embodiment corresponding to the dynamic reconfiguration of the scan chain 800 is shown, the embodiment having a common test point register 818. As shown, the select terminals of the start multiplexer 812, the second multiplexer 814, and the end multiplexer 816 of all the alternate scan chains (e.g., the first scan chain 802, the third scan chain 806, and the fifth scan chain 810) are coupled to the common test point register 818. As shown, each of the other alternate scan chains (e.g., the second scan chain 804 and the fourth scan chain 808) is in a default configuration.

[0068] In an embodiment, the test tool provides a select signal through the test point register 818 to reorganize each alternate scan chain. In an embodiment, the select signal is driven by a flip-flop. In an embodiment, the flip-flop is part of the scan chain and maintains a constant value during the scan shift. In an embodiment, the test tool loads the test pattern for the scan chain. It also provides a select signal to the multiplexer to appropriately reconfigure the selected scan chain corresponding to the test pattern tested.

[0069] Advantageously, the test tool has the flexibility to rearrange the select scan chains based on the test pattern by selecting appropriate select signals. Thus, the test tool can intelligently rearrange the select scan chains based on the test pattern.

[0070] therefore, Figure 8 An embodiment is shown in which the scan chains to be reconfigured are controlled by common test point registers 818. An advantage of having common test point registers 818 is that it simplifies the test setup.

[0071] Fig. 9A block diagram of an embodiment corresponding to dynamic reconfiguration of a scan chain 900 is shown, with a plurality of test point registers 916, 918, and 920. As shown, the select terminals of the start multiplexer 910, the second multiplexer 912, and the end multiplexer 914 of each scan chain are coupled to the corresponding test point registers 916, 918, and 920.

[0072] In an embodiment, the first scan chain 902 and the fourth scan chain 908 can be rearranged by selectively asserting a first selection signal at the first test point register 916, the second scan chain 904 can be rearranged by selectively asserting a second selection signal at the second test point register 918, and the third scan chain 906 can be rearranged by selectively asserting a third selection signal at the third test point register 920.

[0073] In an embodiment, each scan chain to be rearranged includes independent test point registers (e.g., the second scan chain 904 and the third scan chain 906). In an embodiment, a subset of the scan chains to be rearranged includes common test point registers (e.g., the first scan chain 902 and the fourth scan chain 908).

[0074] Therefore, if Figure 8 and Fig. 9 As shown in , achieving controllability via test point registers when rearranging scan chains is non-limiting. In various embodiments, one, a subset, or all of the scan chains can be coupled to test point registers. In some embodiments, the test point registers are common to two or more scan chains. In some embodiments, each scan chain includes an independent test point register for controllability.

[0075] In an embodiment, a test tool may selectively assert select signals on the one or more test point registers based on a desired configuration and rearrange one or more scan chains as described above to improve observability and controllability.

[0076] In an embodiment, the select signal asserted at the test point register is based on static select logic (i.e., the same select signal is asserted for the test pattern to be tested). Therefore, the configuration does not suffer from timing impacts and does not require critical timing interfaces or critical timing paths, for example, to synchronize the select signal during circuit testing based on the disclosed embodiments. It should be noted that the test tool can assert different select signals at the test point register for different test patterns; however, the select signal does not need to be modified when testing the circuit using a single test pattern.

[0077] In an embodiment, the values ​​of the select signals at the one or more test point registers are determined by the test tool based on the test pattern.

[0078] In an embodiment, scan chain reordering can be performed between and across reconfigured segments. Since scan chains can run across flip-flops on the physical layout of the circuit under test, scan chains can be reordered during the physical routing stage of the testability design. In an embodiment, scan chain reordering is based on the reconfigured scan chains, which can simplify the test process.

[0079] In an embodiment, a test tool generates a single set of test patterns, the set of test patterns including a first test pattern based on an original arrangement of scan chains and a second test pattern based on a reconfigured arrangement of selected scan chains. The test tool can dynamically select between the first test pattern and the second test pattern. In an embodiment, the test tool can dynamically determine which of the first test pattern or the second test pattern to use based on, for example, increased test coverage or test efficiency, etc., by using appropriate data to load test points during each pattern.

[0080] Fig.10 Shown is a flow chart of an embodiment method 1000 of a scan chain realizing the reconfiguration disclosed herein. Although the method described below is applicable to a single scan chain, it should be understood that the method can be extended to two or more scan chains. In an embodiment, each alternate scan chain coupled to a common compression and decompression circuit is arranged as described herein. In an embodiment, a test pattern is provided by a test tool. In other embodiments, a test pattern is provided by a LBIST controller.

[0081] In step 1002, the scan chain is segmented into two or more segments. In some embodiments, the segments have the same length. In some embodiments, the segments have different lengths. In an embodiment, the scan chain is segmented into two segments of equal length. In some embodiments, every other scan chain (i.e., alternating scan chains) is segmented. A corresponding multiplexer is arranged at the endpoint of each scan chain segment. For example, in a scan chain with two segments, the starting point multiplexer 506 includes a first input configured to receive a test pattern. The starting point multiplexer 506 output is coupled to the first scan chain segment input. The second input of the starting point multiplexer 506 is coupled to the output of the second segment (continuous with the first segment). The output of the first segment is coupled to the first input of the second multiplexer 508. The second multiplexer 508 output is coupled to the second scan chain segment input. The second input of the second multiplexer 508 is configured to receive the test pattern. The destination multiplexer 510 is configured to have a first input coupled to the output of the second segment and a second input coupled to the output of the first segment. Output of the destination multiplexer 510 .

[0082] In step 1004, the test tool controls different sections using a plurality of test points.

[0083] In step 1006, the test tool generates a single test pattern that includes (i) a first test pattern associated with the original configuration of the scan chain (which corresponds to the second segment following the first segment), and (ii) a second test pattern associated with the reconfigured scan chain (which corresponds to the first segment following the second segment).

[0084] In step 1008, the test tool generates a selection signal at the test point register, and the selection signal of the test point register is coupled to the selection terminals of the starting multiplexer 506, the second multiplexer 508 and the end multiplexer 510. The test tool dynamically selects which input of the corresponding multiplexer is forwarded to its output by asserting the selection signal. In an embodiment, each test point register is associated with a corresponding multiplexer. In an embodiment, the test point register is common to all multiplexers in the scan chain to be reconfigured. In an embodiment, the test tool generates a corresponding selection signal to each test point register. In an embodiment, different scan chains can share a common test point register. In other embodiments, different scan chains can have different test point registers.

[0085] At step 1010, the test tool selects between one of the first pattern or the second pattern of the single test pattern and a select signal based on the arrangement of the scan chain. The output signal at the destination multiplexer 510 is observed and compared to the expected result to determine a fault in the scan chain.

[0086] It is worth noting that all steps outlined in the flowchart are not necessary, but may be optional. In addition, it is similarly possible to consider changing the arrangement of steps, removing one or more steps and path connections, and adding steps and path connections.

[0087] A first aspect relates to a method for testing a scan chain. The method comprises: segmenting the scan chain into two or more segments; adding a corresponding multiplexer at the endpoint of each segment, wherein each pair of sequential segments shares a common multiplexer between; asserting a selection signal at a selection terminal of the multiplexer so that the relative positions of the two or more segments in the rearranged scan chain are rearranged in position; generating a test pattern to be transmitted to an input terminal of the rearranged scan chain, and observing a test result at an output of the rearranged scan chain; and determining a fault condition in the rearranged scan chain based on comparing the test result with an expected result.

[0088] In a first implementation of the method according to the first aspect, the scan chain is segmented into a first segment and a second segment sequentially to each other. In the rearranged scan chain, the position of the first segment is sequentially located after the position of the second segment.

[0089] In a second implementation of the method according to the first aspect, or in any of the foregoing implementations of the first aspect, the first segment and the second segment are equal in length.

[0090] In a third implementation of the method according to the first aspect or any of the foregoing implementations of the first aspect, the scan chain is a first scan chain. The method further includes retaining an original configuration of a second scan chain adjacent to the first scan chain in response to the first scan chain being rearranged.

[0091] In a fourth implementation of the method according to the first aspect, or any of the foregoing implementations of the first aspect, the selection signal is a first selection signal. The method further comprises: segmenting a third scan chain adjacent to the second scan chain into two or more segments; adding a multiplexer at an end point of each segment in the third scan chain, wherein each sequential segment in the third scan chain shares a common multiplexer between; asserting a second selection signal at a selection terminal of the one or more multiplexers in the third scan chain, so that in the rearranged third scan chain, the relative positions of the two or more segments of the third scan chain are rearranged in position; generating a second test pattern to be transmitted to an input terminal of the rearranged third scan chain, and observing a test result at an output end of the rearranged third scan chain; and determining a fault condition in the rearranged third scan chain based on a comparison between the test result and an expected result of the rearranged third scan chain.

[0092] In a fifth implementation of the method according to the first aspect, or any of the foregoing implementations of the first aspect, the first selection signal and the second selection signal are the same selection signal and are asserted at a common test point register.

[0093] In a sixth implementation of the method according to the first aspect, or any of the foregoing implementations of the first aspect, the first scan chain, the second scan chain, and the third scan chain share a common compression circuit, a common decompression circuit, a common combinational logic, or a combination thereof.

[0094] A second aspect relates to a scan chain comprising a plurality of sequential segments and a plurality of multiplexers. Each multiplexer is arranged at an end point of each segment. Each pair of sequential segments shares a common multiplexer between them. Each multiplexer is configured to receive a selection signal so that in a rearranged scan chain, the relative position of each sequential segment is rearranged in position. A test pattern is fed to an input terminal of the rearranged scan chain, and a test result is observed at an output end of the rearranged scan chain. A fault condition in the rearranged scan chain is determined based on a comparison between the test result and an expected result.

[0095] In a first implementation of the scan chain according to the second aspect, the scan chain is segmented into a first segment and a second segment sequentially arranged with respect to each other. In the rearranged scan chain, the position of the first segment is sequentially located after the position of the second segment.

[0096] In a second implementation of the scan chain according to the second aspect, or in the scan chain in any of the foregoing implementations of the second aspect, the first segment and the second segment have the same length.

[0097] In a third implementation of the scan chain according to the second aspect, or in any of the foregoing implementations of the second aspect, the first input terminal of the first multiplexer is configured to receive a test pattern. The second input terminal of the first multiplexer is configured to receive an output signal from the second segment. The output terminal of the first multiplexer is fed to the first segment. The first input terminal of the second multiplexer is configured to receive an output signal from the first segment. The second input terminal of the second multiplexer is configured to receive a test pattern. The output terminal of the second multiplexer is fed to the second segment. The first input terminal of the third multiplexer is configured to receive an output signal from the first segment, the second input terminal of the third multiplexer is configured to receive an output signal from the second segment, and the output terminal of the third multiplexer is observed to determine a fault condition.

[0098] In a third implementation of the scan chain according to the second aspect, or in any previous implementation of the second aspect, the scan chain is a first scan chain. A second scan chain adjacent to the first scan chain maintains an original configuration in response to the first scan chain being rearranged.

[0099] In a fourth implementation of the scan chain according to the second aspect, or in any previous implementation of the second aspect, the selection signal is a first selection signal. The third scan chain shares a common compression circuit, a common decompression circuit, a common combinational logic, or a combination thereof with the first scan chain and the second scan chain. The third scan chain includes a second plurality of sequential segments and a second plurality of multiplexers. Each multiplexer in the second plurality of multiplexers is arranged at an end point of each segment in the second plurality of sequential segments. Each pair of sequential segments in the second plurality of sequential segments shares a common multiplexer between them. Each multiplexer in the second plurality of multiplexers is configured to receive a second selection signal so that in a second rearranged scan chain, the relative position of each sequential segment in the second plurality of sequential segments is rearranged in position. A second test pattern is fed to an input terminal of the second rearranged scan chain, and a second test result is observed at an output end of the second rearranged scan chain. A second fault condition is determined in the second rearranged scan chain based on a comparison between the second test result and a second expected result.

[0100] In a fifth implementation of the scan chain according to the second aspect, or in any of the foregoing implementations of the second aspect, the first selection signal and the second selection signal are the same selection signal and are asserted at a common test point register.

[0101] A third aspect relates to a test system. The test system includes a plurality of scan chains. Each alternating scan chain in the plurality of scan chains includes a plurality of sequential segments and a plurality of multiplexers. Each multiplexer is arranged at an end point of each segment. Each pair of sequential segments shares a common multiplexer between them. Each multiplexer is configured to receive a selection signal so that in a rearranged scan chain, the relative position of each sequential segment is rearranged in position. A test pattern is fed to an input terminal of the rearranged scan chain, and a test result is observed at an output end of the rearranged scan chain. A fault condition is determined in the rearranged scan chain based on a comparison between the test result and an expected result.

[0102] In a first implementation of the test system according to the third aspect, the test system includes a compression circuit, a decompression circuit and a combinational logic. A scan chain in the plurality of scan chains is configured to receive a test signal via the decompression circuit and output a test result via the compression circuit. Two or more scan chains in the plurality of scan chains drive the combinational logic.

[0103] In a second implementation of the test system according to the third aspect, or in any of the foregoing implementations of the third aspect, in a non-rearranged configuration of each alternating scan chain, at least one pair of adjacent scan chains drives a common combinational logic at the same shift cycle. In a rearranged configuration of each alternating scan chain, the at least one pair of adjacent scan chains drives the common combinational logic at different shift cycles.

[0104] In a third implementation of the test system according to the third aspect, or in any of the foregoing implementations of the third aspect, each scan chain is segmented into a first segment and a second segment sequentially to each other. In each rearranged scan chain, the position of the associated first segment is sequentially located after the position of the associated second segment.

[0105] In a fourth implementation of the test system according to the third aspect, or in any of the foregoing implementations of the third aspect, in each alternating scan chain, the first input terminal of each first multiplexer is configured to receive a test pattern, the second input terminal of each first multiplexer is configured to receive an output signal from the second segment, and the output terminal of each first multiplexer is fed to the first segment. The first input terminal of each second multiplexer is configured to receive an output signal from the first segment, the second input terminal of each second multiplexer is configured to receive a test pattern, and the output terminal of each second multiplexer is fed to the second segment. The first input terminal of each third multiplexer is configured to receive an output signal from the first segment, the second input terminal of each third multiplexer is configured to receive an output signal from the second segment, and the output terminal of each third multiplexer is observed to determine a fault condition.

[0106] In a fifth implementation of the test system according to the third aspect, or in any of the preceding implementations of the third aspect, a selection terminal of each multiplexer is coupled to a common test point register.

[0107] Although the present description has been described in detail, it should be understood that various changes, substitutions and alternatives may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. In the various drawings, the same elements are indicated by the same reference numerals. In addition, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, because those of ordinary skill in the art will readily understand from the present disclosure that processes, machines, manufactured products, material components, devices, methods or steps currently existing or to be developed later may perform functions substantially the same as the corresponding embodiments described herein or achieve substantially the same results. Therefore, the appended claims are intended to include these processes, machines, manufactured products, material components, devices, methods or steps within their scope.

[0108] Accordingly, the specification and drawings are to be regarded as illustrative only of the present disclosure as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents falling within the scope of the present disclosure.

Claims

1. A method for testing a scan chain, the method comprising: segmenting the scan chain into two or more segments; adding corresponding multiplexers at the endpoints of each segment, wherein each pair of sequential segments shares a common multiplexer in between; asserting a select signal at a select terminal of the multiplexer such that relative positions of the two or more sections in the rearranged scan chain are positionally rearranged; generating a test pattern to be transmitted to an input terminal of the rearranged scan chain and observing a test result at an output terminal of the rearranged scan chain; as well as A fault condition in the rearranged scan chain is determined based on comparing the test result with an expected result.

2. The method according to claim 1, wherein the scan chain is segmented into a first segment and a second segment sequential to each other, and wherein, In the rearranged scan chain, the position of the first section is sequentially located after the position of the second section. The method of claim 2 , wherein the first section and the second section have the same length. 4 . The method according to claim 1 , wherein the scan chain is a first scan chain, the method further comprising retaining an original configuration of a second scan chain adjacent to the first scan chain in response to the first scan chain being rearranged.

5. The method according to claim 4, wherein the selection signal is a first selection signal, the method further comprising: segmenting a third scan chain adjacent to the second scan chain into two or more segments; adding multiplexers at endpoints of each segment in the third scan chain, wherein each sequential segment in the third scan chain shares a common multiplexer therebetween; asserting a second select signal at a select terminal of the one or more multiplexers in the third scan chain such that relative positions of the two or more sections of the third scan chain are positionally rearranged in the rearranged third scan chain; generating a second test pattern to be transmitted to an input terminal of the rearranged third scan chain, and observing a test result at an output terminal of the rearranged third scan chain; as well as Based on a comparison between the test result and an expected result for the rearranged third scan chain, a fault condition in the rearranged third scan chain is determined. 6 . The method of claim 5 , wherein the first select signal and the second select signal are the same select signal and are asserted at a common test point register.

7. The method of claim 5, wherein the first scan chain, the second scan chain, and the third scan chain share a common compression circuit, a common decompression circuit, a common combinational logic, or a combination thereof.

8. A scan chain, comprising: Multiple sequential segments; as well as a plurality of multiplexers, each multiplexer being arranged at an end point of each segment, wherein each pair of sequential segments shares a common multiplexer therebetween, each multiplexer being configured to receive a selection signal such that the relative position of each sequential segment in the rearranged scan chain is positionally rearranged, wherein a test pattern is fed to an input terminal of the rearranged scan chain, a test result is observed at an output terminal of the rearranged scan chain, and Wherein, a fault condition in the rearranged scan chain is determined based on a comparison between the test result and an expected result.

9. The scan chain according to claim 8, wherein the scan chain is segmented into a first segment and a second segment sequential to each other, and wherein, In the rearranged scan chain, the position of the first section is sequentially located after the position of the second section.

10. The scan chain of claim 9, wherein the first segment and the second segment have the same length.

11. The scan chain of claim 9, wherein a first input terminal of the first multiplexer is configured to receive a test pattern, a second input terminal of the first multiplexer is configured to receive an output signal from the second segment, and an output terminal of the first multiplexer is fed to the first segment, wherein a first input terminal of the second multiplexer is configured to receive an output signal from the first segment, a second input terminal of the second multiplexer is configured to receive a test pattern, and an output terminal of the second multiplexer is fed to the second segment, wherein a first input terminal of the third multiplexer is configured to receive an output signal from the first segment, a second input terminal of the third multiplexer is configured to receive an output signal from the second segment, and an output terminal of the third multiplexer is observed to determine a fault condition. 12 . The scan chain of claim 8 , wherein the scan chain is a first scan chain, and wherein a second scan chain adjacent to the first scan chain maintains an original configuration in response to the first scan chain being rearranged.

13. The scan chain of claim 12, wherein the selection signal is a first selection signal, wherein the third scan chain shares a common compression circuit, a common decompression circuit, a common combinational logic, or a combination thereof with the first scan chain and the second scan chain, and wherein the third scan chain comprises: a second plurality of sequential segments; as well as a second plurality of multiplexers, each of the second plurality of multiplexers being arranged at an endpoint of each of the second plurality of sequential segments, wherein each pair of sequential segments in the second plurality of sequential segments shares a common multiplexer therebetween, each of the second plurality of multiplexers being configured to receive a second selection signal such that a relative position of each of the second plurality of sequential segments is positionally rearranged in a second rearranged scan chain. wherein a second test pattern is fed to an input terminal of the second rearranged scan chain, a second test result is observed at an output of the second rearranged scan chain, and Wherein, a second fault condition in the second rearranged scan chain is determined based on a comparison between the second test result and a second expected result.

14. The scan chain of claim 13, wherein the first selection signal and the second selection signal are the same selection signal and are asserted at a common test point register.

15. A testing system comprising: A plurality of scan chains, wherein each alternating scan chain in the plurality of scan chains comprises: Multiple sequential segments, and a plurality of multiplexers, each multiplexer being arranged at an end point of each segment, wherein each pair of sequential segments shares a common multiplexer therebetween, each multiplexer being configured to receive a selection signal such that the relative position of each sequential segment is positionally rearranged in the rearranged scan chain, wherein a test pattern is fed to an input terminal of the rearranged scan chain, a test result is observed at an output of the rearranged scan chain, and Wherein, a fault condition in the rearranged scan chain is determined based on a comparison between the test result and an expected result.

16. The test system according to claim 15, further comprising a compression circuit, a decompression circuit and a combinational logic, wherein a scan chain in the plurality of scan chains is configured to receive a test signal via the decompression circuit and output a test result via the compression circuit, and wherein, Two or more scan chains of the plurality of scan chains drive the combinatorial logic.

17. The test system according to claim 16, wherein: In the non-rearranged configuration of each alternating scan chain, at least one pair of adjacent scan chains drives a common combinatorial logic at the same shift period, and wherein, in the rearranged configuration of each alternating scan chain, the at least one pair of adjacent scan chains drives the common combinatorial logic at different shift periods.

18. The test system according to claim 15, wherein each scan chain is segmented into a first section and a second section sequential to each other, and wherein, In each rearranged scan chain, the position of the associated first segment is sequentially located after the position of the associated second segment.

19. The test system according to claim 18, wherein: In each alternating scan chain, a first input terminal of each first multiplexer is configured to receive a test pattern, a second input terminal of each first multiplexer is configured to receive an output signal from the second segment, and an output terminal of each first multiplexer is fed to the first segment, wherein a first input terminal of each second multiplexer is configured to receive an output signal from the first segment, a second input terminal of each second multiplexer is configured to receive a test pattern, and an output terminal of each second multiplexer is fed to the second segment, and wherein a first input terminal of each third multiplexer is configured to receive an output signal from the first segment, a second input terminal of each third multiplexer is configured to receive an output signal from the second segment, and an output terminal of each third multiplexer is observed to determine a fault condition.

20. The test system of claim 15, wherein a select terminal of each multiplexer is coupled to a common test point register.

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