High-efficiency solid state disk master control chip

Abstract

The invention discloses a high-efficiency solid state disk master control chip, which relates to the technical field of solid state disk master control chips, and comprises a central processing unit and a flash memory controller, the flash memory controller comprises a communication module, a flash memory control circuit and a comparison circuit; in the invention, in performance, data bus and instruction processing are optimized, read-write is accelerated, delay is reduced, and high-speed storage requirements are met; in the aspect of data, the flash memory control circuit accurately reads and writes, the comparison circuit corrects errors in real time, data reliability is guaranteed, and the problem of flash memory management is avoided; during bad block detection, factory leaving and newly-added bad blocks are accurately judged by means of multiple means such as specific verification data after all pieces are erased, and the central processing unit intelligently judges, saves time and improves efficiency; in hardware collaboration, a data selector intelligently switches paths, static random access and a memory guarantee data stability, a main state machine accurately controls a time sequence, stability is enhanced, and a high-quality storage scheme is provided for the solid state disk.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state hard disk master control chips, in particular to a high-efficiency solid state hard disk master control chip. Background Art

[0002] The SSD main control chip is the core component of the SSD. It is mainly responsible for data transmission management, flash memory chip management and data error correction, and plays a key role in many aspects such as the performance and stability of the SSD.

[0003] Existing solid-state drives have many problems in use. For example, after the NAND Flash is fully erased, the factory bad block marks will be completely lost, making it difficult to detect the factory bad blocks. The conventional factory bad block scanning steps consume production or testing time, affecting production efficiency. In addition, it is difficult to accurately determine the new bad blocks generated during use based on conventional means alone.

[0004] In view of this, a high-efficiency solid state hard disk main control chip is provided to overcome the above problems. Summary of the invention

[0005] The purpose of the present invention is to provide a high-efficiency solid-state hard disk main control chip to solve the problems raised in the above background technology.

[0006] In order to solve the above technical problems, the present invention provides a high-efficiency solid-state hard disk main control chip, including a central processing unit and a flash memory controller; The flash memory controller includes a communication module, a flash memory control circuit, and a comparison circuit; The flash memory control circuit is connected to the flash memory array and is used to control the read and write operations of the flash memory array; The comparison circuit is connected to the read and write data circuit of the flash memory control circuit and is used to compare the written data with the read-back data; The communication module is used to communicate with external devices. After the flash memory array is fully erased, specific verification data is first written to the suspected bad block through the flash memory control circuit, and then the data is read back and compared by the comparison circuit. Combined with the monitoring circuit to monitor the working current during the writing process, it is comprehensively judged whether the block is a factory bad block or a newly added bad block based on the preset current threshold and the comparison result, thereby avoiding a separate bad block scanning process.

[0007] Furthermore, the flash memory controller also includes a data selector, which is connected between the flash memory control circuit and the central processing unit, and is used to select a data transmission path according to different operating modes. During the bad block detection process, the comparison result data of the comparison circuit is preferentially transmitted to the central processing unit for rapid processing to improve the response speed of bad block judgment.

[0008] Furthermore, the flash memory controller also includes a static random access memory for temporarily storing data and comparison results during the writing and reading back process, so that when the central processing unit is busy, the relevant data can be temporarily stored to avoid data loss and provide a buffer for subsequent data processing.

[0009] Furthermore, the monitoring circuit includes a high-precision current sensor for accurately collecting the working current of the flash memory control circuit during read and write operations. The collection accuracy reaches the nanoampere level to ensure that the bad block situation can be accurately judged based on the current threshold. The high-precision current sensor and the flash memory control circuit are integrated in the same chip to reduce signal interference.

[0010] Furthermore, the flash memory controller also includes a main state machine, which is used to coordinate the working timing of the flash memory control circuit, comparison circuit, and monitoring circuit. In the bad block detection process, data writing, reading back, comparison, and current monitoring operations are performed strictly according to the preset timing to ensure the accuracy and stability of the entire detection process.

[0011] Furthermore, the specific verification data is a data sequence with error correction capability generated according to a preset encryption algorithm. The length of the data sequence is adapted to the block size of the flash memory array. When writing and reading back for comparison, it can not only determine whether the data is correct, but also correct minor errors and re-judge, thereby improving the accuracy of bad block judgment.

[0012] Furthermore, the flash memory control circuit adopts multi-level voltage control technology. When performing read and write operations on suspected bad blocks, it can dynamically adjust the voltage level applied to the flash memory array, and more accurately judge the bad block type based on the read and write results and current monitoring conditions at different voltage levels, especially significantly improving the bad block judgment of storage cells in a critical state.

[0013] Furthermore, the comparison circuit adopts a parallel comparison architecture, which can compare the write and readback data of multiple data blocks at the same time, and uses a hash algorithm to perform preliminary screening of the data during the comparison process, thereby reducing the amount of comparison data, improving the comparison efficiency, and thus speeding up the bad block detection speed.

[0014] Compared with the prior art, the present invention has the following beneficial effects: Performance improvement: By optimizing the data bus and instruction processing, the data reading and writing speed is accelerated, the transmission delay is reduced, the overall performance of the solid-state drive is improved, and the high-speed storage requirements of modern computer systems are adapted.

[0015] Reliable data: The flash memory control circuit accurately controls reading and writing, and the comparison circuit corrects errors in real time, which greatly reduces the error rate of data storage and reading, ensures data integrity and reliability, and avoids data problems caused by improper flash memory management.

[0016] Bad block detection is accurate and efficient: After the entire chip is erased, specific verification data combined with multi-dimensional analysis and current monitoring are used to accurately determine factory bad blocks and newly added bad blocks. The central processor intelligently determines that there is no need for separate scanning, saving time and improving production efficiency.

[0017] Hardware collaborative optimization: The data selector intelligently switches paths to improve transmission efficiency, the static random access memory ensures data continuity and stability, and the main state machine's precise timing control ensures that each operation is orderly and accurate, jointly enhancing the stability and reliability of the main control chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The schematic diagram of a high-efficiency solid-state hard disk main control chip of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] See also Figure 1 , the present invention provides a technical solution: See also Figure 1 As shown, an embodiment of a high-efficiency solid-state hard disk master control chip: 1. Overall architecture and basic function implementation: 1. Connection between CPU and flash memory controller: As the core computing unit of the SSD main control chip, the CPU is responsible for overall instruction scheduling and data processing decisions. It is connected to the flash memory controller through a high-speed data bus. This connection mode ensures fast data interaction. For example, when the computer system issues a read or write data instruction, the CPU quickly receives and accurately interprets the instruction, and then sends the corresponding control signal to the flash memory controller.

[0021] Assume that the average processing time of a data request is T 处理 , the average delay of data transmission is T 延迟 Before this efficient connection method was adopted, due to imperfect data transmission management, there may be problems such as complex data transmission paths and signal interference, resulting in T 处理 and T 延迟 With the high-speed data bus connection, data can be directly and quickly transmitted between the CPU and the flash memory controller, greatly reducing the intermediate links of data transmission. 处理 and T 延迟Significantly reduced. According to the SSD performance formula P=f(T 处理 , T 延迟 , …) (where P represents the performance of the solid state drive), when T 处理 and T 延迟 When it decreases, P is improved, which effectively solves the problem of SSD performance degradation caused by poor data transmission management.

[0022] It is necessary to add that: The transmission mode of the high-speed data bus adopts a full-duplex communication mode, allowing data to be transmitted in both directions simultaneously between the central processing unit and the flash memory controller, further improving data transmission efficiency.

[0023] Bus arbitration mechanism: When multiple devices request to use the bus at the same time, an arbitration algorithm based on priority and fairness is adopted to ensure the timeliness of important data transmission while avoiding data transmission delays caused by long waiting times for low-priority devices.

[0024] The application of pipeline technology when the central processing unit processes read and write data instructions: the instruction processing process is divided into multiple stages, such as instruction fetch, decoding, execution, memory access and write back. Instructions at different stages can be processed in parallel, reducing the number of clock cycles for instruction processing and increasing the instruction processing speed.

[0025] Exception handling mechanism of the central processing unit: When an error occurs during data transmission or processing (such as bus error, data verification error, etc.), it can quickly capture the exception and perform corresponding processing, such as attempting data retransmission, error information recording and reporting, etc., to ensure system stability and data reliability.

[0026] (II) Basic module functions of flash memory controller: Communication module: The communication module uses a high-speed serial communication protocol (such as PCIe protocol) to exchange data with external devices. In a typical data write operation, it can receive data at a rate of up to several Gbps and temporarily store it in the internal cache, waiting for further processing by the flash memory control circuit.

[0027] Assume that the data transmission speed is V and the data transmission delay is D. In traditional communication modules, due to the low communication protocol rate and limited data transmission line bandwidth, V is small and D is large. After adopting the high-speed PCIe protocol, its high bandwidth characteristics significantly increase V, while the optimized data transmission line and protocol mechanism greatly reduce D. According to the read-write performance formula R=g(V, D, ...) (where R represents read-write performance), when V increases and D decreases, R is improved, meeting the needs of modern computer systems for high-speed storage.

[0028] It is necessary to add that: When using the AES-GCM mode to encrypt data, the key generation process of the AES encryption algorithm includes using a random number generator to generate initial key materials, and then using a key expansion algorithm to generate the subkeys required for multiple rounds of encryption.

[0029] The authenticated encryption process in GCM mode uses Galois field multiplication to encrypt data and generate a message authentication code (MAC) to ensure the confidentiality and integrity of the data. It also explains how to verify the MAC at the receiving end to detect whether the data has been tampered with.

[0030] Partition management strategy for internal cache: Divide the cache into data write cache area, data read cache area and metadata cache area, which are used to store different types of data respectively, to improve cache utilization and data access speed.

[0031] Dynamic cache allocation algorithm: Dynamically adjust the size of each cache area according to the real-time needs of data transmission. For example, when a large amount of data is written, increase the capacity of the data write cache area to adapt to the cache requirements under different workloads.

[0032] Flash memory control circuit: The flash memory control circuit is directly connected to the flash memory array and generates appropriate voltage pulse sequences according to the instructions of the central processor to achieve accurate writing and reading of data. For example, when writing data, it converts the data into a signal suitable for flash memory storage according to a specific encoding method and accurately applies it to the corresponding storage unit.

[0033] Assume that the data storage error rate is E 存储 , the data read error rate is E 读取 When precise control is not performed, E may be 存储 and E 读取 The flash memory control circuit can accurately store and completely restore data through precise voltage pulse control and specific encoding methods. From the data integrity formula I=h(E 存储 , E 读取 , …) (where I represents data integrity), when E 存储 and E 读取 When it approaches 0, I approaches the maximum value, which effectively ensures the integrity of the data and solves the problem of data error or loss that may be caused by improper management of flash memory chips.

[0034] It is necessary to add that: Calculation method of voltage compensation value: Based on the temperature sensor data of the flash memory chip, the usage time data and the electrical characteristic model of the storage unit, the appropriate voltage compensation value is calculated through a pre-established mathematical formula or lookup table to ensure the accuracy of data writing under different working conditions.

[0035] When performing voltage compensation, the flash memory control circuit works in conjunction with the power management module, which provides an accurate voltage adjustment signal according to the requirements of the flash memory control circuit to achieve dynamic compensation of the write voltage of the flash memory unit.

[0036] The specific implementation steps of the dynamic wear leveling algorithm include: regularly scanning the number of erase and write times and data storage status of the flash memory blocks, and selecting the appropriate time to perform data migration operations according to the set balancing strategy (such as migrating data from blocks with more erase and write times to blocks with fewer erase and write times).

[0037] During the data migration process, ensure the integrity and consistency of the data, for example, adopt data verification and backup and recovery mechanisms, verify and back up the source data before data migration, and perform data integrity verification after migration to ensure that the data is not lost or damaged.

[0038] Comparison circuit: The comparison circuit is connected to the read and write data lines of the flash control circuit to monitor the written and read back data in real time. After the data is written, the flash control circuit sends a copy of the written data to the comparison circuit, and performs a bit-by-bit comparison when reading the data. For example, in a data integrity check, the comparison of a 4KB data block can be completed in a few nanoseconds.

[0039] Assume the number of errors before data correction is N 前 , the number of errors after data correction is N 后 Without a comparison circuit, errors in data storage are difficult to detect and correct in a timely manner. 后 The comparison circuit can detect errors in time through real-time monitoring and comparison and correct them using the error correction mechanism, making N 后 Significantly reduced. According to the data reliability formula S=k(N 前 , N 后 , …) (where S represents data reliability), when N 后 When it decreases, S is improved, which improves the reliability of data storage in the solid-state drive.

[0040] It is necessary to add that: The specific grouping method of the group comparison and marking technology is: grouping according to the logical address or physical address of the data block, each group contains several consecutive data units, and marking the wrong group during the comparison process.

[0041] Format and content of error report: In addition to the error location information, error type, and the original value and error value of the error data, it also includes the grouping information of the error data and the relevant metadata of the data block (such as block number, write time, etc.) to facilitate subsequent fault analysis and processing.

[0042] After detecting an error, the comparison circuit interacts with the central processing unit through an interrupt. When an error is found, the comparison circuit immediately sends an interrupt signal to the central processing unit and stores the error report information in a specific register. After receiving the interrupt, the central processing unit reads the error report and performs corresponding processing.

[0043] 2. Bad block detection mechanism: (I) Bad block detection process after full chip erase: After the whole chip is erased, the flash memory control circuit starts the bad block detection process. First, a suspected bad block is selected and specific verification data is written to it. The data is generated by a special encryption algorithm (such as AES encryption algorithm combined with error correction coding algorithm). The length is adapted to the flash memory array block size, such as 4KB block corresponding to 4KB verification data and contains redundant error correction information.

[0044] Assume that the bad block misjudgment rate is F 误判 When only conventional means are used for detection, the lack of error correction capability and accurate data verification may result in F 误判 Higher. Specific check data can not only determine the correctness of the data, but also correct errors and re-judge. For example, for minor data errors, the data can be restored through error correction coding and the block status can be re-evaluated, thereby reducing F 误判 . The accuracy formula for judging bad blocks is A=(F 误判 ,…) (where A represents the accuracy of bad block judgment), when F 误判 When it decreases, A increases, solving the problem of being difficult to accurately identify bad blocks based on conventional means.

[0045] It is necessary to add that: The specific coding algorithm for error correction coding preprocessing before data encryption: using Reed-Solomon code for error correction coding.

[0046] During the AES encryption process, the data after error correction coding is encrypted in groups, including the determination of group size, the selection of encryption mode and the use of keys, to ensure that the encrypted data can not only ensure security but also facilitate error correction operations after decryption.

[0047] When generating specific (preset) verification data: optimize the verification data generation algorithm according to the physical structure characteristics of the flash memory array block, consider the page structure of the flash memory block, the layout of the storage units in the block, and the coupling relationship between different storage units, and determine the optimal verification data generation method through mathematical modeling and simulation analysis, improve the adaptability of the verification data to the flash memory block, and enhance the accuracy of bad block detection.

[0048] Screening method combined with flash memory chip production batch information: Establish a production batch database to record the quality data of flash memory chips from different batches (such as initial bad block rate, average erase and write life, etc.). When performing bad block detection, adjust the screening threshold of suspected bad blocks according to the batch information of the flash memory chip. For chips from batches with poor quality, adopt more stringent screening standards to improve detection efficiency.

[0049] Use historical usage data to screen suspected bad blocks: Analyze the historical erase and write times, error frequency and other data of the flash memory chip, and prioritize blocks with higher error risks as suspected bad blocks for detection. For example, set a risk assessment model based on historical data, calculate the risk value of each block according to the erase and write times and error frequency, and select blocks with higher risk values ​​for detection.

[0050] The role of current environmental monitoring data in screening suspected bad blocks: Temperature and humidity have an important impact on the performance of flash memory chips. By real-time monitoring of ambient temperature and humidity, combined with the temperature and humidity characteristic curves of flash memory chips, blocks that may have problems are predicted. For example, when the ambient temperature is too high or the humidity is too high, certain environmentally sensitive blocks may be more prone to failure. These blocks are included in the suspected bad block range for detection.

[0051] (II) Operation and comprehensive judgment after writing verification data: After writing the verification data, the flash memory control circuit reads back the data and sends it to the comparison circuit for comparison. At the same time, a high-precision current sensor (nanoampere accuracy) monitors the write current. If the current fluctuation range is within ±10 nanoamperes, the sensor is integrated with the flash memory control circuit to reduce signal interference.

[0052] Assume that the bad block missed detection rate is F 漏检 , the bad block error detection rate is F 错检 When relying solely on data comparison or current monitoring, due to their respective limitations, F 漏检 or F 错检 By combining current monitoring with data comparison, a comprehensive judgment can be made from two dimensions: physical defects (current abnormality) and data storage correctness (data comparison). For example, if the current is normal but the data has a small number of correctable errors, it can be judged as a newly added bad block; if the current is abnormal and the data has many errors and cannot be corrected, it may be a factory bad block, thereby reducing F 漏检 or F 错检From the bad block detection accuracy formula B = (F 漏检 , F 错检 , …) (where B represents the bad block detection accuracy), when F 漏检 and F 错检 When the false detection is reduced, B is increased, which effectively solves the problem of difficult to detect factory bad blocks after full chip erasure.

[0053] It is necessary to add that: The working principle of the temperature compensation circuit: Use temperature sensors such as thermistors or thermocouples to measure the operating temperature of the current sensor, and compensate for the resistance, capacitance and other component parameters in the current measurement circuit according to temperature changes. For example, by adjusting the gain or bias voltage of the amplifier circuit, ensure that the accuracy of current measurement is not affected by temperature changes.

[0054] Design and working mode of voltage reference calibration circuit: Use a high-precision voltage reference source as a reference to regularly calibrate the voltage measurement circuit of the current sensor. For example, by comparing the difference between the measured voltage and the reference voltage, adjust the calibration resistor or capacitor in the measurement circuit to keep the measured voltage within an accurate range at all times, thereby ensuring the accuracy and stability of the current measurement.

[0055] Steps to establish a model for mapping current anomalies to physical defects in flash memory cells: First, a large number of experimental tests are carried out to apply various stresses (such as high temperature, high voltage, long-term reading and writing, etc.) to different types of flash memory chips (such as SLC, MLC, TLC) to simulate different physical defect conditions. At the same time, high-precision current sensors are used to measure the current changes under these conditions.

[0056] The experimental data are analyzed and organized, and data mining and machine learning techniques, such as cluster analysis and decision tree algorithm, are used to associate and classify the current anomaly characteristics (such as current magnitude, current change rate, current fluctuation frequency, etc.) with the physical defect types of flash memory cells (such as transistor breakdown, oxide layer wear, charge leakage, etc.), and establish a mapping model between current anomalies and physical defects.

[0057] The root node of the decision tree is whether the data comparison and current monitoring results are consistent. Different processing nodes are set according to different branch situations (such as normal data comparison but abnormal current, data comparison error but normal current, abnormal data comparison and current monitoring, etc.).

[0058] The operation rules of each processing node are as follows: in the branch where the data comparison is normal but the current is abnormal, first perform multiple data rewriting and comparison operations, and record the current changes of each operation. If the abnormal current persists and does not change much, further check other relevant parameters of the flash memory unit (such as threshold voltage, storage unit capacitance, etc.) to comprehensively determine whether it is a bad block; if the abnormal current disappears after multiple operations, mark the block as a normal block, but continue subsequent monitoring.

[0059] Update and optimization mechanism of the rule engine: According to the newly discovered relationship between a certain current anomaly and bad blocks, new branches and processing rules are added to improve the accuracy and reliability of bad block judgment when the data comparison and current monitoring results are inconsistent.

[0060] (III) Comprehensive judgment logic of the central processing unit: The CPU determines the block type based on the preset current threshold and the comparison result. If the current exceeds the threshold and the data comparison has many errors and cannot be corrected, it is a factory bad block; if the current is normal and the data has a small number of errors and can be corrected, it is a newly added bad block.

[0061] Assume that the bad block detection process time is T 检测 The traditional single bad block scanning process requires a special scanning process and time, resulting in T 检测 This comprehensive judgment method completes the judgment during the data writing, reading back, current monitoring and comparison process, without the need for additional separate scanning. According to the production efficiency formula E=(T 检测 , …) detection (where E represents production efficiency), when T 检测 When it decreases, E increases, avoiding the separate bad block scanning process, saving production or testing time, and improving production efficiency.

[0062] It is necessary to add that: Method for determining the initial current threshold: By performing standard tests on a large number of flash memory chips of the same type, the current characteristics of normal blocks and known bad blocks during write operations are measured under different working conditions (such as normal temperature, high temperature, and low temperature), and statistical analysis methods (such as the mean-standard deviation method, box plot method, etc.) are used to determine the initial current threshold range. For example, the normal block current mean plus a certain multiple of the standard deviation is taken as the current upper limit threshold, and the normal block current mean minus a certain multiple of the standard deviation is taken as the current lower limit threshold.

[0063] Implementation process of adaptive adjustment algorithm: The central processing unit regularly collects the working status information of the flash memory chip, including temperature, number of erase and write times, usage time, etc., and dynamically adjusts the current threshold according to this information. For example, when the temperature of the flash memory chip rises, its resistance will change, which may cause the current to increase. At this time, according to the pre-established temperature-current threshold adjustment model, the upper current threshold is appropriately increased; when the number of erase and write times of the flash memory chip increases, its internal structure may change, resulting in changes in current characteristics. According to the erase and write times-current threshold adjustment model, the current threshold range is adjusted accordingly.

[0064] Methods for verifying and optimizing the adaptive adjustment algorithm: By conducting long-term tests on a large number of solid-state drives in actual application environments, collecting bad block detection result data before and after current threshold adjustment, comparing and analyzing the accuracy and misjudgment rate after adjustment, and optimizing the model parameters in the adaptive adjustment algorithm based on the test results, it is ensured that the algorithm can accurately adapt to different working environments and flash chip status changes, thereby improving the accuracy and reliability of bad block detection.

[0065] 3. Hardware modules work together: (I) Working mode of data selector: The data selector connects the flash memory control circuit and the central processing unit. During normal reading and writing, the path is switched according to the data flow direction. For example, large data blocks are written without excessive intervention from the central processing unit, which increases the writing speed. During bad block detection, the comparison result data is transmitted to the central processing unit within a few microseconds.

[0066] Assume that the data transmission efficiency is U and the bad block judgment response time is T 响应 In normal data transmission, if the data selector cannot intelligently switch the path, the data transmission path will be congested, reducing U; in bad block detection, if the comparison result cannot be transmitted quickly, T 响应 The data selector intelligently switches according to different modes, optimizes the data transmission process, increases U, and shortens T 响应 From the overall performance formula Q=r(U,T 响应 , …) (where Q represents the overall performance), when U improves, T 响应 When shortened, Q increases, further improving the overall performance of the SSD.

[0067] It is necessary to add that: The specific model and parameter selection basis of the multiplexer (MUX) used in the data selector, for example, select a MUX chip with a suitable number of channels, switching speed and signal bandwidth based on factors such as data transmission bandwidth requirements, signal delay requirements and chip power consumption limitations to ensure that it can meet the data transmission requirements under different working modes.

[0068] MUX control logic design: The data selector generates the MUX control signal according to the control signal of the central processor and the current working mode (such as normal read / write mode or bad block detection mode) to realize the intelligent switching of the data transmission path. For example, in the normal read / write mode, when a large data block write instruction is received, the data selector writes the data directly from the external device to the flash memory array through the flash memory control circuit according to the instruction of the central processor. At this time, the MUX control signal switches the data input channel to the write data input terminal of the flash memory control circuit; in the bad block detection mode, when the comparison result data is ready, the data selector switches the MUX control signal to the channel that transmits the comparison result data to the central processor, ensuring that the data can be quickly and accurately transmitted to the central processor for processing.

[0069] The cache management strategy of the data selector during data transmission: When the data transmission path is switched, in order to avoid data loss or transmission interruption, the data selector adopts a cache mechanism. For example, before switching to the path to write to the flash memory array, the data sent from the external device is first cached in the internal small-capacity high-speed cache, and then the cached data is written to the flash memory array at an appropriate speed to ensure the continuity of data transmission; when reading data from the flash memory array and transmitting it to the external device, the cache strategy is also adopted. The data read from the flash memory array is first cached, and then the data is transmitted according to the receiving speed of the external device to improve data transmission efficiency.

[0070] Collaborative optimization mechanism between the data selector and other modules: The data selector works closely with the flash memory control circuit, the central processing unit, and the communication module to improve overall performance. For example, the data selector works with the flash memory control circuit to perform data pre-fetch operations, predicts the next data block that may be needed based on the read and write requests of the central processing unit, and reads the data from the flash memory array to the cache in advance to reduce the delay in data reading; it works with the communication module to perform flow control, adjusts the data transmission rate of the data selector according to the transmission bandwidth and data flow of the communication module, avoids congestion during data transmission, and improves the stability and efficiency of data transmission.

[0071] (II) The role of static random access memory: Static random access memory (SRAM) temporarily stores write and readback data and comparison results in the main control chip. This can avoid data loss when the CPU is busy, such as multitasking.

[0072] Assume that the data loss rate is L. When there is no SRAM buffer, the busy CPU may cause data to be lost due to inadequate processing, making L higher. SRAM provides buffering to ensure data integrity and continuity. From the main control chip stability formula C=s(L, ...) (where C represents the main control chip stability), when L decreases, C increases, which improves the stability of the main control chip in a complex working environment and avoids data loss or processing errors caused by a busy CPU.

[0073] It is necessary to add that: SRAM cache replacement algorithm: When the CPU is busy, the SRAM may store data and comparison results of multiple read and write tasks. When the SRAM cache is full, a suitable cache replacement algorithm, such as the least recently used (LRU) algorithm or a frequency-based cache replacement algorithm, is used to select the appropriate data block for replacement, ensuring that important data and comparison results can be retained in the cache for a long time to avoid data loss.

[0074] SRAM data consistency maintenance mechanism. Since the data stored in SRAM may be accessed and modified by multiple modules (such as flash memory control circuit, central processing unit) at the same time, in order to ensure data consistency, a lock mechanism or transaction memory mechanism is adopted. For example, when the flash memory control circuit writes data to SRAM, it first obtains the write lock to prohibit other modules from accessing the data block. After the writing is completed, the write lock is released to ensure the integrity and consistency of the data and avoid system errors caused by data inconsistency.

[0075] The key role of SRAM in the data processing flow: During the data writing process, the flash memory control circuit first writes the data to the SRAM cache, and then the SRAM cache transfers the data to the flash memory array. In this process, SRAM plays the role of data buffering and verification. For example, after the data is written to SRAM, data verification (such as parity check or CRC check) is performed. If an error is found, the flash memory control circuit is notified to resend the data to ensure that the data written to the flash memory array is correct; during the data reading process, the data read from the flash memory array is first stored in the SRAM, and the central processing unit reads the data from the SRAM and processes it. In this process, SRAM can ensure the continuity of the data. Even if the central processing unit is briefly delayed when processing other tasks, the data can be temporarily stored in the SRAM without loss or interruption.

[0076] SRAM's protection mechanism for dealing with emergencies: In the event of a sudden power outage or system failure, SRAM uses a backup power supply (such as a supercapacitor) to save important data in the cache (such as unfinished read and write task data, bad block detection results, etc.) to a non-volatile memory (such as a specific area of ​​a flash memory chip or an external EEPROM chip). After the system recovers, the data can be reloaded to continue completing unfinished tasks, ensuring data integrity and system stability.

[0077] (III) Coordination function of the main state machine: The main state machine coordinates the timing of the flash control circuit, comparison circuit, and monitoring circuit. In bad block detection, the time interval of each operation is accurately controlled, such as the delay between writing verification data and reading back operations within tens of nanoseconds.

[0078] Assume the detection error rate E 检测 If the timing control of the main state machine is chaotic, the operation sequence and time interval are unreasonable, it will cause E 检测 The precise timing control of the main state machine ensures the accuracy and stability of bad block detection. From the main control chip reliability formula D=t(E 检测 ,…) (where D represents the reliability of the main control chip), when E 检测 When it decreases, D increases, which improves the reliability of the main control chip and the accuracy of bad block detection.

[0079] It is necessary to add that: The main state machine uses a method for accurately controlling the time intervals of each operation in the bad block detection process: using a high-precision clock signal as a time reference, such as a stable clock signal generated by a crystal oscillator. The main state machine triggers each operation based on the rising or falling edge of the clock signal. For example, at the beginning of the write verification data operation, the main state machine records the current clock count value. When the preset write time (such as tens of nanoseconds) is reached, the readback operation is immediately triggered. Through this precise clock counting and triggering mechanism, the accuracy of the time intervals of each operation is ensured.

[0080] State transition logic of the main state machine in different working modes: In addition to the bad block detection mode, the main state machine is also responsible for coordinating the state transitions in various working modes such as normal read-write mode and chip initialization mode. For example, in the chip initialization mode, the main state machine initializes the various modules of the flash controller (such as communication module, flash control circuit, comparison circuit, etc.) in a predetermined order. After completing the initialization, it switches to the normal read-write mode or bad block detection mode according to the request of the external device. During the state transition process, it ensures the correct switching of the states of each module and the continuity of data transmission and processing.

[0081] Error handling process of the main state machine when an error is detected: When the main state machine finds an error (such as data transmission error, comparison error, current monitoring abnormality, etc.) in the process of coordinating the work of each module, it first suspends the current operation process, records the error information in a specific error register, and then takes corresponding processing measures according to the error type and severity. For example, if it is a data transmission error, the main state machine may try to retransmit the data; if it is a comparison error and the number of errors is small, the main state machine may start the error correction mechanism; if it is a serious current monitoring abnormality, the main state machine may mark the relevant flash block as a bad block and notify the central processor for further processing.

[0082] System recovery mechanism of the main state machine after error recovery: After error handling is completed, the main state machine needs to restore the system to normal working state or continue unfinished tasks. For example, after the data is successfully retransmitted, the main state machine continues to perform subsequent operations according to the original operation process; after the error correction mechanism is completed, the main state machine restarts data comparison and other related operations to ensure that the system can operate normally and the integrity and reliability of the data are not affected.

[0083] Summarize: The solid-state hard disk main control chip of the present invention improves the read and write performance in data transmission management by means of the cooperation between the central processing unit and the flash memory controller and its internal modules, and improves the reliability and stability of the flash memory chip by means of the bad block detection mechanism of the flash memory control circuit for accurate reading and writing, the main state machine timing coordination, and specific verification data and current monitoring through the bad block coordination mechanism in terms of flash memory chip management, effectively solves the problem that the factory bad block mark is lost and difficult to detect after the whole chip is erased, and the problem that the newly added bad blocks are difficult to accurately judge, and at the same time avoids the separate bad block scanning process, saves time and improves efficiency. Overall, the performance, stability and reliability of the solid-state hard disk are significantly improved.

Claims

1. A high-efficiency solid-state hard disk main control chip, characterized in that: Including central processing unit, flash memory controller; The flash memory controller includes a communication module, a flash memory control circuit, and a comparison circuit; The flash memory control circuit is connected to the flash memory array and is used to control the read and write operations of the flash memory array; The comparison circuit is connected to the read and write data circuit of the flash memory control circuit and is used to compare the written data with the read-back data; The communication module is used to communicate with external devices. After the flash memory array is fully erased, the flash memory control circuit first writes specific verification data to the suspected bad block, then reads back the data and compares it with the comparison circuit. Combined with the monitoring circuit, the working current during the writing process is monitored, and the preset current threshold and the comparison result are used to comprehensively judge whether the block is a factory bad block or a newly added bad block; The flash memory controller also includes a data selector, which is connected between the flash memory control circuit and the central processing unit and is used to select a data transmission path according to different working modes. During the bad block detection process, the comparison result data of the comparison circuit is preferentially transmitted to the central processing unit for rapid processing; The flash memory controller also includes a static random access memory for temporarily storing data during writing and reading back and comparison results; The monitoring circuit includes a high-precision current sensor for accurately collecting the working current of the flash memory control circuit during the read and write operations, and the high-precision current sensor and the flash memory control circuit are integrated in the same chip; The flash memory controller also includes a main state machine, which is used to coordinate the working timing of the flash memory control circuit, the comparison circuit, and the monitoring circuit; The specific verification data is a data sequence with error correction capability generated according to a preset encryption algorithm, and the length of the data sequence is adapted to the block size of the flash memory array.

2. A high-efficiency solid-state hard disk main control chip as claimed in claim 1, characterized in that: The flash memory control circuit dynamically adjusts the voltage level applied to the flash memory array.

3. A high-efficiency solid-state hard disk main control chip as claimed in claim 2, characterized in that: The comparison circuit adopts a parallel comparison architecture.

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