Conditional branch instruction

Abstract

Various embodiments of the present disclosure relate to conditional branch instructions to support software pipeline techniques. In an example embodiment, a system (100) includes instruction fetch circuitry (115), decoder circuitry (120), and conditional branch circuitry (132). The instruction fetch circuitry (115) is configured to fetch a conditional branch instruction from the memory (110) and provide the instruction to the decoder circuitry (120). The instruction includes an iterative count (stored at a count register (126)) and a plurality of branch destinations (e.g., branch destination registers (127)). The branch destinations include branch destinations corresponding to conditions for which conditional branch circuitry (132) evaluates the iterative count. Decoder circuitry (132) is configured to cause condition branch circuitry (132) to select a branch destination based on a comparison of the iteration count to each of the conditions, and to cause instruction fetch circuitry (115) to fetch an indication of an instruction from a memory location stored at the selected branch destination.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Patent Application No. 63 / 532,941, filed on August 16, 2023, entitled “INSTRUCTION SET TECHNIQUE TO OPTIMIZE REMAINDER OF LOOPITERATIONS,” which is hereby incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to instruction set architectures and, in particular embodiments, to conditional branches. Background Art

[0004] In computing, software pipelining is a technique that can be used to utilize multiple processing resources by scheduling the execution of application code across multiple processing resources in parallel and cyclically. The code within the first loop can be rearranged by unrolling, which can reduce the number of loop iterations by the following techniques: for example, replacing the first loop with a larger second loop containing multiple copies of the instructions of the first loop so that each iteration of the second loop executes multiple iterations of the first loop. In this way, the application code associated with the first loop can be executed multiple times during a single iteration of the second loop. However, the number of smaller loops that can be grouped into larger loops may be limited. In other words, after executing the application code in the larger loop, the processing system may still need to execute the remaining iterations of the application code from the original smaller loop, because the loop count may not be an integer multiple of the number of times the application code is executed in the larger loop. For example, if the originally specified loop is to be executed 43 times, and the loop body of the new larger loop executes 40 iterations of the original loop, then 3 iterations in the original loop must be executed outside the loop body of the larger loop.

[0005] Existing solutions can use prediction and conditional branching techniques to execute the remaining iterations of the application code. For example, in one solution, the compiler can generate several separate instructions that can be used to check each possible result after executing a larger loop (e.g., zero iterations remaining, one iteration remaining, etc.). Each instruction can be executed in a separate cycle. Therefore, although software pipelining is used to improve the efficiency of the processing system, this may still increase the number of processing cycles required when executing the loop. Alternatively, pipelines may not be used, and the compiler can sort the application code so that it is executed in sequence by each processing resource. Although this can avoid the overhead added by using current branching techniques, it cannot provide other processing benefits provided by using software pipelining. Summary of the invention

[0006] Disclosed herein are improvements to instruction set architectures, and more specifically improvements to conditional branch instructions for software pipelining. Software pipelining may refer to performing various operations between different processing resources in parallel and in a manner such that a loop body (comprising an instruction set for performing various operations of a processing resource) may be performed multiple times in a single iteration of the loop body. Any operations remaining after executing the loop body may be referred to as remaining operations and may be performed outside the loop scope. In an example embodiment, a conditional branch instruction may be provided that may indicate that a processing system or a component thereof identifies one of a plurality of locations where instructions associated with the remaining operations are stored. In such an example embodiment, a system includes an instruction acquisition circuit system, a decoder circuit system coupled to the instruction acquisition circuit system, and a conditional branch circuit system coupled to the decoder circuit system. The instruction acquisition circuit system is configured to acquire a conditional branch instruction from a memory and provide the conditional branch instruction to the decoder circuit system. The conditional branch instruction specifies an iteration count and a plurality of branch destinations. The branch destination includes two or more branch destinations corresponding to the conditions for which the conditional branch circuit system evaluates the iteration count. The decoder circuitry is configured to cause the conditional branch circuitry to select a branch destination among the two or more branch destinations based on a comparison of the iteration count to each of the conditions, and to cause the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.

[0007] This summary is provided to introduce in simplified form a series of concepts that are further described in the detailed description below. It is understood that this summary is not intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An example operating environment that may be configured to execute conditional branch instructions in accordance with an embodiment of the present invention is described.

[0009] Figure 2 A series of steps for executing a conditional branch instruction including multiple branch register destinations in an embodiment is described.

[0010] Figure 3 A sequence of steps for executing instructions in a processing system in an embodiment is described.

[0011] Figure 4 An example operating environment that may be configured to execute conditional branch instructions in accordance with an embodiment of the present invention is described.

[0012] Figure 5 An example computer system is described that may be used in embodiments.

[0013] The drawings are not necessarily drawn to scale. In the drawings, like reference numerals represent corresponding parts throughout the several views. In some instances, components or operations may be divided into different blocks or may be combined into a single block. DETAILED DESCRIPTION

[0014] Discussed herein are enhanced components, techniques, systems and methods related to software pipelines and conditional branches when implementing software pipeline technology. Software pipelines may refer to various operations performed between different processing resources in parallel and in a manner that a loop body (comprising an instruction set for performing various operations of processing resources) can be performed multiple times in a single iteration of the loop body. Software pipelines and parallel techniques may be used in a very long word instruction (VLIW) architecture with many parallel functional units. In such an architecture, a compiler may receive a high-level language code specifying a first loop, and create an assembly language code arranged in a loop body of a second loop, wherein the second loop comprises multiple iterations of the first loop. The compiler may construct an assembly language code so that the second loop is executed at a given number of loop iterations. Any operation associated with the first loop remaining after executing the loop body of the second loop may be referred to as a remaining operation, and may be performed outside the loop range. The problem is that such remaining operations may introduce processing capacity overhead and additional processing cycles, thereby possibly reducing the benefits of software pipelines.

[0015] Some existing solutions can use conditional branching techniques (such as a sequence of several conditional branches) to execute the remaining iterations of the application code. For example, in one solution, the compiler can generate several separate instructions, which can be used to check each possible result after the execution cycle (for example, zero iterations remaining, one iteration remaining, etc.). However, each instruction can be executed in a separate cycle. For example, in a pipeline processor, each conditional branch execution may cause a cycle penalty. Therefore, this may increase the number of processing cycles required when executing the loop and increase the number of instruction rows, thereby possibly reducing the efficiency obtained using software pipelining technology.

[0016] In contrast, as described herein, a compiler may use a conditional branch instruction, the conditional branch instruction indicating a location with a count value and a plurality of branch destinations that can be navigated to based on the count value, the conditional branch instruction may be executed in a single processing cycle. When executing a conditional branch instruction, the conditional branch instruction may indicate a processor or a processing system or a component thereof to identify and store instructions related to the corresponding remaining operations or one of the plurality of branch destinations of its indication or position. In various instances, the conditional branch instruction may be executed by a conditional branch circuit system of a processing system, the conditional branch circuit system may include one or more circuit system components of functional units such as a program control unit. An assembly language loop may include instructions executed by other functional units. After executing an assembly language loop up to the number of loop iterations, a conditional branch instruction may be executed, the conditional branch instruction may indicate where the processing system executes the remaining operations outside the scope of the assembly language loop.

[0017] In an example embodiment, a system is provided that includes instruction fetch circuitry, decoder circuitry coupled to the instruction fetch circuitry, and conditional branch circuitry coupled to the decoder circuitry. The instruction fetch circuitry is configured to fetch a conditional branch instruction from a memory and provide the conditional branch instruction to the decoder circuitry. The conditional branch instruction specifies an iteration count and two or more branch destinations. The two or more branch destinations correspond to conditions for which the conditional branch circuitry evaluates the iteration count. The decoder circuitry is configured to cause the conditional branch circuitry to select a branch destination from the two or more branch destinations based on a comparison of the iteration count with each of the conditions, and cause the instruction fetch circuitry to fetch an indication of the instruction from a memory location stored at the selected branch destination.

[0018] In another example embodiment, one or more computer-readable storage media are provided that include program instructions stored thereon. The program instructions include a conditional branch instruction that specifies an iteration count and two or more branch destinations. The two or more branch destinations correspond to conditions for which the processor evaluates the iteration count. When read and executed by a processing system, the program instructions instruct the processor to select a branch destination from the two or more branch destinations based on a comparison of the iteration count to each of the conditions, and to obtain an indication of the instruction from a memory location stored at the selected branch destination.

[0019] In yet another embodiment, a method for executing a conditional branch instruction is provided. The method includes receiving the conditional branch instruction from a memory via an instruction fetch circuit system, and performing a comparison of an iteration count specified by the conditional branch instruction and each of a plurality of conditions corresponding to two or more branch destinations specified by the conditional branch instruction. Based on the results of the comparison, the method includes selecting a branch destination from two or more other branch destinations. The method also includes causing the instruction fetch circuit system to fetch an indication of the instruction from a memory location stored at the selected branch destination.

[0020] Advantageously, such conditional branch instructions can have the technical effect of reducing the number of code or program instruction lines within the application code, which can be executed in a single processing cycle. Therefore, this not only reduces the number of processing cycles used during the execution of the application code (e.g., within a software pipelining use case), but also reduces the overhead and complexity of the application code and its branches.

[0021] Figure 1 An example operating environment that may be configured to execute program instructions, such as conditional branch instructions, in an embodiment is described. Figure 1 An operating environment 100 is illustrated, which shows components of a processing system, including a memory 110, an instruction fetch circuitry 115, a decoder circuitry 120, registers 125, and functional units 130. Registers 125 include a count register 126 and a branch destination register 127. Functional units 130 include program control circuitry 131, conditional branch circuitry 132, and functional circuitry 133. In some embodiments, the elements shown in operating environment 100 may be included within a processing system, such as a microcontroller unit (MCU) or a central processing unit (CPU). In some embodiments, some of the elements shown in operating environment 100 may be included outside of a processing system.

[0022] In various examples, the components of the operating environment 100 may be configured to perform functions and enable functions of peripheral devices by executing program instructions of application code using the functional units 130. The program instructions may be sequenced and repeated using a loop defined by a compiler via software pipelining techniques, so that one or more functional units 130 may execute a set of instructions within the loop a certain number of times, and so that the loop itself may be executed a certain number of times. The processing system may be further configured to execute a set of instructions outside the scope of the loop, which may be referred to as a residual operation.

[0023] The following examples demonstrate sample iteration counts and the processing system's ability to provide context about remaining operations and the role of conditional branching techniques in resolving remaining operations. In the following examples, the processing system is able to execute instructions of a loop body of a first smaller loop for a given number of iterations (e.g., four iterations) in a single loop iteration of a second larger loop. By way of the first example, for precompiled application code indicating 16 iterations of the loop body of the first loop, the processing system may execute the second loop four times, the second loop containing four copies of instructions of the first loop (four loop iterations of the second loop, each loop body iterating the instructions of the first loop four times within a loop iteration of the second loop), and exit the second loop with zero iterations remaining of the loop body of the first loop. This loop behavior may be advantageous when each copy of the instructions of the first loop can be executed in parallel within a single iteration of the second loop. It may also be advantageous when this loop behavior has the potential to reduce the number of loop end checks due to the smaller number of iterations of the second loop.

[0024] However, for application code that requires the number of iterations of the first loop to be not a multiple of the unroll factor (e.g., four), the processing system may need to execute the loop body of the first loop outside the scope of the second loop for a certain number of times to avoid executing too many iterations, executing empty operations, or using unnecessary processing power, such as when executing another iteration of the second loop. By way of a second example, for application code that indicates 42 iterations of the loop body of the first loop, the processing system may execute the second loop 10 times. However, after completing the 10 loop iterations, the application code may specify two additional loop iterations of the first loop that are not in the loop sequence. In other words, another loop iteration of the second loop may cause the instruction to be executed four times, which is two more than the number specified by the precompiled code. Therefore, the two remaining operations may result in an iteration count of 42. By way of a third example, for application code that indicates 51 iterations of the loop body of the first loop, the processing system may execute the second loop 12 times. However, after completing the 12 loop iterations, the application code may specify three additional loop iterations of the first loop that are not in the loop sequence.

[0025] Return to reference Figure 1 In the operating environment 100 of the processing system, components of the processing system may be configured to execute special conditional branch instructions to resolve remaining iterations of the first loop that are out of loop order, which may improve both code efficiency and cycle efficiency.

[0026] The processing system may include instruction fetch circuitry 115, which may represent one or more components of the processing system capable of performing instruction fetch operations during execution of program instructions. For example, instruction fetch circuitry 115 may be configured to fetch instructions stored in memory 110 and provide the instructions to decoder circuitry 120. Memory 110 may represent one or more volatile or non-volatile computer-readable storage media (e.g., random access memory, flash memory) containing instructions, data, etc. Instruction fetch circuitry 115 may be configured to fetch such instructions from memory 110 in an order specified by a compiler when compiling such instructions into application code.

[0027] Decoder circuitry 120 may represent one or more components of a processing system capable of decoding instructions fetched by instruction fetch circuitry 115. Decoder circuitry 120 may identify functional units 130 and registers 125 based on the decoded instructions, and cause functional units 130 to perform various functions specified by the instructions using data and code located in memory 110 and / or registers 125 as indicated by the instructions. In other words, decoder circuitry 120 may identify and enable one or more of registers 125 for use by one or more of functional units 130 during execution of application code. Although in Figure 1 Only one decoder (decoder circuitry 120) is illustrated in FIG. 1 , but several decoders or decoder circuits may be included in the processing system to decode instructions provided to corresponding components of the processing system. For example, each of the functional units 130 may include a decoder circuitry.

[0028] Register 125 may represent a memory location of data and / or instructions that may be stored for use during the execution of the application code. In various instances, register 125 may include a count register 126 and a branch destination register 127, each of which may contain different information from one another. For example, count register 126 may store a numerical value of an iteration count, which may be incremented or decremented during the execution of a loop by the processing system. Branch destination register 127 may store a memory or address location (e.g., an absolute address or an address offset) or an indication thereof, which corresponds to or stores such instructions corresponding to the remaining operations that may be executed a certain number of times outside the loop range. For example, branch destination register 127 may include a first destination corresponding to one or more instructions that exit the loop when zero remaining operations remain after executing a program instruction in the loop, branch destination register 127 may include a second destination corresponding to one or more instructions that execute the instructions in the loop once when one remaining operation remains after executing a program instruction in the loop, and so on. Any number of branch destination registers 127 is contemplated and may be based on the ability of the processing system to execute instructions in parallel among the various functional units.

[0029] Functional unit 130 may be coupled to instruction fetch circuit system 115, decoder circuit system 120, and register 125, and may represent one or more circuits capable of performing one or more operations indicated by program instructions. For example, functional unit 130 may be capable of performing arithmetic operations, comparison operations, digital logic operations, etc. An example of functional unit 130 may include program control circuit system 131, conditional branch circuit system 132, and functional circuit system 133.

[0030] Functional circuitry 133 may represent one or more circuits configured to execute program instructions. In various examples, functional circuitry 133 may refer to various elements of a processing system that execute instructions within a loop and perform iterations of a loop defined by a compiler. Functional circuitry 133 may be instructed by decoder circuitry 120 to perform such iterations. When performing iterations, functional circuitry 133 may store data in registers 125 and / or read instructions and data from registers 125. When decoder circuitry 120 causes functional circuitry 133 to execute instructions of a loop body (i.e., a set of code that is sequenced in a loop and iterated a certain number of times), functional circuitry 133 may repeatedly perform a sequence of operations for a certain number of loop body iterations, and decrement an iteration count at counting register 126 each time functional circuitry 133 completes a loop body iteration until functional circuitry 133 has completed executing a specified number of iterations (loop iterations) of the entire loop.

[0031] Conditional branch circuitry 132 may represent one or more circuits configured to execute program instructions, or more specifically, conditional branch instructions of application code. In an example, conditional branch circuitry 132 may include comparison circuitry, selector circuitry, and output circuitry, as well as other types of circuitry that may perform various functions. The conditional branch instruction may specify various parameters, such as a field or operation type (e.g., QDEC), an indication of a count register 126, an indication of a branch destination register 127, etc., which conditional branch circuitry 132 may use to determine how many remaining operations remain after executing an application code loop. Based on the number of remaining operations, conditional branch circuitry 132 may provide an indication of the location in register 125 where subsequent instructions for execution by functional circuitry 133 may be stored to program control circuitry 131 (i.e., one of branch destination registers 127).

[0032] Program control circuitry 131 may represent one or more circuits configured to perform application code management functions of the processing system. In various examples, program control circuitry 131 may instruct instruction fetch circuitry 115 to fetch certain instructions in a particular order when other functional units 130, such as conditional branch circuitry 132 and functional circuitry 133, execute instructions during runtime operation of the system.

[0033] In operation, the components of the operating environment 100 may be configured to perform a conditional branching process to continue a loop or perform the remaining operations remaining after executing a program instruction in a loop. First, the instruction acquisition circuit system 115 may be configured to obtain a conditional branch instruction from the memory 110. The conditional branch instruction may identify multiple destinations within the register 125. The register may include a count register 126 and a branch destination register 127. In some instances, the count register 126 may store an iteration count corresponding to the number of loop body iterations remaining after executing the first loop for a certain number of loop iterations, and each time the second loop iterates, the iteration count may be reduced by the number of copies of the instruction of the first loop within the second loop. For example, according to the previous above example, for a starting iteration count of 42, and for a second loop containing 4 copies of the instruction, each time the second loop iterates, the iteration count may be decremented by four until two remain. In some instances, the branch destination register 127 may include two or more branch destinations corresponding to the conditions for which the conditional branch circuit system 132 may evaluate the iteration count of the count register 126. Instruction fetch circuitry 115 may provide the conditional branch instruction to decoder circuitry 120 .

[0034] Decoder circuitry 120 may be configured to receive a conditional branch instruction from instruction fetch circuitry 115 and cause conditional branch circuitry 132 to perform various functions. For example, decoder circuitry 120 may cause conditional branch circuitry 132 to perform a comparison of the iteration count stored at count register 126 to determine whether to continue the loop, and if the loop is to be terminated, to compare the iteration count with each of a plurality of conditions corresponding to each of branch destination registers 127 included in the conditional branch instruction. Decoder circuitry 120 may also cause conditional branch circuitry 132 to select one of the branch destination registers 127 based on the result of the comparison. By way of example, if the value of the iteration count is two, conditional branch circuitry 132 may compare the value with each of the condition values ​​associated with each of the branch destination registers 127. In an example where the loop iteration contains a value of four (i.e., the loop body may iterate four times), the first branch destination may contain a condition value of zero, the second branch destination may contain a condition value of one, the third branch destination may contain a condition value of two, and the fourth branch destination may contain a condition value of three. Therefore, conditional branch circuitry 132 may select the third branch destination based on the value of the iteration count.

[0035] Decoder circuitry 120 may then cause conditional branch circuitry 132 to provide the selected branch destination to program control circuitry 131. Program control circuitry 131 may identify the selected branch destination and cause instruction fetch circuitry 115 to fetch an indication of an instruction from a memory location in memory 110 stored at the selected branch destination. In various examples, each of branch destination registers 127 may contain an address or location of memory 110 storing program instructions related to the remaining operations.

[0036] More specifically, in accordance with the previous example, the memory 110 may store a second loop that includes 4 copies of the instruction associated with the first loop. If the value in the count register 126 is greater than or equal to the number of copies (e.g., 4), the conditional branch instruction may cause the conditional branch circuit system 132 to cause the second loop to be executed and cause the value in the count register 126 to be decremented by the number of copies (e.g., 4). After executing the second loop, execution returns to the conditional branch instruction. In contrast, if the value in the count register 126 is less than the number of copies, the same conditional branch instruction may cause the conditional branch circuit system 132 to branch to one of the branch destinations specified by the conditional branch instruction. The first branch destination may correspond to a remaining zero and may specify a memory location beyond the end of these copies of the first loop instruction in the second loop, and may correspond to one or more instructions that exit the loop and move to the next instruction in the application code. The second branch destination may correspond to a remaining 1 and may specify a memory location at the beginning of the final copy of the first loop instruction within the second loop, thereby causing the program instructions of the first loop to be executed once. The third branch destination may correspond to remainder 2 and may specify a memory location at the beginning of the second-to-last copy of the first loop instruction within the second loop, thereby causing the program instructions of the first loop to be executed twice. The fourth branch destination may correspond to remainder 3 and may specify a memory location at the beginning of the third-to-last copy of the first loop instruction within the second loop, thereby causing the program instructions of the first loop to be executed three times.

[0037] Figure 2 A series of steps for executing a conditional branch instruction including multiple branch register destinations in an embodiment is described. Figure 2 Contains process 200, the process reference Figure 1 In various examples, process 200 may be implemented by one or more components of a processing system, such as Figure 1 The instruction fetch circuitry 115, decoder circuitry 120, and functional unit 130 of the processor 200 may be implemented by software, hardware, firmware, or any combination or variation thereof.

[0038] In operation 205, instruction fetch circuitry 115 is configured to fetch conditional branch instructions from memory 110. Instruction fetch circuitry 115 may represent one or more components of a processing system capable of performing instruction fetch operations during execution of program instructions, such as fetching program instructions including conditional branch instructions in an order specified by a compiler when the instructions are compiled into application code.

[0039] In various examples, the conditional branch instruction may identify multiple locations within registers 125 (e.g., memory locations that may store data and / or instructions, or indications thereof, for use during execution of application code). The locations specified by the conditional branch instruction may include count register 126 and branch destination register 127 that contain two or more branch destinations corresponding to conditions for which conditional branch circuitry 132 may evaluate the iteration count of count register 126. Instruction fetch circuitry 115 may provide the conditional branch instruction to decoder circuitry 120.

[0040] Decoder circuitry 120, which may represent one or more components of a processing system capable of decoding instructions fetched by instruction fetch circuitry 115, may be configured to receive conditional branch instructions from instruction fetch circuitry 115 and cause conditional branch circuitry 132 to perform various functions. Conditional branch circuitry 132 may represent a functional unit of functional unit 130 configured to perform a conditional branch process indicated by decoder circuitry 120. Functional unit 130 including conditional branch circuitry 132 may be coupled to instruction fetch circuitry 115, decoder circuitry 120, and registers 125, and may represent one or more circuits capable of performing one or more operations indicated by a program instruction. In an example, conditional branch circuitry 132 may include comparison circuitry, selector circuitry, and output circuitry, as well as other types of circuits that may perform various functions.

[0041] In operation 210, the decoder circuitry 120 may cause the conditional branch circuitry 132 to perform a comparison of the iteration count stored at the count register 126 (e.g., via the comparison circuitry) to determine whether to continue the loop and, if the loop is to be terminated, to compare the iteration count with each of a plurality of conditions corresponding to each of the branch destination registers 127 included in the conditional branch instruction. By way of example, if the value of the iteration count is two, the conditional branch circuitry 132 may compare the value with each of the conditional values ​​associated with each of the branch destination registers 127. In an example where the loop iteration contains a value of four (i.e., the loop body may iterate four times), the first branch destination may be associated with a conditional value of zero, the second branch destination may be associated with a conditional value of one, the third branch destination may be associated with a conditional value of two, and the fourth branch destination may be associated with a conditional value of three. In this example, the conditional branch circuitry 132 may evaluate the conditional value that the iteration count is equal to the third branch destination by performing a comparison.

[0042] In operation 215, decoder circuitry 120 may cause conditional branch circuitry 132 to select a branch destination (ie, one of branch destination registers 127) based on the result of the comparison in operation 210. Following the previous example, conditional branch circuitry 132 may select the third branch destination based on the value of the iteration count.

[0043] In operation 220, decoder circuitry 120 may then cause conditional branch circuitry 132 to provide the selected branch destination to program control circuitry 131. Program control circuitry 131 may identify the selected branch destination and cause instruction fetch circuitry 115 to fetch an indication of an instruction from a memory location in memory 110 stored at the selected branch destination. In various examples, each of branch destination registers 127 may contain a memory location of memory 110 storing program instructions related to the remaining operations. More specifically, in accordance with the previous example, a first branch destination may correspond to a remaining zero and may specify a memory location beyond the end of a copy of the first loop instruction in the second loop and correspond to one or more instructions that exit the loop and move to the next instruction in the application code. A second branch destination may correspond to a remaining 1 and may specify a memory location at the beginning of the final copy of the first loop instruction, thereby causing the program instructions of the first loop to be executed once. A third branch destination may correspond to a remaining 2 and may specify a memory location at the beginning of the second to last copy of the first loop instruction, thereby causing the program instructions of the first loop to be executed twice. The fourth branch destination may correspond to Remainder 3 and may specify a memory location at the beginning of the third to last copy of the first loop instructions, thereby causing the program instructions of the first loop to be executed three times. Thus, in this example, program control circuitry 131 may cause instruction fetch circuitry 115 to fetch instructions from the memory location associated with the third branch destination, so that when instruction fetch circuitry 115 fetches these instructions and provides the instructions to decoder circuitry 120, decoder circuitry 120 may cause functional circuitry 133 to execute instructions to perform operations of the first loop twice outside the range of operations of the loop executed prior to fetching the conditional branch instruction.

[0044] Figure 3 A sequence of steps for executing instructions in a processing system in an embodiment is described. Figure 3 Contains sequence 300, whose reference Figure 1 In various examples, sequence 300 may be implemented by one or more components of a processing system, such as Figure 1 The instruction fetch circuitry 115, decoder circuitry 120, and functional unit 130 of FIG. 300 may be implemented by software, hardware, firmware, or any combination or variation thereof.

[0045] In operation, the processing system including the memory 110, the instruction fetch circuit system 115, the decoder circuit system 120 and the functional unit 130 can be configured to execute program instructions of the application code. The processing system can execute some program instructions in a loop for a certain number of loop iterations. The set of instructions within the loop can be referred to as the loop body, which can also be executed for a certain number of loop body iterations. For example, the processing system can execute the instructions of the loop body of the first smaller loop for a given number of iterations (e.g., four iterations) in a single loop iteration of the second larger loop. Therefore, for a precompiled application code indicating 48 iterations of the loop body, the processing system can execute the second loop 12 times, the second loop containing 4 copies of the instructions of the first loop (12 loop iterations of the second loop, where each loop body iterates the instructions of the first loop 4 times within the loop iteration of the second loop), and exit the second loop with zero iterations remaining of the loop body of the first loop. However, for application code that requires a number of iterations of the first loop that is not an integer multiple of the unroll factor (e.g., four) (e.g., 51 iterations), the processing system may need to execute the loop body of the first loop outside the scope of the second loop for a certain number of times (referred to as remainder operations) (e.g., 3 remainder operations) to avoid executing too many iterations, executing empty operations, or using unnecessary processing power in the case of, for example, executing another iteration of the second loop. With respect to remainder operations, sequence 300 is discussed.

[0046] First, instruction fetch circuitry 115 may be configured to fetch conditional branch instructions from memory 110 after the processing system completes executing instructions in a loop for a certain number of loop iterations. Instruction fetch circuitry 115 may represent one or more components of the processing system capable of performing instruction fetch operations during execution of program instructions, such as fetching program instructions including conditional branch instructions in an order specified by a compiler when the instructions are compiled into application code.

[0047] In various examples, the conditional branch instruction may identify multiple locations within registers 125 (e.g., memory locations that may store data and / or instructions for use during application code execution). These locations may include count register 126 and branch destination register 127 that contains two or more branch destinations corresponding to conditions for which conditional branch circuitry 132 may evaluate the iteration count of count register 126. Instruction fetch circuitry 115 may provide the conditional branch instruction to decoder circuitry 120.

[0048] Decoder circuitry 120, which may represent one or more components of a processing system capable of decoding instructions fetched by instruction fetch circuitry 115, may be configured to receive conditional branch instructions from instruction fetch circuitry 115 and cause conditional branch circuitry 132 to perform various functions. Conditional branch circuitry 132 may represent a functional unit of functional unit 130 configured to perform a conditional branch process indicated by decoder circuitry 120. Functional unit 130 including conditional branch circuitry 132 may be coupled to instruction fetch circuitry 115, decoder circuitry 120, and registers 125, and may represent one or more circuits capable of performing one or more operations indicated by a program instruction. In an example, conditional branch circuitry 132 may include comparison circuitry, selector circuitry, and output circuitry, as well as other types of circuits that may perform various functions.

[0049] The decoder circuitry 120 may cause the conditional branch circuitry 132 to perform a comparison of the iteration count stored at the count register 126 with each of the plurality of conditions corresponding to each of the branch destination registers 127 included in the conditional branch instruction (e.g., via the comparison circuitry). In an example where 51 iterations of the loop body of the first loop are required and the functional units 130 of the processing system may execute four iterations of the loop body in parallel, after executing twelve loop iterations, the value of the iteration count may be three. Thus, if the value of the iteration count is three, the conditional branch circuitry 132 may compare the value with each of the condition values ​​associated with each of the branch destination registers 127. The first branch destination may be associated with a condition value of zero, the second branch destination may be associated with a condition value of one, the third branch destination may be associated with a condition value of two, and the fourth branch destination may be associated with a condition value of three. In this example, the conditional branch circuitry 132 may evaluate that the iteration count is equal to the condition value (three) associated with the fourth branch destination by performing a comparison.

[0050] Based on the result of the comparison, decoder circuitry 120 may enable conditional branch circuitry 132 to select a branch destination (e.g., the fourth branch destination of branch destination register 127). Thus, conditional branch circuitry 132 may select the fourth branch destination based on the value of the iteration count. Decoder circuitry 120 may then enable conditional branch circuitry 132 to provide the selected branch destination to program control circuitry 131. Program control circuitry 131 may identify the selected branch destination and cause instruction fetch circuitry 115 to fetch an indication of an instruction from a memory location in memory 110 stored at the selected branch destination. In various examples, each of branch destination registers 127 may contain a memory location of memory 110 storing a program instruction or an indication thereof related to the remaining operation. More specifically, in accordance with the previous example, the first branch destination may correspond to a remaining zero and may specify a memory location beyond the end of a copy of the first loop instruction in the second loop and correspond to one or more instructions that exit the loop and move to the next instruction in the application code. The second branch destination may correspond to a remaining 1 and may specify a memory location at the beginning of the final copy of the first loop instruction, thereby causing the instructions of the first loop to be executed once. The third branch destination may correspond to remainder 2 and may specify a memory location at the beginning of the second to last copy of the first loop instruction, causing the instruction to be executed twice. The fourth branch destination may correspond to remainder 3 and may specify a memory location at the beginning of the third to last copy of the first loop instruction, causing the instruction to be executed three times. Thus, in this example, program control circuitry 131 may cause instruction fetch circuitry 115 to fetch instructions from the memory location of memory 110 indicated at the fourth branch destination.

[0051] Instruction fetch circuitry 115 may fetch instructions from memory 110 and provide the instructions to decoder circuitry 120. Decoder circuitry 120 may enable functional circuitry 133 to execute the instructions. Following the previous example, the instructions may include program instructions such that when executed, functional circuitry 133 may perform the operations of the first loop three times outside the scope of the second loop.

[0052] Other instances are contemplated in which a different number of loop body iterations may need to be executed, and thus a different number of remaining operations may be left for evaluation by executing the conditional branch instruction.Thus, combinations or variations of sequence 300 may be performed by components of a processing system.

[0053] Figure 4 An example operating environment that may be configured to execute conditional branch instructions in accordance with an embodiment of the present invention is described. Figure 4An operating environment 400 is illustrated that includes conditional branch circuitry 132 and a conditional branch instruction 404 that includes an operation field 405 , a count field 406 , a condition field 407 , and a branch destination field 408 .

[0054] In various examples, conditional branch circuitry 132 may represent one or more circuits configured to execute program instructions, or more specifically, to execute conditional branch instructions of application code, such as conditional branch instruction 404. In an example, conditional branch circuitry 132 includes comparison circuitry 410, selector circuitry 412, and output circuitry 413.

[0055] Conditional branch instruction 404 may include various parameters, values, fields, and instructions corresponding to operations and locations to access such operations or related data. For example, conditional branch instruction 404 may specify an operation field 405, a count field 406, a condition field 407, and a branch destination field 408. Conditional branch instruction 404, when read and executed by conditional branch circuitry 132, may cause conditional branch circuitry 132 to perform various functions, such as determining the number of remaining operations after a certain number of execution iterations of a loop body, and determining where to direct instruction fetch circuitry (e.g., Figure 1 The instruction acquisition circuit system 115) acquires subsequent instructions.

[0056] Operation field 405 may indicate the type of operation supported by the instruction set architecture of the processing system including conditional branch circuitry 132 and other components. In this example, operation field 405 may represent a QDEC operation, which may represent a discontinuity instruction that selects between executing a loop and executing the remaining loop iterations.

[0057] Count field 406 may indicate the name or location of a register (e.g., count register 126) that stores a count value associated with operation field 405. In this example, count field 406 may indicate the A14 register of the processing system (e.g., Figure 1 Registers 125) (e.g., a register set of a C29x CPU used for address generation and loop counting, among other purposes).

[0058] Condition field 407 may indicate a value or register holding a value to be compared with a value associated with count field 406. For example, count field 406 may indicate the location of count register 126, and condition field 407 may specify an unroll factor associated with the loop (e.g., the number of copies of a smaller loop contained within the loop itself). Count register 126 may store iteration count 415. For example, the processing system may execute instructions of the loop body of the first smaller loop for a given number of iterations (e.g., four iterations) in a single loop iteration of the second larger loop. Application code may specify the number of loop body iterations and the number of loop iterations, and while the first loop is executing, iteration count 415 may be incremented or decremented to keep track of the remaining iterations.

[0059] The branch destination field 408 may specify the number of branch destinations, either directly or by specifying a register containing the branch destinations. For example, the branch destination field 408 may specify a first branch destination named "#u9dest0", which may correspond to the branch destination 127-0; a second branch destination named "#u9dest1", which may correspond to the branch destination 127-1; a third branch destination named "#u9dest2", which may correspond to the branch destination 127-2; and a fourth branch destination named "#u9dest3", which may correspond to the branch destination 127-3. The branch destination 127-0 may include a memory address 416, which may include a program instruction set that, when read and executed by a functional unit (e.g., the functional circuit system 133 of the functional unit 130), instructs the processing system to exit the loop and move to another line of code (i.e., there are no remaining operations). Branch destination 127-1 may include a memory address 417, which may include a set of program instructions that, when read and executed by a functional unit, instructs the processing system to perform one iteration of the instructions of the loop (i.e., there is one remaining operation). Branch destination 127-2 may include a memory address 418, which may include a set of program instructions that, when read and executed by a functional unit, instructs the processing system to perform two iterations of the instructions of the loop (i.e., there are two remaining operations). Branch destination 127-3 may include a memory address 419, which may include a set of program instructions that, when read and executed by a functional unit, instructs the processing system to perform three iterations of the instructions of the loop (i.e., there are three remaining operations).

[0060] In operation, the instruction fetch circuitry (e.g., instruction fetch circuitry 115) may be configured to fetch the conditional branch instruction 404 from the memory (e.g., memory 110) after a certain number of loop iterations of the first loop. The instruction fetch circuitry may provide the conditional branch instruction 404 to the decoder circuitry (e.g., decoder circuitry 120), which may cause the conditional branch circuitry 132 to perform various functions based on elements of the conditional branch instruction 404. In various examples, the comparison circuitry 410 may identify elements of the conditional branch instruction 404, such as the operation field 405, the count field 406, and the condition field 407. Based on the operation field 405, the comparison circuitry 410 may be instructed to identify the count register 126 of the register 409, identify the value of the iteration count 415 at the count register 126, and identify the value of the condition field 407 (i.e., the number of loop iterations) to determine a corresponding one of the result 411 and the branch destination 127. In some examples, branch destination 127-0 may correspond to a condition with a value of zero, branch destination 127-1 may correspond to a condition with a value of one, branch destination 127-2 may correspond to a condition with a value of two, and branch destination 127-3 may correspond to a condition with a value of three.

[0061] Comparison circuitry 410 may first be instructed to compare iteration count 415 to the value of condition field 407. If the value of iteration count 415 is equal to or greater than the value of condition field 407, comparison circuitry 410 may output result 411 indicating that iteration count 415 corresponds to branch destination 127-0, and therefore causes the loop to continue and iteration count 415 to be decremented by the value of condition field 407. In an example where the unroll factor is 4, if iteration count 415 is 10, comparison circuitry 410 may determine to continue the loop and decrement iteration count 415 to 6. Then, if the value of iteration count 415 is less than the value of condition field 407, comparison circuitry 410 may be instructed to compare iteration count 415 to the condition of branch destination 127-3. If comparison circuitry 410 determines that the value of iteration count 415 is equal to the condition value of branch destination 127-3, comparison circuitry 410 may output a result 411 indicating that iteration count 415 corresponds to branch destination 127-3 and that the remaining iterations will therefore be executed and iteration count 415 will be decremented by the value of the condition. If comparison circuitry 410 determines that the value of iteration count 415 is not equal to the condition value of branch destination 127-3, comparison circuitry 410 may be instructed to compare iteration count 415 to the condition of branch destination 127-2, and so on, as described in Table 1 below.

[0062] In this example, iteration count 415 may include a loop counter value of one. Comparison circuitry 410 may compare the value of iteration count 415 to the conditions associated with each of branch destination fields 408. Thus, in this example, comparison circuitry 410 may determine result 411 indicating that iteration count 415 corresponds to branch destination 127-1.

[0063] Comparison circuitry 410 may provide result 411 to selector circuitry 412. Selector circuitry 412 may select branch destination 127-1 based on result 411, and may provide an indication containing branch destination 127-1 to output circuitry 413. Output circuitry 413 may output the indication containing branch destination 127-1 to another functional unit, such as a program flow management unit (e.g., program control circuitry 131). In some instances, the program flow management unit may cause instruction fetch circuitry to fetch memory address 417 from branch destination 127-1, which may be shifted left by one bit. In some instances, branch register location 408 may contain an indication of a location in a different memory (e.g., memory 110), from which instruction fetch memory may fetch instructions to perform the remaining operation. In any event, instructions associated with the remaining operation may be executed in response to reading and executing conditional branch instruction 404 in a single cycle, which may advantageously reduce the number of processing cycles required to check the remaining operation and fetch instructions associated with the remaining operation.

[0064] By way of example, the following table may illustrate example syntax and semantics of a conditional branch instruction 404, which the instruction fetch circuitry may provide to the decode circuitry and which may cause the conditional branch circuitry 132 to perform functions as described above, wherein "QDECB{D}" and "DDECB{D}" correspond to the operation field 405, "A14" corresponds to the count field 406, "#count2" corresponds to the condition field 407, and "PC+#u9dest3<<1", "PC+#u9dest2<<1", and "PC+#u9dest1<<1" correspond to the branch destination field 408 and the associated branch destination 127 with the left-shifted final destination address:

[0065]

[0066] Table 1: Conditional branch instruction 404 syntax and semantics

[0067] In instances where the processing system can execute more than four iterations of the instructions of the loop body in a single iteration, the conditional branch instruction 404 can include additional and / or different branch destination fields 408 to evaluate each possible condition and the number of remaining operations to be performed outside the loop range. For example, for a processing system that can execute five iterations of the instructions of the loop body in a single iteration, the conditional branch instruction can include five branch destinations. Four of the five branch destinations can correspond to locations where instructions for performing a certain number of remaining operations are stored, and one of the five branch destinations can correspond to a location where instructions for exiting the loop are stored. Regardless of the number of branch destinations, the conditional branch circuit system 132 can be configured to determine the number of remaining operations and select a branch destination corresponding to the number of remaining operations within a single instruction and a single cycle.

[0068] Figure 5 An example computer system is described that may be used in embodiments. Figure 5 A computing system 501 for generating and / or executing program instructions including conditional branch instructions according to an embodiment of the present technology is described. The computing system 501 represents any system or system collection that can adopt the various operation architectures, processes, scenarios, and sequences disclosed herein for loop iteration execution and conditional branches related to the execution of remaining operations. The computing system 501 can be implemented as a single device, system, or apparatus, or can be implemented in a distributed manner as multiple devices, systems, or apparatuses. The computing system 501 includes, but is not limited to, a processing system 502, a storage system 503, software 505, a communication interface system 507, and a user interface system 509 (optional). The processing system 502 is coupled to the storage system 503, the communication interface system 507, and the user interface system 509 in an operational manner. The computing system 501 can represent a cloud computing device, a distributed computing device, etc.

[0069] The processing system 502 loads and executes software 505 from the storage system 503, or alternatively, runs the software 505 directly from the storage system 503. The software 505 includes and implements application code 506, which represents any of program instructions, conditional branch instructions, and data related to executing software pipelining, instruction acquisition, register enablement, loop iteration execution, iteration count comparison, conditional evaluation, conditional branching, and other application code execution processes discussed with respect to the aforementioned figures. When executed by the processing system 502, the software 505 instructs the processing system 502 to operate as described herein at least for the various processes, operation scenarios, and sequences discussed in the aforementioned embodiments. For example, in an embodiment, the software 505 instructs the processing system 502 to call the conditional branch circuit system 511 to perform the conditional branch process as described herein when executed by the processing system 502. In another embodiment, software 505, when executed by processing system 502, instructs processing system 502 to generate program instructions including conditional branch instructions that can be used to call conditional branch circuitry 511 to perform a conditional branch process as described herein, regardless of where the program instructions may reside (e.g., a server, one or more computer-readable media). Computing system 501 may optionally include additional devices, features, or functions that are not discussed for the sake of brevity.

[0070] Still refer to Figure 5 , processing system 502 may include a microprocessor and other circuitry that retrieves and executes software 505 from a storage system 503. Processing system 502 may be implemented within a single processing device, but may also be distributed among multiple processing devices or subsystems that cooperate to execute program instructions. Examples of processing system 502 include general-purpose central processing units, graphics processing units, digital signal processing units, data processing units, special-purpose processors and logic devices, and any other type of processing device, combination or variation thereof.

[0071] Storage system 503 may include any computer-readable storage media that can be read and written by processing system 502 and that can store software 505. Storage system 503 may include volatile and nonvolatile media, removable and non-removable media, and mutable and non-mutable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules, or other data. Examples of storage media include random access memory, read-only memory, magnetic disks, optical disks, optical media, flash memory, virtual and non-virtual memory, cassettes, magnetic tape, disk storage or other magnetic storage, or any other suitable storage media. In any case, a computer-readable storage medium is not a propagated signal.

[0072] In addition to computer-readable storage media, in some embodiments, storage system 503 may also include computer-readable communication media that can be used to transfer at least some of software 505 internally or externally. Storage system 503 can be implemented as a single storage device, but can also be implemented across multiple storage devices or subsystems that are co-located or distributed relative to each other. Storage system 503 can include additional elements that can communicate with processing system 502 or possibly other systems, such as a controller.

[0073] The software 505 (including the application code 506) may be implemented in program instructions and, among other functions, may instruct the processing system 502, when executed by the processing system 502, to operate as described with respect to the various operational scenarios, sequences, and processes described herein. For example, the software 505 may include program instructions for compiling and / or implementing program instructions including conditional branch instructions as described herein.

[0074] Specifically, program instructions may include various components or modules that cooperate or otherwise interact to implement various processes and operation scenarios described herein. Various components or modules may be embodied in compiled or interpreted instructions, or in some other variant or combination of instructions. Various components or modules may be synchronous or asynchronous, serially or in parallel, in single-threaded environments or multi-threaded environments, in single processors or multi-processor environments, in single host or multi-host environments, or according to any other suitable execution paradigm, variant or combination thereof. Software 505 may include additional processes, programs or components, such as operating system software, virtualization software or other application software. Software 505 may also include firmware or some other form of machine-readable processing instructions that may be executed by processing system 502.

[0075] In general, software 505 can transform the appropriate device, system or apparatus (represented by computing system 501) from a general computing system to a special computing system customized to provide conditional branch instructions as described herein when loaded into processing system 502 and executed. In practice, encoding software 505 on storage system 503 can transform the physical structure of storage system 503. In different embodiments of the present specification, the specific transformation of the physical structure can depend on various factors. Examples of such factors can include, but are not limited to, the technology of the storage media used to implement storage system 503 and whether the computer storage media is characterized as a primary storage device or a secondary storage device, as well as other factors.

[0076] For example, if the computer-readable storage medium is implemented as a semiconductor-based memory, the software 505 can transform the physical state of the semiconductor memory when the program instructions are encoded therein, for example, by transforming the states of transistors, capacitors, or other discrete circuit elements that make up the semiconductor memory. Similar transformations may occur with respect to magnetic or optical media. Other transformations of the physical media are possible without departing from the scope of this specification, with the foregoing examples provided merely to facilitate this discussion.

[0077] The communication interface system 507 may include communication connectors and devices that allow communication with other computing systems through a communication network (not shown). Examples of connectors and devices that together allow communication between systems may include network interface cards, antennas, power amplifiers, radio frequency circuitry, transceivers, and other communication circuitry. The connectors and devices may communicate through a communication medium that is used to exchange communications with other computing systems or system networks, such as metal, glass, air, or any other suitable communication medium. The aforementioned media, connectors, and devices are well known and need not be discussed in detail herein.

[0078] Communications between computing system 501 and other computing systems (not shown) may occur over a communications network and according to various communications protocols, combinations of protocols, or variations thereof. Examples include intranets, interconnects, the Internet, local area networks, wide area networks, wireless networks, wired networks, virtual networks, software-defined networks, data center buses and backplanes, or any other type of network, combination of networks, or variations thereof. The aforementioned communications networks and protocols are well known and need not be discussed in detail herein.

[0079] Although some examples provided herein are described in the context of processors, processing systems, processing and functional circuit systems, circuits, subcircuits, hardware, software, electrical components, and their environments, the systems and methods described herein are not limited to such embodiments and may be applicable to various other processes, systems, applications, devices, etc. Aspects of the present invention may be embodied as systems, methods, computer program products, and other configurable systems. Therefore, aspects of the present invention may be in the form of complete hardware embodiments, complete software embodiments (including firmware, resident software, microcode, etc.), or embodiments of combined software and hardware aspects, which may generally all be referred to herein as "circuits," "modules," or "systems." In addition, aspects of the present invention may be in the form of computer program products implemented in one or more computer-readable media, the computer-readable media having computer-readable program codes embodied therein.

[0080] The phrases "in some embodiments," "according to some embodiments," "in the illustrated embodiments," "in other embodiments," etc. generally mean that the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present technology, and may be included in more than one embodiment. Additionally, such phrases do not necessarily refer to the same embodiment or different embodiments.

[0081] The above specific implementation of the example of technology is not intended to be exhaustive or to limit the technology to the exact form disclosed above. Although the above describes the specific example of technology for illustrative purposes, as those skilled in the relevant art will recognize, various equivalent modifications can be made within the scope of technology. For example, although the process or block is presented in a given order, alternative embodiments can perform routines with steps in different orders or adopt a system with blocks, and some processes or blocks can be deleted, moved, added, subdivided, combined and / or modified to provide alternatives or sub-combinations. Each of these processes or blocks can be implemented in various different ways. In addition, although sometimes a process or block is shown as being performed serially, these processes or blocks can be performed or implemented in parallel instead, or can be performed at different times. In addition, any specific number mentioned herein is only an example; alternative embodiments can adopt different values ​​or ranges.

[0082] The teaching of the technology provided herein can be applicable to other systems, not necessarily the system described above. The elements and actions of the various examples described above can be combined to provide further embodiments of the technology. Some alternative embodiments of the technology can not only include the extra elements of those embodiments described above, but also include fewer elements.

[0083] In view of the above detailed description, these and other changes can be made to the technology. Although the above description describes certain examples of the technology and describes the best mode envisioned, no matter how detailed the above content appears in this article, the technology can be practiced in a variety of ways. The details of the system can vary significantly in its specific embodiment while still being covered by the technology disclosed herein. As mentioned above, the specific terms used when describing certain features or aspects of the technology should not be understood to imply that the terms are redefined herein as any specific characteristics, features or aspects of the technology associated with the terms. In general, unless such terms are clearly defined in the above specific implementation section, the terms used in the attached claims should not be interpreted as limiting the technology to the specific examples disclosed in the specification. Therefore, the actual scope of the present technology not only covers the disclosed examples, but also covers all equivalent ways of practicing or implementing the present technology under the claims.

[0084] Although the present disclosure has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the exemplary embodiments, as well as other embodiments, will be apparent to those skilled in the art after reference to the description.

Claims

1. A system comprising: instruction fetch circuit system; decoder circuitry coupled to the instruction fetch circuitry; as well as conditional branching circuitry coupled to the decoder circuitry; wherein the instruction fetch circuitry is configured to: fetching a conditional branch instruction from a memory, wherein the conditional branch instruction specifies an iteration count and two or more branch destinations corresponding to conditions for which the conditional branch circuitry is to evaluate the iteration count; as well as providing the conditional branch instruction to the decoder circuitry; and wherein the decoder circuitry is configured such that the conditional branching circuitry: selecting a branch destination among the two or more branch destinations based on a comparison of the iteration count with each of the conditions; as well as The instruction fetch circuitry is caused to fetch an indication of an instruction from a memory location stored at a selected branch destination.

2. The system of claim 1 , wherein the decoder circuitry is further configured to cause the conditional branch circuitry to perform the comparison of the iteration count with each of the conditions, wherein each of the conditions corresponds to a branch destination among the two or more branch destinations. 3 . The system of claim 1 , wherein the iteration count is based on a number of remaining operations resulting from executing a loop instruction a certain number of times. 4 . The system of claim 3 , wherein the instruction fetch circuitry is further configured to fetch the loop instruction from the memory and provide the loop instruction to the decoder circuitry.

5. The system of claim 4, wherein the decoder circuitry is further configured to cause conditional branch circuitry to execute the loop instruction the certain number of times and to cause the conditional branch circuitry to decrement the iteration count each time the conditional branch circuitry executes the loop instruction.

6. The system of claim 1, wherein the conditional branch instruction further identifies a field.

7. The system of claim 1, wherein the instruction stored at the memory location at the selected branch destination corresponds to a number of remaining operations.

8. The system of claim 1, further comprising the memory.

9. One or more computer-readable storage media comprising: program instructions stored thereon, the program instructions comprising a conditional branch instruction that specifies an iteration count and two or more branch destinations corresponding to conditions for which a processor is to evaluate the iteration count, wherein the program instructions, when read and executed by a processing system, instruct the processor to: selecting a branch destination among the two or more branch destinations based on a comparison of the iteration count with each of the conditions; as well as An indication of an instruction is fetched from a memory location stored at the selected branch destination.

10. The one or more computer-readable storage media of claim 9, wherein the program instructions further instruct the processor to perform the comparison of the iteration count to each of the conditions, wherein each of the conditions corresponds to a branch destination of the two or more branch destinations.

11. The one or more computer-readable storage media of claim 9, wherein the iteration count is based on a number of remaining operations resulting from executing a loop instruction a certain number of times.

12. The one or more computer-readable storage media of claim 11, wherein the program instructions further comprise loop instructions.

13. The one or more computer-readable storage media of claim 12, wherein the program instructions further instruct the processor to execute the loop instruction the certain number of times and to decrement the iteration count each time the loop instruction is executed.

14. The one or more computer-readable storage media of claim 9, wherein the conditional branch instruction further identifies a field.

15. The one or more computer-readable storage media of claim 9, wherein the instruction stored at the memory location at the selected branch destination corresponds to a number of remaining operations.

16. A method comprising: The instruction fetch circuitry receives a conditional branch instruction from memory; performing a comparison of an iteration count specified by the conditional branch instruction and each of a plurality of conditions corresponding to two or more branch destinations specified by the conditional branch instruction; selecting a branch destination among the two or more branch destinations based on a result of the comparing; as well as The instruction fetch circuitry is caused to fetch an indication of an instruction from a memory location stored at the selected branch destination.

17. The method of claim 16, wherein the iteration count is based on a number of remaining operations resulting from executing a loop instruction a certain number of times.

18. The method of claim 17, further comprising receiving the loop instruction from the memory via the instruction fetch circuitry.

19. The method according to claim 18, further comprising: Execute the loop instruction for the certain number of times; as well as The iteration count is decremented each time the loop instruction is executed.

20. The method of claim 16, wherein the instruction stored at the memory location at the selected branch destination corresponds to a number of remaining operations.

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