Optimization method for cold start time of embedded low-power-consumption system

Abstract

The invention provides a method for optimizing the cold start time of an embedded low-power-consumption system, and the method comprises the steps: S1, initializing two controllers, and respectively recording the two controllers as SFC0 and SFC1; s2, initializing the two Flash, and respectively recording the two Flash as Flash0 and Flash1; s3, switching the LZMA dual channels into a decoding mode; s4, loading a root file system rootfs from the Flash1 to a memory, and using the SFC1; meanwhile, parallel processing: loading a kernel from Flash0 to a memory, and using SFC0; s5, waiting for the completion of the loading of the SFC1; s6, the LZMA channel 0 decompresses the rootfs; meanwhile, parallel processing is performed as follows: an LZMA channel 1 decompresses a kernel; s7, waiting for the completion of the loading of the SFC0; and S8, switching the LZMA into an algorithm mode. By using the method, the starting speed is high, the Flash space is saved, and the memory consumption is low. The method is suitable for the high time requirement in an embedded system.

Description

Technical Field

[0001] The invention belongs to the technical field of fast start of low-power products, and in particular relates to a method for optimizing the cold start time of an embedded low-power system. Background Art

[0002] With the emergence of multiple application fields of embedded products, people's requirements for power consumption of consumer electronics are getting higher and higher. Corresponding solutions are emerging in an endless stream, and power consumption has become an important bottleneck in embedded system design.

[0003] The Windows boot process is a BIOS power-on self-test, which loads the first sector content MBR of the first boot device into RAM, starts the operating system and runs the file system. The boot device can be a USB flash drive, hard disk, or optical drive.

[0004] The embedded Linux system startup process is to run the boot loader from Nor Flash, load the kernel and file system to RAM, and start the kernel and file system. If Nand Flash is selected for startup, the boot loader needs to be loaded into RAM before running; in the battery solution, Nor Flash is generally selected as the startup storage medium to save the time of moving code from Nand to RAM.

[0005] Generally, embedded systems choose a single Flash to save the contents of all partitions. There is no thread mechanism in the boot loader. Loading the kernel and file system is a pipelined job, that is, the CPU processes the program sequentially, and the loading operation needs to be performed twice in succession.

[0006] However, in the prior art, the kernel must be loaded first and then the file system must be loaded into the RAM, which requires two waiting times for the SFC controller to complete the process, and is relatively time-consuming.

[0007] For products that require extremely fast system startup time, most products use uboot to cut unnecessary modules to obtain a better startup speed. However, since the main time is still spent loading and decompressing the kernel and file systems related to user programs, the larger the size, the longer the decompression time and the worse the user experience.

[0008] In addition, the commonly used terms in the prior art include:

[0009] Cold start: The whole machine is powered off, all modules are reset, and then powered on to reinitialize the startup. In this way, the software and hardware processes required for the product to run need to be redone. Reboot soft start only reruns the software code process without powering off the SOC and peripherals.

[0010] SFC: SPI Flash controller. One is to exchange data with Flash devices, and the other is to manage and query Flash devices. SPI Flash is a NOR FLASH of serial communication interface. LZMA: A decompression format, with both hardware and software. It uses a dictionary encoding mechanism similar to LZ77. In general, the compression rate is higher than bzip2. The maximum variable dictionary used for compression can reach 4GB.

[0011] DMA: Direct Memory Access is a function provided by some computer bus architectures that enables data to be sent directly from an attached device (such as a disk drive) to the memory of the computer motherboard. Summary of the invention

[0012] In order to solve the above problems, the purpose of this application is to use the LZMA hardware decompression module developed by Beijing Ingenic Integrated Circuit Co., Ltd. (hereinafter referred to as Ingenic) to perform extreme decompression of the kernel and file system, and use the dual SFC mechanism to load the kernel and file system into memory in parallel. The module has dual-channel decoding and can work synchronously to decompress data.

[0013] Specifically, the present invention provides a method for optimizing the cold start time of an embedded low-power system, the method comprising the following steps:

[0014] S1, two controllers are initialized, denoted as SFC0 and SFC1 respectively;

[0015] S2, two Flashes are initialized, respectively denoted as Flash0 and Flash1; SFC0 corresponds to Flash0, and SFC1 corresponds to Flash1;

[0016] S3, LZMA dual-channel switches to decoding mode;

[0017] The working principle of the LZMA dual channel is as follows: the CPU software configures the code stream data base address, code stream size, target data base address and start-related signals through the AHB control bus for decoding; during decoding, the code stream data is read from the memory through the AXI data bus based on the configured code stream base address for decoding; after decoding, the decoded data is written into the memory through the AXI data bus based on the configured target data address;

[0018] S4, load the root file system rootfs from Flash1 to the memory, using SFC1; at the same time, in parallel: load the kernel from Flash0 to the memory, using SFC0;

[0019] After SFC1 starts loading, DMA is turned on, and DMA is used to move data to memory. In this way, the CPU can execute the following statement to operate SFC0 and use DMA for parallel processing;

[0020] S5, wait for SFC1 to load;

[0021] S6, LZMA channel 0 decompresses rootfs; at the same time, parallel processing: LZMA channel 1 decompresses the kernel; S7, wait for SFC0 to load;

[0022] S8, LZMA switches to algorithm mode.

[0023] In the step S1, the DMA processing mode needs to be configured when the controller SFC is initialized, and the DMA is turned off after the SFC0 is loaded.

[0024] In the step S3, since the hardware LZMA decompression function and the bscaler module used to use the algorithm share a switching signal, one of the bits is set as the trigger bit of the decompression mode, so this bit needs to be switched to the decompression mode before enabling the current function, and the switching of this bit to the decompression mode includes: in the control register Controller Register, the 31st bit is set as the trigger bit, when the bit position is written once as 1, a mode switch is performed; each time 1 is written, a mode switch is performed, and a switching signal is shared with bscaler; 0 indicates that the LZMA encoding mode is not switched; the bscaler module is recorded as bscaler mode for the algorithm, and the same physical memory is used as LZMA, so LZMA needs to be configured in the Controller Register, and the 31st bit is set for decompression function.

[0025] After configuring the DMA processing mode, this gap is used to enable another SFC to load data synchronously, that is, to perform the step S4. The CPU executes instructions sequentially and cannot execute two instructions at a time, that is, it cannot do two things at a time. Therefore, after SFC1 starts loading and DMA is turned on, DMA is used to help the CPU to transfer data during the gap, and the CPU can sequentially execute the next operation SFC0.

[0026] In the method, after SFC1 starts to load the file system into the memory, DMA starts to work, and then SFC0 starts to load the kernel into the memory. At this time, SFC1 uses Flash1 and SFC0 uses Flash0, so the two do not affect each other when reading.

[0027] The step S8 further includes: after waiting for the reading to be completed, that is, after the data loading is completed, switching LZMA to the algorithm bscaler mode for use after the system is started.

[0028] Therefore, the advantages of the present application are: using the present method to achieve fast startup speed, save Flash space, and reduce memory consumption, and it is suitable for embedded systems with high time requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention.

[0030] Figure 1 This is a schematic diagram showing that one of the bits must be switched to decompression mode before enabling the current function.

[0031] Figure 2 It is a schematic diagram of the process of the present application method.

[0032] Figure 3 It is a schematic diagram of the structure of the LZMA dual channel in the embodiment of the method of the present application. DETAILED DESCRIPTION

[0033] In order to more clearly understand the technical content and advantages of the present invention, the present invention is now further described in detail in conjunction with the accompanying drawings.

[0034] like Figure 1 As shown, the present application proposes a method for optimizing the cold start time of an embedded low-power system, comprising the following steps:

[0035] S1, two controllers are initialized, denoted as SFC0 and SFC1 respectively;

[0036] The DMA processing mode needs to be configured when the controller SFC is initialized. DMA is disabled after SFC0 is loaded.

[0037] S2, two Flashes are initialized, respectively denoted as Flash0 and Flash1; SFC0 corresponds to Flash0, and SFC1 corresponds to Flash1;

[0038] S3, LZMA dual-channel switches to decoding mode;

[0039] The structure of the LZMA dual channel can be seen in Figure 3 The working principle is as follows: the CPU software configures the code stream data base address, code stream size, target data base address and start-related signals through the AHB control bus for decoding. During decoding, the code stream data is read from the memory through the AXI data bus based on the configured code stream base address for decoding. After decoding, the decoded data is written into the memory through the AXI data bus based on the configured target data address.

[0040] Since the hardware LZMA decompression function and the bscaler module used to use the algorithm share a switching signal, one of the bits is set as the trigger bit for the decompression mode, so this bit needs to be switched to the decompression mode before enabling the current function, such as Figure 2 As shown: the switching of one bit to the decompression mode includes: in the control register Controller Register, setting the 31st bit as the trigger bit, when the bit position is written once as 1, a mode switch will be performed; each time 1 is written, a mode switch will be performed, and a switching signal is shared with bscaler; 0 indicates that the LZMA encoding mode is not switched; the bscaler module is recorded as bscaler mode for the algorithm, and the same physical memory is used as LZMA, so LZMA needs to be configured in the Controller Register, and the 31st bit is set for decompression function;

[0041] After the DMA processing mode is configured, this gap is used to enable another SFC to load data synchronously, that is, to perform the step S4. The CPU executes instructions sequentially and cannot execute two instructions at a time, that is, it cannot do two things at a time. Therefore, after SFC1 starts loading and DMA is turned on, DMA is used to help the CPU to do data transfer. During the gap, the CPU can sequentially execute the next operation SFC0;

[0042] S4, load the root file system rootfs from Flash1 to the memory, using SFC1; at the same time, in parallel: load the kernel from Flash0 to the memory, using SFC0;

[0043] After SFC1 starts loading, DMA is turned on, and DMA is used to move data to memory. In this way, the CPU can execute the following statement to operate SFC0 and use DMA for parallel processing;

[0044] S5, wait for SFC1 to load;

[0045] S6, LZMA channel 0 decompresses rootfs; at the same time, parallel processing: LZMA channel 1 decompresses the kernel; S7, wait for SFC0 to load;

[0046] S8, LZMA switches to algorithm mode: After waiting for the reading to be completed, that is, after the data is loaded, switch LZMA to the algorithm bscaler mode for use after the system is started.

[0047] In the method, after SFC1 starts to load the file system into the memory, DMA starts to work, and then SFC0 starts to load the kernel into the memory. At this time, SFC1 uses Flash1 and SFC0 uses Flash0, so the two do not affect each other when reading.

[0048] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for optimizing cold start time of an embedded low-power system, characterized in that: The method comprises the following steps: S1, two controllers are initialized, denoted as SFC0 and SFC1 respectively; S2, two Flashes are initialized, respectively denoted as Flash0 and Flash1; SFC0 corresponds to Flash0, and SFC1 corresponds to Flash1; S3, LZMA dual-channel switches to decoding mode; The working principle of the LZMA dual channel is as follows: the CPU software configures the code stream data base address, code stream size, target data base address and start-related signals through the AHB control bus for decoding; during decoding, the code stream data is read from the memory through the AXI data bus based on the configured code stream base address for decoding; after decoding, the decoded data is written into the memory through the AXI data bus based on the configured target data address; S4, load the root file system rootfs from Flash1 to the memory, using SFC1; at the same time, in parallel: load the kernel from Flash0 to the memory, using SFC0; After SFC1 starts loading, DMA is turned on, and DMA is used to move data to memory. In this way, the CPU can execute the following statement to operate SFC0 and use DMA for parallel processing; S5, wait for SFC1 to load; S6, LZMA channel 0 decompresses rootfs; at the same time, in parallel: LZMA channel 1 decompresses the kernel; S7, wait for SFC0 to load; S8, LZMA switches to algorithm mode.

2. The method for optimizing cold start time of an embedded low-power system according to claim 1, characterized in that: In the step S1, the DMA processing mode needs to be configured when the controller SFC is initialized, and the DMA is turned off after the SFC0 is loaded.

3. The method for optimizing cold start time of an embedded low-power system according to claim 2, characterized in that: In the step S3, since the hardware LZMA decompression function and the bscaler module used to use the algorithm share a switching signal, one of the bits is set as the trigger bit of the decompression mode, so this bit needs to be switched to the decompression mode before enabling the current function, and the switching of this bit to the decompression mode includes: in the control register Controller Register, the 31st bit is set as the trigger bit, when the bit position is written once as 1, a mode switch is performed; each time 1 is written, a mode switch is performed, and a switching signal is shared with bscaler; 0 indicates that the LZMA encoding mode is not switched; the bscaler module is recorded as bscaler mode for the algorithm, and the same physical memory is used as LZMA, so LZMA needs to configure Controller Register, and the 31st bit is set for decompression function.

4. The method for optimizing cold start time of an embedded low-power system according to claim 2, characterized in that: After configuring the DMA processing mode, this gap is used to enable another SFC to load data synchronously, that is, to perform the step S4. The CPU executes instructions sequentially and cannot execute two instructions at a time, that is, it cannot do two things at a time. Therefore, after SFC1 starts loading and DMA is turned on, DMA is used to help the CPU to transfer data during the gap, and the CPU can sequentially execute the next operation SFC0.

5. The method for optimizing cold start time of an embedded low-power system according to claim 4, characterized in that: In the method, after SFC1 starts to load the file system into the memory, DMA starts to work, and then SFC0 starts to load the kernel into the memory. At this time, SFC1 uses Flash1 and SFC0 uses Flash0, so the two do not affect each other when reading.

6. The method for optimizing cold start time of an embedded low-power system according to claim 1, characterized in that: The step S8 further includes: after waiting for the reading to be completed, that is, after the data loading is completed, switching LZMA to the algorithm bscaler mode for use after the system is started.

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