Memory system and operation method, system and operation method, and readable storage medium

Abstract

The embodiment of the invention provides a memory system and an operation method, a system and an operation method, and a readable storage medium. The memory system includes a storage device and a controller coupled to the storage device; the controller is configured to receive a read command of a host; accessing a data block of a logic unit of the corresponding storage device according to the reading command, and updating heat information of the data block in a heat table; wherein the popularity information comprises the number of times that the data block is accessed by a reading command of a host; according to the popularity information of the data blocks in the popularity table, determining a selected data block in the plurality of data blocks; sending mapping information corresponding to the selected data block to a host; wherein the mapping information comprises a mapping relation table from a logic address to a physical address.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a memory system and operating method, a system and operating method, and a readable storage medium. Background Art

[0002] For solid state drive (SSD) products without dynamic random access memory (DRAM) cache (i.e., DRAM-less), a portion of the mapping relationship table (Logical to Physical Table, L2P Table) is usually stored in the static random access memory (SRAM) of the controller to improve the performance of the solid state drive product. Summary of the invention

[0003] Embodiments of the present disclosure provide a memory system and operating method, a system and operating method, and a readable storage medium.

[0004] In a first aspect, an embodiment of the present disclosure provides a memory system, comprising a storage device and a controller coupled to the storage device; the controller is configured to: receive a read command from a host; access a data block of a logical unit of the corresponding storage device according to the read command, and update heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; determine a selected data block from a plurality of data blocks according to the heat information of the data block in the heat table; and send mapping information corresponding to the selected data block to the host; wherein the mapping information includes a mapping relationship table from logical address to physical address.

[0005] In some embodiments, the controller is specifically configured to: if the data block accessed by the read command is not in the heat table, add the heat information of the data block accessed by the read command in the heat table; if the data block accessed by the read command is already in the heat table, modify the heat information of the data block accessed by the read command in the heat table.

[0006] In some embodiments, the controller is specifically configured to: determine, based on the heat information of the data block in the heat table, a data block that has been accessed by a read command of the host more than a preset number of times as a selected data block.

[0007] In some embodiments, the controller is further configured to: delete mapping information corresponding to the selected data block in the heat table.

[0008] In some embodiments, when the number of data blocks in the heat table reaches a preset depth of the heat table, the controller is specifically configured to: according to the heat information of the data blocks in the heat table, according to the number of times the data blocks are accessed by the host's read commands, determine the N data blocks with the largest number of accesses by the host's read commands as selected data blocks; wherein N is a natural number greater than or equal to 1.

[0009] In some embodiments, the controller is further configured to: delete mapping information corresponding to all data blocks in the heat table.

[0010] In a second aspect, an embodiment of the present disclosure provides a system, the system comprising a host and a memory system coupled to the host, the memory system comprising a storage device and a controller coupled to the storage device; the controller is configured to: receive a read command from the host; access a data block of a logical unit of the corresponding storage device according to the read command, and update the heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; determine a selected data block from a plurality of data blocks according to the heat information of the data block in the heat table; send mapping information corresponding to the selected data block to the host; wherein the mapping information includes a mapping relationship table from logical address to physical address; the host is configured to: receive the mapping information corresponding to the selected data block.

[0011] In some embodiments, the host includes a host memory; the host memory is configured to: store mapping information corresponding to the selected data block; the host is configured to: send a read command and the mapping information corresponding to the selected data block accessed by the read command; the controller is configured to: receive the read command, and read data from the storage device according to the mapping information corresponding to the selected data block accessed by the read command; the storage device is configured to: store the data corresponding to the read command.

[0012] In a third aspect, an embodiment of the present disclosure provides an operating method of a memory system, wherein the memory system includes a storage device and a controller coupled to the storage device; the operating method includes: receiving a read command from a host; accessing a data block of a logical unit of the corresponding storage device according to the read command, and updating heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; determining a selected data block from a plurality of the data blocks according to the heat information of the data block in the heat table; and sending mapping information corresponding to the selected data block to the host; wherein the mapping information includes a mapping relationship table from logical address to physical address.

[0013] In some embodiments, accessing a data block of a logical unit of the storage device corresponding to the read command and updating the heat information of the data block in the heat table includes: if the data block accessed by the read command is not in the heat table, adding the heat information of the data block accessed by the read command to the heat table; if the data block accessed by the read command is already in the heat table, modifying the heat information of the data block accessed by the read command in the heat table.

[0014] In some embodiments, determining a selected data block from a plurality of the data blocks based on the heat information of the data blocks in the heat table includes: determining a data block that has been accessed by a read command of the host more than a preset number of times as a selected data block based on the heat information of the data blocks in the heat table.

[0015] In some embodiments, after sending the mapping information corresponding to the selected data block to the host, the operation method further includes: deleting the mapping information corresponding to the selected data block in the heat table.

[0016] In some embodiments, when the number of data blocks in the heat table reaches a preset depth of the heat table, determining a selected data block from a plurality of the data blocks based on the heat information of the data blocks in the heat table includes: based on the heat information of the data blocks in the heat table, according to the number of times the data blocks are accessed by the host's read command, determining the N data blocks with the largest number of accesses by the host's read command as selected data blocks; wherein N is a natural number greater than or equal to 1.

[0017] In some embodiments, after sending the mapping information of the selected data block to the host in real time, the operation method further includes: deleting the mapping information corresponding to all data blocks in the heat table.

[0018] In a fourth aspect, an embodiment of the present disclosure provides an operating method of a system, wherein the system includes a host and a memory system coupled to the host, the memory system includes a storage device and a controller coupled to the storage device; the operating method includes: the controller receives a read command from the host; accesses a data block of a logical unit of the corresponding storage device according to the read command, and updates the heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; determines a selected data block from a plurality of data blocks according to the heat information of the data block in the heat table; sends mapping information corresponding to the selected data block to the host; wherein the mapping information includes a mapping relationship table from a logical address to a physical address; and the host receives the mapping information corresponding to the selected data block.

[0019] In some embodiments, the host includes a host memory; after the host receives the mapping information corresponding to the selected data block, the operating method also includes: the host memory stores the mapping information corresponding to the selected data block; the host sends a read command and the mapping information corresponding to the selected data block accessed by the read command; the controller receives the read command and reads data from the storage device according to the mapping information corresponding to the selected data block accessed by the read command; the storage device stores the data corresponding to the read command.

[0020] In a fifth aspect, an embodiment of the present disclosure provides a readable storage medium, wherein the readable storage medium stores a computer program, and when the computer program is executed, the operating method of the system as described in the above technical solution can be implemented.

[0021] The embodiments of the present disclosure provide a memory system and operation method, a system and operation method, and a readable storage medium. In the embodiments of the present disclosure, the heat information of the data block in the heat table is updated in real time according to the data block accessed by each execution of the host read command; according to the heat information of the data block in the heat table, a selected data block is determined from multiple data blocks and the mapping information corresponding to the selected data block is sent to the host. In this way, the heat information of the data block in the heat table can be updated in real time, and the mapping information corresponding to the selected data block can be sent to the host in real time, so that the host can send a read command and obtain the mapping information corresponding to the selected data block accessed by the read command from the host side, thereby improving the data reading efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a memory system provided for some embodiments;

[0023] Figure 2 A schematic diagram of a system provided for some embodiments;

[0024] Figure 3A A schematic diagram of a memory card having a storage device provided for some embodiments;

[0025] Figure 3B A schematic diagram of a solid state drive having a storage device provided for some embodiments;

[0026] Figure 4 A schematic diagram of a memory device including a memory cell array provided for some embodiments;

[0027] Figure 5 A schematic cross-sectional view of a memory cell array including memory strings provided for some embodiments;

[0028] Figure 6 A schematic diagram of a memory device including a memory cell array and a peripheral circuit provided for some embodiments;

[0029] Figure 7 A schematic diagram of a flow chart of executing a read command provided in some embodiments;

[0030] Figure 8 A schematic diagram of a system provided for an embodiment of the present disclosure;

[0031] Fig. 9 A schematic diagram of a process for determining a selected data block provided in an embodiment of the present disclosure;

[0032] Fig.10 The present invention provides a flowchart of an operating method of a memory system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0034] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0038] refer to Figure 1 , Figure 1 A schematic diagram of a memory system provided in some embodiments. Figure 1 As shown, the memory system 100 includes: at least one memory device 102 ; and a controller 104 coupled to the memory device 102 and configured to control the memory device 102 .

[0039] In some embodiments, the controller 104 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0040] In some embodiments, the controller 104 is designed to operate in a high duty cycle environment SSD or embedded Multi-Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0041] The controller 104 may be configured to control the operation of the storage device 102, such as read, erase, and program operations. The controller 104 may also be configured to manage various functions regarding data stored or to be stored in the storage device 102, including but not limited to bad block management, garbage collection, logical address to physical address conversion, wear leveling, etc. In some embodiments, the controller 104 is also configured to process error correction codes (ECC) regarding data read from or written to the storage device 102.

[0042] The controller 104 may also perform any other suitable functions, such as formatting the storage device 102. The controller 104 may communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the controller 104 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0043] The controller 104 and the one or more storage devices 102 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash storage (UFS) package or eMMC package). That is, the memory system 100 can be implemented and packaged into different types of terminal electronic products.

[0044] refer to Figure 2 , Figure 2 Schematic diagram of a system provided in some embodiments. Figure 2 As shown, the system 200 includes a host 202 and a memory system 100 . The memory system 100 has one or more storage devices 102 and a controller 104 .

[0045] In some embodiments, system 200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a storage device therein.

[0046] like Figure 2As shown, the host 202 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 202 may be configured to send data to the storage device 102 or receive data from the storage device 102.

[0047] In some embodiments, the controller 104 is coupled to the storage device 102 and the host 202, and is configured to control the storage device 102. The controller 104 may manage data stored in the storage device 102, and communicate with the host 202.

[0048] refer to Figure 3A , Figure 3A Schematic diagram of a memory card with a storage device provided in some embodiments. Figure 3A As shown, the controller 104 and the single storage device 102 may be integrated into a memory card 302. The memory card 302 may include a Personal Computer Memory Card International Association (PCMCIA) card, a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro), an SD (e.g., SD, miniSD, microSD, SDHC) card, UFS, etc. The memory card 302 may also include a computer program product that connects the memory card 302 to a host (e.g., Figure 2 A memory card connector 304 is coupled to the host 202 in the memory card connector.

[0049] refer to Figure 3B , Figure 3B A schematic diagram of a solid-state drive with a storage device is provided for some embodiments. Figure 3B As shown, the controller 104 and the plurality of storage devices 102 may be integrated into a solid-state drive 306. The solid-state drive 306 may also include a computer that connects the solid-state drive 306 to a host (e.g., Figure 2 The solid-state drive connector 308 is coupled to the host 202 in the memory card. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 306 is greater than the storage capacity and / or operating speed of the memory card 302.

[0050] refer to Figure 4 , Figure 4 A schematic diagram of a memory device including a memory cell array is provided for some embodiments. Figure 4 As shown, the memory device 102 may include a memory cell array 106 and a peripheral circuit 108 coupled to the memory cell array 106. The memory cell array 106 may be a NAND flash memory cell array, wherein the memory cells 112 are provided in the form of an array of memory strings 114, each memory string 114 being formed on a substrate ( Figure 4 In some embodiments, each memory string 114 includes a plurality of memory cells 112 coupled in series and stacked vertically. Each memory cell 112 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 112. Each memory cell 112 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0051] In some embodiments, each memory cell 112 may be a single-level cell (SLC) having two possible storage states and thus may store one bit of data. For example, an SLC may have a first storage state "1" and a second storage state "0", where the threshold voltage distribution of the first storage state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second storage state "0" may correspond to a second voltage range. The first storage state is an erased state, and the second storage state is a programmed state. In some embodiments, each memory cell 112 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a triple-level cell (TLC)), or four bits of data per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC may have a first storage state "11", a second storage state "10", a third storage state "01", and a fourth storage state "00", where the threshold voltage distributions of the first, second, third, and fourth storage states correspond to the first, second, third, and fourth voltage ranges, respectively. The first storage state is an erased state, and the second, third, and fourth storage states are all programmed states. Similarly, TLC may have 8 storage states, including an erased state and 7 programmed states; QLC may have 16 storage states, including an erased state and 15 programmed states.

[0052] like Figure 4 As shown, each memory string 114 may include a source select transistor (Source Selective Transistor, SST) 116 at its source terminal and a drain select transistor (Drain Selective Transistor, DST) 118 at its drain terminal. The source select transistor 116 and the drain select transistor 118 may be configured to activate the selected memory string 114 (column of the array) during read and program operations. In some embodiments, the sources of the memory strings 114 in the same memory block 110 are coupled through the same source line (Source Line, SL) 120 (e.g., a common SL). In other words, in some embodiments, all memory strings 114 in the same memory block (Block) 110 have an array common source (Array Common Source, ACS). In some embodiments, the drain of the drain select transistor 118 of each memory string 114 is coupled to a corresponding bit line (Bit Line, BL) 126, which can be connected via an output bus ( Figure 4 In some embodiments, each memory string 114 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the drain select transistor 118) or a deselection voltage (e.g., 0V) to the corresponding drain select transistor 118 via one or more drain select gate lines (Drain Selective Line, DSL) 124 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the source select transistor 116) or a deselection voltage (e.g., 0V) to the corresponding source select transistor 116 via one or more source select gate lines (Source Selective Line, SSL) 122.

[0053] like Figure 4As shown, the memory string 114 can be organized into a plurality of memory blocks 110, each of which can have a source line 120 (e.g., a common SL coupled to ground). In some embodiments, each memory block 110 is a basic unit for an erase operation, that is, all memory cells 112 on the same memory block 110 are erased at the same time. In order to erase the memory cells 112 in a selected memory block, the source lines 120 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 112 of adjacent memory strings 114 can be coupled by word lines 128, which select which row of memory cells 112 is affected by the read and program operations. In some embodiments, each word line 128 is coupled to a memory page 130 of memory cells 112. Each word line 128 may include a plurality of control gates (gate electrodes) at each memory cell 112 in a corresponding memory page 130 and a gate line coupling the control gates.

[0054] It should be noted that Figure 4 The illustrated storage page is a physical page, which refers to a layer of storage cells on the physical level. The basic data unit for programming and reading operations is a logical page. For SLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 1 logical page. For MLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 2 logical pages. For TLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 3 logical pages. For QLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 4 logical pages.

[0055] refer to Figure 5 , Figure 5 A cross-sectional schematic diagram of a memory cell array including a memory string is provided for some embodiments. Figure 5As shown, the memory string 114 may extend vertically through the memory stack layer 134 above the semiconductor layer 132. The semiconductor layer 132 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0056] The memory stack 134 may include alternating gate conductive layers 136 and gate dielectric layers 138. The number of pairs of gate conductive layers 136 and gate dielectric layers 138 in the memory stack 134 may determine the number of memory cells 112 in the memory cell array 106. The gate conductive layers 136 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 136 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 136 includes a doped polysilicon layer. Each gate conductive layer 136 may include a control gate surrounding the memory cell 112, and may extend laterally at the top of the memory stack 134 as a drain select gate line 124, extend laterally at the bottom of the memory stack 134 as a source select gate line 122, or extend laterally between the drain select gate line 124 and the source select gate line 122 as a word line 128.

[0057] like Figure 4 As shown, the memory string 114 includes a channel structure extending vertically through the memory stack layer 134. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a memory layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the memory layer, and the barrier layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0058] According to some embodiments, a well (e.g., a P-well and / or an N-well) may be formed in semiconductor layer 132, and the source terminal of memory string 114 may contact the well. For example, a source line may be coupled to the well to apply an erase voltage to the well (i.e., the source of the memory string) during an erase operation. In some embodiments, the memory string further includes a channel plug at the drain terminal of memory string 114. It should be understood that although in Figure 5 Not shown, but additional components of the memory cell array 106 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0059] Return to reference Figure 4 , the peripheral circuit 108 may be coupled to the memory cell array 106 via the bit lines 126, the word lines 128, the source lines 120, the source select gate lines 122, and the drain select gate lines 124. The peripheral circuit 108 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 106 by applying a voltage signal and / or a current signal to each target memory cell 112 and sensing a voltage signal and / or a current signal from each target memory cell 112 via the bit lines 126, the word lines 128, the source lines 120, the source select gate lines 122, and the drain select gate lines 124. The peripheral circuit 108 may include various types of peripheral circuits formed using Metal Oxide Semiconductor (MOS) technology.

[0060] refer to Figure 6 , Figure 6 A schematic diagram of a memory device including a memory cell array and a peripheral circuit is provided for some embodiments. Figure 6 As shown, the peripheral circuit includes a page buffer / sense amplifier 402, a column driver 404, a row driver 406, a voltage generator 408, a control logic unit 410, a register 412, an interface (Interface, I / F) 414 and a data bus 416. It should be understood that in some examples, it may also include Figure 6 Additional peripheral circuits not shown.

[0061] The page buffer / sense amplifier 402 may be configured to read data from the memory cell array 106 and program (write) data to the memory cell array 106 according to a control signal from the control logic unit 410. In one example, the page buffer / sense amplifier 402 may store a page of programming data (write data) to be programmed into one memory page 130 of the memory cell array 106. In another example, the page buffer / sense amplifier 402 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 112 coupled to the selected word line 128. In yet another example, the page buffer / sense amplifier 402 may also sense a low-power signal from the bit line 126 representing a data bit stored in the memory cell 112, and amplify a small voltage swing to a recognizable logic level in a read operation. The column driver 404 may be configured to be controlled by the control logic unit 410, and select one or more memory strings 114 by applying a bit line voltage generated from the voltage generator 408.

[0062] The row driver 406 may be configured to be controlled by the control logic unit 410 and select / deselect the memory block 110 of the memory cell array 106 and select / deselect the word line 128 of the memory block 110. The row driver 406 may also be configured to drive the word line 128 using the word line voltage generated from the voltage generator 408. In some embodiments, the row driver 406 may also select / deselect and drive the source selection gate line 122 and the drain selection gate line 124. As described in detail below, the row driver 406 is configured to perform an erase operation on the memory cell 112 coupled to the (one or more) selected word line 128. The voltage generator 408 may be configured to be controlled by the control logic unit 410 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 106.

[0063] The control logic unit 410 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 412 may be coupled to the control logic unit 410 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 414 may be coupled to the control logic unit 410 and act as a control buffer to buffer the data from the host ( Figure 6The interface 414 may receive control commands received from the control logic unit 410 (not shown) and relay them to the control logic unit 410, and buffer status information received from the control logic unit 410 and relay them to the host. The interface 414 may also be coupled to the column driver 404 via the data bus 416, and act as a data input / output (I / O) interface and a data buffer to buffer data and relay them to or from the memory cell array 106.

[0064] At present, for DRAM-less SSD products, a part of the mapping relationship table is usually stored in the SRAM of the controller. However, the cache space of the SRAM of the controller is limited, and only a small number of mapping relationship tables can be stored. The rest of the mapping relationship tables still need to be stored in the storage device. In this way, each time a read command is executed, it is necessary to search the mapping relationship table stored in the controller, and even the mapping relationship table stored in the storage device, which affects the performance of the controller and reduces the reading speed.

[0065] refer to Figure 7 , Figure 7 A flowchart of executing a read command is provided for some embodiments. Figure 7 As shown, the system 200 may include: a host 202, the host 202 including a host memory 204; and a memory system 100 (eg, Figure 7 ), wherein the memory system 100 includes a storage device 102 and a controller 104 coupled to the storage device 102 and configured to control the storage device 102.

[0066] like Figure 7 As shown in ①, the host 202 can send a read command to the memory system 100; Figure 7 As shown in ②, when the mapping relationship table corresponding to the data block accessed by the read command sent by the host 202 is not stored in the controller 104, it is necessary to read the mapping relationship table from the storage device 102; Figure 7 As shown in ③, the controller 104 reads data from the storage device 102 according to the mapping relationship table.

[0067] In some embodiments, the memory system 100 within the system 200 may be, for example, a UFS. In this case, a host performance booster (HPB) may be used in the system 200 to save a portion of the mapping relationship table in the host memory 204 of the host 202. During the process of the host 202 sending a read command, the host 202 may send the mapping relationship table corresponding to the read command and the data block accessed by the read command to the memory system 100, thereby improving data reading efficiency.

[0068] In some embodiments, the memory system 100 in the system 200 may be, for example, an SSD. In this case, a host memory buffer (HMB) may be used in the system 200 to store a portion of the mapping relationship table in the host memory 204 of the host 202. The embodiment of the present disclosure has no special limitation on the type of the memory system, and the embodiment of the present disclosure has no special limitation on the use of a host performance enhancer or a host memory buffer in the system. Functionally, it is sufficient to store a portion of the mapping relationship table in the host memory of the host.

[0069] However, due to the complexity of data reading scenarios, it is difficult to accurately identify which data blocks corresponding to the mapping relationship tables stored in the host memory can effectively improve the data reading efficiency.

[0070] In view of this, embodiments of the present disclosure provide a memory system and operating method, a system and operating method, and a readable storage medium.

[0071] refer to Figure 8 , Figure 8 Schematic diagram of a system provided by an embodiment of the present disclosure. Figure 8 As shown, an embodiment of the present disclosure provides a memory system 100, which includes a storage device 102 and a controller 104 coupled to the storage device 102; the controller 104 is configured to: receive a read command from a host 202; access a data block of a logical unit of the corresponding storage device 102 according to the read command, and update heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; determine a selected data block from a plurality of data blocks according to the heat information of the data block in the heat table; and send mapping information corresponding to the selected data block to the host 202; wherein the mapping information includes a mapping relationship table from a logical address to a physical address.

[0072] Here, the chip may include multiple logic units (Logic Unit, LUN), each logic unit may include multiple storage planes (Plane), each storage plane may include multiple storage blocks, and each storage block may include multiple storage pages. The logic unit is the basic unit for receiving and executing commands. In a logic unit, only one command can be executed independently at a time.

[0073] Here, the memory system can manage data by data block (Region), and one logical unit can form multiple data blocks. In the process of executing the read command, it is necessary to obtain the mapping table of the data block accessed by the read command, so as to obtain its physical address, so as to read data from the storage device according to the physical address.

[0074] In the disclosed embodiment, the heat information of the data block in the heat table can be updated in real time according to each data block accessed by the host read command, that is, the number of times the data block in the heat table is accessed by the host read command is updated in real time. In other words, the heat information in the heat table changes dynamically, and the heat information in the heat table needs to be updated each time a read command is executed.

[0075] In the disclosed embodiment, a selected data block can be determined from among multiple data blocks based on the heat information of the data block in the heat table, and mapping information corresponding to the selected data block can be sent to the host. That is, after the controller identifies the selected data block from among multiple data blocks, it can send the mapping information corresponding to the selected data block to the host. In this way, the mapping information corresponding to the data block stored in the host is the mapping information corresponding to the data block that has been accessed with a high frequency of recent read command executions. By updating the heat information of the data block in the heat table in real time, and sending the mapping information corresponding to the selected data block to the host in real time, the probability of obtaining the mapping information corresponding to the data block accessed by the host read command on the host side can be increased, thereby improving data reading efficiency.

[0076] refer to Fig. 9 , Fig. 9 A schematic diagram of a process for determining a selected data block provided by an embodiment of the present disclosure. Fig. 9 As shown, it is described in detail how to update the heat information in the heat table and how to determine the selected data block among multiple data blocks.

[0077] like Fig. 9 As shown, a heat table with a preset depth of M (for example, M is 256) is initialized, and each record in the heat table includes the management number (Region_id) of the data block and the number of times the data block is accessed by the host's read command (Read_cnt). The number of times the data block is accessed by the host's read command can also be called the number of hits of the data block. In the disclosed embodiment, it is necessary to monitor the data blocks accessed by each read command, and record the number of times the data block is accessed by the host's read command in the "heat table".

[0078] The embodiment of the present disclosure has no special limitation on the preset depth of the heat table, and can be flexibly selected according to actual conditions to meet more application scenarios.

[0079] In some embodiments, the controller 104 is specifically configured to: if the data block accessed by the read command is not in the heat table, add the heat information of the data block accessed by the read command in the heat table; if the data block accessed by the read command is already in the heat table, modify the heat information of the data block accessed by the read command in the heat table.

[0080] like Fig. 9As shown, if the data block accessed by the read command is not in the heat table, that is, there is no heat information of the data block in the heat table, then a new record is added to the heat table to record the management number of the data block and the number of times the data block is accessed by the host's read command is set to 1. If the data block accessed by the read command is already in the heat table, that is, there is heat information of the data block in the heat table, then the heat information is modified in the heat table, and the number of times the data block is accessed by the host's read command is increased by 1.

[0081] In some embodiments, the controller 104 is specifically configured to: determine a data block that has been accessed by a read command of the host 202 more than a preset number of times as a selected data block according to the heat information of the data block in the heat table.

[0082] In some embodiments, the controller 104 is further configured to: delete mapping information corresponding to the selected data block in the heat table.

[0083] like Fig. 9 As shown, if a data block is accessed by the host's read command more times than a preset number of times (for example, the preset number of times is 4), the data block is determined as a selected data block (Active Region), the mapping information corresponding to the selected data block is sent to the host in real time, and the mapping information corresponding to the selected data block in the heat table is deleted, that is, the heat information record is deleted from the heat table.

[0084] In the disclosed embodiment, the selected data block refers to a data block that has been recently accessed with a high frequency by a read command of the host. The controller sends mapping information corresponding to the selected data block to the host in real time, thereby increasing the probability of obtaining mapping information corresponding to the data block accessed by the host read command on the host side, that is, increasing the hit rate of the host read command accessing the selected data block.

[0085] The embodiments of the present disclosure do not have any special restrictions on the preset number of times, and can be flexibly selected according to actual conditions, thereby satisfying more application scenarios.

[0086] In some embodiments, when the number of data blocks in the heat table reaches a preset depth of the heat table, the controller 104 is specifically configured to: based on the heat information of the data blocks in the heat table, according to the number of times the data blocks are accessed by the host's read commands, the N data blocks with the largest number of accesses by the host's read commands are determined as selected data blocks; wherein N is a natural number greater than or equal to 1.

[0087] In some embodiments, the controller is further configured to: delete mapping information corresponding to all data blocks in the heat table.

[0088] like Fig. 9As shown, the number of data blocks in the heat table reaches the preset depth of the heat table, that is, the heat table is full. At this time, the N (for example, 4) data blocks that are accessed the most times by the host's read command can be determined as selected data blocks, the mapping information corresponding to the selected data blocks is sent to the host in real time, and the mapping information corresponding to all data blocks in the heat table is deleted, that is, all heat information records in the heat table are cleared.

[0089] Exemplarily, the number of times all data blocks in the heat table are accessed by the host's read command can be sorted. When all data blocks are arranged from small to large according to the number of times they are accessed by the host's read command, the N data blocks with the lowest sorting can be determined as the selected data blocks; when all data blocks are arranged from large to small according to the number of times they are accessed by the host's read command, the N data blocks with the highest sorting can be determined as the selected data blocks. Of course, the data blocks in the heat table may not be sorted, and the N data blocks with the largest number of times they are accessed by the host's read command can be directly determined as the selected data blocks.

[0090] The embodiments of the present disclosure do not have any special restrictions on the specific value of N, and can be flexibly selected according to actual conditions to meet more application scenarios.

[0091] An embodiment of the present disclosure provides a system, which system 200 includes a host 202 and a memory system 100 coupled to the host 202, and the memory system 100 includes a storage device 102 and a controller 104 coupled to the storage device 102; the controller 104 is configured to: receive a read command from the host 202; access a data block of a logical unit of the corresponding storage device according to the read command, and update heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the host's read command; determine a selected data block from multiple data blocks according to the heat information of the data block in the heat table; send mapping information corresponding to the selected data block to the host 202; wherein the mapping information includes a mapping relationship table from a logical address to a physical address; the host 202 is configured to: receive the mapping information corresponding to the selected data block. Figure 8 The illustrated system 200 may also be referred to as an electronic device.

[0092] like Figure 8 As shown in ④, the controller 104 identifies the selected data block and can send mapping information corresponding to the selected data block to the host 202. The mapping information corresponding to the selected data block can be stored in the host memory 204.

[0093] In some embodiments, the host 202 includes a host memory 204; the host memory 204 is configured to: store mapping information corresponding to a selected data block; the host 202 is configured to: send a read command and mapping information corresponding to the selected data block accessed by the read command; the controller 104 is configured to: receive a read command, and read data from the storage device 102 according to the mapping information corresponding to the selected data block accessed by the read command; the storage device 102 is configured to: store data corresponding to the read command.

[0094] In the disclosed embodiment, the controller can determine the selected data block from the multiple data blocks, and send the mapping information corresponding to the selected data block to the host in real time. When the host sends a read command, the mapping information corresponding to the selected data block accessed by the read command can be obtained from the host memory, and the read command and the mapping information corresponding to the selected data block accessed by the read command are sent to the memory system together. The controller in the memory system receives the read command, obtains the physical address according to the mapping information corresponding to the selected data block accessed by the read command, and reads data from the storage device according to the physical address.

[0095] like Figure 8 As shown in ⑤, the host 202 can send a read command and mapping information corresponding to the selected data block accessed by the read command to the memory system 100; Figure 8 As shown in ⑥, the controller 104 obtains the physical address of the selected data block according to the mapping information corresponding to the selected data block accessed by the read command, and directly reads the data from the storage device 102.

[0096] In the disclosed embodiment, a heat table is set in the controller to record the number of hits of the data block where the read data is located, and the data blocks with a hit number greater than a preset number in the heat table are determined as selected data blocks, or, when the heat table is full, the N data blocks with the largest hit number are determined as selected data blocks; and the controller recommends the mapping information corresponding to the selected data block to the host.

[0097] In the disclosed embodiment, the hit rate of the host read command accessing the selected data block can be improved, the time consumption of reading data can be reduced, and the data reading performance can be improved. In addition, compared with storing the mapping information of the data block in the SRAM of the controller, the cost of the controller can be saved.

[0098] refer to Fig.10 , Fig.10 Flow chart of the operating method of the memory system provided by the embodiment of the present disclosure. Fig.10As shown, an embodiment of the present disclosure provides an operating method of a memory system, wherein the memory system 100 includes a storage device 102 and a controller 104 coupled to the storage device 102; the operating method includes: step S1001: receiving a read command from a host; step S1002: accessing a data block of a logical unit of the corresponding storage device according to the read command, and updating heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; step S1003: determining a selected data block from a plurality of data blocks according to the heat information of the data block in the heat table; step S1004: sending mapping information corresponding to the selected data block to the host; wherein the mapping information includes a mapping relationship table from a logical address to a physical address.

[0099] In the embodiment of the present disclosure, in step S1001 , the memory system 100 receives a read command from the host 202 .

[0100] In the disclosed embodiment, in step S1002 , the memory system 100 accesses the data block of the logical unit of the corresponding storage device 102 according to the read command, and updates the heat information of the data block in the heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host 202 .

[0101] Here, the memory system can update the heat information of the data block in the heat table in real time according to the data block accessed by the read command. Real-time update means that the memory system needs to update the heat information of the data block in the heat table each time it receives a read command. If the data block accessed by the read command is already in the heat table, then the number of times the data block is accessed by the host's read command can be modified in the heat table; if the data block accessed by the read command is not in the heat table, then the data block is added to the heat table and the number of times the data block is accessed by the host's read command is recorded.

[0102] Here, the controller 104 in the memory system 100 updates the heat table in real time, that is, records the management number of the data block accessed by each read command and the number of times the data block is accessed by the host's read command.

[0103] In the disclosed embodiment, in step S1003, a selected data block is determined from a plurality of data blocks according to the heat information of the data blocks in the heat table.

[0104] Here, the controller 104 in the memory system 100 determines the selected data block from the multiple data blocks. Exemplarily, according to the heat information of the data blocks in the heat table, the data blocks that are accessed by the host's read command more than a preset number of times can be determined as the selected data blocks; or, when the heat table is full, according to the heat information of the data blocks in the heat table, according to the number of times the data blocks are accessed by the host's read command, the N data blocks that are accessed the most times by the host's read command are all determined as the selected data blocks.

[0105] In the disclosed embodiment, in step S1004, mapping information corresponding to the selected data block is sent to the host; wherein the mapping information includes a mapping relationship table from logical addresses to physical addresses.

[0106] Here, after the controller 104 in the memory system 100 determines the selected data block from the multiple data blocks, the controller 104 can send the mapping information corresponding to the selected data block to the host 202 in real time. In other words, after the controller 104 identifies the selected data block from the multiple data blocks, the mapping information corresponding to the selected data block can be sent to the host.

[0107] In some embodiments, step S1002 includes: if the data block accessed by the read command is not in the heat table, adding the heat information of the data block accessed by the read command in the heat table; if the data block accessed by the read command is already in the heat table, modifying the heat information of the data block accessed by the read command in the heat table.

[0108] In some embodiments, step S1003 includes: according to the heat information of the data block in the heat table, determining the data block that has been accessed by the host's read command more than a preset number of times as a selected data block.

[0109] In some embodiments, after step S1004, the operation method further includes: deleting mapping information corresponding to the selected data block in the heat table.

[0110] In some embodiments, when the number of data blocks in the heat table reaches a preset depth of the heat table, step S1003 includes: according to the heat information of the data blocks in the heat table, according to the number of times the data blocks are accessed by the host's read commands, the N data blocks with the largest number of accesses by the host's read commands are determined as selected data blocks; wherein N is a natural number greater than or equal to 1.

[0111] In some embodiments, after S1004, the operation method further includes: deleting mapping information corresponding to all data blocks in the heat table.

[0112] An embodiment of the present disclosure provides an operating method of a system, which includes a host and a memory system coupled to the host, the memory system includes a storage device and a controller coupled to the storage device; the operating method includes: the controller receives a read command from the host; accesses a data block of a logical unit of the corresponding storage device according to the read command, and updates the heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; determines a selected data block from a plurality of data blocks according to the heat information of the data block in the heat table; sends mapping information corresponding to the selected data block to the host; wherein the mapping information includes a mapping relationship table from a logical address to a physical address; the host receives the mapping information corresponding to the selected data block.

[0113] In some embodiments, the host includes a host memory; after the host receives mapping information corresponding to the selected data block, the operating method also includes: the host memory stores the mapping information corresponding to the selected data block; the host sends a read command and the mapping information corresponding to the selected data block accessed by the read command; the controller receives the read command and reads data from the storage device according to the mapping information corresponding to the selected data block accessed by the read command; the storage device stores the data corresponding to the read command.

[0114] An embodiment of the present disclosure provides a readable storage medium, which stores a computer program. When the computer program is executed, the operating method of the system in the above technical solution can be implemented.

[0115] The embodiment of the present disclosure further provides a readable storage medium, which stores a computer program. When the computer program is executed, the operating method of the memory system in the above technical solution can be implemented.

[0116] In the embodiments of the present disclosure, the readable storage medium may include: random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, read-only compact disks (CD-ROMs), or any other form of program code medium known in the technical field.

[0117] The embodiments of the present disclosure provide a memory system and an operation method, a system and an operation method, and a readable storage medium. The memory system includes a storage device and a controller coupled to the storage device; the controller is configured to: receive a read command from a host; access a data block of a corresponding logical unit of the storage device according to the read command, and update the heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; according to the heat information of the data block in the heat table, determine a selected data block from a plurality of data blocks; send the mapping information corresponding to the selected data block to the host; wherein the mapping information includes a mapping relationship table from a logical address to a physical address. In the embodiments of the present disclosure, the heat information of the data block in the heat table is updated according to the data block accessed by the host read command each time; according to the heat information of the data block in the heat table, determine a selected data block from a plurality of data blocks and send the mapping information corresponding to the selected data block to the host. In this way, the heat information of the data block in the heat table can be updated in real time, and the mapping information corresponding to the selected data block can be sent to the host in real time, so that the host can send a read command and obtain the mapping information corresponding to the selected data block accessed by the read command from the host side, thereby improving data reading efficiency.

[0118] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0119] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory system, characterized in that: The memory system includes a memory device and a controller coupled to the memory device; the controller is configured to: Receive a read command from the host; Accessing a data block of a logical unit of the corresponding storage device according to the read command, and updating the heat information of the data block in the heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; Determining a selected data block from a plurality of data blocks according to the heat information of the data blocks in the heat table; The mapping information corresponding to the selected data block is sent to the host; wherein the mapping information includes a mapping relationship table from logical address to physical address.

2. The memory system according to claim 1, wherein: The controller is specifically configured as follows: If the data block accessed by the read command is not in the heat table, adding heat information of the data block accessed by the read command to the heat table; If the data block accessed by the read command is already in the heat table, the heat information of the data block accessed by the read command is modified in the heat table.

3. The memory system according to claim 1, wherein: The controller is specifically configured as follows: According to the heat information of the data block in the heat table, a data block accessed by a read command of the host for a number of times greater than a preset number is determined as a selected data block.

4. The memory system according to claim 3, characterized in that: The controller is also configured to: Delete the mapping information corresponding to the selected data block in the heat table.

5. The memory system according to claim 1, wherein: When the number of data blocks in the heat table reaches a preset depth of the heat table, the controller is specifically configured to: According to the heat information of the data blocks in the heat table, according to the number of times the data blocks are accessed by the host's read commands, the N data blocks with the largest number of accesses by the host's read commands are determined as selected data blocks; wherein N is a natural number greater than or equal to 1.

6. The memory system according to claim 5, characterized in that: The controller is also configured to: Delete the mapping information corresponding to all data blocks in the heat table.

7. A system, characterized in that: The system includes a host and a memory system coupled to the host, the memory system includes a storage device and a controller coupled to the storage device; The controller is configured to: receive a read command from a host; access a data block of a corresponding logical unit of the storage device according to the read command, and update heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; determine a selected data block from a plurality of data blocks according to the heat information of the data block in the heat table; send mapping information corresponding to the selected data block to the host; wherein the mapping information includes a mapping relationship table from a logical address to a physical address; The host is configured to receive mapping information corresponding to the selected data block.

8. The system according to claim 7, characterized in that The host includes a host memory; The host memory is configured to: store mapping information corresponding to the selected data block; The host is configured to: send a read command and mapping information corresponding to a selected data block accessed by the read command; The controller is configured to: receive the read command, and read data from the storage device according to mapping information corresponding to the selected data block accessed by the read command; The storage device is configured to store data corresponding to the read command.

9. A method for operating a memory system, characterized in that: The memory system includes a storage device and a controller coupled to the storage device; the operating method includes: Receive a read command from the host; Accessing a data block of a logical unit of the corresponding storage device according to the read command, and updating the heat information of the data block in the heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; Determining a selected data block from a plurality of data blocks according to the heat information of the data blocks in the heat table; The mapping information corresponding to the selected data block is sent to the host; wherein the mapping information includes a mapping relationship table from logical address to physical address.

10. The method for operating a memory system according to claim 9, characterized in that: The step of accessing the data block of the corresponding logical unit of the storage device according to the read command and updating the heat information of the data block in the heat table includes: If the data block accessed by the read command is not in the heat table, adding heat information of the data block accessed by the read command to the heat table; If the data block accessed by the read command is already in the heat table, the heat information of the data block accessed by the read command is modified in the heat table.

11. The method for operating a memory system according to claim 9, wherein: The step of determining a selected data block from a plurality of data blocks according to the heat information of the data block in the heat table includes: According to the heat information of the data block in the heat table, a data block accessed by a read command of the host for a number of times greater than a preset number is determined as a selected data block.

12. The method for operating a memory system according to claim 11, characterized in that: After sending the mapping information corresponding to the selected data block to the host, the operation method further includes: Delete the mapping information corresponding to the selected data block in the heat table.

13. The method for operating a memory system according to claim 9, wherein: When the number of data blocks in the heat table reaches a preset depth of the heat table, determining a selected data block from a plurality of data blocks according to heat information of the data blocks in the heat table includes: According to the heat information of the data blocks in the heat table, according to the number of times the data blocks are accessed by the host's read commands, the N data blocks with the largest number of accesses by the host's read commands are determined as selected data blocks; wherein N is a natural number greater than or equal to 1.

14. The method for operating a memory system according to claim 13, characterized in that: After sending the mapping information of the selected data block to the host in real time, the operation method further includes: Delete the mapping information corresponding to all data blocks in the heat table.

15. A method for operating a system, characterized in that: The system includes a host and a memory system coupled to the host, wherein the memory system includes a storage device and a controller coupled to the storage device; the operating method includes: The controller receives a read command from a host; accesses a data block of a corresponding logical unit of the storage device according to the read command, and updates heat information of the data block in a heat table; wherein the heat information includes the number of times the data block is accessed by the read command of the host; determines a selected data block from a plurality of data blocks according to the heat information of the data block in the heat table; sends mapping information corresponding to the selected data block to the host; wherein the mapping information includes a mapping relationship table from a logical address to a physical address; The host receives mapping information corresponding to the selected data block.

16. The method for operating the system according to claim 15, characterized in that: The host includes a host memory; after the host receives mapping information corresponding to the selected data block, the operation method further includes: The host memory stores mapping information corresponding to the selected data block; The host sends a read command and mapping information corresponding to a selected data block accessed by the read command; The controller receives the read command, and reads data from the storage device according to mapping information corresponding to the selected data block accessed by the read command; The storage device stores data corresponding to the read command.

17. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed, the operating method of the system according to claim 15 or 16 can be implemented.

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