Computing fast interconnect converter chip, memory access processing method, and electronic device

Abstract

The disclosure provides a computing fast interconnection converter chip, a memory access processing method and electronic equipment, and relates to the technical fields of basic hardware research and development, chip design and research, etc. The specific implementation includes: the CXL Switch chip includes at least two CPU uplink port control logic units, at least two CXL downlink port control logic units, an interconnection bus, and a cache control logic unit and a cache; the at least two CPU uplink port control logic units, the at least two CXL downlink port control logic units, and the cache control logic unit and the cache are connected with the interconnection bus respectively; wherein the cache control logic unit and the cache are used to realize that at least two CPU chips connected with the CXL Switch chip can share at least two CXL memory expansion cards connected through the CXL Switch chip. The technology of the disclosure can realize the pooling function of CXL, and effectively enrich the application range of the CXL memory expansion card.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to the research and development of basic hardware, as well as the design and development of chips, and particularly to a computing fast interconnect converter chip, a memory access processing method, and an electronic device. Background Technology

[0002] Compute Express Link (CXL) is a core technology for achieving storage-compute separation.

[0003] With the evolution of CXL technology, extended functionality has emerged, enabling single-machine memory expansion. Specifically, this can be achieved by setting up CXL memory expansion cards. Furthermore, with the evolution of CXL technology, pooling functionality has appeared, allowing memory to be shared among multiple Central Processing Unit (CPU) chips. Summary of the Invention

[0004] This disclosure provides a computing fast interconnect converter chip, a memory access processing method, and an electronic device.

[0005] According to one aspect of this disclosure, a compute fast interconnect converter chip is provided, comprising: at least two compute fast interconnect uplink port control logic units, at least two compute fast interconnect downlink port control logic units, an interconnect bus, and a consistency cache control logic unit and a cache; wherein the at least two compute fast interconnect uplink port control logic units, the at least two compute fast interconnect downlink port control logic units, the consistency cache control logic unit and the cache are respectively connected to the interconnect bus;

[0006] The at least two compute fast interconnect uplink port control logic units are also connected to at least two central processing unit chips; the at least two compute fast interconnect downlink port control logic units are also connected to at least two compute fast interconnect memory expansion cards.

[0007] The consistency cache control logic unit and the cache are used to enable the at least two central processing unit chips to share the at least two compute fast interconnect memory expansion cards.

[0008] According to another aspect of this disclosure, a data memory access processing method based on a chip as described in any of the preceding aspects is provided, wherein the method includes:

[0009] For each compute fast interconnect uplink port control logic unit, the compute fast interconnect uplink port control logic unit receives a memory access request sent by the connected central processing unit chip, the memory access request carrying a memory access address; the memory access address is an address in any of the at least two compute fast interconnect memory expansion cards; and forwards the memory access request to the interconnect bus;

[0010] The interconnect bus forwards the memory access request to the consistency cache control logic unit;

[0011] The consistent cache control logic unit performs data access processing based on the access request.

[0012] According to another aspect of this disclosure, an electronic device is provided, comprising: a computing fast interconnect converter chip as described in any of the preceding aspects.

[0013] According to the technology disclosed herein, CXL memory expansion cards that only support CXL expansion functions can also realize CXL pooling functions, which can effectively enrich the application scope of CXL memory expansion cards.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0015] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0016] Figure 1 This is a schematic diagram based on the first embodiment of the present disclosure;

[0017] Figure 2 This is a schematic diagram according to the second embodiment of the present disclosure;

[0018] Figure 3 This is an application example diagram of a CXL memory card with CXL pooling functionality provided in this disclosure;

[0019] Figure 4 This is a schematic diagram according to the third embodiment of the present disclosure;

[0020] Figure 5 This is a schematic diagram according to the fourth embodiment of the present disclosure;

[0021] Figure 6 This is a schematic diagram according to the fifth embodiment of the present disclosure;

[0022] Figure 7 This is a schematic diagram according to the sixth embodiment of the present disclosure. Detailed Implementation

[0023] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0024] Obviously, the described embodiments are only some, not all, of the embodiments disclosed herein. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0025] It should be noted that the terminal devices involved in the embodiments of this disclosure may include, but are not limited to, smart devices such as mobile phones, personal digital assistants (PDAs), wireless handheld devices, and tablet computers; the display devices may include, but are not limited to, personal computers, televisions, and other devices with display functions.

[0026] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0027] In practical applications, when implementing CXL's extended functions, the CXL controller only needs to perform protocol conversion from the CXL protocol to the Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) controller, without involving cache coherence issues. However, when implementing CXL's pooling function, a CXL switch chip and a CXL controller supporting CXL pooling are generally required. To support CXL's pooling function, in addition to implementing the protocol conversion from the CXL protocol to the DDR controller, logic for handling cache coherence issues also needs to be added.

[0028] In existing technologies, CXL's expansion functionality emerged first, resulting in a large number of CXL memory expansion cards on the market that only support CXL expansion. Later, CXL's pooling functionality appeared. Implementing CXL's pooling functionality requires configuring CXL memory cards that support pooling. However, since CXL memory expansion cards that support CXL expansion do not support pooling, meaning they cannot handle cache coherency issues, CXL memory expansion cards that support CXL expansion cannot implement CXL's pooling functionality.

[0029] Based on the above-mentioned technical problems, this disclosure provides a CXL converter (Switch) chip that enables CXL memory expansion cards that only support CXL expansion functions to also realize CXL pooling functions and be applied in CXL memory sharing scenarios, thereby effectively enriching the application scope of CXL memory expansion cards.

[0030] Figure 1 This is a schematic diagram based on the first embodiment of the present disclosure; as shown Figure 1 As shown, this embodiment provides a CXL converter (Switch) chip 100, including: at least two CXL uplink port control logic units 101, at least two CXL downlink port control logic units 102, an interconnect bus 103, and a coherence cache control logic unit 104 and a cache 105; the at least two CXL uplink port control logic units 101, at least two CXL downlink port control logic units 102, the coherence cache control logic unit 104 and the cache 105 are respectively connected to the interconnect bus 103.

[0031] like Figure 1 As shown, in this embodiment, the consistency cache control logic unit 104 and the cache 105 are configured separately. In practical applications, they can also be configured as an integrated structure. In this embodiment, the consistency cache control logic unit 104 and the cache 105 are connected.

[0032] The coherence cache control logic unit 104 and cache 105 are used to enable at least two CPU chips connected to the CXL Switch chip 100 to share at least two CXL memory expansion cards connected through the CXL Switch chip 100.

[0033] In other words, in this embodiment, at least two CXL uplink port control logic units 101 are also connected to at least two central processing unit chips; at least two CXL downlink port control logic units 102 are also connected to at least two CXL memory expansion cards.

[0034] For example, in a specific implementation, one end of at least two CXL uplink port control logic units 101 is connected to at least two CPU chips; specifically, one end of each CXL uplink port control logic unit 101 is connected to one CPU chip. One end of at least two CXL downlink port control logic units 102 is connected to at least two CXL memory expansion cards; specifically, one end of each CXL downlink port control logic unit is connected to one CXL memory expansion card. The other end of each CXL uplink port control logic unit 101, the other end of each CXL downlink port control logic unit 102, and the coherence cache control logic unit 104 and cache 105 are respectively connected to the interconnect bus 103.

[0035] The CXL memory expansion card in this embodiment is a CXL memory expansion card without CXL pooling capability. The CXL memory expansion card in this embodiment may include a CXL controller and memory modules. In application, the CXL Switch chip 100 of this embodiment can simultaneously connect multiple CPU chips and multiple CXL memory expansion cards. Multiple CXL memory expansion cards can form a memory pool, enabling multiple CPU chips to share the memory pool. Although the multiple CXL memory expansion cards in this embodiment do not support pooling functionality, by setting a coherence cache control logic unit 104 and a cache 105 in the CXL Switch chip 100, logic for handling cache coherence issues can be achieved. Thus, multiple CXL memory expansion cards can perform protocol conversion from the CXL protocol to the DDR controller, and the coherence cache control logic unit 104 and the cache 105 can handle cache coherence issues. Therefore, using the CXL Switch chip 100 of this embodiment, multiple CPU chips can share multiple CXL memory expansion cards. The CXL Switch chip 100 of this embodiment, by setting a consistency cache control logic unit 104 and a cache 105 in the CXL Switch chip 100, enables the CXL Switch chip 100 to achieve memory sharing based on CXL memory expansion cards that do not have pooling capabilities, which can effectively enrich the application scope of CXL memory expansion cards that do not have pooling capabilities; and also makes memory sharing no longer dependent on newly developed CXL memory cards that support pooling functions.

[0036] Figure 2 This is a schematic diagram based on the second embodiment of the present disclosure; as shown Figure 2 As shown, the CXL Switch chip 200 provided in this embodiment is capable of the above-mentioned... Figure 1 Based on the technical solutions of the embodiments shown, the technical solutions of this disclosure will be described in further detail.

[0037] like Figure 2As shown, the CXL Switch chip 200 provided in this embodiment includes the above-mentioned... Figure 1 The structure of the CXL Switch chip 100 in the illustrated embodiment.

[0038] Furthermore, in this embodiment, the consistency cache control logic unit 204 and cache 205 in the CXL Switch chip 200 are described in more detail how at least two CPU chips can share at least two CXL memory expansion cards.

[0039] Specifically, in this embodiment, for each CXL uplink port control logic unit 201, the CXL uplink port control logic unit 201 is used to receive a memory access request sent by the connected CPU chip. The memory access request carries a memory access address. The memory access address is an address in any of the at least two CXL memory expansion cards. In this embodiment, the memory access request is an access request or storage request from the CPU chip to any of the at least two CXL memory expansion cards. That is, the memory access address in this embodiment includes an access address or a storage address.

[0040] Interconnect bus 203 is used to forward memory access requests to coherent cache control logic unit 204;

[0041] The consistent cache control logic unit 204 is used to perform data access processing based on memory access requests.

[0042] It should be noted that when the consistent cache control logic unit 204 performs data access processing based on the access request, it may also need to refer to the data in the cache when necessary.

[0043] Alternatively, in one embodiment of this disclosure, the processing of access requests by the CXL Switch chip 200 of this embodiment is first described, which may specifically include the following:

[0044] For each CXL uplink port control logic unit 201, the CXL uplink port control logic unit 201 is used to receive access requests sent by the connected CPU chip, and the access requests carry access addresses.

[0045] Interconnect bus 203 is used to forward the access request to consistency cache control logic unit 204;

[0046] The consistency cache control logic unit 204 is used to obtain the access address data based on the recorded memory data status information table; and transmit it to the CPU chip through the interconnect bus 203 and the CXL uplink port control logic unit 201.

[0047] In this embodiment, the memory data status information table in the consistency cache control logic unit 204 records the cache status and cache status of the data of the memory address it manages;

[0048] Specifically, the coherence cache control logic unit 204 is responsible for managing the memory address data of at least two CXL memory expansion cards connected to the CXL Switch chip 200. When the data of a certain memory address managed by the unit is read by one of the CPUs connected to the CXL Switch chip 200, the memory address of the read data, the identifier of the CPU reading the data, the operation status of the CPU reading the data, and the status of the data in the cache 205 can be recorded in the memory data status information. The CPU's operation status for reading the data includes reading or reading and modifying. If the operation status is "read," it means that the CPU reading the data has not modified the data at that memory address. In this case, if the cache 205 stores the data at that memory address, it is still in a valid state. If the cache 205 does not store the data at that memory address, the data is stored in the CXL memory expansion card to which the corresponding memory address belongs, and its status is also valid. If the operation status is "read and modify," it means that the CPU reading the data has modified the data at that memory address after reading it. In this case, if the local cache 205 stores the data at that memory address, it is in an invalid state. Similarly, the data at that memory address in the CXL memory expansion card to which that memory address belongs is also invalid. In this embodiment, the consistency cache control logic unit 204 and the corresponding cache 205 appear in pairs, and both must exist simultaneously.

[0049] The consistency cache control logic unit 204 is responsible for managing the data of the memory addresses of at least two CXL memory expansion cards. The data in the recently accessed memory addresses can be stored in the corresponding cache 205 to improve the response speed of subsequent accesses.

[0050] Specifically, in the embodiments of this disclosure, the consistent cache control logic unit 204 obtains access address data based on the recorded memory data status information table, mainly including the following application scenarios:

[0051] For example, in the first application scenario, the access address data can be retrieved from the cache.

[0052] Specifically, the consistency cache control logic unit 204 can determine, based on the recorded memory data status information table and the data stored in the cache, whether the data for the access address is stored in the cache and whether the data is valid. Therefore, it can determine that the data for the access address needs to be retrieved from the cache, and then retrieve the data for that access address from the cache. For example, the consistency cache control logic unit 204 can check whether the data for the access address is stored in the cache based on the memory status information table. If it is stored and valid, the data for the access address can be retrieved directly from the cache. Correspondingly, the consistency cache control logic unit 204 then transmits the retrieved data for the access address to the CPU chip that sent the access request via the interconnect bus 203 and the CXL uplink port control logic unit 201.

[0053] In the second application scenario, the data of the access address can be obtained from the first target CXL memory expansion card corresponding to the access address.

[0054] Specifically, the CXL uplink port control logic unit 201 is used to obtain the identifier of the first target CXL downlink port control logic unit connected to the first target CXL memory expansion card corresponding to the access address according to the preset configuration information and access address; and forward it to the interconnect bus 203 together with the access request; the first target CXL memory expansion card is the CXL memory expansion card corresponding to the access address among at least two CXL memory expansion cards.

[0055] In this embodiment, the preset configuration information may include the identifier of each CXL downlink port control logic unit and the correspondence between the address segments handled by the CXL memory expansion card connected to that CXL downlink port control logic unit. This correspondence is pre-configured and stored in each CXL uplink port control logic unit 201. Based on this, each time an access request is received, the CXL memory expansion card to which the access address in the access request belongs can be obtained based on the correspondence in the configuration relationship, thereby accurately and efficiently obtaining the identifier of the corresponding CXL downlink port control logic unit.

[0056] Interconnect bus 203 is used to forward the memory access request and the identifier of the first target CXL downlink port control logic unit 202 together to the consistency cache control logic unit 204;

[0057] The consistency cache control logic unit 204 is also used to determine, based on the recorded memory data status information table and the data stored in the cache, whether the data for the access address is not stored in the cache, or whether the data for the access address stored in the first target CXL memory expansion card is valid. In this case, it is determined that the data for the access address needs to be obtained from the first target CXL memory expansion card. An access request is sent to the first target CXL memory expansion card via the interconnect bus and the first target CXL downlink port control logic unit 202, so that the first target CXL memory expansion card can read the data from memory and return the data. In this embodiment, the link for returning the data is the reverse link of the access request data. Specifically, the first target CXL memory expansion card returns the data to the consistency cache control logic unit 204 via the first target CXL downlink port control logic unit 202 and the interconnect bus 203. The consistency cache control logic unit 204 then transmits the data to the CPU chip that sent the access request via the interconnect bus 203 and the CXL uplink port control logic unit 201.

[0058] Alternatively, in this embodiment, the data can be read from memory by the first target CXL memory expansion card and then directly transmitted to the CPU chip that sent the access request via the interconnect bus 203 and the CXL uplink port control logic unit 201.

[0059] In the third application scenario, access address data can be obtained from other CPU chips.

[0060] Specifically, the consistency cache control logic unit 204 is also used to determine, based on the recorded memory data status information table and the data stored in the cache 205, whether the data corresponding to the access address in the first target CXL memory expansion card corresponding to the access address is invalid; or whether the data for the access address is not stored in the cache and the data for the access address in the first target CXL memory expansion card corresponding to the access address is invalid; and whether the valid data for the access address is stored in the memory of other CPUs. In this case, a listening command is sent to other CPU chips via the interconnect bus 203 and other CXL uplink port control logic units 201. The listening command carries the access address so that other CPU chips can obtain the data at the access address and return the data. Similarly, the link for returning data is the reverse link of sending the listening command. Specifically, the data obtained by other CPU chips is transmitted to the consistency cache control logic unit 204 via other CXL uplink port control logic units 201 and interconnect bus 203.

[0061] In this embodiment, "other CPUs" refers to CPUs different from the one that issued the access request. "Other CXL uplink port control logic units 201" refers to CXL uplink port control logic units connected to other CPUs.

[0062] In this embodiment, by employing the above three scenarios, it is possible to enable any one of the at least two CPUs to accurately and efficiently access and process the data in any one of the at least two CXL memory expansion cards, thereby effectively enabling at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0063] The following details the processing of data storage requests by the CXL Switch chip 200 in this embodiment, which can specifically include the following two implementation methods:

[0064] In the first implementation, when writing data, it can be written only in cache 205.

[0065] Specifically, for each CXL uplink port control logic unit 201, the CXL uplink port control logic unit 201 is also used to receive a first storage request sent by the connected CPU chip, the first storage request carrying a first storage address and first data;

[0066] The CXL uplink port control logic unit 201 is also used to obtain the identifier of the second target CXL downlink port control logic unit 202 connected to the second target CXL memory expansion card corresponding to the first storage address according to the preset configuration information and the first storage address; and forward it to the interconnect bus 203 together with the first storage request; the second target CXL memory expansion card is the CXL memory expansion card corresponding to the first storage address among at least two CXL memory expansion cards;

[0067] Interconnect bus 203 is used to forward the first storage request and the identifier of the second target CXL downlink port control logic unit 202 together to the consistency cache control logic unit 204;

[0068] The consistency cache control logic unit 204 is used to store the first storage address, the first data, and the identifier of the second target CXL downlink port control logic unit 202 in the cache 205, and update the memory data status information table.

[0069] The data storage mechanism of this implementation prioritizes writing all data into the cache. Then, when the data in the cache becomes invalid, it is written to the corresponding CXL memory expansion card.

[0070] In this embodiment, while storing data in cache 205, it is also necessary to store the identifier of the corresponding second target CXL downlink port control logic unit 202. Specifically, an additional field can be added during storage to store the identifier so that when the first data becomes invalid, it can be stored in the corresponding CXL memory expansion card in a timely and accurate manner.

[0071] For example, alternatively, in the data storage process of this implementation, all data received is first stored in cache 205, so that the data in the cache will be filled quickly. Specifically, when the data in cache 205 is full, the data that is about to expire can be re-cached to a CXL memory expansion card.

[0072] Specifically, cache 205 is also used to identify invalid data when the data is full. The method by which cache 205 identifies invalid data can be by selecting the data with the earliest storage time, the data with the lowest usage frequency, or other methods, which are not limited here. Then, cache 205 is also used to send the invalid data, the corresponding second storage address, and the identifier of the corresponding third target CXL downlink port control logic unit 202 to the interconnect bus 203. The interconnect bus 203, based on the identifier of the third target CXL downlink port control logic unit, sends the invalid data and the corresponding second storage address to the connected third target CXL memory expansion card through the corresponding third target CXL downlink port control logic unit, so that the third target CXL memory expansion card can write the invalid data from the cache to the corresponding second storage address.

[0073] The consistency cache control logic unit 204 is used to update the memory data status information table based on the failed data.

[0074] The second implementation method allows data to be written simultaneously to cache 205 and the corresponding CXL memory expansion card.

[0075] Specifically, for each CXL uplink port control logic unit 201, the CXL uplink port control logic unit 201 is also used to receive a second storage request sent by the connected CPU chip, the second storage request carrying a third storage address and second data.

[0076] The CXL uplink port control logic unit 201 is also used to obtain the identifier of the fourth target CXL downlink port control logic unit connected to the fourth target CXL memory expansion card to be stored, based on the preset configuration information and the third storage address; and forward it to the interconnect bus 203 together with the second storage request; the fourth target CXL memory expansion card is the CXL memory expansion card corresponding to the third storage address among at least two CXL memory expansion cards.

[0077] The interconnect bus 203 is used to forward the second storage request to the consistency cache control logic unit 204; at the same time, based on the identifier of the fourth target CXL downlink port control logic unit, it sends the second storage request to the connected fourth target CXL memory expansion card through the corresponding fourth target CXL downlink port control logic unit, so that the fourth target CXL memory expansion card can write the second data at the corresponding third storage address.

[0078] The consistency cache control logic unit 204 is used to store the third storage address and the second data in the cache 205 and update the memory data status information table.

[0079] The CXL Switch chip 200 in this embodiment, through the configured consistency cache control logic unit 204 and cache 205, employs the above two data storage processing methods to enable any CPU among at least two CPUs to perform accurate and efficient data storage processing on any CXL memory expansion card among at least two CXL memory expansion cards, thereby effectively enabling at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0080] like Figure 2 As shown, the CXL Switch chip 200 in this embodiment also includes a FabricManager (FM) management logic unit 206, which is used to configure the correspondence between the storage address segments corresponding to each CXL memory expansion card and the identifiers of the corresponding connected CXL downlink port control logic units 202, and transmit the correspondence to each CXL uplink port control logic unit 201 through the interconnect bus 203. In this way, the correspondence can be stored as preset configuration information in each CXL uplink port control logic unit 201, providing effective support for subsequent data access and data storage.

[0081] In this embodiment, a CXL memory pooling system can be built using a mature and reliable CXL memory expansion card, without relying on a newly developed CXL memory card that supports pooling functionality. Moreover, in this embodiment, by designing a cache in the CXL Switch chip 200, compared to designing a cache in the CXL memory card, the latency of CPU accessing the CXL memory pool can be reduced more effectively, thereby improving access efficiency.

[0082] Figure 3 This is an application example diagram of a CXL memory card with CXL pooling functionality provided in this disclosure. For example... Figure 3 As shown above, Figure 2The difference between this embodiment and the previous one is that, in order to implement CXL pooling, a memory card that supports CXL pooling is used. Since the memory card supports pooling, the CXL switch chip does not need to be configured. Figure 2 The consistency cache control logic unit 204 and cache 205 are included.

[0083] like Figure 3 As shown, the CXL Switch chip 300 in this embodiment includes: at least two CXL uplink port control logic units 301, at least two CXL downlink port control logic units 302, and an interconnect bus 303;

[0084] Among them, one end of at least two CXL uplink port control logic units 301 is connected to at least two CPU chips; one end of each CXL uplink port control logic unit 301 is connected to one CPU chip.

[0085] At least two CXL downlink port control logic units 302 are connected at one end to at least two CXL memory cards with pooling function, and each CXL downlink port control logic unit 302 is connected at one end to a CXL memory card with pooling function.

[0086] The other end of each CXL uplink port control logic unit 301 and the other end of each CXL downlink port control logic unit 302 are respectively connected to the interconnect bus 303.

[0087] exist Figure 3 In the architecture shown, the process of the CPU chip accessing the CXL memory pool can include the following steps:

[0088] 1. Taking memory read as an example, the CPU chip sends a memory read request to the CXL Switch chip 300; the memory read request can carry the request type and memory address; the request type can identify whether the request is a read request or a write request;

[0089] 2. The CXL uplink port control logic unit 301 of the CXL Switch chip 300 can determine the identifier of the CXL downlink port control logic unit 302 to be accessed according to the preset configuration information and memory access address; and send a memory read request and the identifier of the CXL downlink port control logic unit 302 to the interconnect bus 303.

[0090] 3. The interconnect bus 303 sends a memory read request to the corresponding CXL downlink port control logic unit 302 based on the identifier of the CXL downlink port control logic unit 302;

[0091] 4. The CXL downlink port control logic unit 302 sends the memory read request to the CXL memory card with pooling function;

[0092] 5. The CXL memory card determines whether the latest data corresponding to the memory address exists in other CPU chips. If the latest data exists in other CPU chips, the CXL memory card sends a listen command to notify other CPU chips to write the latest data back to the CXL memory card. The listen command is sent to other CPU chips via the CXL downlink port control logic unit 302, interconnect bus 303, and the CXL uplink port control logic unit 301 corresponding to the other CPU in the CXL Switch chip 300. The other CPU chips send the latest data corresponding to the memory address to the CXL memory card via the CXL uplink port control logic unit 301, interconnect bus 303, and CXL downlink port control logic unit 302 corresponding to the other CPU in the CXL Switch chip 300. Then, the CXL memory card sends the acquired data to the CPU chip that issued the memory access request via the CXL downlink port control logic unit 302, interconnect bus 303, and CXL uplink port control logic unit 301.

[0093] If the CXL memory card determines that the latest data corresponding to the memory address is in the CXL memory card, the CXL memory card directly reads the data at that memory address and sends it to the CPU chip that issued the memory access request via the CXL downlink port control logic unit 302, interconnect bus 303, and CXL uplink port control logic unit 301 of the CXL Switch chip 300.

[0094] With the above Figure 3 Compared to the embodiments shown, Figure 1 and Figure 2 In the illustrated embodiment, the CXL memory expansion card is a memory card that supports memory expansion, but it does not support pooling functionality. Therefore, this type of CXL memory expansion card does not support the use of... Figure 3 The CXLSwitch chip shown implements memory sharing. At this point, it is necessary to use... Figure 1 or Figure 2 The architecture shown implements memory sharing.

[0095] After discussing with the above Figure 3 Compared to the embodiments shown, Figure 1 and Figure 2 The illustrated embodiment, through the coherence cache control logic unit and cache set in the CXL Switch chip, can effectively enable at least two CPUs to share the memory of at least two memory expansion cards. Figure 1 and Figure 2The technical solution of the illustrated embodiment can utilize the mature and reliable CXL memory expansion card to build a CXL memory pooling system without relying on newly developed CXL memory cards that support pooling functionality. Furthermore, in this embodiment, by designing a cache within the CXL switch chip, compared to designing a cache within the CXL memory card, the latency of CPU accessing the CXL memory pool can be reduced more effectively.

[0096] Figure 4 This is a schematic diagram based on the third embodiment of this disclosure; as shown Figure 5 As shown, this embodiment provides a method based on the above... Figure 1 or Figure 2 The data memory access processing method of the chip in the illustrated embodiment may specifically include the following steps:

[0097] S401. For each CXL uplink port control logic unit in the CXL Switch chip, the CXL uplink port control logic unit receives a memory access request sent by the connected CPU chip. The memory access request carries a memory access address. The memory access address is the address in any one of the at least two CXL memory expansion cards. The memory access request is then forwarded to the interconnect bus.

[0098] S402, The interconnect bus forwards memory access requests to the consistency cache control logic unit;

[0099] S403, the consistent cache control logic unit, performs data access processing based on memory access requests.

[0100] The data access processing method in this embodiment is as described above. Figure 1 or Figure 2 The CXL Switch chip in the illustrated embodiment implements data access processing for at least two CXL memory expansion cards via at least two CPUs. For a detailed explanation of the implementation principle, please refer to the above. Figure 2 The relevant descriptions of the embodiments shown will not be repeated here.

[0101] The data access processing method in this embodiment, based on the coherence cache control logic unit in the CXL Switch chip, can perform data access processing on memory access requests, providing effective support for at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0102] Figure 5 This is a schematic diagram based on the fourth embodiment of this disclosure; the data memory access processing method of the chip in this embodiment, as described above... Figure 4 Based on the technical solutions of the illustrated embodiments, taking data access as an example, the technical solutions of this disclosure will be further described in detail. Figure 5As shown, the data memory access processing method of the chip in this embodiment may specifically include the following steps:

[0103] The S501 and CXL uplink port control logic units receive access requests sent by the connected CPU chips, which carry access addresses, and forward the access requests to the interconnect bus.

[0104] S502, the interconnect bus forwards access requests to the consistency cache control logic unit;

[0105] The S503 coherent cache control logic unit obtains the access address data based on the recorded memory data status information table; and transmits it to the CPU chip through the interconnect bus and CXL uplink port control logic unit.

[0106] For example, step S503, in its specific implementation, can include the following three scenarios:

[0107] Scenario 1: When the consistent cache control logic unit determines that it needs to retrieve data with an access address from the cache based on the recorded memory data status information table and the data stored in the cache, it retrieves the data with the access address from the cache.

[0108] Scenario 2: When the consistent cache control logic unit determines that it needs to obtain memory data from the first target CXL memory expansion card based on the recorded memory data status information table and the data stored in the cache, it sends an access request to the first target CXL memory expansion card through the interconnect bus and the first target CXL downlink port control logic unit, based on the identifier of the first target CXL downlink port control logic unit obtained in advance. This allows the first target CXL memory expansion card to read the data from memory and return the data. The first target CXL memory expansion card is the CXL memory expansion card corresponding to the access address among at least two CXL memory expansion cards. The first target CXL downlink port control logic unit is the CXL downlink port control logic unit connected to the first target CXL memory expansion card.

[0109] At this point, correspondingly, when the consistency cache control logic unit determines that memory data needs to be obtained from the first target CXL memory expansion card based on the recorded memory data status information table and the data stored in the cache, before sending an access request to the first target CXL memory expansion card through the interconnect bus and the first target CXL downlink port control logic unit based on the pre-obtained identifier of the first target CXL downlink port control logic unit, it may also include:

[0110] The CXL uplink port control logic unit obtains the identifier of the first target CXL downlink port control logic unit connected to the first target CXL memory expansion card corresponding to the access address based on the preset configuration information and access address; and forwards it to the interconnect bus along with the access request.

[0111] The interconnect bus forwards the memory access request and the identifier of the first target CXL downlink port control logic unit to the consistency cache control logic unit.

[0112] Scenario 3: When the coherent cache control logic unit determines that the data at the access address is stored in the memory of another CPU based on the recorded memory data status information table and the data stored in the cache, it sends a listening command to the other CPU chip through the interconnect bus and other CXL uplink port control logic units. The listening command carries the access address so that the other CPU chip can obtain the data at the access address and return the data.

[0113] The three scenarios described above in this embodiment correspond to the above... Figure 2 For details on the three application scenarios shown in the embodiments, please refer to the above. Figure 2 The relevant descriptions of the embodiments shown will not be repeated here.

[0114] The chip data access processing method of this embodiment, by adopting the above three scenarios, enables any one of at least two CPUs to accurately and efficiently access data in any one of at least two CXL memory expansion cards, providing effective support for at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0115] Figure 6 This is a schematic diagram according to the fifth embodiment of this disclosure; as shown Figure 6 As shown, the data memory access processing method of the chip in this embodiment is based on the above... Figure 4 Based on the technical solution of the illustrated embodiment, taking data storage as an example, the specific steps may include the following:

[0116] The S601 and CXL uplink port control logic units receive a first storage request sent by the connected CPU chip. The first storage request carries a first storage address and first data. The first storage request is then forwarded to the interconnect bus.

[0117] S602, the CXL uplink port control logic unit obtains the identifier of the second target CXL downlink port control logic unit connected to the second target CXL memory expansion card corresponding to the first storage address according to the preset configuration information and the first storage address; and forwards it to the interconnect bus together with the first storage request; the second target CXL memory expansion card is the CXL memory expansion card corresponding to the first storage address among at least two CXL memory expansion cards;

[0118] S603, while the interconnect bus forwards the first storage request to the consistency cache control logic unit, it also forwards the identifier of the second target CXL downlink port control logic unit to the consistency cache control logic unit.

[0119] S604, the consistency cache control logic unit stores the first storage address, the first data and the identifier of the acquired second target CXL downlink port control logic unit in the cache, and updates the memory data status information table;

[0120] Further, this embodiment may also include the following steps:

[0121] (a) When the cache is full, it identifies invalid data and sends the invalid data, the corresponding second storage address, and the identifier of the corresponding third target CXL downlink port control logic unit to the interconnect bus. The interconnect bus, based on the identifier of the third target CXL downlink port control logic unit, sends the invalid data and the corresponding second storage address to the connected third target CXL memory expansion card through the corresponding third target CXL downlink port control logic unit, so that the third target CXL memory expansion card can write the invalid data in the cache to the corresponding second storage address.

[0122] (b) The consistency cache control logic unit updates the memory data status information table based on the invalidated data.

[0123] Specifically, the second data can be extended with fields to store the identifier of the corresponding second target CXL downlink port control logic unit.

[0124] Figure 6 The data storage mechanism provided in the illustrated embodiment corresponds to the above. Figure 2 For details regarding the data storage method of the first implementation in the illustrated embodiment, please refer to the above. Figure 2 The relevant descriptions of the embodiments shown will not be repeated here.

[0125] The CXL Switch chip 200 in this embodiment, through the configured consistency cache control logic unit 204 and cache 205, and using the above-mentioned data storage processing, enables any one of at least two CPUs to perform accurate and efficient data storage processing on any one of at least two CXL memory expansion cards, thus providing effective support for at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0126] Figure 7 This is a schematic diagram according to the sixth embodiment of this disclosure; as shown Figure 7 As shown, the data memory access processing method of the chip in this embodiment is based on the above... Figure 4 Based on the technical solution of the illustrated embodiment, taking data storage as an example, the specific steps may include the following:

[0127] The S701 and CXL uplink port control logic units receive a second storage request sent by the connected CPU chip. The second storage request carries a third storage address and second data. The second storage request is then forwarded to the interconnect bus.

[0128] S702, the CXL uplink port control logic unit obtains the identifier of the fourth target CXL downlink port control logic unit connected to the fourth target CXL memory expansion card corresponding to the third storage address according to the preset configuration information and the third storage address; and forwards it to the interconnect bus together with the second storage request; the fourth target CXL memory expansion card is the CXL memory expansion card corresponding to the third storage address among at least two CXL memory expansion cards;

[0129] S703, based on the identifier of the fourth target CXL downlink port control logic unit, the interconnect bus sends a second storage request to the connected fourth target CXL memory expansion card through the corresponding fourth target CXL downlink port control logic unit, so that the fourth target CXL memory expansion card can write second data at the corresponding third storage address;

[0130] The S704 interconnect bus also forwards a second memory request to the consistency cache control logic unit;

[0131] The S705 consistency cache control logic unit stores the third storage address and the second data in the cache and updates the memory data status information table.

[0132] Steps S704-S705 and step S703 may not have a sequential relationship.

[0133] Figure 7 To and Figure 6 The different data storage mechanisms shown in the embodiments correspond to the above. Figure 2 The second implementation shown in the embodiment describes a data storage method. For details, please refer to the above. Figure 2 The relevant descriptions of the embodiments shown will not be repeated here.

[0134] The CXL Switch chip 200 in this embodiment, through the configured consistency cache control logic unit 204 and cache 205, and using the above-mentioned data storage processing, enables any one of at least two CPUs to perform accurate and efficient data storage processing on any one of at least two CXL memory expansion cards, thus providing effective support for at least two CPUs to share the memory of at least two CXL memory expansion cards.

[0135] Further, optionally, this embodiment may also include the following steps:

[0136] (1) Configure the correspondence between the address segments of each CXL memory expansion card and the identifiers of the corresponding connected CXL downlink port control logic units;

[0137] (2) The configured correspondence is stored in the control logic unit of each CXL uplink port through the interconnect bus.

[0138] By establishing the correspondence between the address segments of each configured CXL memory expansion card and the identifiers of the corresponding connected CXL downlink port control logic units, it is easy to... Figures 5-7 The scenario illustrated in this embodiment provides effective support for data access or data storage.

[0139] Specifically, steps (1) and (2) can be implemented by the FM management logic unit. For details, please refer to the above. Figure 2 The relevant descriptions of the embodiments shown will not be repeated here.

[0140] This embodiment may also provide an electronic device, which may include the above-mentioned features. Figure 1 or Figure 2 The CXL Switch chip shown in the embodiment. Specifically, it can be adopted as described above. Figures 4-7 The processing flow of access requests or storage requests in the illustrated embodiment involves memory access processing within shared memory. For details, please refer to the descriptions in the related embodiments above, which will not be repeated here.

[0141] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0142] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A computing fast interconnect converter chip, comprising: The system includes at least two compute fast interconnect uplink port control logic units, at least two compute fast interconnect downlink port control logic units, an interconnect bus, and a consistency cache control logic unit and a cache; the at least two compute fast interconnect uplink port control logic units, the at least two compute fast interconnect downlink port control logic units, the consistency cache control logic unit, and the cache are respectively connected to the interconnect bus; The consistency cache control logic unit and the cache are used to enable at least two central processing unit chips connected to the compute fast interconnect converter chip to share at least two compute fast interconnect memory expansion cards connected through the compute fast interconnect converter chip. The cache is also used to identify invalid data when the data is full, and send the invalid data, the corresponding second storage address, and the identifier of the corresponding third target computing fast interconnect downlink port control logic unit to the interconnect bus. The interconnect bus then sends the invalid data and the corresponding second storage address to the connected third target computing fast interconnect memory expansion card through the third target computing fast interconnect downlink port control logic unit, so that the third target computing fast interconnect memory expansion card can write the invalid data in the cache to the corresponding second storage address. It also includes a structure manager management logic unit, used to configure the correspondence between the address segments of each of the compute fast interconnect memory expansion cards and the identifiers of the corresponding connected compute fast interconnect downlink port control logic units; and to transmit the correspondence to each of the compute fast interconnect uplink port control logic units through the interconnect bus.

2. The chip according to claim 1, wherein, For each of the aforementioned compute fast interconnect uplink port control logic units, the compute fast interconnect uplink port control logic unit is used to receive a memory access request sent by the connected central processing unit chip, the memory access request carrying a memory access address; the memory access address is an address in any of the at least two compute fast interconnect memory expansion cards; the memory access request is an access request or storage request from the central processing unit chip for any of the at least two compute fast interconnect memory expansion cards; the memory access address includes an access address or a storage address; The interconnect bus is used to forward the memory access request to the consistency cache control logic unit; The consistent cache control logic unit is used to perform data access processing based on the access request.

3. The chip according to claim 1, wherein, For each of the aforementioned compute fast interconnect uplink port control logic units, the compute fast interconnect uplink port control logic unit is used to receive an access request sent by the connected central processing unit chip, the access request carrying an access address; The interconnect bus is used to forward the access request to the consistency cache control logic unit; The consistency cache control logic unit is used to obtain the data of the access address based on the recorded memory data status information table; and transmit it to the central processing unit chip through the interconnect bus and the compute fast interconnect uplink port control logic unit.

4. The chip according to claim 3, wherein, The compute fast interconnect uplink port control logic unit is used to obtain the identifier of the first target compute fast interconnect downlink port control logic unit connected to the first target compute fast interconnect memory expansion card corresponding to the access address according to preset configuration information and the access address; and forward it to the interconnect bus together with the access request; the first target compute fast interconnect memory expansion card is the compute fast interconnect memory expansion card corresponding to the access address among the at least two compute fast interconnect memory expansion cards; The interconnect bus is used to forward the access request and the identifier of the first target computing fast interconnect downlink port control logic unit to the consistency cache control logic unit. The consistency cache control logic unit is further configured to, based on the recorded memory data status information table and the data stored in the cache, when it is determined that memory data needs to be obtained from the first target computing fast interconnect memory expansion card, send the access request to the first target computing fast interconnect memory expansion card through the interconnect bus and the first target computing fast interconnect downlink port control logic unit, so that the first target computing fast interconnect memory expansion card can read the data from memory and return the data.

5. The chip according to claim 3, wherein, The consistency cache control logic unit is further configured to, based on the recorded memory data status information table and the data stored in the cache, when determining that the data of the access address is stored in the memory of other central processing units, send a listening command to other central processing unit chips through the interconnect bus and other computing fast interconnect uplink port control logic unit. The listening command carries the access address so that the other central processing unit chips can obtain the data of the access address and return the data.

6. The chip according to claim 3, wherein, The consistent cache control logic unit is used to retrieve the data of the access address from the cache when it is determined that the data of the access address needs to be retrieved from the cache based on the recorded memory data status information table and the data stored in the cache.

7. The chip according to claim 2, wherein, For each of the aforementioned compute fast interconnect uplink port control logic units, the compute fast interconnect uplink port control logic unit is further configured to receive a first storage request sent by the connected central processing unit chip, wherein the first storage request carries a first storage address and first data; The compute fast interconnect uplink port control logic unit is further configured to obtain, according to preset configuration information and the first storage address, the identifier of the second target compute fast interconnect downlink port control logic unit connected to the second target compute fast interconnect memory expansion card corresponding to the first storage address; and forward it to the interconnect bus together with the first storage request; the second target compute fast interconnect memory expansion card is the compute fast interconnect memory expansion card corresponding to the first storage address among the at least two compute fast interconnect memory expansion cards; The interconnect bus is used to forward the first storage request and the identifier of the second target computing fast interconnect downlink port control logic unit to the consistency cache control logic unit. The consistency cache control logic unit is used to store the first storage address, the first data, and the identifier of the second target computing fast interconnect downlink port control logic unit in the cache, and update the memory data status information table.

8. The chip according to claim 7, wherein, The consistency cache control logic unit is used to update the memory data status information table based on the failed data.

9. The chip according to claim 2, wherein, For each of the aforementioned compute fast interconnect uplink port control logic units, the compute fast interconnect uplink port control logic unit is further configured to receive a second storage request sent by the connected central processing unit chip, the second storage request carrying a third storage address and second data; The compute fast interconnect uplink port control logic unit is further configured to obtain, according to preset configuration information and the third storage address, the identifier of the fourth target compute fast interconnect downlink port control logic unit connected to the fourth target compute fast interconnect memory expansion card corresponding to the third storage address; and forward it to the interconnect bus together with the second storage request; the fourth target compute fast interconnect memory expansion card is the compute fast interconnect memory expansion card corresponding to the third storage address among the at least two compute fast interconnect memory expansion cards; The interconnect bus is used to forward the second storage request to the consistency cache control logic unit; at the same time, based on the identifier of the fourth target computing fast interconnect downlink port control logic unit, the second storage request is sent to the connected fourth target computing fast interconnect memory expansion card through the corresponding fourth target computing fast interconnect downlink port control logic unit, so that the fourth target computing fast interconnect memory expansion card can write the second data at the corresponding third storage address; The consistency cache control logic unit is used to store the third storage address and the second data in the cache and update the memory data status information table.

10. A data memory access processing method based on the chip according to any one of claims 1-9, wherein, The method includes: For each compute fast interconnect uplink port control logic unit, the compute fast interconnect uplink port control logic unit receives a memory access request sent by the connected central processing unit chip, the memory access request carrying a memory access address; the memory access address is an address in any of the at least two compute fast interconnect memory expansion cards; and forwards the memory access request to the interconnect bus; The interconnect bus forwards the memory access request to the consistency cache control logic unit; The consistent cache control logic unit performs data access processing based on the access request.

11. The method according to claim 10, wherein, The compute fast interconnect uplink port control logic unit receives memory access requests from the connected central processing unit chip, including: The computing fast interconnect uplink port control logic unit receives an access request sent by the connected central processing unit chip, the access request carrying an access address; The consistent cache control logic unit performs data access processing based on the memory access request, including: The consistency cache control logic unit obtains the data of the access address based on the recorded memory data status information table; and transmits it to the central processing unit chip through the interconnect bus and the compute fast interconnect uplink port control logic unit.

12. The method according to claim 11, wherein, The consistent cache control logic unit obtains the data of the access address based on the recorded memory data status information table, including: The consistent cache control logic unit, based on the recorded memory data status information table and the data stored in the cache, determines when it is necessary to retrieve the data of the access address from the cache, and then retrieves the data of the access address from the cache.

13. The method according to claim 11, wherein, The consistent cache control logic unit obtains the data of the access address based on the recorded memory data status information table, including: The consistency cache control logic unit, based on the recorded memory data status information table and the data stored in the cache, determines when it needs to obtain memory data from the first target compute fast interconnect memory expansion card. Based on the pre-acquired identifier of the first target compute fast interconnect downlink port control logic unit, it sends the access request to the first target compute fast interconnect memory expansion card via the interconnect bus and the first target compute fast interconnect downlink port control logic unit. This allows the first target compute fast interconnect memory expansion card to read data from memory and return the data. The first target compute fast interconnect memory expansion card is the compute fast interconnect memory expansion card corresponding to the access address among the at least two compute fast interconnect memory expansion cards. The first target compute fast interconnect downlink port control logic unit is a compute fast interconnect downlink port control logic unit connected to the first target compute fast interconnect memory expansion card. When the consistency cache control logic unit determines that memory data needs to be obtained from the first target computing fast interconnect memory expansion card based on the recorded memory data status information table and the data stored in the cache, before sending the access request to the first target computing fast interconnect memory expansion card through the interconnect bus and the first target computing fast interconnect downlink port control logic unit based on the pre-acquired identifier of the first target computing fast interconnect downlink port control logic unit, the method further includes: The compute fast interconnect uplink port control logic unit obtains the identifier of the first target compute fast interconnect downlink port control logic unit connected to the first target compute fast interconnect memory expansion card corresponding to the access address according to the preset configuration information and the access address; and forwards it to the interconnect bus together with the access request. The interconnect bus forwards the memory access request and the identifier of the first target compute fast interconnect downlink port control logic unit to the consistency cache control logic unit.

14. The method according to claim 11, wherein, The consistent cache control logic unit obtains the data of the access address based on the recorded memory data status information table, including: Based on the recorded memory data status information table and the data stored in the cache, when the consistency cache control logic unit determines that the data of the access address is stored in the memory of other central processing units, it sends a listening command to other central processing unit chips through the interconnect bus and other computing fast interconnect uplink port control logic unit. The listening command carries the access address so that the other central processing unit chips can obtain the data of the access address and return the data.

15. The method according to claim 10, wherein, The compute fast interconnect uplink port control logic unit receives memory access requests from the connected central processing unit chip, including: The computing fast interconnect uplink port control logic unit receives a first storage request sent by the connected central processing unit chip, the first storage request carrying a first storage address and first data; The consistent cache control logic unit performs data access processing based on the memory access request, including: The consistency cache control logic unit stores the first storage address, the first data, and the identifier of the pre-acquired second target computing fast interconnect downlink port control logic unit in the cache, and updates the memory data status information table; Before the consistency cache control logic unit stores the first storage address, the first data, and the identifier of the pre-acquired second target computing fast interconnect downlink port control logic unit in the cache, and updates the memory data status information table, the method further includes: The compute fast interconnect uplink port control logic unit obtains the identifier of the second target compute fast interconnect downlink port control logic unit connected to the second target compute fast interconnect memory expansion card corresponding to the first storage address according to the preset configuration information and the first storage address; and forwards it to the interconnect bus together with the first storage request; the second target compute fast interconnect memory expansion card is the compute fast interconnect memory expansion card corresponding to the first storage address among the at least two compute fast interconnect memory expansion cards; While forwarding the first storage request to the consistency cache control logic unit, the interconnect bus also forwards the identifier of the second target compute fast interconnect downlink port control logic unit to the consistency cache control logic unit.

16. The method according to claim 15, wherein, The method further includes: When the cache is full, it identifies invalid data and sends the invalid data, the corresponding second storage address, and the identifier of the corresponding third target computing fast interconnect downlink port control logic unit to the interconnect bus. The interconnect bus, based on the identifier of the third target computing fast interconnect downlink port control logic unit, sends the invalid data and the corresponding second storage address to the connected third target computing fast interconnect memory expansion card through the corresponding third target computing fast interconnect downlink port control logic unit, so that the third target computing fast interconnect memory expansion card can write the invalid data in the cache to the corresponding second storage address. The consistency cache control logic unit updates the memory data status information table based on the invalidated data.

17. The method according to claim 10, wherein, The compute fast interconnect uplink port control logic unit receives memory access requests from the connected central processing unit chip, including: The computing fast interconnect uplink port control logic unit receives a second storage request sent by the connected central processing unit chip, the second storage request carrying a third storage address and second data; The consistent cache control logic unit performs data access processing based on the memory access request, including: The consistency cache control logic unit stores the third storage address and the second data in the cache and updates the memory data status information table. The method further includes: The compute fast interconnect uplink port control logic unit obtains the identifier of the fourth target compute fast interconnect downlink port control logic unit connected to the fourth target compute fast interconnect memory expansion card corresponding to the third storage address according to the preset configuration information and the third storage address; and forwards it to the interconnect bus together with the second storage request; the fourth target compute fast interconnect memory expansion card is the compute fast interconnect memory expansion card corresponding to the third storage address among the at least two compute fast interconnect memory expansion cards; Based on the identifier of the fourth target computing fast interconnect downlink port control logic unit, the interconnect bus sends the second storage request to the connected fourth target computing fast interconnect memory expansion card through the corresponding fourth target computing fast interconnect downlink port control logic unit, so that the fourth target computing fast interconnect memory expansion card can write the second data at the corresponding third storage address.

18. The method according to any one of claims 13 and 15-17, wherein, The method further includes: Configure the correspondence between the address segments of each of the aforementioned compute fast interconnect memory expansion cards and the identifiers of the corresponding connected compute fast interconnect downlink port control logic units; The correspondence is stored in the control logic unit of each computing fast interconnect uplink port through the interconnect bus.

19. An electronic device comprising a computing fast interconnect converter chip as described in any one of claims 1-9.

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