A method and system for modeling scenarios for storage chip fabrication

Abstract

The application relates to the technical field of storage chips and discloses a scene modeling method for storage chip preparation, which comprises the following steps: generating an internal circuit diagram of a storage chip by means of disassembled parts, identifying an equivalent circuit diagram of the internal circuit diagram, constructing an equivalent circuit model of the equivalent circuit diagram, performing model differentiation on the equivalent circuit model, generating an electric signal modeling result of the storage chip by means of the differentiated model, querying heat generating parts of the storage chip from the disassembled parts, identifying a heat generating circuit diagram of the heat generating parts by means of the internal circuit diagram, constructing a heat generating circuit model of the heat generating circuit diagram, calculating heat generating parameters of the heat generating parts in the heat generating circuit model, querying deformed parts of the storage chip from the disassembled parts, calculating deformed parameters of the deformed parts, constructing an initial deformation model between temperature parameters and the deformed parameters of the deformed parts, and adjusting the accuracy of the initial deformation model by means of a particle swarm algorithm. The application can detail scene modeling while reducing the workload of scene modeling.

Description

TECHNICAL FIELD

[0001] The application relates to a scene modeling method and system for storage chip preparation and belongs to the technical field of storage chips. BACKGROUND

[0002] With the development of chip preparation technology and the development of 5G technology, the quality requirements for prepared storage chips are gradually increasing, for example, high preparation requirements for the thermal stability and electrical signal stability of storage chips. However, the existing technology still cannot meet the preparation quality requirements of storage chips.

[0003] At present, some schemes use scene modeling and simulation simulation to simulate and test various parameters of the storage chip to be put into use. The scene modeling refers to the process of abstracting the running logic of various parameters of the storage chip in operation into a mathematical model. The simulation simulation refers to the process of simulating the running logic of various parameters of the storage chip in operation. Both of them are processes of describing the running logic of the storage chip. However, neither the former nor the latter is modeled in the prior art. The storage chip is modeled as a whole, and the internal parts of the storage chip are not modeled. For example, when the storage chip is installed on a certain A device, the prior art models the electrical signal, temperature and other data of the storage chip as a whole on the A device, and there is no scheme that can model the internal parts of a single storage chip. In addition, the storage chip is the result of circuit integration, which inevitably contains a large number of electronic devices. If these large numbers of electronic devices are modeled one by one, the modeling workload will be huge. Therefore, there is an urgent need for a solution that can detail the scene modeling while reducing the scene modeling workload. SUMMARY

[0004] The application provides a scene modeling method, system and computer readable storage medium for storage chip preparation, which mainly aims to detail the scene modeling while reducing the scene modeling workload.

[0005] To achieve the above-mentioned purpose, the application provides a scene modeling method for storage chip preparation, which comprises the following steps:

[0006] Divide the storage chip into a modeling scene, wherein the modeling scene comprises an electrical signal scene, a temperature scene and a structure scene;

[0007] In the electrical signal scene, the storage chip is disassembled to obtain disassembled parts, the internal circuit diagram of the storage chip is generated by using the disassembled parts, the equivalent circuit diagram of the internal circuit diagram is identified, the equivalent circuit model of the equivalent circuit diagram is constructed, the model of the equivalent circuit model is differentiated to obtain a differentiated model, and the electrical signal modeling result of the storage chip is generated by using the differentiated model.

[0008] In the temperature scenario, a heating component of the storage chip is queried from the disassembled components, a heating circuit diagram of the heating component is identified by using the internal circuit diagram, a heating circuit model of the heating circuit diagram is constructed, a heating parameter belonging to the heating component in the heating circuit model is calculated, the heating parameter is inserted into the heating circuit model, and a temperature modeling result of the storage chip is obtained;

[0009] In the structure scenario, a deformation component of the storage chip is queried from the disassembled components, a deformation parameter of the deformation component is calculated, an initial deformation model between a temperature parameter of the deformation component and the deformation parameter is constructed, the initial deformation model is adjusted in accuracy by using a preset particle swarm algorithm, an adjusted deformation model is obtained, and a structure modeling result of the storage chip is determined by using the adjusted deformation model;

[0010] The electrical signal modeling result, the temperature modeling result and the structure modeling result are taken as a scenario modeling result of the storage chip in the to-be-modeled scenario.

[0011] Optionally, the equivalent circuit diagram of the internal circuit diagram is identified, and the equivalent circuit diagram includes:

[0012] When a first plurality of resistors and a single capacitor are connected in parallel in the internal circuit diagram, the first plurality of resistors is merged by using the following formula to obtain a first merged resistor:

[0013]

[0014] wherein R1 represents the first merged resistor, r1 represents an r1th resistor in the first plurality of resistors, and r1' represents a number of the first plurality of resistors;

[0015] When a second plurality of resistors are connected in series and there is no capacitor between the second plurality of resistors in the internal circuit diagram, the second plurality of resistors is merged to obtain a second merged resistor;

[0016] When a third plurality of resistors are connected in parallel and there is no capacitor between the third plurality of resistors in the internal circuit diagram, the third plurality of resistors is merged by using the following formula to obtain a third merged resistor:

[0017]

[0018] wherein R3 represents the third merged resistor, r3 represents an r3th resistor in the third plurality of resistors, and r3' represents a number of the third plurality of resistors;

[0019] The internal circuit diagram is converted into an equivalent circuit diagram using the first combined resistor, the second combined resistor, and the third combined resistor.

[0020] Optionally, constructing the equivalent circuit model of the equivalent circuit diagram includes:

[0021] Find the input and output terminals in the equivalent circuit diagram.

[0022] Identify the first main circuit resistor at the input terminal, the parallel resistor connected in parallel with the capacitor between the input terminal and the output terminal, and the second main circuit resistor at the output terminal;

[0023] Based on the first main circuit resistance, the parallel resistance, and the second main circuit resistance, an equivalent circuit model of the equivalent circuit diagram is constructed.

[0024] Optionally, the step of performing model differentiation on the equivalent circuit model to obtain a differentiated model includes:

[0025] The equivalent circuit model is differentiated using the following formula to obtain the differentiated model:

[0026]

[0027] in, This represents a differential model, where t represents time, I0(t) represents the input current value, and U1(t), U2(t), and U... n (t) represents the parallel resistance, n represents the number of parallel resistances, m1, m2, m... n Denotes the order of the derivative. Let m1 be the derivative of U1(t). Let m be the m² derivative of U²(t). U n m of (t) n Derivatives of order R, R1, R2, R n Indicates parallel resistors, C1, C2, C n This indicates the capacitor connected in parallel with the parallel resistor.

[0028] Optionally, the heating circuit model for constructing the heating circuit diagram includes:

[0029] Identify the circuit input and output terminals in the heating circuit diagram;

[0030] Based on the circuit input and output terminals, the heating circuit model of the heating circuit diagram is constructed using the following formula:

[0031]

[0032] in, Let w0 represent the total power input to the circuit input terminal, ΔT represent the temperature difference between the circuit input terminal and the circuit output terminal, R0 represent the thermal resistance between the circuit input terminal and the circuit output terminal, and C0 represent the heat capacity corresponding to R0.

[0033] Optionally, calculating the heating parameters belonging to the heating component in the heating circuit model includes:

[0034] Construct a temperature difference model between the input and output temperatures in the heating circuit model;

[0035] Construct the thermal resistance of the heat-generating component;

[0036] The temperature difference model and the thermal resistance of the component are used as heating parameters.

[0037] Optionally, calculating the deformation parameters of the deformable part includes:

[0038] The average distance difference between atoms in the deformed part is calculated using the following formula:

[0039]

[0040] Where y1 represents the average distance difference, d uv This represents the distance between the u-th atom and the v-th atom in the deformed part. u′ represents the average distance between any two atoms in the deformed part. 2 v0 represents the number of atoms in the deformed part, and v0 represents the volume of the deformed part.

[0041] The number of atoms melted in the deformed part can be calculated using the following formula:

[0042]

[0043] Where y2 represents the amount melted. Let represent the average distance between the u1-th neighboring atom and the u2-th neighboring atom of the u-th atom. This indicates that the u-th atom is the center, and... A sphere with radius , express The number of atoms inside, This represents the number of atoms in the u1-th neighborhood, u″″ u Indicates conformity The number of the u-th atom, d0 represents the distance between atomic layers in the deformed part, u 0 Indicates the number of atoms in an atomic layer of a deformed part;

[0044] The average distance difference and the amount of melting are used as the deformation parameters of the deformed part.

[0045] Optionally, constructing an initial deformation model relating the temperature parameters and the deformation parameters of the deformable part includes:

[0046] Obtain the internal circuit diagram, and identify the deformable circuit diagram of the deformable part from the internal circuit diagram;

[0047] The deformed parts in the deformed circuit diagram are integrated to obtain integrated parts;

[0048] Collect historical temperature and deformation parameter values ​​of the integrated parts within a historical time period;

[0049] A temperature-deformation scatter plot is constructed with the historical temperature parameter value on the x-axis and the historical deformation parameter value on the y-axis.

[0050] Determine the first curve model of the coordinate points in the temperature-deformation scatter plot;

[0051] Substituting the temperature parameter and the deformation parameter into the independent and dependent variables of the first curve model, a second curve model is obtained.

[0052] The second curve model is subjected to calculus with respect to the time variable to obtain the initial deformed model.

[0053] Optionally, the step of adjusting the accuracy of the initial deformation model using a preset particle swarm optimization algorithm to obtain an adjusted deformation model includes:

[0054] The preset particle swarm optimization algorithm includes:

[0055] Randomly generate the initial regression coefficients of the initial deformation model;

[0056] Calculate the fitness value between the virtual deformation parameters and the real deformation parameters of the initial deformation model under the initial regression coefficients;

[0057] The individual optimal position and global optimal position of the initial regression coefficients are updated using the fitness values;

[0058] Based on the individual optimal position and the global optimal position, the initial regression coefficients are updated to obtain the updated regression coefficients;

[0059] When the fitness value corresponding to the updated regression coefficient meets the preset fitness value, the initial deformation model is adjusted for accuracy using the updated regression coefficient to obtain the adjusted deformation model.

[0060] To address the aforementioned problems, the present invention also provides a scene modeling system for memory chip fabrication, the system comprising:

[0061] The scene segmentation module is used to segment the scene to be modeled for the memory chip, wherein the scene to be modeled includes electrical signal scene, temperature scene and structural scene;

[0062] An electrical signal modeling module is used to disassemble the memory chip in the electrical signal scenario to obtain disassembled parts, generate an internal circuit diagram of the memory chip using the disassembled parts, identify the equivalent circuit diagram of the internal circuit diagram, construct an equivalent circuit model of the equivalent circuit diagram, perform model differentiation on the equivalent circuit model to obtain a differentiated model, and generate the electrical signal modeling result of the memory chip using the differentiated model.

[0063] The temperature modeling module is used to query the heat-generating components of the memory chip from the disassembled parts under the temperature scenario, identify the heat-generating circuit diagram of the heat-generating components using the internal circuit diagram, construct a heat-generating circuit model of the heat-generating circuit diagram, calculate the heat-generating parameters belonging to the heat-generating components in the heat-generating circuit model, insert the heat-generating parameters into the heat-generating circuit model, and obtain the temperature modeling result of the memory chip.

[0064] The structural modeling module is used to query the deformable parts of the memory chip from the disassembled parts in the structural scenario, calculate the deformation parameters of the deformable parts, construct an initial deformation model between the temperature parameters of the deformable parts and the deformation parameters, adjust the accuracy of the initial deformation model using a preset particle swarm optimization algorithm to obtain an adjusted deformation model, and use the adjusted deformation model to determine the structural modeling result of the memory chip.

[0065] The scene modeling module is used to take the electrical signal modeling result, the temperature modeling result and the structural modeling result as the scene modeling result of the memory chip in the scene to be modeled.

[0066] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0067] At least one processor; and,

[0068] A memory communicatively connected to the at least one processor; wherein,

[0069] The memory stores instructions that can be executed by the at least one processor, which executes the instructions to implement the scene modeling method for memory chip fabrication described above.

[0070] To address the aforementioned issues, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the scene modeling method described above for memory chip fabrication.

[0071] Compared to the problems described in the background art, this embodiment of the invention disassembles the memory chip into multiple subdivided components, thereby enabling detailed modeling of these subdivided components. Furthermore, this embodiment identifies the equivalent circuit diagram of the internal circuit diagram to simplify complex circuit diagrams with numerous components, reducing the workload of subsequent data modeling based on the circuit diagram. Further, this embodiment constructs an equivalent circuit model of the equivalent circuit diagram to abstract the internal circuit logic of the memory chip into a model form. Further, this embodiment performs model differentiation on the equivalent circuit model to observe the changes in voltage and current signals over time and the relationship between voltage and current signals. Further, this embodiment... The internal circuit diagram is used to identify the heating circuit diagram of the heat-generating component, which is then converted into an equivalent circuit diagram containing only the heat-generating component. Further, this embodiment calculates the deformation parameters of the deformable component to calculate the parameters of each deformable component, performing structural scene modeling on each component's data. Further, this embodiment constructs an initial deformation model between the temperature parameters and the deformation parameters of the deformable component to generate a regression model between the temperature parameters and the deformation parameters, thereby determining the relationship between the deformation parameters and temperature changes. Further, this embodiment uses a preset particle swarm optimization algorithm to adjust the accuracy of the initial deformation model, obtaining an adjusted deformation model, which is then used to solve for the unknown regression coefficients in the initial deformation model using the particle swarm optimization algorithm. Therefore, the scene modeling method proposed in this invention for memory chip fabrication can refine scene modeling while reducing the workload of scene modeling. Attached Figure Description

[0072] Figure 1 This is a flowchart illustrating a scene modeling method for memory chip fabrication according to an embodiment of the present invention.

[0073] Figure 2 This is a schematic diagram of the modules for implementing the scene modeling method for memory chip fabrication according to an embodiment of the present invention;

[0074] Figure 3 This is a schematic diagram of the structure of an electronic device that implements the scene modeling method for memory chip fabrication according to an embodiment of the present invention.

[0075] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0076] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0077] This application provides a scene modeling method for memory chip fabrication. The execution entity of this scene modeling method for memory chip fabrication includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the scene modeling method for memory chip fabrication can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0078] Example 1:

[0079] Reference Figure 1 The diagram shown is a flowchart illustrating a scene modeling method for memory chip fabrication according to an embodiment of the present invention. In this embodiment, the scene modeling method for memory chip fabrication includes:

[0080] S1. Divide the memory chip into models, wherein the models include electrical signal models, temperature models, and structural models.

[0081] In this embodiment of the invention, the memory chip refers to a memory with storage function composed of integrated circuits, such as dynamic random access memory (DRAM) and static random access memory (SRAM). The scenario to be modeled refers to the memory chip's operating logic scenario that needs to be abstracted into a mathematical model or simulated. Further, the electrical signal scenario refers to the scenario of changes in current and voltage signals in the circuit of the memory chip under the scenario of input current and input voltage. The temperature scenario refers to the scenario of temperature changes in different regions of the chip under the scenario of input current and input voltage. The structural scenario refers to the scenario of changes in the internal structure (e.g., atoms, crystals, and amorphous materials) of the memory chip under the scenario of input current and input voltage.

[0082] S2. In the electrical signal scenario, the memory chip is disassembled to obtain disassembled parts. The internal circuit diagram of the memory chip is generated using the disassembled parts. The equivalent circuit diagram of the internal circuit diagram is identified. An equivalent circuit model of the equivalent circuit diagram is constructed. The equivalent circuit model is modeled by micro-differentiation to obtain a micro-differentiation model. The electrical signal modeling result of the memory chip is generated using the micro-differentiation model.

[0083] This invention disassembles the memory chip to break it down into multiple subdivided parts, which are then modeled in detail in subsequent steps.

[0084] Optionally, the process of disassembling the memory chip to obtain disassembled parts refers to the process of breaking down the memory chip as a whole into multiple parts.

[0085] Optionally, the process of generating the internal circuit diagram of the memory chip using the disassembled parts refers to the process of abstracting the physical integrated circuit on the memory chip into a circuit diagram, that is, drawing the circuit distribution on the memory chip into a circuit diagram.

[0086] Furthermore, embodiments of the present invention identify the equivalent circuit diagram of the internal circuit diagram to simplify and integrate complex circuit diagrams with a large number of components, thereby reducing the workload of subsequent data modeling based on the circuit diagram.

[0087] The equivalent circuit diagram refers to a simplified circuit diagram that only includes power supply, resistors, and capacitors.

[0088] In one embodiment of the present invention, identifying the equivalent circuit diagram of the internal circuit diagram includes: when there are a first plurality of resistors connected in parallel with a single capacitor in the internal circuit diagram, combining the first plurality of resistors using the following formula to obtain a first combined resistor:

[0089]

[0090] Where R1 represents the first merging resistor, This represents the r1-th resistor in the first plurality of resistors, where r1′ represents the number of the first plurality of resistors.

[0091] When there are a second or more resistors connected in series in the internal circuit diagram and there is no capacitor between the second or more resistors, the second or more resistors are combined to obtain a second combined resistor; when there are a third or more resistors connected in parallel in the internal circuit diagram and there is no capacitor between the third or more resistors, the third or more resistors are combined using the following formula to obtain a third combined resistor:

[0092]

[0093] Where R3 represents the third merging resistor, This represents the r3rd resistor in the third or more resistors, where r3′ represents the number of the third or more resistors.

[0094] The internal circuit diagram is converted into an equivalent circuit diagram using the first combined resistor, the second combined resistor, and the third combined resistor.

[0095] Here, the first plurality of resistors refers to a plurality of resistors connected in parallel with a single capacitor.

[0096] Optionally, when there are a second or more resistors connected in series in the internal circuit diagram and there is no capacitor between the second or more resistors, the principle of merging the second or more resistors to obtain the second merged resistor is similar to the principle of merging the first or more resistors to obtain the first merged resistor, and will not be elaborated further here.

[0097] Optionally, the process of converting the internal circuit diagram into an equivalent circuit diagram using the first combined resistor, the second combined resistor, and the third combined resistor refers to the process of replacing the electronic components in the original internal circuit diagram with the first combined resistor, the second combined resistor, and the third combined resistor.

[0098] Furthermore, in this embodiment of the invention, an equivalent circuit model of the equivalent circuit diagram is constructed to abstract the circuit operation logic inside the memory chip into a model form.

[0099] In one embodiment of the present invention, constructing the equivalent circuit model of the equivalent circuit diagram includes: querying the input terminal and output terminal in the equivalent circuit diagram; identifying a first main circuit resistor at the input terminal, a parallel resistor connected in parallel with a capacitor between the input terminal and the output terminal, and a second main circuit resistor at the output terminal; and constructing the equivalent circuit model of the equivalent circuit diagram using the following formula based on the first main circuit resistor, the parallel resistor, and the second main circuit resistor:

[0100] U out (t)=U int (t)-(I0(t)R0+U1(t)+U2(t)...U n (t)+I0(t)R′0)

[0101] Among them, U out (t)=U int (t)-(I0(t)R0+U1(t)+U2(t)...U n (t)+I′0(t)R′0) represents the equivalent circuit model, U int (t) represents the voltage value input to the input terminal, t represents the time, I0(t) represents the current value input to the input terminal, R0 represents the resistance of the first main circuit, U1(t), U2(t), U n (t) represents the voltage across the parallel resistors, n represents the number of parallel resistors, and R′0 represents the resistance of the second main circuit.

[0102] Wherein, the first main circuit resistor refers to the resistor connected in series with the power supply, and the second main circuit resistor refers to the resistor connected in series with the load terminal.

[0103] Furthermore, in this embodiment of the invention, the equivalent circuit model is differentiated to observe the changes of voltage and current signals over time, and the relationship between voltage and current signals.

[0104] In one embodiment of the present invention, the step of model differentiation of the equivalent circuit model to obtain a differentiated model includes: performing model differentiation on the equivalent circuit model using the following formula to obtain a differentiated model:

[0105]

[0106] in, This represents a differential model, where t represents time, I0(t) represents the input current value, and U1(t), U2(t), and U... n (t) represents the parallel resistance, n represents the number of parallel resistances, m1, m2, m... n Denotes the order of the derivative. Let m1 be the derivative of U1(t). Let m be the m² derivative of U²(t). U n m of (t) n Derivatives of order R, R1, R2, R n Indicates parallel resistors, C1, C2, C n This indicates the capacitor connected in parallel with the parallel resistor.

[0107] Optionally, the process of generating the electrical signal modeling result of the memory chip using the micro-differentiation model refers to the process of using the micro-differentiation model as the electrical signal modeling result.

[0108] S3. Under the stated temperature scenario, query the heat-generating components of the memory chip from the disassembled parts, identify the heat-generating circuit diagram of the heat-generating components using the internal circuit diagram, construct a heat-generating circuit model of the heat-generating circuit diagram, calculate the heat-generating parameters belonging to the heat-generating components in the heat-generating circuit model, insert the heat-generating parameters into the heat-generating circuit model, and obtain the temperature modeling result of the memory chip.

[0109] In this embodiment of the invention, the heating element refers to an electronic device that generates heat under the action of input current and input voltage signal, such as a resistor.

[0110] Furthermore, in this embodiment of the invention, the internal circuit diagram is used to identify the heating circuit diagram of the heating component, so as to convert the internal circuit diagram into an equivalent circuit diagram that only includes the heating component.

[0111] The heating circuit diagram refers to the conversion of the internal circuit diagram into an equivalent circuit diagram that only includes the heating component.

[0112] Optionally, the process of identifying the heating circuit diagram of the heating component using the internal circuit diagram refers to removing the non-heating component from the internal circuit diagram and integrating the circuit diagram composed of the remaining heating components into an equivalent circuit diagram.

[0113] In one embodiment of the present invention, constructing the heating circuit model of the heating circuit diagram includes: identifying the circuit input terminal and the circuit output terminal in the heating circuit diagram; and constructing the heating circuit model of the heating circuit diagram using the following formula based on the circuit input terminal and the circuit output terminal:

[0114]

[0115] in, Let w0 represent the total power input to the circuit input terminal, ΔT represent the temperature difference between the circuit input terminal and the circuit output terminal, R0 represent the thermal resistance between the circuit input terminal and the circuit output terminal, and C0 represent the heat capacity corresponding to R0.

[0116] In one embodiment of the present invention, calculating the heating parameters belonging to the heating component in the heating circuit model includes: constructing a temperature difference model between the input and output temperatures in the heating circuit model; and constructing the component thermal resistance of the heating component using the following formula:

[0117]

[0118] Where R0 represents the thermal resistance of the component, α represents the thermal conductivity of the heating component, s represents the area of ​​the heating component, and l represents the thickness of the heating component.

[0119] The temperature difference model and the thermal resistance of the component are used as heating parameters.

[0120] The temperature difference model refers to the temperature difference between the input temperature and the output temperature.

[0121] S4. In the structural scenario, query the deformable parts of the memory chip from the disassembled parts, calculate the deformation parameters of the deformable parts, construct an initial deformation model between the temperature parameters of the deformable parts and the deformation parameters, use a preset particle swarm optimization algorithm to adjust the accuracy of the initial deformation model to obtain an adjusted deformation model, and use the adjusted deformation model to determine the structural modeling result of the memory chip.

[0122] In this embodiment of the invention, the deformable part refers to a part whose internal structure changes with temperature, such as a part on a memory chip that switches between crystal and amorphous components at temperature.

[0123] Furthermore, in this embodiment of the invention, the deformation parameters of the deformable parts are calculated to calculate the parameters of each deformable part, and a structural scene model is performed on the data of each part.

[0124] In one embodiment of the present invention, calculating the deformation parameters of the deformable part includes: calculating the average distance difference between atoms in the deformable part using the following formula:

[0125]

[0126] Where y1 represents the average distance difference, d uv This represents the distance between the u-th atom and the v-th atom in the deformed part. u′ represents the average distance between any two atoms in the deformed part. 2 v0 represents the number of atoms in the deformed part, and v0 represents the volume of the deformed part.

[0127] The number of atoms melted in the deformed part can be calculated using the following formula:

[0128]

[0129] Where y2 represents the amount melted. Let represent the average distance between the u1-th neighboring atom and the u2-th neighboring atom of the u-th atom. This indicates that the u-th atom is the center, and... A sphere with radius , express The number of atoms inside, This represents the number of atoms in the u1-th neighborhood, u″″ u Indicates conformity The number of the u-th atom, d0 represents the distance between atomic layers in the deformed part, u 0 Indicates the number of atoms in an atomic layer of a deformed part;

[0130] The average distance difference and the amount of melting are used as the deformation parameters of the deformed part.

[0131] The average distance difference refers to the average difference in distance between atoms, and the melting quantity refers to the change in the number of atoms inside the deformed part due to the influence of temperature.

[0132] Furthermore, in this embodiment of the invention, an initial deformation model is constructed between the temperature parameters and the deformation parameters of the deformable part, which is then used to generate a regression model between the temperature parameters and the deformation parameters, thereby determining the relationship between the deformation parameters and temperature.

[0133] The initial deformation model refers to a regression model containing unknown regression coefficients between the temperature parameter and the deformation parameter.

[0134] In one embodiment of the present invention, constructing an initial deformation model between the temperature parameters and deformation parameters of the deformable part includes: acquiring an internal circuit diagram and identifying the deformation circuit diagram of the deformable part from the internal circuit diagram; integrating the deformable parts in the deformation circuit diagram to obtain an integrated part; collecting historical temperature parameter values ​​and historical deformation parameter values ​​of the integrated part over a historical period; constructing a temperature-deformation scatter plot between the historical temperature parameter values ​​and the historical deformation parameter values, with the historical temperature parameter values ​​as the abscissa and the historical deformation parameter values ​​as the ordinate; determining a first curve model for the coordinate points in the temperature-deformation scatter plot; substituting the temperature parameters and deformation parameters into the independent and dependent variables in the first curve model to obtain a second curve model; and performing calculus processing on the second curve model with respect to the time variable to obtain the initial deformation model.

[0135] The first curve model refers to the curve function estimated based on the distribution of the temperature-deformation scatter plot, and is not the fitting result of all coordinate points in the temperature-deformation scatter plot. For example, if the distribution of coordinate points in the temperature-deformation scatter plot resembles an oblique line, then y = kx + b is taken as the first curve model; if the distribution of coordinate points in the temperature-deformation scatter plot resembles a parabola, then y squared = 2px is taken as the first curve model.

[0136] Optionally, the principle of integrating the deformed parts in the deformed circuit diagram to obtain the integrated parts is similar to the principle of identifying the equivalent circuit diagram of the internal circuit diagram. For example, when two deformed parts are connected in series, the deformation parameters of the two parts are merged into a sum of deformation parameters. Furthermore, the process of performing calculus processing on the second curve model with respect to the time variable to obtain the initial deformed model refers to performing partial derivative processing on the second curve model with respect to the time variable.

[0137] Furthermore, in this embodiment of the invention, the initial deformation model is adjusted for accuracy using a preset particle swarm optimization algorithm to obtain an adjusted deformation model, which is then used to solve for the unknown regression coefficients in the initial deformation model using the particle swarm optimization algorithm.

[0138] The adjusted deformation model refers to the initial deformation model after the accurate regression coefficients have been solved.

[0139] In one embodiment of the present invention, the step of adjusting the accuracy of the initial deformation model using a preset particle swarm optimization algorithm to obtain an adjusted deformation model includes: the preset particle swarm optimization algorithm includes: randomly generating initial regression coefficients of the initial deformation model; calculating the fitness value between the virtual deformation parameters and the real deformation parameters of the initial deformation model under the initial regression coefficients; updating the individual best position and the global best position of the initial regression coefficients using the fitness value; updating the initial regression coefficients according to the individual best position and the global best position to obtain updated regression coefficients; and when the fitness value corresponding to the updated regression coefficients meets the preset fitness value, adjusting the accuracy of the initial deformation model using the updated regression coefficients to obtain an adjusted deformation model.

[0140] Wherein, the virtual deformation parameter refers to the value of the dependent variable calculated by substituting the initial regression coefficient into the initial deformation model, the real deformation parameter refers to the value of the fixed dependent variable corresponding to the independent variable in the initial deformation model, and the fitness value refers to the error between the virtual deformation parameter and the real deformation parameter.

[0141] For example, the preset particle swarm optimization algorithm includes: randomly generating a set of solutions as the initial positions and velocities of particles (i.e., regression coefficients); calculating the fitness value of each particle according to the objective function of the problem; for each particle, if its fitness value is better than the previous individual best fitness value, then updating the individual best position; in the entire particle swarm, if the fitness value of a certain particle is better than the current global best fitness value, then updating the global best position; updating the velocity and position of the particles: updating the velocity and position of the particles according to the formula corresponding to the particle swarm optimization algorithm; repeating the above steps until the global best fitness value meets the preset accuracy.

[0142] Furthermore, in this embodiment of the invention, the structural modeling result refers to the adjusted deformation model.

[0143] S5. The electrical signal modeling result, the temperature modeling result, and the structural modeling result are used as the scene modeling result of the memory chip in the scene to be modeled.

[0144] Compared to the problems described in the background art, this embodiment of the invention disassembles the memory chip into multiple subdivided components, thereby enabling detailed modeling of these subdivided components. Furthermore, this embodiment identifies the equivalent circuit diagram of the internal circuit diagram to simplify complex circuit diagrams with numerous components, reducing the workload of subsequent data modeling based on the circuit diagram. Further, this embodiment constructs an equivalent circuit model of the equivalent circuit diagram to abstract the internal circuit logic of the memory chip into a model form. Further, this embodiment performs model differentiation on the equivalent circuit model to observe the changes in voltage and current signals over time and the relationship between voltage and current signals. Further, this embodiment... The internal circuit diagram is used to identify the heating circuit diagram of the heat-generating component, which is then converted into an equivalent circuit diagram containing only the heat-generating component. Further, this embodiment calculates the deformation parameters of the deformable component to calculate the parameters of each deformable component, performing structural scene modeling on each component's data. Further, this embodiment constructs an initial deformation model between the temperature parameters and the deformation parameters of the deformable component to generate a regression model between the temperature parameters and the deformation parameters, thereby determining the relationship between the deformation parameters and temperature changes. Further, this embodiment uses a preset particle swarm optimization algorithm to adjust the accuracy of the initial deformation model, obtaining an adjusted deformation model, which is then used to solve for the unknown regression coefficients in the initial deformation model using the particle swarm optimization algorithm. Therefore, the scene modeling method proposed in this invention for memory chip fabrication can refine scene modeling while reducing the workload of scene modeling.

[0145] Example 2:

[0146] like Figure 2 The diagram shown is a functional block diagram of the scene modeling system for memory chip fabrication according to the present invention.

[0147] The scene modeling system 200 for memory chip fabrication described in this invention can be installed in an electronic device. Depending on the functions implemented, the scene modeling system for memory chip fabrication may include a scene segmentation module 201, an electrical signal modeling module 202, a temperature modeling module 203, a structural modeling module 204, a scene modeling module 205, a step return module 206, and a result generation module 207. The modules described in this invention can also be called units, referring to a series of computer program segments that can be executed by the processor of an electronic device and perform a fixed function, stored in the memory of the electronic device.

[0148] In this embodiment of the invention, the functions of each module / unit are as follows:

[0149] The scene segmentation module 201 is used to segment the scene to be modeled of the memory chip, wherein the scene to be modeled includes an electrical signal scene, a temperature scene, and a structural scene.

[0150] The electrical signal modeling module 202 is used to disassemble the memory chip in the electrical signal scenario to obtain disassembled parts, generate an internal circuit diagram of the memory chip using the disassembled parts, identify the equivalent circuit diagram of the internal circuit diagram, construct an equivalent circuit model of the equivalent circuit diagram, perform model differentiation on the equivalent circuit model to obtain a differentiated model, and generate the electrical signal modeling result of the memory chip using the differentiated model.

[0151] The temperature modeling module 203 is used to query the heat-generating components of the memory chip from the disassembled parts under the temperature scenario, identify the heat-generating circuit diagram of the heat-generating components using the internal circuit diagram, construct a heat-generating circuit model of the heat-generating circuit diagram, calculate the heat-generating parameters belonging to the heat-generating components in the heat-generating circuit model, insert the heat-generating parameters into the heat-generating circuit model, and obtain the temperature modeling result of the memory chip.

[0152] The structural modeling module 204 is used to query the deformable parts of the memory chip from the disassembled parts in the structural scenario, calculate the deformation parameters of the deformable parts, construct an initial deformation model between the temperature parameters of the deformable parts and the deformation parameters, adjust the accuracy of the initial deformation model using a preset particle swarm algorithm to obtain an adjusted deformation model, and use the adjusted deformation model to determine the structural modeling result of the memory chip.

[0153] The scene modeling module 205 is used to use the electrical signal modeling result, the temperature modeling result, and the structural modeling result as the scene modeling result of the memory chip in the scene to be modeled.

[0154] In detail, the modules in the scene modeling system 200 for memory chip fabrication described in this embodiment of the invention employ the same methods as described above. Figure 1 The same technical means are used for scene modeling under memory chip fabrication as described in the previous article, and can produce the same technical effect, so they will not be repeated here.

[0155] Example 3:

[0156] like Figure 3 The diagram shown is a structural schematic of an electronic device that implements a scene modeling method for memory chip fabrication according to an embodiment of the present invention.

[0157] The electronic device 1 may include a processor 10, a memory 11, a bus 12 and a communication interface 13, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a scene modeling program for memory chip fabrication.

[0158] The memory 11 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device 1, such as a plug-in portable hard drive, SmartMediaCard (SMC), SecureDigital (SD) card, or FlashCard. Furthermore, the memory 11 can include both internal and external storage units of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as code for scene modeling programs fabricated using memory chips, but also to temporarily store data that has been output or will be output.

[0159] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., scene modeling programs based on memory chips) and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0160] The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. The bus is configured to enable communication between the memory 11 and at least one processor 10, etc.

[0161] Figure 3 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0162] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management device, thereby enabling functions such as charging management, discharging management, and power management. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0163] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0164] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or a standard wired or wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0165] It should be understood that the embodiments described are for illustrative purposes only and are not limited to this structure in the scope of the patent application.

[0166] The scene modeling program for memory chip fabrication stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When run in the processor 10, it can achieve the following:

[0167] The memory chip is divided into models of different scenarios, including electrical signal scenarios, temperature scenarios, and structural scenarios.

[0168] In the electrical signal scenario, the memory chip is disassembled to obtain disassembled parts. The disassembled parts are used to generate the internal circuit diagram of the memory chip. The equivalent circuit diagram of the internal circuit diagram is identified, and the equivalent circuit model of the equivalent circuit diagram is constructed. The equivalent circuit model is modeled by model differentiation to obtain a differentiated model. The differentiated model is used to generate the electrical signal modeling result of the memory chip.

[0169] Under the stated temperature scenario, the heat-generating components of the memory chip are queried from the disassembled parts. The heat-generating circuit diagram of the heat-generating components is identified using the internal circuit diagram. A heat-generating circuit model of the heat-generating circuit diagram is constructed. The heat-generating parameters belonging to the heat-generating components in the heat-generating circuit model are calculated. The heat-generating parameters are then inserted into the heat-generating circuit model to obtain the temperature modeling result of the memory chip.

[0170] In the structural scenario, the deformable parts of the memory chip are queried from the disassembled parts, the deformation parameters of the deformable parts are calculated, an initial deformation model between the temperature parameters of the deformable parts and the deformation parameters is constructed, the initial deformation model is adjusted for accuracy using a preset particle swarm optimization algorithm to obtain an adjusted deformation model, and the structural modeling result of the memory chip is determined using the adjusted deformation model.

[0171] The electrical signal modeling result, the temperature modeling result, and the structural modeling result are used as the scene modeling result of the memory chip in the scene to be modeled.

[0172] Specifically, the processor 10's implementation method for the above instructions can be found in [reference needed]. Figures 1 to 3 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0173] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0174] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0175] The memory chip is divided into models of different scenarios, including electrical signal scenarios, temperature scenarios, and structural scenarios.

[0176] In the electrical signal scenario, the memory chip is disassembled to obtain disassembled parts. The disassembled parts are used to generate the internal circuit diagram of the memory chip. The equivalent circuit diagram of the internal circuit diagram is identified, and the equivalent circuit model of the equivalent circuit diagram is constructed. The equivalent circuit model is modeled by model differentiation to obtain a differentiated model. The differentiated model is used to generate the electrical signal modeling result of the memory chip.

[0177] Under the stated temperature scenario, the heat-generating components of the memory chip are queried from the disassembled parts. The heat-generating circuit diagram of the heat-generating components is identified using the internal circuit diagram. A heat-generating circuit model of the heat-generating circuit diagram is constructed. The heat-generating parameters belonging to the heat-generating components in the heat-generating circuit model are calculated. The heat-generating parameters are then inserted into the heat-generating circuit model to obtain the temperature modeling result of the memory chip.

[0178] In the structural scenario, the deformable parts of the memory chip are queried from the disassembled parts, the deformation parameters of the deformable parts are calculated, an initial deformation model between the temperature parameters of the deformable parts and the deformation parameters is constructed, the initial deformation model is adjusted for accuracy using a preset particle swarm optimization algorithm to obtain an adjusted deformation model, and the structural modeling result of the memory chip is determined using the adjusted deformation model.

[0179] The electrical signal modeling result, the temperature modeling result, and the structural modeling result are used as the scene modeling result of the memory chip in the scene to be modeled.

[0180] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0181] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0182] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0183] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A scene modeling method for memory chip fabrication, characterized in that, The method comprises: dividing a to-be-modeled scene of a storage chip, wherein the to-be-modeled scene comprises an electrical signal scene, a temperature scene and a structure scene; under the electrical signal scene, performing chip disassembly on the storage chip to obtain disassembled parts, generating an internal circuit diagram of the storage chip by using the disassembled parts, identifying an equivalent circuit diagram of the internal circuit diagram, constructing an equivalent circuit model of the equivalent circuit diagram, performing model differentiation on the equivalent circuit model to obtain a differentiated model, and generating an electrical signal modeling result of the storage chip by using the differentiated model; under the temperature scene, querying a heat generating part of the storage chip from the disassembled parts, identifying a heat generating circuit diagram of the heat generating part by using the internal circuit diagram, constructing a heat generating circuit model of the heat generating circuit diagram, calculating a heat generating parameter of the heat generating part in the heat generating circuit model, and inserting the heat generating parameter into the heat generating circuit model to obtain a temperature modeling result of the storage chip; under the structure scene, querying a deformed part of the storage chip from the disassembled parts, calculating a deformation parameter of the deformed part, constructing an initial deformation model between a temperature parameter and the deformation parameter of the deformed part, performing accuracy adjustment on the initial deformation model by using a preset particle swarm algorithm to obtain an adjusted deformation model, and determining a structure modeling result of the storage chip by using the adjusted deformation model; taking the electrical signal modeling result, the temperature modeling result and the structure modeling result as a scene modeling result of the storage chip under the to-be-modeled scene.

2. The method for modeling scenarios against storage chip preparation of claim 1, wherein, The identification of the equivalent circuit diagram of the internal circuit diagram comprises: when a first plurality of resistors and a single capacitor are in parallel in the internal circuit diagram, the first plurality of resistors are merged by using the following formula to obtain a first merged resistor: wherein R1 represents a first combined resistance, wherein Rr1 represents an r1th resistance of the first plurality of resistances, and r1' represents a number of the first plurality of resistances. when a second plurality of resistors are in series and there is no capacitor between the second plurality of resistors in the internal circuit diagram, the second plurality of resistors are merged to obtain a second merged resistor; when a third plurality of resistors are in parallel and there is no capacitor between the third plurality of resistors in the internal circuit diagram, the third plurality of resistors are merged by using the following formula to obtain a third merged resistor: wherein R3 represents a third combined resistance, wherein R3 represents a third combined resistance, wherein R3 represents a third combined resistance, wherein R3 represents a third combined resistance, wherein R3 represents a third combined resistance, wherein R3 represents a third combined resistance, wherein R3 represents a third combined resistance, wherein R3 represents a third combined resistance, wherein R the internal circuit diagram is converted into an equivalent circuit diagram by using the first merged resistor, the second merged resistor and the third merged resistor.

3. The method for modeling scenarios for storage chip preparation of claim 1, wherein, The construction of the equivalent circuit model of the equivalent circuit diagram comprises: querying an input terminal and an output terminal in the equivalent circuit diagram; identifying a first trunk resistor on the input terminal, a parallel resistor in parallel with a capacitor between the input terminal and the output terminal, and a second trunk resistor on the output terminal; constructing an equivalent circuit model of the equivalent circuit diagram according to the first trunk resistor, the parallel resistor and the second trunk resistor.

4. The method for modeling scenarios for storage chip preparation of claim 1, wherein, The model differentiation on the equivalent circuit model to obtain a differentiated model comprises: the model differentiation on the equivalent circuit model by using the following formula to obtain a differentiated model: wherein denotes a differential model, t denotes a time, I0(t) denotes a current value inputted from an input terminal, U1(t), U2(t), U n (t) denotes a parallel resistance, n denotes a number of the parallel resistances, m1, m2, m n denotes a derivative order, denotes an m1-order derivative of U1(t), denotes an m2-order derivative of U2(t), denotes an m n -order derivative of U n (t), R1, R2, R n denotes a parallel resistance, C1, C2, C n denotes a capacitor connected in parallel with the parallel resistance.

5. The method for modeling scenarios for storage chip preparation of claim 1, wherein, The construction of the heat generating circuit model of the heat generating circuit diagram comprises: identifying a circuit input terminal and a circuit output terminal in the heat generating circuit diagram; According to the circuit input end and the circuit output end, a heat circuit model of the heat circuit diagram is constructed by using the following formula: wherein, represents a heating circuit model, w0 represents the total power input at the circuit input, ΔT represents the temperature difference between the circuit input and the circuit output, R0 represents the thermal resistance between the circuit input and the circuit output, and C0 represents the heat capacity corresponding to R0.

6. The method for modeling scenarios for storage chip preparation of claim 1, wherein, The calculation of the heat parameters of the heat parts in the heat circuit model comprises: A temperature difference model between the input end temperature and the output end temperature in the heat circuit model is constructed; A part thermal resistance of the heat part is constructed; The temperature difference model and the part thermal resistance are taken as the heat parameters.

7. The method for modeling scenarios for storage chip preparation of claim 1, wherein, The calculation of the deformation parameters of the deformation part comprises: The average distance of atoms in the deformation part is calculated by using the following formula: where y1 represents the average difference in distance, d uv denotes the distance between the u-th atom and the v-th atom in the deformed part, denotes the average distance between two atoms in the deformed part, u' 2 denotes the number of atoms in the deformed part, v0 denotes the volume of the deformed part; The melting number of atoms in the deformation part is calculated by using the following formula: wherein y2 represents the number of melting, represents the average distance between the u1th neighbor atom and the u2th neighbor atom of the uth atom, represents the number of atoms within a sphere with the uth atom as the center and as the radius, represents the number of atoms within a sphere with the uth atom as the center and represents the number of atoms within a sphere with the uth atom as the center and u1 represents the number of u1th neighbor atoms, u" u represents the number of uth atoms that satisfy represents the distance between the atomic layers in the deformed part, u 0 represents the number of atoms of the atomic layers in the deformed part; The average distance and the melting number are taken as the deformation parameters of the deformation part.

8. The method for modeling scenarios for storage chip preparation of claim 1, wherein, The construction of an initial deformation model between the temperature parameters and the deformation parameters of the deformation part comprises: An internal circuit diagram is obtained, and a deformation circuit diagram of the deformation part is identified from the internal circuit diagram; The deformation parts in the deformation circuit diagram are integrated to obtain integrated parts; Historical temperature parameter values and historical deformation parameter values of the integrated parts in a historical period are collected; A temperature-deformation scatter plot between the historical temperature parameter values and the historical deformation parameter values is constructed with the historical temperature parameter values as the horizontal coordinates and the historical deformation parameter values as the vertical coordinates; A first curve model of coordinate points in the temperature-deformation scatter plot is determined; The temperature parameters and the deformation parameters are substituted into independent variables and dependent variables in the first curve model to obtain a second curve model; Integral processing is performed on the second curve model with respect to a time variable to obtain an initial deformation model.

9. The method for modeling scenarios for storage chip preparation of claim 1, wherein, The initial deformation model is adjusted in precision by using a preset particle swarm algorithm to obtain an adjusted deformation model, comprising: The preset particle swarm algorithm comprises: Initial regression coefficients of the initial deformation model are randomly generated; An adaptability value between virtual deformation parameters and real deformation parameters of the initial deformation model under the initial regression coefficients is calculated; The individual best position and the global best position of the initial regression coefficients are updated by using the adaptability value; The initial regression coefficients are updated according to the individual best position and the global best position to obtain updated regression coefficients; When an adaptability value corresponding to the updated regression coefficients meets a preset adaptability value, the initial deformation model is adjusted in precision by using the updated regression coefficients to obtain an adjusted deformation model.

10. A system for modeling scenarios for storage chip fabrication, the system comprising: The system comprises: A scene division module is configured to divide a to-be-modeled scene of a storage chip, wherein the to-be-modeled scene comprises an electrical signal scene, a temperature scene, and a structure scene; An electrical signal modeling module is configured to, in the electrical signal scene, disassemble the storage chip to obtain disassembled parts, generate an internal circuit diagram of the storage chip by using the disassembled parts, identify an equivalent circuit diagram of the internal circuit diagram, construct an equivalent circuit model of the equivalent circuit diagram, perform model differentiation on the equivalent circuit model to obtain a differentiated model, and generate an electrical signal modeling result of the storage chip by using the differentiated model. The temperature modeling module is configured to query, under the temperature scenario, a heat generating component of the storage chip from the disassembled components, identify a heat generating circuit diagram of the heat generating component by using the internal circuit diagram, construct a heat generating circuit model of the heat generating circuit diagram, calculate a heat generating parameter of the heat generating component in the heat generating circuit model, insert the heat generating parameter into the heat generating circuit model, and obtain a temperature modeling result of the storage chip. The structure modeling module is configured to query, under the structure scenario, a deformation component of the storage chip from the disassembled components, calculate a deformation parameter of the deformation component, construct an initial deformation model between a temperature parameter of the deformation component and the deformation parameter, adjust the accuracy of the initial deformation model by using a preset particle swarm algorithm to obtain an adjusted deformation model, and determine a structure modeling result of the storage chip by using the adjusted deformation model. The scenario modeling module is configured to take the electrical signal modeling result, the temperature modeling result, and the structure modeling result as a scenario modeling result of the storage chip under the to-be-modeled scenario.

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