Neuron circuit
By using pulse width modulation integrated electronic neurons in highly integrated chips, using pulse length to represent data and perform digital weight evaluation, the challenges of existing neural networks in terms of speed, size and energy consumption are solved, and efficient data processing is achieved and low power neuron design.
Patent Information
- Application Number
- CN202411102223.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-16
- Filing Date
- 2024-08-12
- Publication Date
- 2025-02-21
AI Technical Summary
Existing neural networks face challenges in speed, size and energy consumption when implementing efficient neuronal signal processing, especially in highly integrated chips.
Integrated electronic neurons using pulse width modulation represent analog data values through the length of the pulse, and use digital methods to evaluate weighted data, which is converted into current through a three-state buffer to generate output pulses.
Neurons that process data efficiently in highly integrated chips are realized, reducing computational volume and memory access bottlenecks, while reducing power consumption.
Smart Images
Figure CN119494378A_ABST
Abstract
Description
[0001] Neural networks (NNs) determine the technical level of artificial intelligence (AI). They are circuit representations of real neurons in the brain. Their purpose is to simulate these parts of the brain as much as possible in order to achieve human-like intelligence through circuits.
[0002] The main challenges are the speed of neuronal signal processing, the size of neurons, and the energy required to operate such an artificial brain.
[0003] To understand the latest advances in artificial intelligence, it is necessary to understand the basic concepts of different neural networks.
[0004] The most widely used are so-called convolutional neural networks (CNNs). These are used for so-called "deep learning," i.e. a learning process similar to that of the brain. In biology, this is the equivalent of a learning child.
[0005] CNN is most widely used in image processing and image recognition. The advantage of CNN is that it can be completely described by mathematics. Therefore, CNN can be implemented digitally in a digital computer or Field Programmable Gate Array (FPGA).
[0006] CNNs are easy to implement in a digital environment, but their main drawback is that they are computationally expensive due to the presence of multiply accumulate circuits (MACs). There is also a bottleneck in memory access. They also consume a lot of power.
[0007] There is another type of neural network that can extend the concept of neural networks by taking into account time or simultaneity. These spiking neural networks (SNNs) are closer to real biological models.
[0008] As the name suggests, information is not represented by numbers, but by pulses of different heights and times. Since the pulse time is very short, SNN works much faster than CNN. In addition, its power consumption is much lower than CNN.
[0009] In summary, CNN requires huge digital computing power to be implemented; SNN requires analog circuits, which are impossible or difficult to implement in highly integrated circuits with a structure width of less than 10 nanometers.
[0010] The task of the present invention is to propose an advanced neuron that can be implemented in a highly integrated chip.
[0011] This object is achieved according to the invention by the features of the claims.
[0012] In principle, in the present invention, the data (signal) to be processed is neither represented by binary words like CNN nor by pulses of different amplitudes like SNN.
[0013] Analog data is represented by pulses of varying lengths. The data value is encoded based on the length of the pulse.
[0014] This method of representation has great advantages in terms of processing data, since the pulses can be forwarded in a purely digital manner. In addition, they use only one signal line, regardless of the analog value range.
[0015] Therefore, an essential feature of the present invention is the use of integrated electronic neurons whose input and output signals are pulse width modulated.
[0016] The weight data used to evaluate (i.e., multiply) the pulse-width modulated input data is applied digitally to the neurons and converted into current by tri-state buffers that are staggered according to the drive strength.
[0017] The current generated by the tri-state buffer is used to charge and / or discharge the capacitor, and the resulting voltage is converted into pulses of different lengths by the buffer with or without hysteresis.
[0018] It is particularly advantageous if the neurons are implemented in an FPGA and connected in a configurable manner using the routing structures commonly used by FPGAs.
[0019] In this case, the FPGA configuration data can be at least partially used.
[0020] In this way, the weight data of the neuron can at least partially utilize the configuration data of the FPGA configurable logic block.
[0021] In particular, the weight data of neurons can be shared from the LookUp Table (LUT) configuration data of the FPGA configurable logic block.
[0022] Flexibility would also benefit if the number of neuron inputs were configurable.
[0023] In a chip implementation, the use of configurable logic blocks or neurons can be configured at any time.
[0024] "Configurable" means that the settings can be adjusted through the configuration data flow.
[0025] Figure 1 A neuron implementation according to the invention is shown (only one input is shown).
Claims
1. A neuron circuit, characterized in that: An integrated electronic neuron is used in which both input and output signals are pulse width modulated.
2. The neuron circuit according to claim 1, characterized in that: Weight data used to evaluate pulse width modulated input data is applied digitally to the neurons and converted into current by tri-state buffers that are staggered according to drive strength.
3. Neuronal circuit according to one or more of the preceding claims, characterized in that The current generated by the tri-state buffer is used to charge and / or discharge a capacitor, and the voltage generated thereby is converted into pulses of different lengths by a buffer with or without hysteresis function.
4. Neuron circuit according to one or more of the preceding claims, characterized in that The neurons are connected in a configurable manner through a routing structure commonly used in a Field Programmable Gate Array (FPGA).
5. Neuronal circuit according to one or more of the preceding claims, characterized in that The weight data of the neuron at least partially utilizes the configuration data of a configurable logic block of a Field Programmable Gate Array (FPGA).
6. Neuronal circuit according to one or more of the preceding claims, characterized in that The weight data of the neuron is shared from the configuration data of the Look Up Table (LUT) of the configurable logic block of the Field Programmable Gate Array (FPGA).
7. Neuron circuit according to one or more of the preceding claims, characterized in that The number of inputs to the neuron is configurable.
8. Neuron circuit according to one or more of the preceding claims, characterized in that The use of configurable logic blocks or neurons is configurable.