Memory device including sense amplifier and method of storing data thereof

Abstract

A memory device includes: a memory cell array including memory cells; a single-ended bit line sense amplifier connected to the memory cell through a bit line and a complementary bit line, and electrically connected through one of the bit line or the complementary bit line in response to the memory cell being activated; and a cell storage data inverting circuit configured to invert cell storage data in response to a first number of bits having a first level included in input data being greater than a second number of bits having a second level included in the input data, complementary input data generated by inverting the input data is transmitted to the single-ended bit line sense amplifier, and a data inverting flag indicating that the input data is inverted is transmitted to the single-ended bit line sense amplifier. The single-ended bit line sense amplifier stores the complementary input data in the memory cell array, and stores the data inversion flag in a specified partial region of the memory cell array.

Description

Technical Field

[0001] Example embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a memory device including a sensing sense amplifier and a method of storing data therein. Background Art

[0002] Semiconductor memory devices can be classified as volatile memory devices or nonvolatile memory devices. Compared with nonvolatile memory, volatile memory devices can exhibit faster reading and / or writing speeds. However, when the power applied to the volatile memory device is turned off, the data stored in the volatile memory device may disappear. In contrast, a nonvolatile memory device can retain the data stored in the nonvolatile memory device even when the power is turned off. Therefore, nonvolatile memory devices are used to store content that must be saved regardless of whether power is supplied or not.

[0003] Volatile memory devices may periodically perform refresh operations to maintain stored data. Volatile memory devices consume a large amount of current during a read operation or a refresh operation to switch the state of a memory cell to an activated state. Specifically, during a read operation or a refresh operation, a large amount of current is consumed in a bit line sense amplifier. Summary of the invention

[0004] Example embodiments of the present disclosure provide a memory device including a single-ended bit line sense amplifier and a method of storing data in a memory cell array such that a logic level is biased to reduce current consumed in the single-ended bit line sense amplifier during a read operation or a refresh operation.

[0005] According to an embodiment, a memory device includes: a memory cell array, the memory cell array includes a plurality of memory cells; a single-ended bit line sense amplifier, the single-ended bit line sense amplifier is connected to the plurality of memory cells through bit lines and complementary bit lines, and is electrically connected through the bit lines and one of the complementary bit lines when the plurality of memory cells are activated; and a cell storage data inversion circuit, the cell storage data inversion circuit sends complementary input data generated by inverting the input data to the single-ended bit line sense amplifier when the number of bits having a first level in the input data is greater than the number of bits having a second level, and sends a data inversion flag indicating that the input data is inverted to the single-ended bit line sense amplifier; the single-ended bit line sense amplifier stores the complementary input data in the memory cell array, and stores the data inversion flag in a specified partial area of ​​the memory cell array.

[0006] According to an embodiment, a memory device includes: a peripheral circuit region; and a memory cell region, the memory cell region being stacked on the peripheral circuit region; the memory cell region including a memory cell array, the memory cell array including normal memory cells and error correction code cells; the peripheral circuit region including: a single-ended bit line sense amplifier, the single-ended bit line sense amplifier being connected to the memory cell array through a bit line and a complementary bit line, and being electrically connected through one of the bit line and the complementary bit line when the memory cell array is activated; a cell storage data inversion circuit, the cell storage data inversion circuit sending complementary input data generated by inverting the input data to the single-ended bit line sense amplifier when the number of bits having a first level in the input data is greater than the number of bits having a second level, and sending a data inversion flag indicating that the input data is inverted to the single-ended bit line sense amplifier; and a cell storage data inversion register, the cell storage data inversion register storing the data inversion flag; the single-ended bit line sense amplifier stores the complementary input data in the memory cell array and stores the data inversion flag in the cell storage data inversion register.

[0007] According to an embodiment, a method for storing data in a memory device including a single-ended bit line sense amplifier includes: receiving input data; determining a logic level of a bit included in the input data; generating a data inversion flag corresponding to the input data when the number of bits having a first level among the bits included in the input data is greater than the number of bits having a second level; inverting the input data into complementary input data; storing the complementary input data in a memory cell array; and storing the data inversion flag in a designated area. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0009] Figure 1 is a block diagram illustrating a memory system according to example embodiments.

[0010] Figure 2 It is shown Figure 1 Block diagram of a storage device.

[0011] Figure 3 It is shown Figure 2 Schematic diagram of the connection between a memory cell array and a bit line sense amplifier.

[0012] Figure 4 It is shown Figure 3 Schematic diagram of the connection between the memory cell block and the sense amplifier group in FIG.

[0013] Figure 5 It is shown Figure 4 Schematic diagram of a sense amplifier.

[0014] Figure 6 It is shown Figure 2 Schematic diagram of an example of a data storage method of a storage device.

[0015] Figure 7 It shows that according to Figure 6 A diagram of a data storage method storing data in a memory cell array.

[0016] Figure 8 It is shown Figure 2 Schematic diagram of another example of a data storage method of a memory device.

[0017] Fig. 9 It is shown Figure 2 Schematic diagram of another example of a data storage method of a memory device.

[0018] Fig.10 It is shown Figure 2 Schematic diagram of another example of a data storage method of a memory device.

[0019] Fig.11 It is shown Figure 2 Schematic diagram of another example of a data storage method of a memory device.

[0020] Fig.12 It is shown Figure 2 Flow chart of a data storage method of a storage device. DETAILED DESCRIPTION

[0021] Below, example embodiments of the present disclosure will be described in sufficient detail and clarity to enable those of ordinary skill in the art to implement the example embodiments.

[0022] Below, DRAM will be used as an example to illustrate the features and functions of the present disclosure. However, those of ordinary skill in the art can easily understand other features and performances from the information disclosed herein. The present disclosure can be implemented or applied to other embodiments. In addition, the detailed description can be modified or changed according to the viewpoint and application without departing from the scope, spirit and other purposes of the present disclosure.

[0023] Figure 1 is a block diagram illustrating a memory system according to an example embodiment. Figure 1 , the memory system 1000 may include a memory controller 1100 and a memory device 1200 .

[0024] According to example embodiments, the memory controller 1100 may perform an access operation of writing data to the memory device 1200 or reading data stored in the memory device 1200. For example, the memory controller 1100 may generate a command CMD and an address ADDR for writing data to the memory device 1200 or reading data stored in the memory device 1200. The memory controller 1100 may include a memory controller that controls the memory device 1200, such as at least one of a system on chip (SoC) of an application processor (AP), a central processing unit (CPU), a digital signal processor (DSP), and a graphics processing unit (GPU).

[0025] According to example embodiments, the memory controller 1100 may provide various signals to the memory device 1200 to control the overall operation of the memory device 1200. For example, the memory controller 1100 may control memory access operations, such as read operations and write operations, of the memory device 1200. The memory controller 1100 may provide a command CMD and an address ADDR to the memory device 1200 to write data DATA into the memory device 1200 or read data DATA from the memory device 1200.

[0026] According to example embodiments, the memory controller 1100 may generate various types of commands CMD to control the memory device 1200. For example, the memory controller 1100 may generate a memory request corresponding to a memory operation of changing a state of a memory among a plurality of memory banks to read or write data DATA. As an example, the memory request may include an activation request for changing the state of a memory among a plurality of memory banks to an activation state. The memory device 1200 may activate a row, such as a word line, included in the memory bank in response to the activation request. The memory request may include a precharge request for changing the state of the memory bank from an activation state to a standby state after the reading or writing of the data DATA is completed.

[0027] In addition, the memory controller 1100 may generate an input / output (I / O) request (e.g., a column address strobe (CAS) request) for the memory device 1200 to perform a read operation or a write operation of the data DATA. As an example, the I / O request may include a read request for reading the data DATA from the activated memory bank. The I / O request may include a write request for writing the data DATA in the activated memory bank. The memory controller 1100 may generate a refresh command to control the refresh operation of the memory bank. However, the types of commands CMD described herein are only exemplary, and other types of commands CMD may exist.

[0028] According to example embodiments, the memory device 1200 may output data DATA requested to be read by the memory controller 1100 to the memory controller 1100, or may store data DATA requested to be written by the memory controller 1100 in a memory cell of the memory device 1200. The memory device 1200 may input and output data DATA based on a command CMD and an address ADDR. The memory device 1200 may include a plurality of memory banks.

[0029] The memory device 1200 may be a volatile memory device such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) DRAM, a DDR SDRAM, a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), and a static random access memory (SRAM), etc. Alternatively, the memory device 1200 may be implemented as a nonvolatile memory device such as a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), a spin transfer torque RAM (STT-RAM), etc. In this specification, the advantages of the present disclosure are described based on DRAM, but example embodiments are not limited thereto.

[0030] According to example embodiments, the memory bank may include a memory cell array divided in units of the memory bank, a row decoder, a column decoder, a sense amplifier, a write driver, etc. The memory bank may store data DATA requested to be written into the memory device 1200 through the write driver, and may read the data DATA requested to be read using the sense amplifier. The memory bank may also include a component for a refresh operation to store and maintain data in the cell array, or an address-based selection circuit.

[0031] Figure 2 It is shown Figure 1 A block diagram of a memory device. Figure 2 The memory device 1200 may include a memory cell array 1210, an address buffer 1220, a row decoder 1221, a column decoder 1222, a bit line sense amplifier 1230, a command decoder 1240, a control logic 1250, a cell storage data inversion (Data Stored in cell Inverision, DSI) circuit 1260 and an input / output circuit 1270.

[0032] According to example embodiments, the memory cell array 1210 may include a plurality of memory cells arranged in a matrix of rows and columns. For example, the memory cell array 1210 may include a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to the rows of the memory cells, and the plurality of bit lines BL may be connected to the columns of the memory cells.

[0033] According to an example embodiment, the address buffer 1220 may be Figure 1 The memory controller 1100 receives the address ADDR. For example, the address ADDR may include a row address RA for addressing a row of the memory cell array 1210 and a column address CA for addressing a column of the memory cell array 1210. The address buffer 1220 may send the row address RA to the row decoder 1221, and may send the column address CA to the column decoder 1222.

[0034] According to example embodiments, the row decoder 1221 may select one of a plurality of word lines WL connected to the memory cell array 1210. The row decoder 1221 may decode a row address RA received from the address buffer 1220 to select a single word line corresponding to the row address RA and may activate the selected word line.

[0035] According to example embodiments, the column decoder 1222 may select a predetermined bit line from a plurality of bit lines BL of the memory cell array 1210. The column decoder 1222 may decode a column address CA received from the address buffer 1220 to select a predetermined bit line BL corresponding to the column address CA.

[0036] According to example embodiments, the bit line sense amplifier 1230 may be connected to the bit line BL of the memory cell array 1210. For example, the bit line sense amplifier 1230 may sense a voltage change of a selected bit line among a plurality of bit lines BL, and may amplify and output the voltage change. The bit line sense amplifier 1230 may operate as a single-ended sense amplifier. In some example embodiments of the single-ended sense amplifier, there is a difference in current consumption depending on a unit bit included in the data DATA during an activation operation or a refresh operation. As an example, the bit line sense amplifier 1230 may consume more current in a memory cell storing a high level (or logic 1) (e.g., a first level) than in a memory cell storing a low level (or logic 0) (e.g., a second level).

[0037] As another example, the bit line sense amplifier 1230 may consume less current in a memory cell storing a high level (or logic 1) than in a memory cell storing a low level (or logic 0). Hereinafter, the bit line sense amplifier 1230 will be described assuming that the current consumption in a memory cell storing a low level (or logic 0) is lower. However, even when the bit line sense amplifier 1230 consumes less current in a memory cell storing a high level (or logic 1), the data storage method of the present disclosure may be applied.

[0038] According to an example embodiment, the command decoder 1240 may decode a write enable signal (WE), a row address strobe signal (RAS), a column address strobe signal (CAS), and a chip select signal (CS) received from the memory controller 1100, so that a control signal corresponding to the command CMD is generated in the control logic 1250. The command CMD may include an activation request, a read request, a write request, or a precharge request. The control logic 1250 may control the overall operation of the bit line sense amplifier 1230 by a control signal corresponding to the command CMD. The control logic 1250 may generate a control signal so that the bit line sense amplifier 1230 operates as a single-ended sense amplifier. In addition, the control logic 1250 may control the overall operation of the memory device 1200.

[0039] According to an example embodiment, the DSI circuit 1260 may invert the data DATA transmitted from the input / output circuit 1270, and transmit the inverted data to the bit line sense amplifier 1230. For example, the DSI circuit 1260 may check the number of low-level bits (or logic 0) or the number of high-level bits (or logic 1) included in the data DATA. As an example, when the number of low-level bits is less than or equal to a specified reference value (e.g., half of the number of total bits), the DSI circuit 1260 may invert the data DATA. As another example, when the number of high-level bits is greater than or equal to a specified reference value (e.g., half of the number of total bits), the DSI circuit 1260 may invert the data DATA.

[0040] According to example embodiments, when the data DATA is inverted, the DSI circuit 1260 may generate a data inversion flag indicating that the inverted data is stored in the memory cell array 1210. The DSI circuit 1260 may transmit the inverted data and the data inversion flag to the bit line sense amplifier 1230. When the data DATA is inverted, the bit line sense amplifier 1230 may store the data inversion flag in a designated area of ​​the memory cell array 1210. Therefore, during a read operation of the inverted data, the bit line sense amplifier 1230 may read the data inversion flag together, and the DSI circuit 1260 may restore the inverted data back to the data DATA and output the data DATA through the input / output circuit 1270.

[0041] According to example embodiments, the input / output circuit 1270 may output data DATA to the memory controller 1100 through a data pad based on a voltage sensed and amplified from the bit line sense amplifier 1230. For example, the input / output circuit 1270 may include an input buffer or an output buffer. The input buffer or the output buffer may be connected to the data pad. The input / output circuit 1270 may perform a serialization operation or a deserialization operation of the data DATA.

[0042] Figure 3 It is shown Figure 2 Schematic diagram of the connection between a memory cell array and a bit line sense amplifier. Figure 4 It is shown Figure 3 Schematic diagram of the connection between the memory cell block and the sense amplifier group in FIG. Figure 5 It is shown Figure 4 A schematic diagram of a sense amplifier. Figures 2 to 5 , the memory cell array 1210 may include a plurality of memory cell blocks (CB_1 to CB_n) and a plurality of sense amplifier blocks (SG_1 to SG_n+1) (where n is a natural number). Each sense amplifier block SG_i may correspond to two adjacent memory cell blocks (CB_i-1, CB_i) among the plurality of memory cell blocks (CB_1 to CB_n) and may be connected to two adjacent memory cell blocks (CB_i-1, CB_i) (where i is a natural number of 2 or greater).

[0043] According to example embodiments, each memory cell block CB_i may include a plurality of bit lines BL extending in a predetermined direction (e.g., a column direction). A plurality of memory cells may be connected to each bit line BL. The memory cell block CB_i may also include a plurality of word lines WL extending in different directions (e.g., a row direction). A plurality of memory cells MC connected to each bit line BL may be connected to the plurality of word lines WL, respectively.

[0044] In some example embodiments, Figure 3 As shown, some memory cell blocks (CB_1 to CB_n) may include complementary bit lines BLB as bit lines. In some example embodiments, memory cell blocks on which bit lines BL are formed and memory cell blocks on which complementary bit lines BLB are formed may be alternately arranged, and the bit lines BL and the complementary bit lines BLB may form complementary bit line pairs.

[0045] According to example embodiments, the sense amplifier block SG_i may be connected to some bit lines BL of one memory cell block CB_i-1 and some complementary bit lines BLB of another memory cell block CB_i. As an example, the sense amplifier block SG_i may be connected to the odd bit lines BL of the memory cell block CB_i-1 and the odd complementary bit lines BLB of the memory cell block CB_i. In some example embodiments, the even bit lines BL of the memory cell block CB_i-1 may be connected to another sense amplifier block SG_i-1, and the even complementary bit lines BLB of the memory cell block CB_i may be connected to another sense amplifier block SG_i-1. As another example, the sense amplifier block SG_i may be connected to the even bit lines BL of the memory cell block CB_i-1 and the even complementary bit lines BLB of the memory cell block CB_i.

[0046] According to example embodiments, the sense amplifier block SG_1 located at one end may be connected to the bit line BL of one memory cell CB_1 , and the sense amplifier block SG_n+1 located at the other end may be connected to the one memory cell CB_1 .

[0047] According to example embodiments, the sense amplifier block SG_i may include a plurality of sense amplifiers SA. The plurality of sense amplifiers SA may each correspond to some bit lines BL of the memory cell block CB_i-1, and may each correspond to some complementary bit lines BLB of another memory cell block CB_i. Each sense amplifier SA may be connected to a corresponding bit line BL among some bit lines (e.g., odd bit lines) BL of the memory cell block CB_i-1 and a corresponding complementary bit line BLB among some complementary bit lines (e.g., odd complementary bit lines) BLB of another memory cell block CB_i.

[0048] like Figure 4 As shown, the bit lines BL1 and BL3 in the cell array block CB_i-1 can be connected to the sense amplifiers (SA_i, 1) and (SA_i, 2) of the sense amplifier block SG_i, respectively. The bit lines BL2 and BL4 can be connected to the sense amplifiers (SA_i-1, 1) and (SA_i-1, 2) of the sense amplifier block SG_i-1, respectively. For ease of explanation, Figure 4 FIG. 1 shows a word line WL and a memory cell MC connected to the word line WL. In addition, although each memory cell MC Figure 4 2 and 3. The memory cell MC is shown as including a transistor and a capacitor, but the structure of the memory cell MC is not limited thereto.

[0049] refer to Figure 5 , a sense amplifier (SA_i,1) can be connected to a bit line BL1 and a complementary bit line BLB1. Figure 5In the figure, for the convenience of explanation, a memory cell MC1 connected to the bit line BL1, a word line WL_i-1 connected to the memory cell MC1, a memory cell MC2 connected to the complementary bit line BLB1, and a word line WL_i connected to the memory cell MC2 are shown. Figure 5 2 , each of the memory cells MC1 and MC2 is illustrated as including a transistor and a capacitor, but the structure of each of the memory cells MC1 and MC2 is not limited thereto.

[0050] For example, the sense amplifier (SA_i, 1) may include a first inverter INV1 and a second inverter INV2. An input terminal of the first inverter INV1 may be connected to a complementary sense bit line SBLB. An output terminal of the first inverter INV1 may be connected to a sense bit line SBL through a first switch SW1. The sense bit line SBL may be connected to a bit line BL1 through a third switch SW3. The bit line BL1 may be connected to a first memory cell MC1, and the first memory cell MC1 may be connected to a word line WL_i-1. An input terminal of the second inverter INV2 may be connected to the sense bit line SBL. An output terminal of the second inverter INV2 may be connected to a complementary sense bit line SBLB through a second switch SW2. The complementary sense bit line SBLB may be connected to a complementary bit line BLB1 through a fourth switch SW4. The complementary bit line BLB1 may be connected to a second memory cell MC2, and the second memory cell MC2 may be connected to a word line WL_i.

[0051] According to example embodiments, the sense amplifier (SA_i, 1) may operate in a single-ended manner. For example, the third switch SW3 may electrically isolate the sense amplifier (SA_i, 1) from the bit line BL1 based on the first isolation signal ISO1. When the first isolation signal ISO1 is at an inactive level (e.g., a low level), the third switch SW3 may electrically isolate the sense amplifier (SA_i, 1) from the bit line BL1. When the first isolation signal ISO1 is at an active level (e.g., a high level), the third switch SW3 may connect the sense amplifier (SA_i, 1) to the bit line BL1.

[0052] In addition, the fourth switch SW4 can electrically isolate the sense amplifier (SA_i, 1) from the complementary bit line BLB1 based on the second isolation signal ISO2. When the second isolation signal ISO2 is at an inactive level (e.g., a low level), the fourth switch SW4 can electrically isolate the sense amplifier (SA_i, 1) from the complementary bit line BLB1. When the second isolation signal ISO2 is at an active level (e.g., a high level), the fourth switch SW4 can connect the sense amplifier (SA_i, 1) to the complementary bit line BLB1.

[0053] Therefore, according to the first isolation signal ISO1 and the second isolation signal ISO2, the sense amplifier (SA_i, 1) can be connected to one of the first memory cell MC1 included in one memory cell block CB_i-1 or the second memory cell MC2 included in another memory cell block CB_i. During an activation operation or a refresh operation, the sense amplifier (SA_i, 1) operating in a single-ended manner can consume more current from a memory cell storing a high level (or logic 1) than from a memory cell storing a low level (or logic 0).

[0054] Figure 6 It is shown Figure 2 Schematic diagram of an example of a data storage method of a storage device. Figure 2 and Figure 6 , the memory device 1200 may convert the input data with a bias and store the bias data. The DSI circuit 1260 may include a global input / output driver (GIODRV) 1261a, a DSI control unit 1262a, and a global input / output multiplexer (GIOMUX) 1263a. The DSI control unit 1262a may be placed between the global input / output driver 1261a and the global input / output multiplexer 1263a.

[0055] According to an example embodiment, the DSI circuit 1260 may determine most of the logic levels of the input data DIN. Based on the determination result, the DSI circuit 1260 may generate a data inversion flag DSIF to indicate which inversion data is stored in the memory cell array 1210. For example, the global input / output driver 1261a may amplify the input data DIN and transmit the amplified data of the input data DIN to the DSI control unit 1262a. The DSI control unit 1262a may determine most of the logic levels of the input data DIN.

[0056] As an example, the DSI control unit 1262a may check the number of logic 1s (e.g., high level) included in the input data DIN. When the number of logic 1s included in the input data DIN is less than or equal to half the number of bits included in the input data DIN, the DSI control unit 1262a may transfer the input data DIN to the global input / output multiplexer 1263a as is. The global input / output multiplexer 1263a may transfer the input data DIN to the bit line sense amplifier 1230, and the bit line sense amplifier 1230 may store the input data DIN in the memory cell array 1210.

[0057] When the number of logic 1s included in the input data DIN is greater than half (or most) of the number of bits included in the input data DIN, the DSI control unit 1262a may generate a data inversion flag DSIF. The DSI control unit 1262a may invert the input data DIN and send the complementary input data DINB together with the data inversion flag DSIF to the global input / output multiplexer 1263a. The global input / output multiplexer 1263a may send the complementary input data DINB and the data inversion flag DSIF to the bit line sense amplifier 1230.

[0058] The bit line sense amplifier 1230 may store the complementary input data DINB in ​​the memory cell array 1210. The bit line sense amplifier 1230 may store the data inversion flag DSIF in the DSI register 1211 included in the memory cell array 1210. The memory device 1200 may allocate a portion of the memory cell array 1210 to the DSI register 1211. During a read operation of the complementary input data DINB, the bit line sense amplifier 1230 may read the data inversion flag DSIF, and the DSI control unit 1262a may restore the complementary input data DINB to the input data DIN, and output the restored input data DIN through the input / output circuit 1270.

[0059] As another example, the DSI control unit 1262a may check the number of logic 0s (e.g., low level) included in the input data DIN. When the number of logic 0s included in the input data DIN is less than or equal to half the number of bits included in the input data DIN, the DSI control unit 1262a may transfer the input data DIN to the global input / output multiplexer 1263a as is. The global input / output multiplexer 1263a may transfer the input data DIN to the bit line sense amplifier 1230, and the bit line sense amplifier 1230 may store the input data DIN in the memory cell array 1210.

[0060] When the number of logic 0s included in the input data DIN is greater than half (or most) of the number of bits included in the input data DIN, the DSI control unit 1262a may generate a data inversion flag DSIF. The DSI control unit 1262a may invert the input data DIN and send the complementary input data DINB together with the data inversion flag DSIF to the global input / output multiplexer 1263a. The global input / output multiplexer 1263a may send the complementary input data DINB and the data inversion flag DSIF to the bit line sense amplifier 1230.

[0061] The bit line sense amplifier 1230 may store the complementary input data DINB in ​​the memory cell array 1210. The bit line sense amplifier 1230 may store the data inversion flag DSIF in the DSI register 1211 included in the memory cell array 1210. The memory device 1200 may allocate a portion of the memory cell array 1210 to the DSI register 1211.

[0062] As described above, the memory device 1200 may store the input data DIN as is or invert it according to the logic level of the bit included in the input data DIN. Therefore, the data bit level stored in the memory cell array 1210 may be configured to be biased (e.g., having a large number of logic 0s or a large number of logic 1s). The memory device 1200 may determine whether to invert the input data DIN based on the bit level that causes more power to be consumed during an activation operation or a refresh operation of the bit line sense amplifier 1230 operating in a single-ended manner.

[0063] For example, when logic 1 (or a high level) is stored in the memory cell array 1210 and the amount of current consumed by the bit line sense amplifier 1230 during an activation operation or a refresh operation is large, when the number of logic 1s included in the input data DIN is greater than half (or most) of the number of bits included in the input data DIN, the DSI control unit 1262a may invert the input data DIN and generate a data inversion flag DSIF.

[0064] As another example, when logic 0 (or a low level) is stored in the memory cell array 1210 and the amount of current consumed by the bit line sense amplifier 1230 during an activation operation or a refresh operation is large, when the number of logic 0s included in the input data DIN is greater than half (or most) of the number of bits included in the input data DIN, the DSI control unit 1262a may invert the input data DIN and generate a data inversion flag DSIF.

[0065] Hereinafter, for ease of explanation, it is assumed that the amount of current consumed by the bit line sense amplifier 1230 during an activation operation or a refresh operation is large when a logic 1 (or a high level) is stored in the memory cell array 1210. However, even when a logic 0 (or a low level) is stored in the memory cell array 1210 and the amount of current consumed by the bit line sense amplifier 1230 during an activation operation or a refresh operation is large, the data inversion storage method of the present disclosure may be applied.

[0066] Figure 7 It shows that according to Figure 6 A diagram of a data storage method storing data in a memory cell array. Figure 7 The memory cell array 1210 is exemplarily shown to be connected to the bit line sense amplifier 1230 via four bit lines. Figure 6 and Figure 7 , the memory device 1200 may receive “1101”, “1111”, “0010”, and “1001” as input data DIN.

[0067] according to Figure 6 Data storage method, since the number of logical 1s is greater than half, the input data "1101" may be inverted and stored as "0010" in the memory cell connected to the first word line WL1. Since the number of logical 1s is greater than half, the input data "1111" may be inverted and stored as "0000" in the memory cell connected to the second word line WL2. Since the number of logical 1s is less than the majority, the input data "0010" may not be inverted and may be stored as "0010" in the memory cell connected to the third word line WL3. Since the number of logical 1s is less than the majority, the input data "1001" may not be inverted and may be stored as "1001" in the memory cell connected to the fourth word line WL4.

[0068] Therefore, the memory cell array 1210 can store a larger number of logic 0s (e.g., second level) than logic 1s (e.g., first level) as a whole. That is, the memory cell array 1210 can store input data so that the logic level is biased. Therefore, the bit line sense amplifier 1230 operating in a single-ended manner can reduce current consumption during an activation operation or a refresh operation.

[0069] Figure 8 It is shown Figure 2 FIG. 1 is a diagram showing another example of a data storage method of a memory device. Figure 2 and Figure 8 , the memory device 1200 may convert the input data with a bias and store the bias data. The DSI circuit 1260 may include a global input / output driver (GIODRV) 1261b, a DSI control unit 1262b, and a global input / output multiplexer (GIOMUX) 1263b. The DSI control unit 1262b may be placed before the global input / output driver 1261b.

[0070] According to an example embodiment, the DSI circuit 1260 may determine most of the logic levels of the input data DIN, and generate a data inversion flag DSIF based on the determination result. For example, the DSI control unit 1262b may determine most of the logic levels (e.g., logic 1) of the input data DIN. The DSI control unit 1262b may check the number of logic 1s (e.g., high level) included in the input data DIN.

[0071] When the number of logic 1s included in the input data DIN is less than or equal to half the number of bits included in the input data DIN, the DSI control unit 1262b may transfer the input data DIN to the global input / output driver 1261b as is. The global input / output driver 1261b may amplify the input data DIN and send the amplified data of the input data DIN to the global input / output multiplexer 1263b. The global input / output multiplexer 1263b may transfer the input data DIN to the bit line sense amplifier 1230, and the bit line sense amplifier 1230 may store the input data DIN in the memory cell array 1210.

[0072] When the number of logic 1s included in the input data DIN is greater than half (or most) of the number of bits included in the input data DIN, the DSI control unit 1262b may generate a data inversion flag DSIF. The DSI control unit 1262b may send the data inversion flag DSIF to the global input / output multiplexer 1263b. The DSI control unit 1262b may invert the input data DIN and send the complementary input data DINB to the global input / output driver 1261b. The global input / output driver 1261b may amplify the complementary input data DINB and send the amplified data of the complementary input data DINB to the global input / output multiplexer 1263b. The global input / output multiplexer 1263b may send the complementary input data DINB and the data inversion flag DSIF to the bit line sense amplifier 1230.

[0073] The bit line sense amplifier 1230 may store the complementary input data DINB in ​​the memory cell array 1210. The bit line sense amplifier 1230 may store the data inversion flag DSIF in the DSI register 1211 included in the memory cell array 1210. The memory device 1200 may allocate a portion of the memory cell array 1210 to the DSI register 1211.

[0074] During a read operation of the complementary input data DINB, the bit line sense amplifier 1230 may read the data inversion flag DSIF. The DSI control unit 1262 b may restore the complementary input data DINB to the input data DIN and output the restored input data DIN through the input / output circuit 1270 .

[0075] Fig. 9 It is shown Figure 2 FIG. 1 is a diagram showing another example of a data storage method of a storage device. Figure 2 and Fig. 9, the memory device 1200 may further include an error correction circuit 1280. The memory cell array 1210 may include an error correction code unit 1212 which stores an error correction code ECC generated by the error correction circuit 1280.

[0076] In various example embodiments, the error correction circuit 1280 may be configured to implement block ECC and / or convolutional ECC. Block ECC is typically used in conjunction with a fixed-size block of bits or a predetermined-size symbol. Convolutional ECC is typically used for a bit stream or symbol stream of arbitrary length. Examples of block ECC include Reed–Solomon, Golay, BCH, multidimensional parity check, and Hamming code. Convolutional ECC includes, but is not limited to, the Viterbi algorithm. According to an example embodiment, the input / output circuit 1270 may send the received input data DIN to the error correction circuit 1280. For example, the error correction circuit 1280 may generate an error correction code ECC based on the input data DIN. The error correction circuit 1280 may send the error correction code ECC to the DSI circuit 1260.

[0077] According to example embodiments, the input / output circuit 1270 may transfer the received input data DIN to the DSI circuit 1260. For example, the DSI circuit 1260 may determine a majority logic level (eg, logic 1) of the input data DIN.

[0078] When the number of logic 1s included in the input data DIN is less than or equal to half the number of bits included in the input data DIN, the DSI circuit 1260 may transmit the input data DIN as it is to the bit line sense amplifier 1230. At this time, the DSI circuit 1260 may transmit the error correction code ECC together with the input data DIN to the bit line sense amplifier 1230. The bit line sense amplifier 1230 may store the input data DIN in the memory cell array 1210. The bit line sense amplifier 1230 may store the error correction code ECC in the error correction code unit 1212.

[0079] When the number of logic 1s included in the input data DIN is greater than half (or most) of the number of bits included in the input data DIN, the DSI circuit 1260 may generate a data inversion flag DSIF. In addition, the DSI circuit 1260 may invert the input data DIN and transmit complementary input data DINB to the bit line sense amplifier 1230. The DSI circuit 1260 may combine the data inversion flag DSIF and the error correction code ECC, and transmit the combined data of the data inversion flag DSIF and the error correction code ECC to the bit line sense amplifier 1230.

[0080] The bit line sense amplifier 1230 may store the complementary input data DINB in ​​the memory cell array 1210. The bit line sense amplifier 1230 may store the combined data of the data inversion flag DSIF and the error correction code ECC in the error correction code unit 1212.

[0081] During a read operation of the complementary input data DINB, the bit line sense amplifier 1230 may read the data inversion flag DSIF together, and the DSI circuit 1260 may restore the complementary input data DINB to the input data DIN and output the restored input data DIN through the input / output circuit 1270 .

[0082] Fig.10 It is shown Figure 2 FIG. 1 is a diagram showing another example of a data storage method of a memory device. Figure 2 , Fig. 9 and Fig.10 , the memory device 1200 may have a Cell Over Periphery (COP) structure in which the memory cell region 100 is stacked on the peripheral circuit region 200 .

[0083] According to example embodiments, the memory cell region 100 may include a memory cell array 1210. The memory cell array 1210 may include a normal cell 110 and an error correction code unit 1212. The peripheral circuit region 200 may include Figure 2 The address buffer 1220, the row decoder 1221, the column decoder 1222, the bit line sense amplifier 1230, the command decoder 1240, the control logic 1250 and the data inversion storage circuit 1260, the input / output circuit 1270, or Fig. 9 Error correction circuit 1280.

[0084] In addition, the peripheral circuit area 200 may include a DSI register 210. The DSI register 210 may be placed below the error correction code unit 1212. Fig.10 For convenience of explanation, the address buffer 1220, the row decoder 1221, the column decoder 1222, the command decoder 1240, the control logic 1250, the input / output circuit 1270, and the error correction circuit 1280 are not shown.

[0085] According to example embodiments, the DSI circuit 1260 may determine a majority logic level (e.g., logic 1) of the input data DIN. For example, when the number of logic 1s included in the input data DIN is less than or equal to half the number of bits included in the input data DIN, the DSI circuit 1260 may transmit the input data DIN as is to the bit line sense amplifier 1230. The bit line sense amplifier 1230 may store the input data DIN in the normal cell 110 of the memory cell array 1210.

[0086] When the number of logic 1s included in the input data DIN is greater than half (or most) of the number of bits included in the input data DIN, the DSI circuit 1260 may generate a data inversion flag DSIF. In addition, the DSI circuit 1260 may invert the input data DIN and send complementary input data DINB together with the data inversion flag DSIF to the bit line sense amplifier 1230.

[0087] The bit line sense amplifier 1230 may store the complementary input data DINB in ​​the normal cell 110 of the memory cell array 1210. The bit line sense amplifier 1230 may store the data inversion flag DSIF in the DSI register 210 of the peripheral circuit region 200. During a read operation of the complementary input data DINB, the bit line sense amplifier 1230 may read the data inversion flag DSIF together, and the DSI circuit 1260 may restore the complementary input data DINB to the input data DIN, and output the restored input data DIN through the input / output circuit 1270.

[0088] Fig.11 It is shown Figure 2 FIG. 1 is a diagram showing another example of a data storage method of a memory device. Figure 2 , Fig. 9 and Fig.11 , the memory device 1200 may have a cell-on-periphery (COP) structure in which the memory cell region 100 is stacked on the peripheral circuit region 200. The memory cell region 100 may include a memory cell array 1210.

[0089] According to example embodiments, the memory cell array 1210 may include a normal cell 110 and an error correction code unit 1212. The peripheral circuit region 200 may include Figure 2 The address buffer 1220, the row decoder 1221, the column decoder 1222, the bit line sense amplifier 1230, the command decoder 1240, the control logic 1250 and the data inversion storage circuit 1260, the input / output circuit 1270, or Fig. 9 Error correction circuit 1280.

[0090] In addition, the peripheral circuit area 200 may include a DSI register 210. The DSI register 210 may be placed below the normal cell 110. The DSI register 210 may be placed below some of the normal cell groups in the plurality of normal cell groups. Fig.11 For convenience of explanation, the address buffer 1220, the row decoder 1221, the column decoder 1222, the command decoder 1240, the control logic 1250, the input / output circuit 1270, and the error correction circuit 1280 are not shown.

[0091] According to example embodiments, the DSI circuit 1260 may determine a majority logic level (e.g., logic 1) of the input data DIN. For example, when the number of logic 1s included in the input data DIN is less than or equal to half the number of bits included in the input data DIN, the DSI circuit 1260 may transmit the input data DIN as is to the bit line sense amplifier 1230. The bit line sense amplifier 1230 may store the input data DIN in the normal cell 110 of the memory cell array 1210.

[0092] When the number of logic 1s included in the input data DIN is greater than a half (or a majority) of the number of bits included in the input data DIN, the DSI circuit 1260 may generate a data inversion flag DSIF. In addition, the DSI circuit 1260 may invert the input data DIN and transmit complementary input data DINB together with the data inversion flag DSIF to the bit line sense amplifier 1230. The bit line sense amplifier 1230 may store the complementary input data DINB in ​​the normal cell 110 of the memory cell array 1210.

[0093] The bit line sense amplifier 1230 may store the data inversion flag DSIF in the DSI register 210 of the peripheral circuit region 200. During a read operation of the complementary input data DINB, the bit line sense amplifier 1230 may read the data inversion flag DSIF together, and the DSI circuit 1260 restores the complementary input data DINB to the input data DIN and outputs the restored input data DIN through the input / output circuit 1270.

[0094] Fig.12 It is shown Figure 2 A flowchart of a data storage method of a storage device. Figures 2 to 12 , the memory device 1200 may convert input data with a bias and store the biased data.

[0095] According to example embodiments, in operation S110, the memory device 1200 may receive input data DIN. For example, the input / output circuit 1270 may receive the input data DIN from the memory controller 1100. The input / output circuit 1270 may transfer the received input data DIN to the DSI circuit 1260.

[0096] According to example embodiments, in operation S120, the memory device 1200 may determine most logic levels of bits included in the input data DIN. As an example, the DSI circuit 1260 may check the number of logic 1s (e.g., a high level) included in the input data DIN. As another example, the DSI circuit 1260 may check the number of logic 0s (e.g., a low level) included in the input data DIN.

[0097] According to example embodiments, in operation S130, the memory device 1200 may check whether the number of logic 1s included in the input data DIN is greater than half of the number of bits included in the input data DIN. For example, when the number of logic 1s included in the input data DIN is less than or equal to half of the number of bits included in the input data DIN ( Fig.12 When the number of logic 1s included in the input data DIN is greater than half (or most) of the number of bits included in the input data DIN ( Fig.12 ), the DSI circuit 1260 may perform operation S150.

[0098] According to example embodiments, in operation S140, when the number of logic 1s included in the input data DIN is less than or equal to half the number of bits included in the input data DIN ( Fig.12 12), the memory device 1200 may store the input data DIN as is in the memory cell array 1210. For example, the DSI circuit 1260 may directly transmit the input data DIN to the bit line sense amplifier 1230.

[0099] According to example embodiments, in operation S150, when the number of logic 1s included in the input data DIN is greater than a half (or a majority) of the number of bits included in the input data DIN ( Fig.12 ), the memory device 1200 may generate a data inversion flag DSIF which indicates which inverted data is stored in the memory cell array 1210. For example, the DSI circuit 1260 may generate the data inversion flag DSIF.

[0100] According to example embodiments, in operation S160 , the memory device 1200 may invert the input data DIN into complementary input data DINB. For example, the DSI circuit 1260 may invert the input data DIN and transmit the complementary input data DINB to the bit line sense amplifier 1230 .

[0101] As an example, in Figure 6 In the embodiment, the DSI circuit 1260 may include a global input / output driver (GIODRV) 1261a, a DSI control unit 1262a, and a global input / output multiplexer (GIOMUX) 1263a. The DSI control unit 1262a may be placed between the global input / output driver 1261a and the global input / output multiplexer 1263a. The DSI control unit 1262a may invert the input data DIN and output the complementary input data DINB.

[0102] As another example, in Figure 8 In the embodiment, the DSI circuit 1260 may include a global input / output driver (GIODRV) 1261b, a DSI control unit 1262b, and a global input / output multiplexer (GIOMUX) 1263b. The DSI control unit 1262b may be placed before the global input / output driver 1261b. The DSI control unit 1262b may invert the input data DIN and output the complementary input data DINB.

[0103] According to example embodiments, in operation S170, the memory device 1200 may store complementary input data DINB together with a data inversion flag DSIF. For example, the bit line sense amplifier 1230 may store the complementary input data DINB in ​​the memory cell array 1210. The data inversion flag DSIF may be stored in various regions.

[0104] As an example, the bit line sense amplifier 1230 may store the data inversion flag DSIF in the DSI register 1211 included in the memory cell array 1210. As another example, the DSI circuit 1260 may combine the data inversion flag DSIF and the error correction code ECC and transmit the combined data to the bit line sense amplifier 1230. The bit line sense amplifier 1230 may store the combined data of the data inversion flag DSIF and the error correction code ECC in the error correction code unit 1212.

[0105] As another example, in the COP structure memory device 1200, the bit line sense amplifier 1230 may store the data inversion flag DSIF in the DSI register 210 provided in the peripheral circuit region 200. The DSI register 210 may be provided below the error correction code unit 1212 included in the memory cell array 1210. Alternatively, the DSI register 210 may be placed below the normal cell 110 included in the memory cell array 1210.

[0106] As described above, the memory device 1200 may store data in the memory cell array 1210 such that there are more memory cells storing a low level (or logic 0) (e.g., the second level) than memory cells storing a high level (or logic 1) (e.g., the first level). That is, the memory cell array 1210 may store data such that the logic levels stored in the memory cell array 1210 are biased. During an activation operation or a refresh operation, the bit line sense amplifier 1230 operating in a single-ended manner may consume more current from a memory cell storing a high level (or logic 1) than from a memory cell storing a low level (or logic 0).

[0107] Therefore, when the number of memory cells storing a low level (or logic 0) in the memory cell array 1210 is greater than the number of memory cells storing a high level (or logic 1) (or a low level (or logic 0) is biased and stored in the memory cell array 1210), the bit line sense amplifier 1230 operating in a single-ended manner can reduce current consumption during an activation operation or a refresh operation.

[0108] According to the present disclosure, by storing input data in a memory cell array so that a logic level of the input data is biased, current consumed in a bit line sense amplifier during a read operation or a refresh operation can be reduced.

[0109] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

[0110] Any functional blocks shown in the figure and described above can be implemented in a processing circuit system, such as hardware including logic circuits, a hardware / software combination such as a processor that executes software, or a combination thereof. For example, the processing circuit system can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0111] In various example embodiments herein, reference may be made to various circuit elements, including but not limited to capacitors, resistors, inductors, switches, amplifiers, comparators, filters, and transistors. Various types of digital, analog, active and / or passive components may be used to implement the example embodiments. For example, different transistor types may be used depending on whether positive logic or negative logic is used, the manufacturing process employed, etc. In addition, unless otherwise specifically stated herein, there are many available types of filters, comparators, switches, etc. that may be used to implement the example embodiments.

[0112] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of..." preceding a list of elements modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "A, B, and / or C" both mean A, B, C, or any combination thereof.

Claims

1. A storage device, comprising: A memory cell array, the memory cell array comprising a plurality of memory cells; a single-ended bit line sense amplifier connected to the plurality of memory cells through bit lines and complementary bit lines and electrically connected through one of the bit lines or the complementary bit lines in response to the plurality of memory cells being activated; as well as A cell storage data inversion circuit, the cell storage data inversion circuit being configured to send complementary input data generated by inverting the input data to the single-ended bit line sense amplifier in response to a first number of bits with a first level included in the input data being greater than a second number of bits with a second level included in the input data, and to send a data inversion flag indicating that the input data is inverted to the single-ended bit line sense amplifier, wherein the single-ended bit line sense amplifier is configured to store the complementary input data in the memory cell array and to store the data inversion flag in a specified partial area of ​​the memory cell array.

2. The memory device according to claim 1, wherein: The cell storage data inversion circuit is configured to send the input data as is to the single-ended bit line sense amplifier in response to the first number of bits having the first level being less than or equal to the second number of bits having the second level, and The single-ended bit line sense amplifier is configured to store the input data intact in the memory cell array.

3. The memory device according to claim 1, wherein: The first level is a high level, and, wherein the second level is a low level.

4. The memory device according to claim 1, wherein: The unit storage data inversion circuit comprises: a global input / output driver configured to amplify and output the input data; a cell storage data inversion control unit configured to generate the data inversion flag and invert the input data to generate the complementary input data in response to the first number of bits having the first level being greater than the second number of bits having the second level; and a global input / output multiplexer configured to send the input data to the single-ended bit line sense amplifier or send the complementary input data and the data inversion flag to the single-ended bit line sense amplifier based on whether the cell storage data inversion control unit generates the complementary input data, The unit storage data inversion control unit is arranged between the global input / output driver and the global input / output multiplexer.

5. The memory device according to claim 1, wherein: The unit storage data inversion circuit comprises: a cell storage data inversion control unit, the cell storage data inversion control unit being configured to generate the data inversion flag and invert the input data into the complementary input data in response to the first number of bits having the first level being greater than the second number of bits having the second level; a global input / output driver configured to amplify and output data received from the unit storage data inversion control unit; and a global input / output multiplexer configured to send the input data to the single-ended bit line sense amplifier or send the complementary input data and the data inversion flag to the single-ended bit line sense amplifier based on whether the cell storage data inversion control unit sends the data inversion flag to the global input / output multiplexer, The unit storage data inversion control unit is arranged before the global input / output driver and is configured to send the data inversion flag to the global input / output multiplexer.

6. The memory device according to claim 1, further comprising: an error correction circuit configured to generate an error correction code based on the input data, wherein the cell storage data inversion circuit is configured to send the combined data of the data inversion flag and the error correction code to the single-ended bit line sense amplifier in response to the first number of bits having the first level being greater than the second number of bits having the second level, and The single-ended bit line sense amplifier is configured to store the combined data in an error correction code unit included in the memory cell array.

7. The memory device according to claim 1, wherein: The single-ended bit line sense amplifier is further configured to store the data inversion flag in a data inversion register of a cell individually designated in the memory cell array.

8. The memory device according to claim 1, wherein: The single-ended bit line sense amplifier comprises: a first inverter including a first output terminal connected to a sense bit line through a first switch and a first input terminal connected to a complementary sense bit line; and a second inverter including a second output terminal connected to the complementary sense bit line through a second switch and a second input terminal connected to the sense bit line, wherein the sensing bit line is connected to the bit line via a third switch, wherein the complementary sensing bit line is connected to the complementary bit line via a fourth switch, wherein, in response to the first memory cell connected to the bit line being activated, the electrical connection between the single-ended bit line sense amplifier and the complementary bit line is cut off by the fourth switch, and In response to the second memory cell connected to the complementary bit line being activated, the electrical connection between the single-ended bit line sense amplifier and the bit line is cut off by the third switch.

9. A storage device, comprising: Peripheral circuit area; as well as a memory cell region, the memory cell region being stacked on the peripheral circuit region, wherein the memory cell region comprises a memory cell array, the memory cell array comprises normal memory cells and error correction code cells, Wherein, the peripheral circuit area includes: a single-ended bit line sense amplifier connected to the memory cell array through a bit line and a complementary bit line and electrically connected through one of the bit line and the complementary bit line when the memory cell array is activated, a cell storage data inversion circuit configured to transmit complementary input data generated by inverting the input data to the single-ended bit line sense amplifier in response to a first number of bits having a first level included in the input data being greater than a second number of bits having a second level included in the input data, and conditionally transmit a data inversion flag indicating that the input data is inverted to the single-ended bit line sense amplifier, and a unit storage data inversion register, wherein the unit storage data inversion register is configured to store the data inversion flag, The single-ended bit line sense amplifier is configured to store the complementary input data in the memory cell array and store the data inversion flag in the cell storage data inversion register.

10. The memory device according to claim 9, wherein: The unit storage data inversion register is arranged below the error correction code unit.

11. The memory device according to claim 9, wherein: The cell storage data inversion register is arranged below the normal storage cell.

12. The memory device according to claim 9, wherein: The unit storage data inversion circuit comprises: a global input / output driver configured to amplify and output the input data; a cell storage data inversion control unit configured to generate the data inversion flag and invert the input data into the complementary input data in response to the first number of bits having the first level being greater than the second number of bits having the second level; and a global input / output multiplexer configured to send the input data to the single-ended bit line sense amplifier or send the complementary input data and the data inversion flag to the single-ended bit line sense amplifier based on whether the cell storage data inversion control unit generates the complementary input data, The unit storage data inversion control unit is arranged between the global input / output driver and the global input / output multiplexer.

13. The memory device according to claim 9, wherein: The unit storage data inversion circuit comprises: a cell storage data inversion control unit, the cell storage data inversion control unit being configured to generate the data inversion flag and invert the input data into the complementary input data in response to the first number of bits having the first level being greater than the second number of bits having the second level; a global input / output driver configured to amplify and output data received from the unit storing data inverting control unit; and a global input / output multiplexer configured to send the input data to the single-ended bit line sense amplifier or send the complementary input data and the data inversion flag to the single-ended bit line sense amplifier based on whether the cell storage data inversion control unit sends the data inversion flag to the global input / output multiplexer, The unit storage data inversion control unit is arranged before the global input / output driver and is configured to send the data inversion flag to the global input / output multiplexer.

14. The memory device according to claim 9, wherein: When the cell storage data inversion circuit is configured to send the input data as is to the single-ended bit line sense amplifier when the number of bits having the first level is less than or equal to the number of bits having the second level, and The single-ended bit line sense amplifier is configured to store the input data as is in the normal memory cell.

15. A method of storing data in a memory device including a single-ended bit line sense amplifier, the method comprising: Receive input data; determining a logic level of a bit included in the input data; In response to a first number of bits of the input data having a first level being greater than a second number of bits of the input data having a second level, generating a data inversion flag corresponding to the input data; Inverting the input data into complementary input data; storing the complementary input data in a memory cell array; as well as The data inversion flag is stored in a designated area.

16. The method according to claim 15, further comprising: When the first number of bits having the first level is less than or equal to the second number of bits having the second level, the input data is stored in the memory cell array as is.

17. The method according to claim 15, wherein: Storing the data inversion flag in the designated area includes storing the data inversion flag in a cell storage data inversion register included in the memory cell array.

18. The method according to claim 15, further comprising: generating an error correction code based on the input data; as well as The combined data of the error correction code and the data inversion flag is stored in an error correction code unit included in the memory cell array.

19. The method according to claim 15, wherein: The memory device is configured to have a periphery-on-cell structure in which a memory cell region is stacked on a peripheral circuit region, and The storing of the data inversion flag in the designated area includes storing the data inversion flag in a unit storage data inversion register disposed in the peripheral circuit area.

20. The method according to claim 19, wherein: The cell storage data inversion register is disposed under a normal memory cell located in the memory cell region or under an error correction code cell located in the memory cell region.

Images