Semiconductor device

Abstract

The utility model provides a semiconductor device, which is applied to the technical field of semiconductors. According to the utility model, by changing the width of the interval between the adjacent bit line structures, the widths of the connecting pad structures formed between the different adjacent bit line structures are different in the horizontal direction, so that the positions of part of the second isolation structures are shifted, and the purpose of communicating part of the adjacent connecting pad structures is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory, including an array area composed of multiple memory cells and a peripheral area composed of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell. However, due to the limitations of process technology, existing dynamic random access memories still have many defects, and further improvements are needed to effectively enhance the performance and reliability of related memory components. Utility Model Content

[0003] The purpose of the present invention is to provide a semiconductor device to improve the reliability and performance of the semiconductor device.

[0004] In order to solve the above technical problems, the present invention provides a semiconductor device, which may at least include:

[0005] substrate;

[0006] a plurality of bit line structures, including a first bit line structure and a second bit line structure disposed on a substrate and spaced apart from each other;

[0007] a plurality of connection pad structures, arranged between adjacent bit line structures;

[0008] A plurality of isolation structures are provided between adjacent connection pad structures, wherein the isolation structures include:

[0009] a first isolation structure directly contacting the first bit line structure and the connection pad structure;

[0010] The second isolation structure is located between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the connection pad structure.

[0011] Optionally, a first interval between adjacent first bit line structures may be smaller than a second interval between adjacent first bit line structures and second bit line structures.

[0012] Optionally, the connection pad structure may further include:

[0013] a first connection pad structure, disposed between adjacent first bit line structures;

[0014] The second connection pad structure is arranged between the adjacent first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connection pad structure.

[0015] Optionally, the second connection pad structure is connected to the first connection pad structure adjacent thereto.

[0016] Optionally, the second isolation structure may be isolated from the first bit line structure and the second bit line structure.

[0017] Optionally, there is a first distance between adjacent first isolation structures, and a second distance between adjacent first isolation structures and second isolation structures, and the first distance is smaller than the second distance.

[0018] Optionally, the semiconductor device may further include:

[0019] A plurality of contact structures are arranged under the connection pad structure, and the width of the contact structure located under the first connection pad structure in the horizontal direction is smaller than the width of the contact structure located under the second connection pad structure in the horizontal direction.

[0020] Optionally, the width of the first bit line structure in the horizontal direction may be smaller than the width of the second bit line structure in the horizontal direction.

[0021] Optionally, the semiconductor device may further include:

[0022] The third bit line structure is located between the adjacent first bit line structure and the second bit line structure, and at least one of the connection pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

[0023] Optionally, the third bit line structure may include a semiconductor layer and a metal layer stacked sequentially from bottom to top, and the connection pad structure is in direct contact with the metal layer.

[0024] In the present invention, by setting the interval between adjacent first bit line structures and second bit line structures to be larger than the interval between adjacent first bit line structures, the width of the connection pad structure formed between the two adjacent first bit line structures in the horizontal direction is smaller than the width of the connection pad structure formed between the adjacent first bit line structure and the second bit line structure in the horizontal direction, thereby causing the second isolation structure formed in the connection pad structure between the adjacent first bit line structure and the second bit line structure to be offset in a direction close to the second bit line structure, so as to achieve the purpose of allowing the connection pad structure between the adjacent first bit line structure and the second bit line structure to be connected with the connection pad structure adjacent to it and located between the adjacent first bit line structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following detailed description, they are used to explain the present application but do not constitute a limitation of the present application. In the accompanying drawings:

[0026] Figure 5 It is a structural diagram of the semiconductor device in the first embodiment of the present utility model.

[0027] Figure 6 The semiconductor device provided in the first embodiment of the present invention Figure 5 Top view of the structure shown.

[0028] Figures 1 to 4 、 Figure 7 The semiconductor device provided in the first embodiment of the present invention is prepared along the Figure 6 The schematic diagram of the structure of a partial area of ​​the AA' tangent line in the top view is shown.

[0029] Figure 12 Schematic diagram of the structure of the semiconductor device in the second embodiment of the present invention.

[0030] Figure 13 The semiconductor device provided in the second embodiment of the present invention Figure 12 Top view of the structure shown.

[0031] Figures 8 to 11 、 Figure 14 The semiconductor device provided in the second embodiment of the present invention is prepared along the Figure 13 The schematic diagram of the structure of a partial area of ​​the AA' tangent line in the top view is shown.

[0032] Wherein, the accompanying drawings are marked as follows:

[0033] 100-substrate, 110-trench isolation, 120-insulating layer, 130-bit line material layer, 131-semiconductor layer, 132-barrier layer, 133-metal layer, 134-capping layer, BL-bit line structure, BL1-first bit line structure, BL2-second bit line structure, BL3-third bit line structure, SP1-first spacer, SP2-second spacer, SP3-third spacer, SP4-fourth spacer, 140-sidewall structure, 141-first sidewall, 142-second sidewall, 150-contact structure, 160-silicide layer, 170-connection pad structure, 170.1-first connection pad layer, 170.2-second connection pad layer, 171-first connection pad structure, 172-second connection pad structure, 180-isolation structure, 181-first isolation structure, 182-second isolation structure, d1-first spacing, d2-second spacing.

[0034] In the drawings, like components are given like reference numerals, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0035] The semiconductor device proposed by the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. Many specific details are set forth in the following description to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.

[0036] Please refer to Figure 5 and Figure 6 , Figure 6 The diagram shows a partial top view of a semiconductor device according to the first embodiment of the present invention. Figure 5 The semiconductor device according to the first embodiment of the present invention is shown along Figure 6 The semiconductor device of the present invention can be used to manufacture dynamic random access memory (DRAM), and can also be applied to other types of memory without departing from the spirit of the present invention.

[0037] like Figure 5As shown, the semiconductor device includes a substrate 100, a plurality of bit line structures BL, a plurality of connection pad structures 170, and a plurality of isolation structures 180. The substrate 100 may be any suitable substrate material known in the art, such as, but not limited to, a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), a silicon-on-insulator substrate, or a substrate composed of other suitable materials. In one embodiment, a plurality of trench isolations 110 (e.g., comprising silicon oxide) may be further provided within the substrate 100 to define a plurality of active regions (not shown) extending in the same direction (not shown) within the substrate 100. For example, the trench isolations 110 in this embodiment may be in the form of long strips. Furthermore, an insulating layer 120 is provided on the substrate 100. Specifically, the insulating layer 120 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as, but not limited to, an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. Illustratively, the insulating layer 120 in this embodiment is a single-layer structure (eg, including a silicon nitride layer).

[0038] In this embodiment, a bitline structure BL is disposed on a substrate 100 and includes, in detail, a plurality of first bitline structures BL1 and a second bitline structure BL2, which are separated from each other and have different widths and spacings. Specifically, the plurality of first bitline structures BL1 are sequentially arranged along a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction), and the second bitline structure BL2 is located on one side and outside of the plurality of first bitline structures BL1. Specifically, if the horizontal width of the first bitline structure BL1 is a first width and the horizontal width of the second bitline structure BL2 is a second width, then the first width is smaller than the second width. If the spacing between adjacent first bitline structures BL1 is a first spacing SP1 and the spacing between adjacent first bitline structures BL1 and second bitline structures BL2 is a second spacing SP2, then the first spacing SP1 is smaller than the second spacing SP2. In one embodiment, the first bitline structure BL1 and the second bitline structure BL2 have the same multiple bitline material layers, such as a bitline material layer 130 consisting of a semiconductor layer 131, a barrier layer 132, a metal layer 133, and a cap layer 134 stacked in ascending order. The semiconductor layer 131 may be made of, but not limited to, single crystal silicon (crystalline silicon), polycrystalline silicon (poly silicon), amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials. The barrier layer 132 may be made of, but not limited to, a metal, metal silicide, or metal nitride, such as, but not limited to, titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), or tungsten nitride (WN). The metal layer 133 may be made of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials. The capping layer 134 may include a dielectric material such as, but not limited to, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination thereof. For example, the semiconductor layer 131 may be made of polysilicon, the barrier layer 132 may be made of cobalt silicide (CoSi), the metal layer 133 may be made of tungsten (W), and the capping layer 134 may be made of silicon nitride (SiN).

[0039] In addition, the sidewalls of the first bit line structure BL1 and the second bit line structure BL2 in this embodiment may also be provided with a sidewall structure 140. The sidewall structure 140 may also have a multi-layer structure, for example Figure 5The first sidewall 141 and the second sidewall 142 are stacked in sequence along the horizontal direction, and the first sidewall 141 is in direct contact with the sidewall of the first bitline structure BL1 or the second bitline structure BL2. Specifically, the first sidewall 141 and the second sidewall 134 can each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination thereof, but not limited thereto. Exemplarily, the material of the first sidewall 141 is silicon oxide (SiO2), and the material of the second sidewall 142 is silicon nitride (SiN).

[0040] Continue to refer to Figure 5 As shown, the semiconductor device in this embodiment may further include multiple contact structures 150 and silicide layers 160. A contact structure 150 and a silicide layer 160 are formed within a first spacer SP1 between adjacent first bitline structures BL1, and within a second spacer SP2 between the first bitline structure BL1 and the second bitline structure BL2, respectively. The contact structures 150 are separated from the bitline structures BL by sidewall structures 140 on both sides and do not directly contact them. The contact structures 150 extend vertically within the substrate 100 between adjacent bitline structures BL in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction) to electrically connect to the substrate 100. In one embodiment, the contact structures 150 may be made of, but are not limited to, single crystal silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable silicon-containing semiconductor materials. Exemplarily, the material of the contact structure 150 is phosphorus-doped silicon (SiP).

[0041] Furthermore, the connection pad structure 170 in this embodiment is specifically disposed between adjacent bitline structures BL and conformally covers the top surface of the silicide layer 160, the top surface of the sidewall structure 140, and the top surface of the bitline structure BL, while the isolation structure 180 is specifically disposed between adjacent connection pad structures 170. In one embodiment, the connection pad structure 170 may include a first connection pad layer 170.1 and a second connection pad layer 170.2 stacked sequentially from bottom to top. The first connection pad layer 170.1 may be made of a conductive barrier material such as titanium and / or titanium nitride (TiN), tantalum (Ta), and / or tantalum oxide (TaN), preferably titanium nitride (TiN), but not limited thereto. The second connection pad layer 170.2 may be made of a metal such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, preferably tungsten (W), but not limited thereto.

[0042] In this embodiment, since the first spacing SP1 between adjacent first bit line structures BL1 and the second spacing SP2 between adjacent first bit line structures BL1 and second bit line structures BL2 are different, that is, the first spacing SP1 < the second spacing SP2, the connection pad structure 170 located between adjacent first bit line structures BL1 and the connection pad structure 170 located between adjacent first bit line structures BL1 and second bit line structures BL2 and the silicide layer 160 and contact structure 150 thereunder are also different in horizontal width. For ease of distinction, in this embodiment, the connection pad structure located between adjacent first bit line structures BL1 is named a first connection pad structure 171, and the connection pad structure located between adjacent first bit line structures BL1 and second bit line structures BL2 is named a second connection pad structure 172 (e.g., Figure 4 Therefore, in the embodiment of the present invention, the horizontal width of the second connection pad structure 172 is greater than the horizontal width of the first connection pad structure 171, and the horizontal width of the contact structure 150 located below the first connection pad structure 171 is also smaller than the horizontal width of the contact structure 150 located below the second connection pad structure 172.

[0043] Under this configuration, the isolation structure 180 in this embodiment can also be divided into a first isolation structure 181 and a second isolation structure 182 due to the difference between the first spacing SP1 between adjacent first bit line structures BL1 and the second spacing SP2 between adjacent first bit line structures BL1 and second bit line structures BL2. Figure 5Specifically, the first isolation structure 181 vertically passes through the first connection pad structure 171 and directly contacts the first bitline structure BL1. The second isolation structure 182 vertically passes through the second connection pad structure 172 and its bottom surface is completely covered by the second connection pad structure 172, so that the second isolation structure 182 is isolated from the first bitline structure BL1 and the second bitline structure BL2 located on both sides of the second connection pad structure 172 through which it passes. In other words, if the spacing between adjacent first isolation structures 181 is a first spacing d1, and the spacing between adjacent first isolation structures 181 and second isolation structures 182 is a second spacing d2, then the first spacing d1 is less than the second spacing d2. In one embodiment, the isolation structures 180 (including the first isolation structures 181 and the second isolation structures 182) can be made of the same material and can specifically include a nitride, such as silicon nitride, or an oxide, such as silicon oxide, preferably silicon nitride, but not limited thereto.

[0044] In the conventional technology, the adjacent first connection pad structure 171 and the second connection pad structure 172 usually need to be isolated by a second isolation structure 182 to avoid short circuit between the two contact structures 150 located below the adjacent first connection pad structure 171 and the second connection pad structure 172. However, since the first bit line structure BL1 and the second bit line structure BL2 adjacent thereto located at the edge are often used as dummy structures for adjusting the pattern density of the semiconductor device in actual applications, the second isolation structure 182 located in the second spacer SP2 between the adjacent first bit line structure BL1 and the second bit line structure BL2 is process-shifted in the horizontal direction close to the second bit line structure BL2 in an embodiment of the present invention, so that the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2 are connected, thereby avoiding the technical problem of some contact structures being peeled off during processes such as photolithography due to differences in pattern density, thereby improving the reliability and performance of the semiconductor device.

[0045] In addition, please refer to Figure 7 As shown, the semiconductor device in this embodiment may further include a capacitor structure CAP disposed on the first connection pad structure 171 between adjacent first bit line structures BL1, wherein the capacitor structure CAP includes a lower electrode BE, a dielectric layer DL, and an upper electrode TE. The lower electrode BE is disposed on the first connection pad structure 171, the upper electrode TE is disposed on the lower electrode BE, and the dielectric layer DL is disposed between the upper electrode TE and the lower electrode BE.

[0046] It should be understood that the “common shape” in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the morphological similarities and correlations between two or more shapes.

[0047] A person skilled in the art will readily appreciate that, to meet actual product requirements, the semiconductor device of the present invention may have other aspects and is not limited to the aforementioned aspects. The following further describes other embodiments or variations of the semiconductor device of the present invention. For simplicity, the following description will primarily detail the differences between the various embodiments, without reiterating the similarities. Furthermore, identical components in the various embodiments of the present invention are designated with the same reference numerals to facilitate cross-reference between the various embodiments.

[0048] Please refer to Figure 12 and Figure 13 , Figure 13 The diagram shows a partial top view of a semiconductor device according to a second embodiment of the present invention. Figure 12 The semiconductor device according to the second embodiment of the present invention is shown along Figure 13 A schematic cross-sectional view of a portion of the area along the AA' line is shown. The structure of the semiconductor device of this embodiment is substantially the same as that of the semiconductor device of the aforementioned first embodiment. For example, the semiconductor device also includes a plurality of first bitline structures BL1 disposed horizontally and spaced apart from each other on a substrate 100, a second bitline structure BL2 located outside one side of the plurality of first bitline structures BL1, and a plurality of contact structures 150. The similarities are not further described here. The main difference between the semiconductor device of this embodiment and the aforementioned first embodiment is that at least one third bitline structure BL3 is further disposed among the plurality of bitline structures BL of the semiconductor device, and the top surface of the third bitline structure BL3 is located at a different level than the top surfaces of the first bitline structure BL1 and the second bitline structure BL2, so that the second isolation structure 182 located on the top surface of the third bitline structure BL3 is also different.

[0049] Specifically, if Figure 12As shown, the semiconductor device in this embodiment includes a third bitline structure BL3 disposed between adjacent first bitline structures BL1 and second bitline structures BL2, such that a plurality of first bitline structures BL1, one third bitline structure BL3, and one second bitline structure BL2 are horizontally spaced apart, and a top surface of the third bitline structure BL3 is lower than top surfaces of the first bitline structures BL1 and the second bitline structures BL2. In one embodiment, the third bitline structure BL3 comprises multiple layers of the same bitline material, such as the semiconductor layer 131 (e.g., polysilicon), the barrier layer 132 (e.g., cobalt silicide), and the metal layer 133 (e.g., tungsten), stacked sequentially from bottom to top. The third spacing SP3 between the third bitline structure BL3 and the adjacent first bitline structure BL1 can be the same as the first spacing SP1 between adjacent first bitline structures BL1, and the fourth spacing SP4 between the third bitline structure BL3 and the adjacent second bitline structure BL2 can be smaller than the third structure SP3.

[0050] It should be noted that, in this embodiment, the connection pad structure 170 is still divided into a first connection pad structure 171 and a second connection structure, and the isolation structure 180 is also still divided into a first isolation structure 181 and a second isolation structure 182; since the multi-layer bit line material layer of the third bit line structure BL3 does not include the capping layer 134, the connection pad structure 170 located in the adjacent first bit line structure BL1 and the second bit line structure BL2 in this embodiment is changed from one in the aforementioned first embodiment to two in this embodiment, namely, a second connection pad structure 172 located in the third interval SP3 on the top surface of the third bit line structure BL3 and between the first bit line structure BL1 adjacent thereto (at this time, the first connection pad layer 170.1 in the second connection pad structure 172 is in direct contact with the metal layer 134 of the third bit line structure BL3), and a second connection pad structure 172 located in the fourth interval SP4 between the third bit line structure BL3 and the second bit line structure BL2 adjacent thereto and on the top surface of the second bit line structure BL2.

[0051] Under this setting, the isolation structure 180 located between the first bit line structure BL1 and the second bit line structure BL2 in this embodiment is also changed from a second isolation structure 182 in the aforementioned first embodiment whose bottom is completely covered by the second connection pad structure 172 to a second isolation structure 182 located above the third bit line structure BL3 and isolated from the third bit line structure BL3 and the bit line structures BL on both sides thereof, and a second isolation structure 182 located above the second bit line structure BL2 and in direct contact with the second bit line structure BL2.

[0052] Obviously, in this embodiment, the second isolation structure 182 located above the third bit line structure BL3 has undergone a process offset, so that the two adjacent second connection pad structures 172 located above the third bit line structure BL3 are connected, thereby avoiding the technical problem of some contact structures being peeled off during processes such as lithography due to large differences in graphic density, thereby improving the reliability and performance of semiconductor devices.

[0053] Furthermore, based on the same concept, an embodiment of the present invention also provides a method for manufacturing the semiconductor device, which may specifically include the following steps:

[0054] Step S100, providing a substrate 100;

[0055] Step S200 , forming a plurality of bit line structures BL, wherein the bit line structures BL include a first bit line structure BL1 and a second bit line structure BL2 , which are spaced apart from each other and disposed on a substrate 100 ;

[0056] Step S300 , forming a plurality of connection pad structures 170 , wherein the connection pad structures 170 are disposed between adjacent bit line structures BL;

[0057] In step S400, a plurality of isolation structures 180 are formed and arranged between adjacent connection pad structures 170. The isolation structure 180 includes a first isolation structure 181 that is in direct contact with the first bit line structure BL1 and the connection pad structure 170, and a second isolation structure 182 that is located between the first bit line structure BL1 and the second bit line structure BL2, and the bottom surface of the second isolation structure 182 is completely covered by the connection pad structure 170.

[0058] In order to enable a person skilled in the art to which the present invention relates to easily understand the method for manufacturing a semiconductor device in an embodiment of the present invention, the method for manufacturing a semiconductor device proposed in the present invention will be further described below in combination with various structural schematic diagrams during the preparation process of the manufacturing method.

[0059] Please refer to Figures 1 to 7 As shown, Figures 1 to 7 This is a structural diagram of the manufacturing method of the semiconductor device provided in the first embodiment of the present invention during the preparation process.

[0060] Please refer to Figure 1, performing the above steps S100 and S200: providing a substrate 100, and forming a plurality of trenches in the substrate 100 by an etching process, and then filling the plurality of trenches with an insulating material (such as silicon oxide, silicon nitride, etc.) by a deposition process, such as at least one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, to form a plurality of trench isolations 110. The plurality of trench isolations 110 define a plurality of active areas in the substrate 100. Then, forming an insulating layer 120 (such as a silicon oxide layer or a silicon nitride layer) on the substrate 100 and a plurality of bit line material layers on the insulating layer 120. Specifically, forming the multi-layer bit line material layer can include forming a semiconductor layer 131, a barrier layer 132, a metal layer 133 and a capping layer 134 in sequence from bottom to top on the substrate 100. Exemplarily, the material of the semiconductor layer 131 is polysilicon, the material of the barrier layer 132 is cobalt silicide (CoSi), the material of the metal layer 133 is tungsten (W), and the material of the capping layer 134 is silicon nitride (SiN). Subsequently, the multilayer structure of the bit line material layer is sequentially etched in the vertical direction using an etching process, thereby forming a plurality of mutually separated bit line structures BL therein; specifically, the bit line structure BL comprises a plurality of first bit line structures BL1 and a second bit line structure BL2, the plurality of first bit line structures BL1 are sequentially arranged in the horizontal direction, the second bit line structure BL2 is located on one side outside the plurality of first bit line structures BL1, and the width of the first bit line structure BL1 in the horizontal direction is smaller than the width of the second bit line structure BL2 in the horizontal direction, and the first spacing SP1 between adjacent first bit line structures BL1 is smaller than the second spacing SP2 between adjacent first bit line structures BL1 and second bit line structures BL2.

[0061] Please refer to Figure 2 , following the above-mentioned step S200, sidewall structures 140 are formed on both sides of the multiple first bit line structures BL1 and the second bit line structure BL2, which are self-aligned to the side walls of the first bit line structure BL1 and the second bit line structure BL2; in one embodiment, the sidewall structure 140 has a multi-layer structure, such as a first sidewall 141 (such as silicon oxide) and a second sidewall 142 (such as silicon nitride) stacked in sequence along the horizontal direction.

[0062] Please refer to Figure 3, following the above step S200: utilizing an etching process, etching downward along the vertical direction to form a storage node contact groove (not shown) on the outside of the sidewall structure 140 after removing the insulating layer 120 and part of the substrate 100, and then forming a contact material layer (not shown) to fully cover the substrate 100 and fill the storage node contact groove, and then utilizing an etching or planarization process to remove the contact material layer outside the storage node contact groove until the top surfaces of the bit line structure BL and the sidewall structure 140 are exposed, thereby obtaining contact structures 150 respectively located in the storage node contact groove. Among them, the contact material layer may be a silicon-containing semiconductor material, such as phosphorus-doped silicon. Then, a metal material layer (not shown) is deposited on the substrate 100, and the metal material layer and the substrate 100 and other structures are silicided, so that the top of the contact structure 150, whose material is a silicon-containing semiconductor material, such as phosphorus-doped silicon, reacts with the metal material layer to form a silicide layer 160, and obtain Figure 3 At this time, since the first spacing SP1 between adjacent first bit line structures BL1 and the second spacing SP2 between adjacent first bit line structures BL1 and second bit line structures BL2 are different, that is, the first spacing SP1 < the second spacing SP2, the horizontal width of the contact structure 150 and the silicide layer 160 thereon between adjacent first bit line structures BL1 is also different from the horizontal width of the contact structure 150 and the silicide layer 160 thereon between adjacent first bit line structures BL1 and second bit line structures BL2, that is, the horizontal width of the contact structure 150 and the silicide layer 160 thereon between adjacent first bit line structures BL1 is smaller than the horizontal width of the contact structure 150 and the silicide layer 160 thereon between adjacent first bit line structures BL1 and second bit line structures BL2.

[0063] Please refer to Figure 4, perform the above step S300: use a deposition process to deposit a first connection pad material layer (for example, titanium nitride) and a second connection pad material layer (for example, metal tungsten) of the connection pad structure 170 on the substrate 100, and etch them to form a first connection pad layer 170.1 wrapped on the surface of the silicide layer 160, the first bit line structure BL1 and the second bit line structure BL2, and a second connection pad layer 170.2 filling the gap between the adjacent first bit line structure BL1 and the second bit line structure BL2 and with a top surface higher than the top surface of the first bit line structure BL1, thereby forming a connection pad structure 170 including the first connection pad layer 170.1 and the second connection pad layer 170.2 arranged in sequence from bottom to top. Similarly, due to the difference between the first spacing SP1 between adjacent first bit line structures BL1 and the second spacing SP2 between adjacent first bit line structures BL1 and second bit line structures BL2, the multiple connection pad structures 170 in this embodiment can be specifically divided into first connection pad structures 171 and second connection pad structures 172 according to their different widths in the horizontal direction, wherein the first connection pad structure 171 is located between adjacent first bit line structures BL1, and the second connection pad structure 172 is located between adjacent first bit line structures BL1 and second bit line structures BL2, and the width of the first connection pad structure 171 in the horizontal direction is smaller than the width of the second connection pad structure 172 in the horizontal direction.

[0064] Please refer to Figure 5 , performing the above-mentioned step S400: forming a mask layer (not shown) on the connection pad structure 180, wherein the mask layer has an isolation structure pattern therein, and using the mask layer as a mask, utilizing an etching process to vertically form a plurality of isolation structures 180 on the connection pad structure 170 on one side of the bitline structure BL and a portion of the bitline structure BL. Specifically, the isolation structure 180 includes a first isolation structure 181 and a second isolation structure 182 that are spaced apart from each other and disposed sequentially along the horizontal direction. The first isolation structure 181 passes through the first connection pad structure 171, and its bottom surface extends onto the first bitline structure BL1 to directly contact the corresponding first bitline structure BL1. The second isolation structure 182 passes through the second connection pad structure 172, and its bottom surface is completely covered by the second connection pad structure 172, so that the second isolation structure 182 is isolated from the first bitline structure BL1 and the second bitline structure BL2 located on both sides of the second connection pad structure 172 through which it passes. In one embodiment, the material of the isolation structure 180 (including the first isolation structure 181 and the second isolation structure 182) may be the same and may specifically include nitride, such as silicon nitride, or may include oxide, such as silicon oxide, and is preferably silicon nitride, but is not limited thereto.

[0065] Please refer to Figure 7Following step S400, a capacitor structure CAP may be formed on the first connection pad structure 171 between adjacent first bit line structures BL1. The capacitor structure CAP includes a lower electrode BE, a dielectric layer DL, and an upper electrode TE. The lower electrode BE is disposed on the first connection pad structure 171, the upper electrode TE is disposed on the lower electrode BE, and the dielectric layer DL is disposed between the upper and lower electrodes TE.

[0066] It should be noted that, since the embodiment of the present invention is based on the fact that the first bit line structure BL1 located at the edge of the cell area and the second bit line structure BL2 located on the peripheral area are often used as dummy structures for adjusting the pattern density of the cell area in actual applications, the second isolation structure 182 located in the second spacer SP2 between the adjacent first bit line structure BL1 and the second bit line structure BL2 is process-shifted in the horizontal direction close to the second bit line structure BL2 so that the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2 are connected, when the isolation structure 180 is formed using the above step S400, When the manufacturing process adopted by the present invention forms an isolation trench (not shown, at the same position as the isolation structure) in the first connection pad structure 171 and the second connection pad structure 172, the isolation trench located in the second connection pad structure 172 needs to be offset along the horizontal direction close to the second bit line structure BL2, and then the entire bottom surface of the second isolation structure 182 formed after filling the isolation trench with insulating material (such as silicon nitride) by a deposition process is covered by the second connection pad structure 172, thereby realizing the connection between the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2.

[0067] Please refer to Figures 8 to 14 As shown, Figures 8 to 14 This is a structural schematic diagram of the manufacturing method of a semiconductor device provided in the second embodiment of the present invention during the preparation process.

[0068] The structure of the semiconductor device of this embodiment is substantially the same as the manufacturing method of the semiconductor device of the aforementioned first embodiment, and the similarities are not repeated here. The main difference between the manufacturing method of the semiconductor device of this embodiment and the manufacturing method of the aforementioned first embodiment is that after performing the above-mentioned step S200 to form a plurality of first bit line structures BL1 and a second bit line structure BL2 sequentially spaced apart from each other in the horizontal direction, the cap layer 134 of a first bit line structure BL1 adjacent to the second bit line structure BL2 can be further removed by an etching process such as a dry etching process to form a third bit line structure BL3 between the adjacent first bit line structures BL1 and the second bit line structure BL2. Figure 8 It should be understood that in other embodiments, the sidewall structure 140 may be formed on the sidewalls of the first bit line structure BL1 and the second bit line structure BL2, and then an etching process may be used to form the sidewall structure 140. Figure 9 The structure described above is not limited thereto.

[0069] In summary, in the present invention, by setting the interval between adjacent first bit line structures and second bit line structures to be larger than the interval between adjacent first bit line structures, the width of the connection pad structure formed between the two adjacent first bit line structures in the horizontal direction is smaller than the width of the connection pad structure formed between the adjacent first bit line structure and the second bit line structure in the horizontal direction, thereby causing the second isolation structure formed in the connection pad structure between the adjacent first bit line structure and the second bit line structure to be offset in a direction close to the second bit line structure, thereby achieving the purpose of allowing the connection pad structure between the adjacent first bit line structure and the second bit line structure to be connected with the connection pad structure adjacent to it and located between the adjacent first bit line structures.

[0070] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0071] Each embodiment in this specification is described in a related manner. Similar portions between the various embodiments can be referenced to each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device, electronic device, and computer-readable storage medium embodiments are generally similar to the method embodiments, so their descriptions are relatively simple. For related portions, reference can be made to the descriptions of the method embodiments.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; a plurality of bit line structures, including a first bit line structure and a second bit line structure disposed on a substrate and spaced apart from each other; a plurality of connection pad structures, arranged between adjacent bit line structures; A plurality of isolation structures are provided between adjacent connection pad structures, wherein the isolation structures include: a first isolation structure directly contacting the first bit line structure and the connection pad structure; The second isolation structure is located between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the connection pad structure.

2. The semiconductor device according to claim 1, wherein A first spacing between adjacent first bit line structures is smaller than a second spacing between adjacent first bit line structures and second bit line structures.

3. The semiconductor device according to claim 2, wherein The connection pad structure includes: a first connection pad structure, disposed between adjacent first bit line structures; The second connection pad structure is arranged between the adjacent first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connection pad structure.

4. The semiconductor device according to claim 3, wherein The second connection pad structure is connected to the first connection pad structure adjacent thereto.

5. The semiconductor device according to claim 1, wherein The second isolation structure is isolated from the first bit line structure and the second bit line structure.

6. The semiconductor device according to claim 1, wherein There is a first distance between adjacent first isolation structures, and a second distance between adjacent first isolation structures and second isolation structures, and the first distance is smaller than the second distance.

7. The semiconductor device according to claim 3, wherein Also includes: A plurality of contact structures are arranged under the connection pad structure, and the width of the contact structure located under the first connection pad structure in the horizontal direction is smaller than the width of the contact structure located under the second connection pad structure in the horizontal direction.

8. The semiconductor device according to claim 1, wherein A width of the first bit line structure in the horizontal direction is smaller than a width of the second bit line structure in the horizontal direction.

9. The semiconductor device according to claim 1, wherein Also includes: The third bit line structure is located between the adjacent first bit line structure and the second bit line structure, and at least one of the connection pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

10. The semiconductor device according to claim 9, wherein The third bit line structure includes a semiconductor layer and a metal layer stacked sequentially from bottom to top, and the connection pad structure is in direct contact with the metal layer.

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