Three-dimensional dynamic random access memory array structure

Abstract

The present disclosure provides a three-dimensional DRAM array structure including L layers, M rows, and N columns of DRAM cell structures, each DRAM cell structure including first and second gate transistors having a tubular channel, disposed in a vertical direction and electrically connected in parallel, and a storage capacitor of a tubular structure disposed between the first and second gate transistors in the vertical direction, an inner electrode of the second transistor is connected to the first source / drain of the first and second gate-all-around transistors, and an outer electrode is connected to a source line; the M * N bit lines respectively extend in a tubular structure jointly formed by the first and second gate-all-around transistors and the storage capacitor in the M-row and N-column DRAM unit structure along the vertical direction, and are respectively connected to second source / drain electrodes of the first and second gate-all-around transistors; the L * M first word lines and the L * M second word lines extend in the first horizontal direction and are connected to grid electrodes of the first fence transistors and the second fence transistors in the L layers of DRAM unit structures respectively, and the M rows of DRAM unit structures are divided into M / s row groups.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a three-dimensional dynamic random access memory (DRAM) array structure. Background Art

[0002] Since Intel Corporation invented Dynamic Random Access Memory (DRAM) in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit typically consists of a selection transistor and a storage capacitor (1T1C structure) for storing charge. In a DRAM cell structure that uses a conventional planar horizontal transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), to implement the selection transistor, the transistor's source, gate, and drain are arranged horizontally parallel to the substrate surface. Because the transistor's source, gate, and drain each occupy independent areas in the horizontal direction, the scaling of the DRAM cell circuit structure is limited by gate length and contact size, making it impossible to meet the continued scaling requirements of DRAM devices. This in turn limits the integration density and bandwidth of DRAM devices.

[0004] Therefore, in recent years, a vertical DRAM cell structure has been proposed, in which the source, gate, and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface. This eliminates the need for additional area and facilitates the miniaturization of the DRAM array structure. Furthermore, by vertically stacking multiple layers of DRAM cells to form a three-dimensional DRAM array, memory integration density can be further increased.

[0005] DRAM manufacturing is a highly competitive industry. The industry continually needs to reduce the size of individual cells and increase memory cell density, thereby packing more memory onto a single memory chip.

[0006] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0007] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel three-dimensional dynamic random access memory (DRAM) array structure.

[0008] According to one aspect of the present disclosure, a three-dimensional DRAM array structure is provided, comprising: a plurality of DRAM cell structures arranged into L layers, M rows, and N columns, wherein L, M, and N are natural numbers greater than 1, each of the plurality of DRAM cell structures comprising: a first gate-all-around transistor and a second gate-all-around transistor, each having a tubular channel structure, arranged in sequence in a vertical direction and electrically connected in parallel, and a storage capacitor having a tubular structure, arranged in a vertical direction between the first gate-all-around transistor and the second gate-all-around transistor, with an inner electrode connected to a first source / drain of the first gate-all-around transistor and the second gate-all-around transistor, and an outer electrode connected to a source line; and M×N bit lines, respectively arranged in the vertical direction between the M rows and N columns of the DRAM cell. The first gate-around transistor and the second gate-around transistor and the storage capacitor in the structure extend inside the tubular structure and are respectively connected to the second source / drain of the first gate-around transistor and the second gate-around transistor in the M-row N-column DRAM cell structure; L×M first word lines extend along the first horizontal direction and are respectively connected to the gate of the first gate-around transistor in the L-layer M-row DRAM cell structure; and L×M second word lines extend along the first horizontal direction and are respectively connected to the gate of the second gate-around transistor in the L-layer M-row DRAM cell structure, wherein the M-row DRAM cell structure is divided into M / s row groups, where s is a natural number greater than 1, and each row group shares the same L first word lines and L second word lines.

[0009] The DRAM cell structure constituting the DRAM array structure according to the present disclosure includes two gate-all-around transistors and a storage capacitor mirrored in the vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two gate-all-around transistors are formed by the same semiconductor material layer, and thus has the advantages of simple structure and good switching performance.

[0010] Furthermore, the DRAM array structure according to the present disclosure can achieve three-dimensional vertical integration by stacking multiple layers of DRAM cells, thereby improving integration density. Furthermore, the DRAM array structure according to the present disclosure can be stacked on a circuit substrate including multiple circuits, thereby achieving system-level three-dimensional vertical integration, thereby significantly reducing the area overhead of the circuit system.

[0011] Furthermore, the DRAM array structure according to the present disclosure can maximize the use of the area in the horizontal direction by arranging the DRAM cell structure in a honeycomb arrangement in the horizontal direction.

[0012] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the inventive concept.

[0014] Figure 1 is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0015] Figure 2 is a perspective view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0016] Figure 3 is a top view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0017] Figure 4 is shown along Figure 3 FIG. 5 is a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken along line AA′ in FIG.

[0018] Figure 5 is shown along Figure 3 FIG. 5 is a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken along line BB′ in FIG.

[0019] Figure 6 is shown along Figure 4 FIG. 5 is a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken along line CC′ in FIG.

[0020] Figure 7 is shown along Figure 4 FIG. 5 is a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken along line DD′ in FIG.

[0021] Figure 8 The embodiment according to the present disclosure is shown by Figure 1 The equivalent circuit diagram of the DRAM array structure formed by the DRAM cell structure shown.

[0022] Figure 9 It shows Figure 8 FIG. 1 is an equivalent circuit diagram of a DRAM cell structure in a first row of a DRAM array structure according to an embodiment of the present disclosure.

[0023] Figure 10 It shows Figure 8 FIG. 1 is a schematic perspective view of a first-layer first-row DRAM cell structure of a DRAM array structure according to an embodiment of the present disclosure.

[0024] Figure 11 It shows Figure 8 is a top view of a partial DRAM array structure of a DRAM array structure according to an embodiment of the present disclosure.

[0025] Figure 12 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line AA' in Figure 11

[0026] Figure 13 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line BB' in Figure 11

[0027] Figure 14 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line CC' in Figure 12

[0028] Figure 15 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line DD' in Figure 12

[0029] Figure 16 is an equivalent circuit diagram illustrating a DRAM array structure having an alternative configuration of word lines according to an embodiment of the present disclosure.

[0030] Figure 17 is an equivalent circuit diagram illustrating a DRAM array structure having an alternative configuration of bit lines according to an embodiment of the present disclosure.

[0031] Figure 18 is an equivalent circuit diagram illustrating a DRAM array structure having an alternative configuration of word lines and bit lines according to an embodiment of the present disclosure.

[0032] Figure 19 is a top view of a partial DRAM array structure of a DRAM array structure according to another embodiment of the present disclosure.

[0033] Figure 20 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line AA' in Figure 19

[0034] Figure 21 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line BB' in Figure 19

[0035] Figure 22 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line CC' in Figure 20 ​​​​​​​

[0036] Figure 23 is shown along Figure 20 FIG. 5 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken along line DD′ in FIG. DETAILED DESCRIPTION

[0037] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be implemented without these specific details or with one or more equivalent configurations. In addition, each exemplary embodiment can be different, but does not have to be exclusive. For example, without departing from the present invention, the specific features of other exemplary embodiments can be used or implemented in some exemplary embodiments.

[0038] Unless otherwise specified, the exemplary embodiments described should be understood as providing exemplary features of varying details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or reconfigured without departing from the inventive concept.

[0039] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0040] Although terms such as "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0041] The terms used herein are for the purpose of describing specific embodiments, but are not intended to be restrictive. As used herein, the singular forms "a" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprise" and / or "comprising" mean that there are stated features, steps, operations, elements, parts and / or their groups, but do not exclude the presence or increase of one or more other features, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to account for the inherent deviations in the values ​​measured, calculated and / or provided that are recognized by those of ordinary skill in the art.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0043] The various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be exhaustive and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout, the same reference numerals represent the same components. Furthermore, in the drawings, for clarity of illustration, the components are not necessarily drawn to scale, and the proportions and dimensions of the components may be exaggerated.

[0044] Hereinafter, a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 An equivalent circuit diagram of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown.

[0046] like Figure 1 As shown, the DRAM cell structure 100 according to the embodiment of the present disclosure may adopt a 2T1C (i.e., two gate transistors and one storage capacitor) cell structure. Specifically, the DRAM cell structure 100 may include two gate-all-around (GAA) transistors sequentially arranged in a vertical direction (z direction) and electrically connected in parallel, i.e., a first GAA transistor T1 and a second GAA transistor T2. The first and second GAA transistors T1 and T2 may each have (as described below with reference to Figures 2 to 17The channel of the tubular structure (described above) is used as a gate transistor of the DRAM cell structure 100.

[0047] According to an embodiment of the present disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2 are commonly connected to one plate (inner electrode) of the memory capacitor C, and the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 are commonly connected to the bit line BL. According to an embodiment of the present disclosure, the bit line BL can extend in the vertical direction (z direction). In addition, according to an embodiment of the present disclosure, the gate G1 of the first GAA transistor T1 can be connected to the first word line WLA, and the gate G2 of the second GAA transistor T2 can be connected to the second word line WLB. According to an embodiment of the present disclosure, the first word line WLA and the second word line WLB can extend along the first horizontal direction (y direction) and overlap in the vertical direction (z direction). According to an embodiment of the present disclosure, the first word line WLA and the second word line WLB can be shorted together. Alternatively, according to an embodiment of the present disclosure, the first word line WLA and the second word line WLB may not be shorted together to control the first GAA transistor T1 and the second GAA transistor T2 respectively.

[0048] Furthermore, according to an embodiment of the present disclosure, the other plate (external electrode) of the storage capacitor C can be connected to a source line SL. Those skilled in the art will appreciate that, in a DRAM array structure composed of the DRAM cell structure 100 according to the present disclosure, the source lines SL of all DRAM cell structures can be connected together in common or in groups, and thus the source line SL may also be referred to herein as a "common electrode."

[0049] Figure 2 A perspective view of a DRAM cell structure 100 is shown according to an embodiment of the present disclosure. Figure 3 A top view of a DRAM cell structure 100 is shown, according to an embodiment of the present disclosure. Figure 4 Shown along Figure 3 1 is a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken along line AA′ in FIG. Figure 5 Shown along Figure 3 1 is a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken along line BB′ in FIG. Figure 6 Shown along Figure 4 FIG. 1 is a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken along line CC′ in FIG. Figure 7 Shown along Figure 4 DD′ in FIG. 1 is a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure.

[0050] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a bit line hole (eg, Figure 3 、 Figure 6 and Figure 7 The hole having a circular cross section in the center as shown in FIG1 ), and the common electrode groove (such as FIG1 ) extending in the first horizontal direction (y direction) and penetrating the DRAM cell structure 100 in the vertical direction (z direction) Figure 2 、 Figure 3 、 Figure 4 、 Figure 6 and Figure 7 The trenches are shown on either side of the central bitline hole).

[0051] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a conductor line 109 disposed in a bit line hole, the conductor line 109 extending in a vertical direction (z direction) and may be used as Figure 1 The bit line BL of the DRAM cell structure 100 shown in FIG. According to an embodiment of the present disclosure, the material used to form the conductor line 109 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. In particular, according to an embodiment of the present disclosure, the conductor line 109 may have a cylindrical shape extending in the vertical direction (z direction). For example, as Figure 3 、 Figure 6 and Figure 7 As shown, the conductor wire 109 may be a cylinder having a first diameter d1 .

[0052] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a semiconductor material layer 107 having a tubular structure and surrounding a conductor line 109 and a first isolation material layer 111 disposed in a bit line hole. Figure 4 and Figure 5 As shown more clearly, the upper and lower ends of the semiconductor material layer 107 directly contact the conductor line 109, and the middle portion of the semiconductor material layer 107 is separated from the conductor line 109 by the first isolation material layer 111. In other words, according to an embodiment of the present disclosure, the semiconductor material layer 107 and the first isolation material layer 111 both have a tubular structure surrounding the conductor line 109. Figure 3 、 Figure 6 and Figure 7In the figure, the tubular structure has a circular cross-section, but the present disclosure is not limited thereto. Those skilled in the art should recognize that the tubular structure may also have a cross-section of any other shape, such as an elliptical, square or rectangular cross-section, and the cross-sectional shape of the conductor line 109 may be adjusted accordingly.

[0053] According to an embodiment of the present disclosure, the material used to form the first isolation material layer 111 can be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, phosphate glass, or a combination thereof. According to an embodiment of the present disclosure, the material used to form the first isolation material layer 111 can also be a low-K material. The low-K material can have a lower dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of approximately 3.9, and the first isolation material layer 111 can include a low-K material with a dielectric constant of approximately 3.9 or lower. According to an embodiment of the present disclosure, the low-K material can include porous silicon oxide (SiO2), organic silicon, fluorinated silicon glass (FSG), hydrogen silsesquioxane (HSQ), silicon oxycarbide (SiCOH), or polymer materials such as parylene, polyimide (PI), etc. According to an embodiment of the present disclosure, the material used to form the first isolation material layer 111 can also be a combination of the above-mentioned dielectric materials and the above-mentioned low-K materials.

[0054] According to an embodiment of the present disclosure, the material used to form the semiconductor material layer 107 may be a semiconductor thin film material, such as single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compounds, compound semiconductors, oxide semiconductors, sulfide semiconductors, graphene, or a combination thereof. According to an embodiment of the present disclosure, the material used to form the semiconductor material layer 107 may be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium oxide (InO), zinc oxide (ZnO), indium tungsten oxide (InWO), or indium aluminum oxide (InAlO) in different proportions. In particular, according to an embodiment of the present disclosure, the semiconductor material layer 107 may include a single layer of IGZO or a stack of multiple layers of IGZO in different proportions.

[0055] Furthermore, according to an embodiment of the present disclosure, as described in more detail below, the semiconductor material layer 107 may be formed as follows: Figure 1 The source / drain regions and channel regions of the first GAA transistor T1 and the second GAA transistor T2 are shown, wherein the source / drain regions of the first GAA transistor T1 and the second GAA transistor T2 correspond to the first source / drain S / D11 and the second source / drain S / D12 of the first GAA transistor T1 and the first source / drain S / D21 and the second source / drain S / D22 of the second GAA transistor T2. It should be noted here that the source / drain region described from a structural perspective is equivalent to the source / drain described from a circuit perspective. In addition, according to an embodiment of the present disclosure, the semiconductor material layer 107 can also be formed as follows: Figure 1 The inner electrode of the storage capacitor C is shown. Therefore, according to an embodiment of the present disclosure, the storage capacitor C may also have a tubular structure.

[0056] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include two first dielectric layers 106 disposed in the bit line hole and surrounding the upper and lower ends of the semiconductor material layer 107, respectively. According to an embodiment of the present disclosure, the two first dielectric layers 106 may be formed as follows: Figure 1 The gate dielectrics of the first GAA transistor T1 and the second GAA transistor T2 are shown. Figure 4 and Figure 5 As shown, according to an embodiment of the present disclosure, the first dielectric layer 106 may also have a tubular structure with a bent cross-section. In other words, Figures 2 to 5 As shown, in a cross-section along the vertical direction (z direction), the first dielectric layer 106 may have a thinner first portion near the end of the conductor line 109 and a thicker second portion farther from the end of the conductor line 109 relative to the first portion. The first portion and the second portion may be connected by a connecting portion in the horizontal direction. According to an embodiment of the present disclosure, the material used to form the first dielectric layer 106 may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), or a combination thereof.

[0057] Therefore, according to an embodiment of the present disclosure, the first GAA transistor T1 and the second GAA transistor T2 are each formed to have a tubular structure and each has a tubular channel.

[0058] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a lower first gate layer 104 and an upper second gate layer 105 disposed to surround the thicker second portion of the lower and upper first dielectric layers 106, respectively. Figure 2 and Figure 6 As shown, according to an embodiment of the present disclosure, the first gate layer 104 and the second gate layer 105 may have a strip shape with a hole in the middle. According to an embodiment of the present disclosure, the first gate layer 104 may correspond to Figure 1 The gate G1 of the first GAA transistor T1 is shown, and the second gate layer 105 may correspond to Figure 1 The gate G2 of the second GAA transistor T2 is shown. Figure 2 、 Figure 3 and Figure 5As shown, according to an embodiment of the present disclosure, the first gate layer 104 may extend in the first horizontal direction (y direction) to further correspond to Figure 1 The first word line WLA is connected to the first gate G1 of the first GAA transistor T1. Accordingly, according to an embodiment of the present disclosure, the second gate layer 105 can extend in the first horizontal direction (y direction) to further correspond to the first word line WLA of the first gate G1 of the first GAA transistor T1. Figure 1 The second word line WLB is shown connected to the gate G2 of the second GAA transistor T2. According to an embodiment of the present disclosure, the first word line WLA and the second word line WLB can be led out from the far end in the first horizontal direction (y direction).

[0059] Therefore, according to an embodiment of the present disclosure, the DRAM cell structure 100 may have a bit line BL extending in a vertical direction (z-direction), and a first word line WLA and a second word line WLB extending in a first horizontal direction (y-direction). According to an embodiment of the present disclosure, the bit line BL of the DRAM cell structure 100 may extend vertically within a tubular structure formed by the first and second GAA transistors T1 and T2 and the storage capacitor C. Furthermore, according to an embodiment of the present disclosure, the first gate layer 104 and the second gate layer 105 corresponding to the first and second word lines WLA and WLB of the DRAM cell structure 100 may overlap in the vertical direction (z-direction).

[0060] In addition, according to an embodiment of the present disclosure, the material used to form the first gate layer 104 and the second gate layer 105 may include titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline silicon / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof.

[0061] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include two second isolation material layers 103 disposed to surround the thinner first portion of the upper and lower first dielectric layers 106, respectively. Figure 2 and Figure 3 As shown, according to an embodiment of the present disclosure, the second isolation material layer 103 may have a strip shape with a hole in the middle. According to an embodiment of the present disclosure, the material used to form the second isolation material layer 103 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiCOH), or aluminum oxide (Al2O3). According to an embodiment of the present disclosure, the first isolation material layer 111 and the second isolation material layer 103 may be formed of the same or different isolation materials.

[0062] like Figure 4 and Figure 5 As shown, according to an embodiment of the present disclosure, as described above, the semiconductor material layer 107 may include a formation indicated by a shadow in the vertical direction (z direction). Figure 1 The first portion 1071 of the channel region of the first and second GAA transistors T1 and T2, and the first portion 1071 formed between Figure 1 The first source / drain region of the first GAA transistor T1 (corresponding to the first source / drain S / D11 of the first GAA transistor T1), the first source / drain region of the second GAA transistor T2 (corresponding to the first source / drain S / D21 of the second GAA transistor T2), and the second portion 1072 of the inner electrode of the memory capacitor C are shown. Therefore, according to an embodiment of the present disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2 are connected to the inner electrode of the memory capacitor C. According to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 are separated from the conductor line 109 (bit line BL) by a first isolation material layer 111 surrounding the conductor line 109 (bit line BL).

[0063] According to an embodiment of the present disclosure, the doping type, doping concentration and / or atomic component ratio of the second portion 1072 of the semiconductor material layer 107 can be changed by material modification processes such as doping and etching, so that it has better conductivity as the internal electrode of the memory capacitor C. That is, according to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 can have different doping types, doping concentrations and / or atomic component ratios. According to an embodiment of the present disclosure, when the semiconductor material layer 107 is an IGZO oxide semiconductor, all or part of the gallium (Ga) atoms in the second portion 1072 can be removed by, for example, an etching process to improve its conductivity, or part of the oxygen (O) atoms in the second portion 1072 can be removed by, for example, an etching process to form metal atom fillings or oxygen atom vacancies to improve its conductivity.

[0064] In addition, if Figure 4 and Figure 5 As shown, according to the embodiment of the present disclosure, as described above, the semiconductor material layer 107 may further include two ends of the contact conductor line 109 along the vertical direction (z direction) for Figure 1The third portion 1073 of the second source / drain region of the first GAA transistor T1 (corresponding to the second source / drain S / D12 of the first GAA transistor T1) and the second source / drain region of the second GAA transistor T2 (corresponding to the second source / drain S / D22 of the second GAA transistor T2) is shown, as well as a first horizontal connection portion 1074 connecting the first portion 1071 and the third portion 1073. Therefore, according to an embodiment of the present disclosure, the third portion 1073 of the semiconductor material layer 107 is in contact with the conductor line 109, so that the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 corresponding to the third portion 1073 of the semiconductor material layer 107 are connected to the bit line BL corresponding to the conductor line 109.

[0065] like Figure 3 As shown, according to an embodiment of the present disclosure, the third portion 1073 of the semiconductor material layer 107 of the tubular structure may have a second diameter d2 that is greater than the first diameter d1 of the conductor line 109. Figures 3 to 7 As shown, according to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 of the tubular structure may have a third diameter d3 that is greater than the second diameter d2 of the third portion 1073 of the semiconductor material layer 107 .

[0066] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a second dielectric layer 108 disposed in the common electrode groove and serving as a capacitor dielectric for the storage capacitor C. According to an embodiment of the present disclosure, the second dielectric layer 108 may be conformally formed along the groove wall of the common electrode groove. Figure 2 and Figure 4 As shown, according to an embodiment of the present disclosure, the second dielectric layer 108 may contact the two second isolation material layers 103, the first gate layer 104 and the second gate layer 105, and the second portion of the semiconductor material layer 107 in the second horizontal direction (x direction). Figure 2 and Figure 5 As shown, according to an embodiment of the present disclosure, the second dielectric layer 108 may contact the second portion of the semiconductor material layer 107 in a first horizontal direction (y direction). The first horizontal direction, ie, the y direction, may be perpendicular to the second horizontal direction, ie, the x direction.

[0067] In addition, according to an embodiment of the present disclosure, the material used to form the second dielectric layer 108 may be a high-K material. The high-K material may have a higher dielectric constant than silicon oxide. Silicon oxide may have a dielectric constant of approximately 3.9, and the second dielectric layer 108 may include a high-K material having a dielectric constant of approximately 4 or greater. According to an embodiment of the present disclosure, the high-K material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanium oxide (SrTiO3), or a combination thereof.

[0068] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include an electrode layer 110 extending along the surface of the second dielectric layer 108 and filling the common electrode groove. According to an embodiment of the present disclosure, the electrode layer 110 may correspond to Figure 1 The outer electrode of the storage capacitor C shown, that is, the common electrode of the storage capacitor C, and the source line SL. Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the electrode layer 110 corresponding to the external electrode of the storage capacitor C and the source line SL can extend in the first horizontal direction (y direction) and penetrate the DRAM cell structure 100 in the vertical direction (z direction). According to an embodiment of the present disclosure, the material used to form the electrode layer 110 can include titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polysilicon / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof. Therefore, according to an embodiment of the present disclosure, the storage capacitor C of the DRAM cell structure 100 can be formed as a pillar capacitor.

[0069] In addition, although not shown in the figures, according to an embodiment of the present disclosure, a third isolation material layer may be further provided between the first gate layer 104 and the second gate layer 105 and the second dielectric layer 108 to reduce parasitic capacitance and leakage current between the external electrode (source line SL) of the storage capacitor and the gates G1 and G2 (i.e., the first and second word lines WLA and WLB) of the first and second GAA transistors T1 and T2.

[0070] Figure 8 The embodiment of the present disclosure is shown in FIG. Figure 1 The equivalent circuit diagram of the DRAM array structure 200 formed by the DRAM cell structure shown in FIG. Figure 8 As shown, according to the embodiment of the present disclosure, by Figure 1The DRAM array structure 200 formed by the illustrated DRAM cell structure may be a three-dimensional DRAM array structure stacked in a vertical direction (z direction).

[0071] like Figure 8 As shown, according to an embodiment of the present disclosure, the DRAM array structure 200 may include: Figure 1 Multiple DRAM cell structures 100 are shown. For clarity, certain reference numerals within each DRAM cell structure are omitted. According to an embodiment of the present disclosure, multiple DRAM cell structures are arranged into L layers, M rows, N columns, and L layers, where L, M, and N are all natural numbers greater than 1. In this document, each of the multiple DRAM cell structures included in the DRAM array structure 200 can be represented as Clmn, that is, a DRAM cell structure located in the mth row, nth column, and lth layer in the DRAM array structure 200, where m, n, and l are natural numbers, and 1≤m≤M, 1≤n≤N, and 1≤l≤L. In addition, in this document, M represents the number of rows of DRAM cell structures of the DRAM array structure 200 along the first horizontal direction (y direction), N represents the number of columns of DRAM cell structures of the DRAM array structure 200 along the second horizontal direction (x direction), and L represents the number of layers of DRAM cell structures of the DRAM array structure 200 along the vertical direction (z direction).

[0072] According to an embodiment of the present disclosure, cell selection operations of a plurality of DRAM cell structures included in the DRAM array structure 200 may be performed through L×M first word lines WLA11 to WLALM and L×M second word lines WLB11 to WLBLM and M×N bit lines BL11 to BLMN.

[0073] Therefore, if Figure 8 As shown, according to an embodiment of the present disclosure, in the DRAM array structure 200, each layer in the L-layer DRAM cell structure includes M rows and N columns, totaling M×N DRAM cell structures, each row in the M-row DRAM cell structure includes L layers and N columns, totaling L×N DRAM cell structures, and each column in the N-column DRAM cell structure includes L layers and M rows, totaling L×M DRAM cell structures.

[0074] As mentioned above Figures 1 to 7 As described, each of the multiple DRAM cell structures included in the DRAM array structure 200 may include: a first GAA transistor and a second GAA transistor, both having a tubular structure channel, arranged in sequence in a vertical direction and electrically connected in parallel; and a storage capacitor, having a tubular structure, arranged between the first GAA transistor and the second GAA transistor in the vertical direction, and its inner electrode is connected to the first source / drain of the first GAA transistor and the second GAA transistor.

[0075] In addition, if Figure 8 As shown, according to an embodiment of the present disclosure, the DRAM array structure 200 may further include M×N bit lines BL11 to BLMN, which extend in a vertical direction inside a tubular structure composed of L first GAA transistors and L second GAA transistors and L storage capacitors in the M rows and N columns DRAM cell structure, and are respectively connected to the second source / drain of the L first GAA transistors and L second GAA transistors in the M rows and N columns DRAM cell structure.

[0076] In addition, although not shown, according to an embodiment of the present disclosure, in each row of the M-row DRAM array structure, L first word lines WLA1m to WLALm may be connected to L second word lines WLB1m to WLBLm, respectively. Figure 8 As shown, in the first row of the DRAM array structure, the first word line WLA11 can be connected to the second word line WLB11, the first word line WLA21 can be connected to the second word line WLB21, and so on, until the first word line WLAL1 can be connected to the second word line WLBL1. According to an embodiment of the present disclosure, in each row of the M-row DRAM array structure, the corresponding connections of the L first word lines and the L second word lines can be implemented from a remote end outside the array. Herein, since the pairs of first word lines WLAlm and second word lines WLBlm extending along the first horizontal direction (y direction) can be connected together, they can be collectively referred to as word lines WL and are given the same number as the corresponding first word line WLAlm and second word line WLBlm, i.e., WLlm. At this point, according to an embodiment of the present disclosure, the cell selection operation of the multiple DRAM cell structures included in the DRAM array structure 200 can be performed through the L×M word lines WL11 to WLLM and the M×N bit lines BL11 to BLMN.

[0077] In addition, according to an embodiment of the present disclosure, the DRAM array structure 200 may further include L source lines SL corresponding to the L-layer DRAM cell structures, which extend along the first horizontal direction (y direction) and are respectively connected to the external electrodes of the storage capacitors in the L-layer DRAM cell structures. Figure 8 As shown, according to an embodiment of the present disclosure, the L source lines SL can be connected together by a common electrode groove provided between the bit lines and extending vertically (z-direction) throughout the entire DRAM array structure 200. In this case, the source lines SL also extend in the vertical direction (z-direction). Although not shown, according to an alternative embodiment of the present disclosure, the L source lines SL can also be connected together only in common or in groups outside the DRAM array structure 200, omitting the common electrode groove.

[0078] Figure 9 is a diagram illustrating Figure 8 An equivalent circuit diagram of the first row of DRAM cell structures C111 to CL1N of the DRAM array structure 200 according to the embodiment of the present disclosure is shown in FIG. 2B. As shown in FIG. 2B, each of the N x L DRAM cell structures C111 to CL1N in the first row of the DRAM array structure 200 includes a first GAA transistor T1, a second GAA transistor T2, and a storage capacitor C. Figure 9 As shown in FIG. 2A, the first row first column first layer DRAM cell structure C111 is provided at the intersection of the first row first column bit line BL11 extending in the vertical direction (z direction) and the first layer word line (the first word line WLA11 and the second word line WLB11) extending in the first horizontal direction (y direction). By analogy, Figure 9 As shown in FIG. 2A, the first row of the DRAM array structure 200 includes N x L DRAM cell structures C111 to CL1N.

[0079] As described above with reference to Figure 1 , according to the embodiment of the present disclosure, each of the plurality of DRAM cell structures constituting the DRAM array structure 200, for example, Figure 9 As shown in FIG. 2B, the DRAM cell structure C111 includes a first GAA transistor T1, a second GAA transistor T2, and a storage capacitor C.

[0080] Figure 10 is a diagram illustrating Figure 8 A schematic perspective view of the first layer first row DRAM cell structure of the DRAM array structure 200 according to the embodiment of the present disclosure is shown in FIG. 3A. As shown in FIG. 3A, in the first layer first row DRAM cell structure of the DRAM array structure, the first layer first row word line WL11 (the first word line WLA11 and the second word line WLB11) can extend in the first horizontal direction (y direction), and the first row bit line (only BL11 to BL13 are shown) can extend in the vertical direction (z direction). According to the embodiment of the present disclosure, the source line SL of the first layer DRAM cell structure can extend in the first horizontal direction (y direction). In addition, as shown in FIG. 3A, the source line SL can also be connected together with the source line SL in other layers in the common electrode groove extending in the vertical direction (z direction). Figure 10 Figure 10

[0081] In addition, as shown in FIG. 3B, according to the embodiment of the present disclosure, the mth row nth column bit line BLmn can be commonly connected to the second source / drain of the L first GAA transistors and the L second GAA transistors in the mth row nth column DRAM cell structure of the DRAM array structure 200 for performing a cell selection operation on the mth row nth column DRAM cell structure. Figures 8 to 10

[0082] Figure 11 is a diagram illustrating Figure 8 ​​​FIG. 1 is a top view of a partial DRAM array structure 201 of a DRAM array structure 200 according to an embodiment of the present disclosure. Figure 12 is shown along Figure 11 FIG. 2 is a cross-sectional view of a DRAM array structure 201 according to an embodiment of the present disclosure, taken along line AA′ in FIG. Figure 13 is shown along Figure 11 FIG. 2 is a cross-sectional view of a DRAM array structure 201 according to an embodiment of the present disclosure, taken along line BB′ in FIG. Figure 14 is shown along Figure 12 FIG. 2 is a cross-sectional view of a DRAM array structure 201 according to an embodiment of the present disclosure, taken along line CC′ in FIG. Figure 15 is shown along Figure 12 DD′ in FIG. 1 is a cross-sectional view of a DRAM array structure 201 according to an embodiment of the present disclosure.

[0083] It should be noted that Figures 11 to 15 The example shown in Figure 8 The local DRAM array structure 201 of a portion of the DRAM array structure 200 shown in the figure includes DRAM cell structures C111, C112, C121, C122, C211, C212, C221 and C222 from the first layer, first row and first column to the second layer, second row and second column. These eight DRAM cell structures are arranged in two rows, two columns and two layers.

[0084] According to an embodiment of the present disclosure, the M rows and N columns of bit lines BL11 to BLMN of the DRAM array structure 200 may extend in a vertical direction (z-direction) and be arranged in an M×N matrix in a first horizontal direction (y-direction) and a second horizontal direction (x-direction). Furthermore, according to an embodiment of the present disclosure, the L layers of DRAM cell structures of the DRAM array structure 200 are stacked sequentially in the vertical direction, and each layer of DRAM cell structures includes M×N DRAM cell structures.

[0085] Specifically, if Figures 11 to 15 As shown, two rows and two columns of four bit lines BL11, BL12, BL21 and BL22 may extend in the vertical direction (z direction) and be arranged in a 2×2 matrix in the first horizontal direction (y direction) and the second horizontal direction (x direction). Figure 12 and Figure 13 As shown, the first layer of DRAM cell structures C111, C112, C121, and C122 are stacked above the second layer of DRAM cell structures C211, C212, C121, and C222.

[0086] like Figure 11 and Figure 12As shown, the first-tier, first-row, first word line WLA11 is connected to the gates of the first GAA transistors in the first-tier, first-row DRAM cell structures C111 and C112, and the first-tier, second word line WLB11 is connected to the gates of the second GAA transistors in the first-tier, first-row DRAM cell structures C111 and C112. Similarly, the first-tier, second-row, first word line WLA12 is connected to the gates of the first GAA transistors in the first-tier, second-row DRAM cell structures C121 and C122, and the first-tier, second-row, second word line WLB12 is connected to the gates of the second GAA transistors in the first-tier, second-row DRAM cell structures C121 and C122. Similarly, the second-tier, first-row, first word line WLA21 is connected to the gates of the first GAA transistors in the second-tier, first-row DRAM cell structures C211 and C212, and the second-tier, first-row, second word line WLB21 is connected to the gates of the second GAA transistors in the second-tier, first-row DRAM cell structures C211 and C212. Similarly, the second-layer second-row first word line WLA22 is connected to the gates of the first GAA transistors in the second-layer second-row DRAM cell structures C221 and C222, and the second-layer second-row second word line WLB22 is connected to the gates of the second GAA transistors in the second-layer second-row DRAM cell structures C221 and C222.

[0087] like Figures 11 to 15As shown, four bit lines BL11, BL12, BL21, and BL22 are respectively formed in four bit line holes extending in the vertical direction (z direction) through the DRAM array structure. Specifically, the first row and first column bit line BL11 extends vertically inside the tubular structure formed by the first GAA transistor and the second GAA transistor and the storage capacitor in the first row and first column DRAM cell structures C111 and C211, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the first row and first column DRAM cell structures C111 and C211. Similarly, the first row and second column bit line BL12 extends vertically inside the tubular structure formed by the first GAA transistor and the second GAA transistor and the storage capacitor in the first row and second column DRAM cell structures C112 and C212, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the first row and second column DRAM cell structures C112 and C212. Similarly, the second-row, first-column bit line BL21 extends vertically within the tubular structure formed by the first and second GAA transistors and storage capacitors in the second-row, first-column DRAM cell structures C121 and C221, and is connected to the second sources / drains of the first and second GAA transistors in the second-row, first-column DRAM cell structures C121 and C221. Similarly, the second-row, second-column bit line BL22 extends vertically within the tubular structure formed by the first and second GAA transistors and storage capacitors in the second-row, second-column DRAM cell structures C122 and C222, and is connected to the second sources / drains of the first and second GAA transistors in the second-row, second-column DRAM cell structures C122 and C222.

[0088] According to an embodiment of the present disclosure, in each of the M rows × N columns of the DRAM cell structure, the first and second source / drain electrodes, the channel region, and the inner electrodes of the storage capacitor of the first and second GAA transistors are formed from the same semiconductor material layer. That is, according to an embodiment of the present disclosure, in each of the M × N bitline holes that penetrate the L-layer DRAM cell structure in the vertical direction (z direction), the first and second source / drain electrodes, the channel region, and the inner electrodes of the storage capacitor of the first and second GAA transistors in the L-layer DRAM cell structure are formed from the same semiconductor material layer having a tubular structure. That is, the semiconductor material layer having the tubular structure extends vertically (z direction) through the entire DRAM array structure 200.

[0089] Specifically, if Figures 11 to 15As shown, the first source / drain and second source / drain electrodes, channel regions, and internal electrodes of storage capacitors of the first and second GAA transistors in the first-layer DRAM cell structure C111 and the second-layer DRAM cell structure C211 connected to the first-row, first-column bit line BL11 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain electrodes, channel regions, and internal electrodes of storage capacitors of the first and second GAA transistors in the first-layer DRAM cell structure C112 and the second-layer DRAM cell structure C212 connected to the first-row, second-column bit line BL12 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain electrodes, channel regions, and internal electrodes of storage capacitors of the first and second GAA transistors in the first-layer DRAM cell structure C121 and the second-layer DRAM cell structure C221 connected to the second-row, first-column bit line BL21 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain, channel region and internal electrodes of the storage capacitor of the first and second GAA transistors in the first-layer DRAM cell structure C122 and the second-layer DRAM cell structure C222 connected to the second-row and second-column bit line BL22 are formed by the same semiconductor material layer.

[0090] According to an embodiment of the present disclosure, the common electrode groove can extend in the first horizontal direction (y direction) and penetrate the L-layer DRAM array structure in the vertical direction (z direction). At this time, the L source lines SL corresponding to the L-layer DRAM cell structure can be connected together in the vertical direction (z direction). In addition, according to an embodiment of the present disclosure, DRAM cell structures in adjacent rows in the second horizontal direction (x direction) can share a common electrode groove. In addition, as described above, the capacitor dielectric and external electrodes of the storage capacitors in each DRAM cell structure of the DRAM array structure 200 can be set in the common electrode groove.

[0091] Alternatively, according to an embodiment of the present disclosure, in the DRAM array structure 200 , the common electrode groove may be omitted, and the source lines SL may extend only in the first horizontal direction (y direction) and be connected together in common or in groups outside the DRAM array structure 200 .

[0092] Figure 16 is an equivalent circuit diagram illustrating a DRAM array structure 200 ′ having an alternative configuration of word lines according to an embodiment of the present disclosure. Figure 16 In, with Figure 8 The same components are denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0093] Combine Figure 8 Reference Figure 16 , Figure 16The DRAM array structure 200' shown is similar to Figure 8 The difference of the DRAM array structure 200 shown is that, in the first layer of the DRAM cell structure, the M first word lines WLA11 to WLA1M can be connected together by a common first word line GWLA1 extending in the second horizontal direction (x direction), and the M second word lines WLB11 to WLB1M can be connected together by a common second word line GWLB1 extending in the second horizontal direction (x direction). Specifically, Figure 16 As shown, the first word lines WLA11 to WLA1M of the first-tier DRAM cell structure can be connected together by a first-tier common first word line GWLA1 extending in the second horizontal direction (x-direction), and the second word lines WLB11 to WLB1M of the first-tier DRAM cell structure can be connected together by a first-tier common second word line GWLB1 extending in the second horizontal direction (x-direction). Similarly, the first word lines WLA21 to WLA2M of the second-tier DRAM cell structure can be connected together by a second-tier common first word line GWLA2 extending in the second horizontal direction (x-direction), and the second word lines WLB21 to WLB2M of the second-tier DRAM cell structure can be connected together by a second-tier common second word line GWLB2 extending in the second horizontal direction (x-direction). And so on, the first word lines WLAL1 to WLALM of the L-th layer DRAM cell structure can be connected together by the L-th layer common first word line GWLAL extending in the second horizontal direction (x direction), and the second word lines WLBL1 to WLBLM of the L-th layer DRAM cell structure can be connected together by the L-th layer common second word line GWLBL extending in the second horizontal direction (x direction).

[0094] At this time, according to an embodiment of the present disclosure, the DRAM array structure 200' has L common first word lines GWLA1 to GWLAL, L common second word lines GWLB1 to GWLBL, and M×N bit lines BL11 to BLMN. According to an embodiment of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented through the common first word line GWLA1, the common second word line GWLB1, and the bit line BLmn.

[0095] Furthermore, according to an embodiment of the present disclosure, in each row of the M-row DRAM array structure, L first word lines WLA1m to WLALm are connected to L second word lines WLB1m to WLBLm, respectively. Figure 16The illustrated DRAM array structure 200' can be further simplified to L common word lines GWL1 to GWLL. At this time, according to an embodiment of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented by the common word line GWLl and the bit line BLmn.

[0096] Accordingly, Figure 16 The illustrated DRAM array structure 200', compared to Figure 8 The illustrated DRAM array structure 200 can simplify the word line configuration.

[0097] Figure 17 is an equivalent circuit diagram illustrating a DRAM array structure 200" having an alternative configuration of bit lines according to an embodiment of the present disclosure. In Figure 17 the same components are denoted by the same reference numerals, and repetitive description thereof will be omitted. Figure 8 In connection with

[0098] reference will be made to Figure 8 , Figure 17 , Figure 17 The illustrated DRAM array structure 200" is different from the illustrated DRAM array structure 200 in that, in the nth column of DRAM cell structures, M bit lines BL1n to BLMn can be connected together by an nth column of common bit lines GBLn extending in the second horizontal direction (x direction). Specifically, as Figure 8 illustrated, the bit lines BL11 to BLM1 of the first column of DRAM cell structures can be connected together by a first column of common bit lines GBL1 extending in the second horizontal direction (x direction). Similarly, the bit lines BL12 to BLM2 of the second column of DRAM cell structures can be connected together by a second column of common bit lines GBL2 extending in the second horizontal direction (x direction). By analogy, the bit lines BL1N to BLMN of the Nth column of DRAM cell structures can be connected together by an Nth column of common bit lines GBLN extending in the second horizontal direction (x direction). Figure 17 At this time, according to an embodiment of the present disclosure, the DRAM array structure 200" has L x M first word lines WLA11 to WLALM, L x M second word lines WLB11 to WLBLM, and N common bit lines GBL1 to GBLN. According to an embodiment of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200" can be implemented by the first word line WLAlm, the second word line WLBlm, and the common bit line GBLn.

[0099]

[0100] ​Furthermore, according to an embodiment of the present disclosure, in each row of the M-row DRAM array structure, L first word lines WLA1m to WLALm are connected to L second word lines WLB1m to WLBLm, respectively. Figure 17 The DRAM array structure 200" shown can be further simplified into L×M word lines WL11 to WLLM. At this time, according to an embodiment of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200" can be implemented through the word line WLlm and the common bit line GBLn.

[0101] therefore, Figure 17 The DRAM array structure 200" shown is compared to Figure 8 The DRAM array structure 200 shown can simplify the bit line configuration.

[0102] Figure 18 is an equivalent circuit diagram illustrating a DRAM array structure 200"' having an alternative configuration of word lines and bit lines according to an embodiment of the present disclosure. Figure 18 In, with Figure 8 The same components are denoted by the same reference numerals, and repeated descriptions thereof will be omitted.

[0103] Combine Figure 8 、 Figure 16 and Figure 17 Reference Figure 18 , Figure 18 The DRAM array structure 200" shown can be viewed as Figure 16 The DRAM array structure 200' and Figure 17 Specifically, according to an embodiment of the present disclosure, M rows of DRAM cell structures can be divided into several row groups, that is, two or more rows of DRAM cell structures can be combined into one row group. As an example and not a limitation, in Figure 18 As shown in the DRAM array structure 200', M rows of DRAM cell structures may include M / 2 row groups, that is, every two rows of DRAM cell structures may be combined into one row group. Those skilled in the art will appreciate that each row group in the M rows of DRAM cell structures may also include three or more rows.

[0104] According to an embodiment of the present disclosure, the word lines of the DRAM cell structures of the multiple rows included in each row group can be connected together by a common word line extending in the second horizontal direction (x direction). Figure 18In the illustrated DRAM array structure 200', in the first row group, the first word line and the second word line of the two rows of DRAM cell structures in the first layer can be connected together through the common first word line GWLA11 and the common second word line GWLB11, respectively, and the first word line and the second word line of the two rows of DRAM cell structures in the second layer can be connected together through the common first word line GWLA21 and the common second word line GWLB21, respectively. Similarly, in the first row group, the first word line and the second word line of the two rows of DRAM cell structures in the Lth layer can be connected together through the common first word line GWLAL1 and the common second word line GWLBL1, respectively. Similarly, in Figure 18 In the illustrated DRAM array structure 200', in the second row group, the first word lines and the second word lines of the two rows of DRAM cell structures in the first layer can be connected together through the common first word line GWLA12 and the second word line GWLB12, respectively, and the first word lines and the second word lines of the two rows of DRAM cell structures in the second layer can be connected together through the common first word line GWLA22 and the common second word line GWLB22, respectively. Similarly, in the second row group, the first word lines and the second word lines of the two rows of DRAM cell structures in the Lth layer can be connected together through the common first word line GWLAL2 and the common second word line GWLBL2, respectively.

[0105] Furthermore, according to an embodiment of the present disclosure, bit lines of the same column of the DRAM cell structure of the corresponding row in each row group can be connected together. Figure 18 In the DRAM array structure 200'' shown, the bit lines of the first row and first column DRAM cell structures in each row group can be connected together by a common bit line GBL11 extending in the second horizontal direction (x direction), and the bit lines of the first row and second column DRAM cell structures in each row group can be connected together by a common bit line GBL12 extending in the second horizontal direction (x direction), until the bit lines of the first row and N column DRAM cell structures in each row group can be connected together by a common bit line GBL1N extending in the second horizontal direction (x direction). Similarly, in Figure 18 In the illustrated DRAM array structure 200', the bit lines of the second row and first column DRAM cell structures in each row group can be connected together via a common bit line GBL21 extending in the second horizontal direction (x-direction), and the bit lines of the second row and second column DRAM cell structures in each row group can be connected together via a common bit line GBL22 extending in the second horizontal direction (x-direction), until the bit lines of the second row and N column DRAM cell structures in each row group can be connected together via a common bit line GBL2N extending in the second horizontal direction (x-direction).

[0106] At this time, according to an embodiment of the present disclosure, the DRAM array structure 200'" has L×M / 2 common first word lines GWLA11 to GWLAL(M / 2), L×M / 2 common second word lines GWLB11 to GWLBL(M / 2), and 2N common bit lines GBL11 to GBL2N.

[0107] In addition, according to an embodiment of the present disclosure, in each layer of the L-layer DRAM cell structure, the common first word line GWLA and the common second word line GWLB of the DRAM cell structures of multiple rows included in each row group can be further connected together. Figure 18 The DRAM array structure 200'" shown can be further simplified to include L×M / 2 common word lines GWL11 to GWLL(M / 2).

[0108] therefore, Figure 18 The DRAM array structure 200" shown is compared to Figure 8 The DRAM array structure 200 shown can simplify both bit line and word line configurations.

[0109] Compare Figure 8 and Figures 16 to 18 The DRAM array structure shown is a case where the corresponding first word line WLA and second word line WLB are connected together. Figure 8 The operation of the illustrated DRAM array structure 200 requires L×M word lines and M×N bit lines, ie, a total of L×M+M×N lines. Figure 16 The operation of the illustrated DRAM array structure 200 ′ requires L word lines and M×N bit lines, ie, a total of L+M×N lines. Figure 17 The operation of the DRAM array structure 200" shown requires L x M word lines and N bit lines, that is, a total of L x M + N lines. Figure 18 The operation of the DRAM array structure 200'' shown requires L×M / 2 word lines and 2N bit lines, that is, a total of L×M / 2+2N lines are required. As is well known to those skilled in the art, the number of L (i.e., the number of layers) is usually smaller than the number of M (i.e., the number of rows) and the number of N (i.e., the number of columns). For example, the DRAM array structure may include a 64-layer 1024-row×1024-column cell structure, that is, L=64, M=N=1024. Obviously, in this example, Figure 8 and Figures 16 to 18 The DRAM array structure shown is ordered by the number of lines required for operation as follows: Figure 8 L×M+M×N=<1114112> Figure 16 L+M×N=<1048640> Figure 17 L×M+N=66560> Figure 18L×M / 2+2N=34816. Obviously, Figure 18 The operation of the DRAM array structure 200"' shown requires a minimum number of lines. In addition, as described above, although Figure 18 2 shows that in the DRAM array structure 200', each row group includes two rows, but the present disclosure is not limited thereto, and each row group may also include three or more rows. That is, Figure 18 The number of lines required for the operation of the DRAM array structure 200" shown may be L×M / s+N×s, where s is a natural number greater than 1. As will be described below with reference to Figures 19 to 23 As described above, the upper limit of s is determined by factors such as the manufacturing process. By adjusting the size of s, the number of lines required for the operation of the DRAM array structure 200" can be minimized, thereby reducing the area overhead of the corresponding memory peripheral driver circuit and reducing the parasitic capacitance of the bit lines.

[0110] Despite Figures 10 to 15 The DRAM cell structure of the DRAM array structure 200 is shown as being arranged in a matrix along the first horizontal direction (y direction) and the second horizontal direction (x direction), but the present disclosure is not limited thereto. According to an embodiment of the present disclosure, as shown below in combination with Figures 19 to 23 To describe in more detail, the DRAM cell structures of the DRAM array structure 200'" may also be arranged in a hexagonal form, ie, a honeycomb form, in a plane defined by a first horizontal direction (y direction) and a second horizontal direction (x direction).

[0111] Figure 19 A top view of a partial DRAM array structure according to another embodiment of the present disclosure is shown. Figure 20 is shown along Figure 19 FIG. 5 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken along line AA′ in FIG. Figure 21 is shown along Figure 19 FIG. 5 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken along line BB′ in FIG. Figure 22 is shown along Figure 20 FIG. 5 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken along line CC′ in FIG. Figure 23 is shown along Figure 20 FIG. 5 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken along line DD′ in FIG.

[0112] It should be noted that Figures 19 to 23 The example shows the use of Figure 18 The DRAM array structure 200" shown in FIG. 1 is similar to the local DRAM array structure of the DRAM array structure, except that Figures 19 to 23 In the partial DRAM array structure shown, every four rows are combined into a row group instead of every two rows. In other words, Figures 19 to 23 The DRAM array structure shown has M / 4 row groups. Figures 19 to 23 The DRAM cell structure of the 1st column of the 1st row group (including the 1st to 4th rows) of the 1st layer of the DRAM array structure is shown, which includes the DRAM cell structures C111, C112, C121, C122, C123, C131, C132, C141, C142, C143 of the 1st layer and the DRAM cell structures C211, C212, C221, C222, C223, C231, C232, C241, C242, C243 of the 2nd layer.

[0113] According to the embodiments of the present disclosure, Figures 19 to 23 As shown, the row groups of the DRAM array structure can be defined by common electrode grooves. That is, according to an embodiment of the present disclosure, the common electrode grooves can extend in a first horizontal direction (y direction) and penetrate the DRAM array structure in a vertical direction (x direction) between the row groups. By using common electrode grooves to define the row groups, no common electrode grooves are provided between the rows in each row group, and thus the word lines corresponding to the rows in each row group are short-circuited together in the second horizontal direction (x direction), thereby avoiding the need to further provide common word lines to connect the word lines corresponding to multiple rows in each row group.

[0114] exist Figures 19 to 23 In FIG, each of the 20 DRAM cell structures is shown by a dotted line. In particular, Figures 19 to 23 As shown, each DRAM cell structure has a cylindrical configuration with a radius Rd.

[0115] According to the embodiments of the present disclosure, Figures 19 to 23 As shown, the DRAM cell structures (and corresponding bit lines) in each row group of M rows of DRAM cell structures can be arranged in a regular hexagonal (honeycomb) form in a first horizontal direction (y-direction) and a second horizontal direction (x-direction). In addition, according to an embodiment of the present disclosure, L layers of DRAM cell structures in the DRAM array structure are stacked sequentially in the vertical direction, and each layer of DRAM cell structures includes M×N DRAM cell structures.

[0116] Accordingly, if Figures 19 to 23 As shown, the ten bit lines BL11, BL12, BL21, BL22, BL23, BL31, BL32, BL41, BL42, and BL43 may extend in a vertical direction (z direction) and be arranged in a honeycomb form on a plane defined by a first horizontal direction (y direction) and a second horizontal direction (x direction). Figure 20and Figure 21 As shown, the DRAM cell structures C111, C112, C121, C122, C123, C131, C132, C141, C142, and C143 of the first layer are stacked on the DRAM cell structures C211, C212, C221, C222, C223, C231, C232, C241, C242, and C243 of the second layer, respectively.

[0117] In addition, if Figure 20 and Figure 21 As shown, the first-layer common first word line GWLA11 is connected to the gate of the first GAA transistor in each DRAM cell structure C111, C112, C121, C122, C123, C131, C132, C141, C142, and C143 of the first-layer first row group, and the first-layer common second word line GWLB11 is connected to the gate of the second GAA transistor in each DRAM cell structure C111, C112, C121, C122, C123, C131, C132, C141, C142, and C143 of the first-layer first row group. Similarly, the second-layer common first word line GWLA21 is connected to the gate of the first GAA transistor in each DRAM cell structure C211, C212, C221, C222, C223, C231, C232, C241, C242, and C243 of the second-layer first row group, and the second-layer common second word line GWLB21 is connected to the gate of the second GAA transistor in each DRAM cell structure C211, C212, C221, C222, C223, C231, C232, C241, C242, and C243 of the second-layer first row group.

[0118] In addition, if Figure 19 、 Figure 22 and Figure 23 As shown, ten bit lines BL11, BL12, BL21, BL22, BL23, BL31, BL32, BL41, BL42, and BL43 may be formed in ten bit line holes extending vertically (z-direction) through the DRAM array structure. Specifically, for example, bit line BL11 extends vertically and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the DRAM cell structures C111 and C211.

[0119] As mentioned above, Figures 19 to 23 The structure of each DRAM cell in the DRAM array structure shown and the connection configuration with the corresponding bit line and word line are similar to those described above. Figures 11 to 17Each of the DRAM cell structures in the described DRAM array structure and the connection configuration with the respective bit lines and word lines are identical, and thus are not further described in detail here for the sake of brevity. In comparison with the DRAM array structure shown in Figures 11 to 17 the arrangement of the DRAM cell structures in the DRAM array structure shown in Figures 19 to 23 the DRAM cell structures in the DRAM array structure shown in Figures 11 to 17 the arrangement of the DRAM cell structures in the DRAM array structure shown in

[0120] Furthermore, as shown in Figures 19 to 23 in the first row group of the DRAM array structure defined by the adjacent common electrode trenches, the DRAM cell structures are arranged in a hexagonal pattern, i.e. a honeycomb pattern. In other words, in Figures 19 to 23 the first row group of the DRAM array structure, the four rows of DRAM cell structures extending in the first horizontal direction (y-direction) are arranged staggered with respect to each other, at which time the pitch of the adjacent common electrode trenches in the second horizontal direction (x-direction) can be calculated as (2+3√3) Rd. Figures 11 to 17 the arrangement of the DRAM cell structures in the DRAM array structure shown in

[0121] In the DRAM array structure 200"' shown in Figure 18 in the DRAM array structure 200"' shown in

[0122] Therefore, within a row group of the DRAM array structure defined by adjacent common electrode grooves, two or more rows of DRAM cell structures extending in the first horizontal direction (y-direction) may be arranged, staggered or not staggered. The number of rows of DRAM cell structures arranged within a row group of the DRAM array structure defined by adjacent common electrode grooves may be determined by factors such as the manufacturing process and the width of the common bit line.

[0123] In addition, according to an embodiment of the present disclosure, the common electrode groove can also be omitted in the DRAM array structure 200. In this case, the unit structure of the DRAM array structure 200 can be arranged in a honeycomb form on a plane defined by the first horizontal direction (y direction) and the second horizontal direction (x direction).

[0124] The DRAM cell structure constituting the DRAM array structure according to the present disclosure includes two gate-all-around transistors and a storage capacitor mirrored in the vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two gate-all-around transistors are formed by the same semiconductor material layer, and thus has the advantages of simple structure and good switching performance.

[0125] In particular, the unit structure utilizes a vertical structure to solve the connection problem between the source and drain of the transistor and the inner electrode of the storage capacitor, and is suitable for three-dimensional vertical integration of multi-layer units. Moreover, the vertical structure is suitable for one-time processing of multi-layer units, without the need for multiple epitaxial processes and processing processes, and has low manufacturing costs.

[0126] Furthermore, the DRAM array structure according to the present disclosure can achieve three-dimensional vertical integration by stacking multiple layers of DRAM cells, thereby improving integration density. Furthermore, the DRAM array structure according to the present disclosure can be stacked in a circuit substrate including multiple circuits, thereby achieving system-level three-dimensional vertical integration, thereby significantly reducing the area overhead of the circuit system.

[0127] Furthermore, the DRAM array structure according to the present disclosure can maximize the use of the area in the horizontal direction by arranging the DRAM cell structure in a honeycomb pattern on a plane defined by the first horizontal direction (y direction) and the second horizontal direction (x direction).

[0128] While numerous details have been described herein, these should not be construed as limiting the disclosure or the scope of possible protection, but rather as describing features that can be particular to certain embodiments. Certain features described herein in the context of separate embodiments can also be implemented in combination. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any suitable subcombination. Furthermore, although features can be described above as acting in certain combinations and even initially claimed as such, in some cases, one or more features from a claimed combination can be excised from the combination, and the claimed combination can be directed to a subcombination or variation of a subcombination.

Claims

1. A three-dimensional dynamic random access memory (DRAM) array structure, comprising: A plurality of DRAM cell structures are arranged in L layers, M rows, and N columns, where L, M, and N are natural numbers greater than 1, each of the plurality of DRAM cell structures comprising: A first gate-all-around transistor and a second gate-all-around transistor, each having a tubular channel structure, are arranged in sequence in a vertical direction and electrically connected in parallel, and a storage capacitor having a tubular structure, disposed vertically between the first gate-all-around transistor and the second gate-all-around transistor, with an inner electrode connected to the first source / drain of the first gate-all-around transistor and the second gate-all-around transistor, and an outer electrode connected to a source line; M×N bit lines extending vertically inside a tubular structure formed by a first all-around gate transistor and a second all-around gate transistor and a storage capacitor in an M-row, N-column DRAM cell structure, and connected to second sources / drains of the first all-around gate transistor and the second all-around gate transistor in the M-row, N-column DRAM cell structure, respectively; L×M first word lines extending along a first horizontal direction and respectively connected to gates of first gate-all-around transistors in L layers and M rows of DRAM cell structures; and L×M second word lines extending along the first horizontal direction and respectively connected to the gates of the second gate-all-around transistors in the L layers and M rows of DRAM cell structures; M rows of DRAM cell structures are divided into M / s row groups, where s is a natural number greater than 1, and each row group shares the same L first word lines and L second word lines.

2. The three-dimensional DRAM array structure according to claim 1 , further comprising: M×N bit line holes extend in the vertical direction and penetrate the DRAM array structure, and the M×N bit lines are respectively arranged in the M×N bit line holes.

3. The three-dimensional DRAM array structure according to claim 1, wherein: L layers of DRAM cell structures are stacked sequentially in the vertical direction, and In each row group, L first word lines and L second word lines are alternately stacked in sequence in the vertical direction.

4. The three-dimensional DRAM array structure according to claim 1, wherein: In each row group, the DRAM cell structure is arranged in a square or regular hexagonal form in the horizontal direction.

5. The three-dimensional DRAM array structure according to claim 1, in, The L first word lines in each row group are respectively connected to L second word lines, and The bit lines of the same column of the DRAM cell structure of the corresponding row in each row group are connected together.

6. The three-dimensional DRAM array structure according to claim 1 , further comprising: L source lines, corresponding to the L layers of DRAM cell structures, extend along the first horizontal direction and are respectively connected to external electrodes of storage capacitors in the L layers of DRAM cell structures.

7. The three-dimensional DRAM array structure according to claim 6, further comprising: A common electrode groove extends in the first horizontal direction and penetrates the DRAM array structure in the vertical direction between row groups, and the L source lines are connected together through the common electrode groove.

8. The three-dimensional DRAM array structure according to claim 6, wherein: The L source lines are connected together in common or in groups outside the DRAM array structure.

9. The three-dimensional DRAM array structure according to claim 1, wherein: The first and second sources / drains, the channel regions, and the inner electrodes of the storage capacitors of the first and second gate-all-around transistors in the L-layer DRAM cell structure of each of the M rows and N columns are formed from the same semiconductor material layer.

10. The three-dimensional DRAM array structure according to claim 9, wherein: The semiconductor material layer includes a single IGZO layer or a stack of multiple IGZO layers with different ratios.

11. The three-dimensional DRAM array structure according to claim 9, wherein: The semiconductor material layer includes single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene or a combination thereof.

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