Memory, bit line control method and electronic equipment

Abstract

The present disclosure provides a memory, a bit line control method and an electronic device, in a first chip of the memory, each memory array chip includes a plurality of memory layer groups stacked in sequence along a third direction, in the memory layer groups of odd numbers, each local bit line is coupled to a respective first common bit line via a respective bit line selector, and in the memory layer groups of odd numbers, each local bit line is coupled to a respective second common bit line via a respective bit line selector. Each local bit line is coupled to a respective second common bit line through a respective pre-charge switch; in the even-numbered storage layer group, each local bit line is coupled to a respective first common bit line through a respective pre-charge switch, and each local bit line is coupled to a respective second common bit line through a respective bit line selector.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and particularly to a memory, a bit line control method, and an electronic device. Background Art

[0002] With the development of semiconductor technology, semiconductor memories are widely used in electronic devices. Dynamic Random Access Memory (DRAM) belongs to a type of volatile memory. Because of its fast access speed, dynamic random access memory is often used as a cache.

[0003] A dynamic random access memory mainly includes two parts: a periphery circuit and a memory array (core). In order to further improve the storage density, a three-dimensional DRAM (3D DRAM) sets the periphery circuit and the memory array (core) in two independent chips respectively, and then connects the two chips by bonding. However, for the current 3D DRAM, there is a serious local bit line coupling problem (BL-to-BL Coupling), resulting in the loss of sensing margin. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory, a bit line control method, and an electronic device.

[0005] The technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, the present disclosure provides a memory. The memory includes a first chip. The first chip includes a plurality of memory array slices, and each memory array slice includes a plurality of memory layer groups stacked in sequence along a third direction; each memory layer group has a plurality of local bit lines extending along a first direction, and the plurality of local bit lines are arranged in sequence along a second direction; a first common bit line is provided on a first side of each memory layer group, and a second common bit line is provided on a second side of each memory layer group. The first side and the second side are opposite to each other along the first direction. The first direction and the second direction intersect, and the third direction is perpendicular to the first direction and perpendicular to the second direction; each memory layer group further includes a plurality of bit line selectors and a plurality of precharge switches; the plurality of memory layer groups are numbered along the third direction: in the odd-numbered memory layer groups, each local bit line is coupled to its respective first common bit line via its respective bit line selector, and each local bit line is coupled to its respective second common bit line via its respective precharge switch; in the even-numbered memory layer groups, each local bit line is coupled to its respective first common bit line via its respective precharge switch, and each local bit line is coupled to its respective second common bit line via its respective bit line selector.

[0007] In some embodiments, a first stepped contact structure is further provided on a first side of the first common bit line, and a second stepped contact structure is further provided on a second side of the second common bit line. Both the first stepped contact structure and the second stepped contact structure are connected to the sense amplification region; the first common bit lines of the odd-numbered storage layer groups are connected to the first stepped contact structure, and the second common bit lines of the even-numbered storage layer groups are connected to the second stepped contact structure.

[0008] In some embodiments, both the first stepped contact structure and the second stepped contact structure include multiple levels of steps. Each first common bit line of the odd-numbered storage layer groups is coupled to one sense amplifier in the sense amplification region via one step of the first stepped contact structure; each second common bit line of the even-numbered storage layer groups is coupled to one sense amplifier in the sense amplification region via one step of the second stepped contact structure.

[0009] In some embodiments, for the first stepped contact structure, a plurality of consecutive levels of steps form a step group, and multiple step groups are arranged at intervals along a second direction; for the second stepped contact structure, a plurality of consecutive levels of steps form a step group, and multiple step groups are arranged at intervals along the second direction.

[0010] In some embodiments, the memory further includes a second chip. The first chip and the second chip are stacked along a third direction and are bonded to each other; the sense amplification region is located in the second chip.

[0011] In some embodiments, each memory array slice further includes a plurality of local word lines, and each local word line penetrates through a plurality of storage layer groups along the third direction.

[0012] In some embodiments, the memory further includes a plurality of common word lines extending along the second direction, and a plurality of local word lines aligned along the second direction are coupled to the same common word line.

[0013] In some embodiments, the storage layer group further includes a plurality of memory cells, and each memory cell is respectively connected to a local bit line and a local word line;

[0014] The memory is configured to, during a read operation or a write operation, for a selected memory cell, control the bit line selector of the local bit line connected thereto to be in an on state, and control the precharge switch of the local bit line connected thereto to be in an off state; for an unselected memory cell, control the bit line selector of the local bit line connected thereto to be in an off state, and control the precharge switch of the local bit line connected thereto to be in an on state.

[0015] In some embodiments, in the odd-numbered storage layer groups, each precharge switch is located on a third side of the corresponding local bit line, and each bit line selector is located on a fourth side of the corresponding local bit line; the third side and the fourth side are opposite to each other along the second direction.

[0016] In the even-numbered memory bank groups, each precharge switch is located on the fourth side of the corresponding local bit line, and each bit line selector is located on the third side of the corresponding local bit line.

[0017] In some embodiments, both the bit line selector and the precharge switch are CMOS switches.

[0018] In a second aspect, embodiments of the present disclosure provide a bit line control method, which is applied to the memory as described in the first aspect. The method includes:

[0019] Based on the address signal, select a plurality of local bit lines aligned along the third direction in the target memory array slice;

[0020] In the odd-numbered memory bank groups, control the selected local bit lines to be electrically connected to the first common bit line of the memory bank group to which they belong, and control the unselected local bit lines to be electrically connected to the second common bit line of the memory bank group to which they belong; and, in the even-numbered memory bank groups, control the selected local bit lines to be electrically connected to the second common bit line of the memory bank group to which they belong, and control the unselected local bit lines to be electrically connected to the first common bit line of the memory bank group to which they belong.

[0021] In some embodiments, the method further includes:

[0022] Control the bit line selector of the selected local bit line to be in the on state, and the precharge switch of the selected local bit line to be in the off state, so that the selected local bit lines in the odd-numbered memory banks are electrically connected to the first common bit line, and the selected local bit lines in the even-numbered memory banks are electrically connected to the second common bit line;

[0023] Control the bit line selector of the unselected local bit line to be in the off state, and the precharge switch of the unselected local bit line to be in the on state, so that the unselected local bit lines in the odd-numbered memory banks are electrically connected to the second common bit line, and the unselected local bit lines in the even-numbered memory banks are electrically connected to the first common bit line.

[0024] In some embodiments, the method further includes: for the odd-numbered memory bank groups, control the potential of the second common bit line to be the precharge potential; and make the potential of the first common bit line be a low potential or a high potential through charge sharing and sense amplification processing; for the even-numbered memory bank groups, control the potential of the first common bit line to be the precharge potential; and make the potential of the second common bit line be a low potential or a high potential through charge sharing and sense amplification processing; wherein, low potential < precharge potential < high level.

[0025] In a third aspect, embodiments of the present disclosure provide an electronic device, and the electronic device includes the memory as described in the first aspect.

[0026] Embodiments of the present disclosure provide a memory, a bit line control method, and an electronic device. For odd-numbered storage layer groups, local bit lines are connected to a first common bit line through a bit line selector and connected to a second common bit line through a precharge switch; for even-numbered storage layer groups, local bit lines are connected to the second common bit line through a bit line selector and connected to the first common bit line through a precharge switch. At the same time, all the first common bit lines are arranged in sequence in a direction perpendicular to the storage layer group, and all the second common bit lines are arranged in a direction perpendicular to the storage layer group. In this way, during the sense amplification process, for two adjacent first common bit lines in the third direction, one of the first common bit lines must be in the sense amplification state (high potential or low potential), and the other first common bit line is in the precharge potential; for two adjacent second common bit lines in the third direction, one of the second common bit lines must be in the sense amplification state (high potential or low potential), and the other second common bit line is in the precharge potential. The coupling situation between adjacent common bit lines is significantly reduced, improving the sense amplification margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1A is a schematic structural diagram of a storage array slice in a first chip;

[0028] Figure 1B is a schematic partial structural diagram of a storage array slice;

[0029] Figure 2 is a schematic specific structural diagram of a storage array slice;

[0030] Figure 3 is a schematic diagram of the bit line-bit line coupling effect in a storage array slice;

[0031] Figure 4 is a schematic structural diagram of a storage array slice in a first chip provided by an embodiment of the present disclosure;

[0032] Figure 5A is a top view schematic diagram of a storage layer group;

[0033] Figure 5B is a top view schematic diagram of a storage layer group provided by an embodiment of the present disclosure;

[0034] Figure 6 is another schematic structural diagram of a storage array slice in a first chip provided by an embodiment of the present disclosure;

[0035] Figure 7 is a schematic partial structural diagram of a memory provided by an embodiment of the present disclosure;

[0036] Figure 8 is another schematic structural diagram of a storage array slice in a first chip provided by an embodiment of the present disclosure;

[0037] Figure 9 Schematic diagram of a stacked structure of a memory provided by an embodiment of the present disclosure;

[0038] Figure 10 Schematic diagram of a storage array slice in a first chip provided by an embodiment of the present disclosure;

[0039] Figure 11 Schematic diagram of the working state of a storage array slice provided by an embodiment of the present disclosure;

[0040] Figure 12 Schematic diagram of the bit line-bit line coupling effect in a storage array slice provided by an embodiment of the present disclosure;

[0041] Figure 13 Schematic flowchart of a bit line control method provided by an embodiment of the present disclosure. Detailed implementation manners

[0042] In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be construed as limiting the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

[0043] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0044] If similar descriptions such as "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" only distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0046] Glossary:

[0047] WL (Word Line): Word line;

[0048] BL (Bit Line): Bit line;

[0049] CMOS (Complementary Metal Oxide Semiconductor): Complementary Metal Oxide Semiconductor;

[0050] TSV (Through-Silicon-Via): Through-Silicon-Via;

[0051] Mat (Memory Array Tile): Memory Array Tile.

[0052] Before introducing the embodiments of the present disclosure, the following three directions for describing three-dimensional structures that may be used in the planes involved in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0053] A semiconductor chip may include a top surface on the front side and a bottom surface on the back side opposite to the front side; in the case of ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g., perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as the third direction; at the same time, the extending direction of the local bit line in the semiconductor chip is defined as the first direction, and the extending direction of the local word line in the semiconductor chip is defined as the second direction, and the first direction and the second direction intersect.

[0054] For 3D DRAM, it includes a first chip and a second chip stacked along the third direction, and the memory array (Core) is distributed in the first chip, and the peripheral control region (Periphery), sense amplifier region, etc. are distributed in the second chip. For the first chip, the memory array (Core) includes a large number of memory cells, and these memory cells are further divided into multiple memory array tiles (Mat) for better control and management. Please refer to Figure 1A , which shows a schematic structural diagram of the memory array tile 11 in the first chip. As Figure 1A shown, each memory array tile 11 includes a plurality of sub-array tiles arranged in sequence along the second direction, each sub-array tile includes a plurality of memory regions stacked in sequence along the third direction, each memory region includes 2 memory layer groups arranged along the first direction, and a staircase contact structure (Staircase) 14 is provided between the first memory layer group and the second memory layer group. Please refer to Figure 1B , which is Figure 1A an enlarged schematic diagram of the local structure in Figure 1B shown, each memory layer group includes a plurality of local bit lines Local BL extending along the first direction, the local word line Local WL penetrates through a plurality of memory layer groups along the third direction, and a memory cell is formed at the convergence of the local word line and the local bit line ( Figure 1B represented by a five-pointed star in Figure 2, which shows a specific structural schematic diagram of each memory layer group in the memory array chip 11. As Figure 2 shown, a first common bit line (Common BL) 12 and a second common bit line 13 are respectively arranged on the left and right sides of each memory layer group. The left ends of all the local bit lines in this memory layer group are connected to the left first common bit line 12 through a precharge switch Eq, and the right ends of all the local bit lines in this memory layer group are connected to the right second common bit line 13 through a bit line selector Se. At the same time, each second common bit line is coupled to a sense amplifier SA in the sense amplification area through a step contact structure 14.

[0055] Taking reading data as an example, a group of target memory cells aligned along the third direction are enabled by turning on the target word line. At the same time, the bit line selector Se of the local bit lines connected to this group of target memory cells is turned on. At this time, each target memory cell is connected to its corresponding second common bit line 13, so that a group of second common bit lines 13 aligned along the third direction share charges with their respective target memory cells and are sense amplified, so as to be at a high potential or a low potential (depending on the data stored in the target memory cell); the bit line selector Se of the unselected local bit lines is turned off and the precharge switch Eq is turned on, and at the same time all the first common bit lines 12 are charged to the precharge potential, so that all the unselected local bit lines are at the precharge potential. Here, the precharge potential can be an intermediate potential, and the intermediate potential can be half of the memory array power supply voltage (Vblh), that is, the intermediate potential = 1 / 2Vblh. That is to say, in the above scenario, the first common bit lines 12 are all at the precharge potential, and the second common bit lines 13 are at a high potential or a low potential. Due to the parasitic capacitance between two adjacent common bit lines along the third direction, serious bit line-to-bit line coupling (BL-to-BL Coupling) occurs. For example Figure 3 , the coupling capacitance between adjacent second common bit lines is denoted as C_BL2BL. Assuming that a certain second common bit line 13 changes from 0V to a high potential (such as 1V) after charge sharing and sense amplification processing, the bit line-to-bit line coupling will cause the voltage of the adjacent second common bit line 13 to also increase, so that the potential of the adjacent second common bit line 13 may not accurately represent the data stored in the corresponding target memory cell. Similar problems also exist in writing data.

[0056] Briefly speaking, in a storage array slice, the local bit lines of the same storage layer group share a first common bit line and also share the same second common bit line. Whether to connect to the second common bit line is selected by a bit line selector, and whether to connect to the first common bit line is selected by a precharge switch. The second common bit line of each layer is interconnected with a sense amplifier SA through a corresponding stepped contact structure 14. In this case, the second common bit lines of each layer perform sense amplification on the same side, and there is a serious inter-bit line coupling effect between them, resulting in a loss of the sensing margin.

[0057] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0058] In an embodiment of the present disclosure, a memory is provided, which includes a first chip 20. Refer to Figure 4 , which shows a schematic structural diagram of a first chip 20 provided by an embodiment of the present disclosure. As Figure 4 shown, the first chip 20 includes a plurality of storage array slices 21 ( Figure 4 only 1 is shown), and the plurality of storage array slices 21 can be arranged along a first direction, or along a second direction, or be arrayed along the first direction and the second direction.

[0059] Each storage array slice 21 includes a plurality of storage layer groups stacked in sequence along a third direction (such as Figure 4 210o, 210e... in Figure 4 ); each storage layer group has a plurality of local bit lines extending along the first direction, and the plurality of local bit lines are arranged in sequence along the second direction. The first side (such as Figure 4 the left side in

[0060] ) of each storage layer group has a first common bit line 220, and the second side (such as Figure 4 the right side in

[0060] ) of each storage layer group has a second common bit line 230. It should be noted that the first side and the second side are opposite to each other along the first direction; the first direction and the second direction intersect, and the third direction is perpendicular to the first direction and perpendicular to the second direction. Exemplarily, the first direction and the second direction are perpendicular, or the first direction and the second direction may also form a certain angle. In Figure 4 , both the first common bit line 220 and the second common bit line 230 extend along the second direction, but this does not constitute a relevant limitation.

[0061] Each storage layer group also includes a plurality of bit line selectors Se and a plurality of precharge switches Eq, and each local bit line corresponds to a separate bit line selector Se, and each local bit line also corresponds to a separate precharge switch Eq.

[0062] Here, the bit line selector Se and the plurality of precharge switches Eq are both switching devices. Exemplarily, the bit line selector Se employs a CMOS switch, and the precharge switch Eq employs a CMOS switch.

[0063] For ease of explanation, the plurality of memory layer groups are numbered along the third direction. For example, in Figure 4 , from bottom to top, the 0th memory layer group is numbered 210e, the 1st memory layer group is numbered 210o, the 2nd memory layer group is numbered 210e, the 3rd memory layer group is numbered 210o...

[0064] In the oddly numbered memory layer groups 210o, each local bit line is coupled to its respective first common bit line 220 via its respective bit line selector Se, and each local bit line is coupled to its respective second common bit line 230 via its respective precharge switch Eq; in the evenly numbered memory layer groups 210e, each local bit line is coupled to its respective first common bit line 220 via its respective precharge switch Eq, and each local bit line is coupled to its respective second common bit line 230 via its respective bit line selector.

[0065] It should be noted that in Figure 4 , each memory array chip includes 5 memory layer groups, but this is only for illustration and does not constitute a limitation; at the same time, each memory layer group illustrates 4 local bit lines, but in practice, the number of local bit lines in each memory layer group can be more or less.

[0066] It should be understood that for those common bit lines connected to the local bit lines through the bit line selector Se, in a read operation, a write operation, or other operations involving data, its function is to share charge with the selected memory cell and perform sense amplification processing under the action of a sense amplifier; for those common bit lines connected to the local bit lines through the precharge switch Eq, in a read operation, a write operation, or other operations involving data, its function is to provide a precharge potential; exemplarily, the precharge potential can be an intermediate potential 1 / 2Vblh, where Vblh is the power supply potential of the memory array, and can also be understood as the power supply potential of the sense amplifier.

[0067] Please refer to Figure 5A , which shows a top view schematic diagram of a memory array chip 11 ( Figures 1A to 3 the memory array chip 11 schematically shown). As shown in FIG. 5, in the memory array chip 11, for all memory layer groups, the precharge switch Eq is located on the left side, the bit line selector Se is located on the right side, and the projections of the precharge switches Eq / bit line selectors Se of different memory layer groups along the third direction overlap, resulting in synchronous sense amplification of a plurality of second common bit lines 13 aligned along the third direction, thus causing a serious bit line coupling problem.

[0068] Please refer to Figure 5B, which shows a top view schematic diagram of a storage array slice 21 provided by an embodiment of the present disclosure. As Figure 5B shown, for the odd-numbered storage layer groups 210o, their bit line selectors Se are located on the left, and their precharge switches Eq are located on the right; for the even-numbered storage layer groups 210e, their precharge switches Eq are located on the left, and their precharge switches Eq are located on the right. In particular, in Figure 5B , the bit line selector Se of the odd-numbered storage layer group 210o and the precharge switch Eq of the numbered storage layer group 210e may overlap, and the precharge switch Eq of the odd-numbered storage layer group 210o and the bit line selector Se of the numbered storage layer group 210e may overlap. Here, they are drawn separately only for convenience of viewing.

[0069] Specifically, for the first chip 20, the first common bit lines 220 of two adjacent storage layer groups are adjacent in the third direction, and the second common bit lines 230 of two adjacent storage layer groups are adjacent in the third direction. However, any first common bit line 220 and any second common bit line 230 are not adjacent in the third direction. At the same time, for the odd-numbered storage layer groups 210o, their local bit lines are connected to the first common bit line 220 through the bit line selector Se and connected to the second common bit line 230 through the precharge switch Eq; for the even-numbered storage layer groups 210e, their local bit lines are connected to the second common bit line 230 through the bit line selector Se and connected to the first common bit line 220 through the precharge switch Eq. Thus, during the sense amplification process, for the selected multiple storage layer groups, for two adjacent first common bit lines 220, one first common bit line 220 must be in the sense amplification state (high potential or low potential, depending on the specific data value), and the other first common bit line 220 is in the precharge potential; for two adjacent second common bit lines 230, one second common bit line 230 must be in the sense amplification state (high potential or low potential, depending on the specific data value), and the other second common bit line is in the precharge potential, low potential < precharge potential < high potential. However, the two adjacent common bit lines do not perform the sense amplification process simultaneously, so the two common bit lines adjacent in the third direction are not in the sense amplification state at the same time, and thus the coupling situation between the two adjacent common bit lines is significantly weakened, improving the sense amplification margin.

[0070] In some embodiments, please refer to Figure 6, a first stepped contact structure 240 is further provided on a first side of the first common bit line 220, and a second stepped contact structure 250 is further provided on a second side of the second common bit line 230. Both the first stepped contact structure 240 and the second stepped contact structure 250 are connected to the sense amplification region; the first common bit line 220 of the odd-numbered memory layer groups 210o is connected to the first stepped contact structure 240, and the second common bit line 230 of the even-numbered memory layer groups 220e is connected to the second stepped contact structure 250.

[0071] It should be noted that the sense amplification region includes a plurality of sense amplifiers (SA), also known as sensitive amplifiers, which sense and amplify the electrical signals of the common bit lines connected to the selected memory cells. Eventually, the potential of the common bit line reaches a low potential or a high potential, so as to achieve the purpose of reading data from or writing data into the selected memory cell.

[0072] Here, since 3D DRAM mostly forms a memory structure by vertically stacking multiple layers of memory cells (i.e., multiple memory layer groups), in order to ensure that the sense amplifier can be smoothly connected to the common bit lines in each memory layer group, a 3D stepped contact structure (Staircase) needs to be formed. Different steps of the stepped contact structure are electrically isolated, and one step is correspondingly connected to a common bit line (connected to the bit line connector Se), so that the common bit line is connected to the sense amplifier SA in the sense amplification region to implement sense amplification processing.

[0073] At the same time, since for the odd-numbered memory layer groups 210o, the local bit lines are connected to the first common bit line 220 through the bit line selector Se; for the even-numbered memory layer groups 210e, the local bit lines are connected to the second common bit line 230 through the bit line selector Se. Therefore, two adjacent memory layer groups along the third direction will perform sensing amplification (Sensing) on the first common bit line 220 and the second common bit line 230 respectively. For two adjacent common bit lines along the third direction, one must be in the sensing amplification state (low potential or high potential), and the other is in the pre-charge potential, thereby reducing the bit line-bit line mutual coupling effect and increasing the margin of sensitive amplification. At the same time, the stepped contact structures will be evenly distributed on both sides of the memory array chip 21 without increasing the extra area.

[0074] In some embodiments, both the first stepped contact structure 240 and the second stepped contact structure 250 include multiple steps. Each first common bit line 220 of the odd-numbered memory layer groups 210o is coupled to a sense amplifier in the sense amplification region through a step of the first stepped contact structure 240; each second common bit line 230 of the even-numbered memory layer groups 210e is coupled to a sense amplifier in the sense amplification region through a step of the second stepped contact structure 250.

[0075] When the number of stacked layers in the storage layer group is relatively large, the area of the stepped structure region gradually increases, resulting in an increase in chip manufacturing cost. To reduce the stepped area, the embodiments of the present disclosure adopt a grouped stepped contact structure.

[0076] In some embodiments, for the first stepped contact structure 240, several consecutive steps form a step group, and multiple step groups are arranged at intervals along the second direction; for the second stepped contact structure 250, several consecutive steps form a step group, and multiple step groups are arranged at intervals along the second direction.

[0077] Please refer to Figure 7 , which shows a connection schematic diagram of a step group provided by the embodiments of the present disclosure. Figure 7 Taking the example that each step group includes 3 steps for illustration. For convenience of description, the storage layer groups are numbered from bottom to top, and the second common bit lines 230 of the 0th, 2nd, and 4th storage layer groups are respectively connected to the 1st step group of the second stepped contact structure 250, and the second common bit lines 230 of the 6th, 8th, and 10th storage layer groups are respectively connected to the 2nd step group of the second stepped contact structure 250... At the same time, the first common bit lines 220 of all odd-numbered storage layer groups (the 1st, 3rd, 5th... storage layer groups) are connected to the first stepped contact structure 240 (not shown in the figure as it is blocked).

[0078] In this way, different step groups are arranged in sequence along the second direction, and the size of each step along the first direction does not need to be designed too long.

[0079] In addition, in Figure 7 , different steps in the same step group are spaced apart, but this is only for more intuitively showing its connection relationship with the corresponding storage layer group. In actual application scenarios, different steps in the same step group can be closely connected as long as the above-mentioned connection relationship with the storage layer group is followed.

[0080] In some embodiments, please refer to Figure 8 , in the odd-numbered storage layer group 210o, each precharge switch Eq is located on the third side of the corresponding local bit line (for example, Figure 7 the side facing outward along the paper surface in Figure 7 ), and each bit line selector Se is located on the fourth side of the corresponding local bit line (for example,

[0081] the side facing inward along the paper surface in Figure 5A, in the memory array slice 11, for all memory layer groups, the precharge switch Eq is located on the left side, the bit line selector Se is located on the right side, and the projections of the precharge switches Eq / bit line selectors Se of different memory layer groups overlap along the third direction, resulting in synchronous sense amplification of multiple second common bit lines 13 aligned along the third direction, thus causing a serious problem of bit line mutual coupling.

[0082] Please refer to Figure 5B , for the memory layer groups 210o with odd numbers, their bit line selectors Se are located at the lower left, and their precharge switches Eq are located at the upper right; for the memory layer groups 210e with even numbers, their precharge switches Eq are located at the upper left, and their bit line selectors Se are located at the lower right.

[0083] In this way, for the same memory layer group, its bit line selector Se and precharge switch Eq are respectively located on both sides of the local bit line to which they belong along the second direction, and the layout is more reasonable; at the same time, for two adjacent memory layer groups along the third direction, the projections of the bit line selector Se of one memory layer group and the precharge switch Eq of the other memory layer group along the third direction do not overlap, avoiding the coupling effect between the switches.

[0084] In some embodiments, please refer to Figure 9 , the aforementioned memory is a three-dimensional memory, which further includes a second chip 30. The first chip 20 and the second chip 30 are stacked along the third direction, and the first chip 20 and the second chip 30 are bonded and connected; the aforementioned sense amplification region is located in the second chip 30.

[0085] It should be noted that the bonded connection means that two chips are electrically connected through a hybrid bonding structure (Hybrid bonding, also known as bonding pillars). Hybrid bonding is a process of creating a permanent bond between heterogeneous or homogeneous chips. "Hybrid" means forming dielectric-dielectric and metal-metal bonds between two surfaces, which has the following advantages: (1) Shorter interconnection distance: Not only does it not require leads to be interconnected with each other, nor does it require TSVs to pass through the entire CMOS layer. Interconnection can be achieved simply by connecting the copper contacts in the back end; (2) Higher interconnection density: The area of the copper contacts is very small. Compared with the tin balls and TSVs with a diameter of hundreds of microns, the pitch size of the copper contacts in the hybrid bonding process is even less than 10 microns. Undoubtedly, a higher interconnection density can be achieved; (3) Lower cost: Undoubtedly, it takes more time to interconnect each chip individually. Wafer bonding can achieve large-area and high-density interconnection, which makes a leapfrog contribution to the improvement of production capacity. Naturally, the production cost can also be reduced.

[0086] In some embodiments, please refer to Figure 10 , each memory array slice 21 further includes multiple local word lines ( Figure 10Only one is shown), and each local word line penetrates multiple storage layer groups along the third direction. A storage cell is formed at the intersection of each local word line and the corresponding local bit line ( Figure 10 the five-pointed star in).

[0087] In this way, each local word line will activate multiple storage cells aligned along the third direction, and these multiple storage cells will perform read / write synchronously; at the same time, for two adjacent storage cells along the third direction, one storage cell must perform read / write through the first common bit line 220 on one side, and the other storage cell performs read / write through the first common bit line 220 on the other side. Therefore, the influence of bit line coupling is small, and the performance of the memory can be improved.

[0088] In some embodiments, please refer to Figure 10 , the memory further includes multiple common word lines extending along the second direction ( Figure 10 only one is shown), and multiple local word lines aligned along the second direction are coupled to the same common word line.

[0089] Specifically, the first local word line in each sub-array slice is coupled to a common word line, the second local word line in each sub-array slice is coupled to another common word line, the third local word line in each sub-array slice is coupled to yet another common word line...

[0090] In some embodiments, the storage cell (cell) formed at the intersection of the local word line and the local word line includes at least a 1T1C structure, or other known and feasible storage structures. The 1T1C structure includes an N-type transistor and one capacitor.

[0091] The memory 20 is configured to, during a read operation or a write operation, for the selected storage cell, control the bit line selector Se of the local bit line connected thereto to be in an on state, and control the precharge switch Eq of the local bit line connected thereto to be in an off state; for the unselected storage cell, control the bit line selector Se of the local bit line connected thereto to be in an off state, and control the precharge switch Eq of the local bit line connected thereto to be in an on state.

[0092] Please refer to Figure 11 , which shows a schematic diagram of the working state of a storage array slice provided by an embodiment of the present disclosure. In particular, Figure 11Top views of a storage layer group 210o with odd numbers and a storage layer group 210e with even numbers, respectively. When the selected local word line Local WL is turned on, multiple storage cells aligned in the third direction are all turned on. At this time, the bit line selector Se of the local bit line Local BL corresponding to the selected local word line is in the on state and the precharge switch Eq is in the off state; at the same time, the bit line selector Se of the local bit line Local BL corresponding to the unselected local word line is in the off state and the precharge switch Eq is in the on state. Specifically:

[0093] (1) Please refer to Figure 11 , for the storage layer group 210o with odd numbers, the 4th local bit line (numbered from bottom to top) Local BL therein is connected to the first common bit line 220o on the left through the bit line selector Se, so that the voltage of the first common bit line 220o gradually increases from 0V (assuming reading data 1), and then reaches 1V after sense amplification; however, the second common bit line 230o is precharged to the precharge potential (e.g., 0.5V), and the 1st to 3rd local bit lines Local BL are all connected to the second common bit line 230o through the corresponding precharge switch Eq, so that the 1st to 3rd local bit lines Local BL are maintained at the precharge potential of 0.5V;

[0094] (2) Please refer to Figure 11 , for the storage layer group 210e with even numbers, the 4th local bit line therein is connected to the second common bit line 230e on the right through the bit line selector Se, so that the voltage of the second common bit line 230e gradually increases from 0V (assuming reading data 1), and then reaches 1V after sense amplification, but the first common bit line 220e is precharged to the precharge potential of 0.5V, and the 1st to 3rd local bit lines Local BL are all connected to the first common bit line 220e through the corresponding precharge switch Eq, so that the 1st to 3rd local bit lines Local BL are maintained at the precharge potential of 0.5V.

[0095] It should be understood that in the third direction, the first common bit line 220o (the voltage changes from 0V to 1V after charge sharing and sense amplification) is adjacent to the first common bit line 220e (the voltage is the precharge potential of 0.5V), and the second common bit line 230o (the voltage is the precharge potential of 0.5V) is adjacent to the second common bit line 230e (the voltage changes from 0V to 1V after charge sharing and sense amplification), that is, at most one of the two adjacent common bit lines performs sense amplification processing, thereby reducing the bit line-bit line coupling problem.

[0096] Please refer to Figure 12, taking a 5 - stacked memory layer group as an example, the first common bit lines 220o of the 1st and 3rd memory layer groups both change from 0V to 1V, that is, sense - amplification processing is performed, and the first common bit lines 220e of the 0th, 2nd, and 4th memory layer groups are all at the pre - charge potential of 0.5V, and no sense - amplification processing is performed; meanwhile, the second common bit lines 230e of the 0th, 2nd, and 4th memory layer groups both change from 0V to 1V, that is, sense - amplification processing is performed, and the second common bit lines 230o of the 1st and 3rd memory layer groups are all at the pre - charge potential of 0.5V, and no sense - amplification processing is performed. Thus, it can be seen that for adjacent common bit lines on the same side, the data potential (low potential / high potential) after sense - amplification and the pre - charge potential always appear alternately, thereby reducing the bit - line - to - bit - line coupling problem and improving the margin of sense - amplification at the same time.

[0097] Of course, the above is only illustrated by taking the high potential = 1V and the pre - charge potential = 0.5V as examples; of course, in other embodiments, the values of the low potential, the pre - charge potential, and the high potential can be arbitrary, as long as the low potential < the pre - charge potential < the high potential is satisfied.

[0098] In summary, the embodiments of the present disclosure provide a three - dimensional memory. The three - dimensional memory includes a first chip 20 and a second chip 30. The first chip 20 and the second chip 30 are stacked and arranged along the third direction, and the two are connected by a hybrid bonding method. The first chip 20 is mainly used to fabricate a memory array (Core), and is specifically divided into multiple memory array slices (Mat) for better control and management; the second chip 30 is mainly used to fabricate a peripheral control area (Periphery) and a sense - amplification area. In the first chip 20, each memory array slice includes a plurality of memory layer groups stacked along the third direction. The common bit lines Common BL of the odd - numbered layers (i.e., the odd - numbered memory layer groups) and the even - numbered layers (i.e., the even - numbered memory layer groups) will be controlled by independent bit - line selectors BL selector and pre - charge switches Eq Device respectively; the local bit lines Local BL between adjacent memory layer groups along the third direction will perform sense - amplification Sensing on both sides along the first direction of the memory layer group. For the common bit lines arranged continuously along the third direction, they will be alternately arranged in a sense - amplification state Sensing and a pre - charge potential, thereby reducing BL - to - BL coupling; on the other hand, the memory array slice also includes stepped contact structures distributed on both sides, so that the first common bit line of the odd - numbered layer is connected to the stepped contact structure BL staircase on the first side along the first direction, and the second common bit line of the even - numbered layer is connected to the stepped contact structure on the second side along the second direction. The stepped contact structures are arranged on both sides respectively, so there is no increase in area.

[0099] In another embodiment of the present disclosure, refer to Figure 13, which shows a schematic flow diagram of a test method provided by an embodiment of the present disclosure. As Figure 13 shown, this test method is applied to the Figure 4 memory shown in Figure 4 . The memory includes a first chip 20 and a second chip 30 stacked along a first direction. The first chip 20 includes a plurality of memory array slices 21, and each memory array slice includes a plurality of memory layer groups (such as Figure 4 210o, 210e... in Figure 4 ) stacked in sequence along a third direction; each memory layer group has a plurality of local bit lines extending along the first direction, and the plurality of local bit lines are arranged in sequence along a second direction. A first common bit line 220 is provided on the first side (such as the left side in

[0100] ) of each memory layer group, and a second common bit line 230 is provided on the second side (such as the right side in

[0101] ) of each memory layer group. Each memory layer group also includes a plurality of bit line selectors Se and a plurality of precharge switches Eq, and each local bit line corresponds to a separate bit line selector Se and a separate precharge switch Eq. For the convenience of description, the plurality of memory layer groups are numbered along the third direction. In the odd-numbered memory layer groups 210o, each local bit line is coupled to its respective first common bit line 220 via its respective bit line selector Se, and each local bit line is coupled to its respective second common bit line 230 via its respective precharge switch Eq; in the even-numbered memory layer groups 210o, each local bit line is coupled to its respective first common bit line 220 via its respective precharge switch Eq, and each local bit line is coupled to its respective second common bit line 230 via its respective bit line selector.

[0102] This method includes:

[0103] S501: Based on the address signal, select a plurality of local bit lines aligned along the third direction in the target memory array slice;

[0104] S502: In the odd-numbered memory layer groups, control the selected local bit lines to be electrically connected to the coupled first common bit lines, and control the unselected local bit lines to be electrically connected to the coupled second common bit lines; and, in the even-numbered memory layer groups, control the selected local bit lines to be electrically connected to the coupled second common bit lines, and control the unselected local bit lines to be electrically connected to the coupled first common bit lines.

[0105] The bit line selector that controls the unselected local bit lines is in an off state, and the precharge switches of the unselected local bit lines are in an on state, so that the unselected local bit lines in the odd-numbered memory layers are electrically connected to the second common bit line, and the unselected local bit lines in the even-numbered memory layers are electrically connected to the first common bit line.

[0106] In some embodiments, the method further includes:

[0107] For the odd-numbered memory layer groups, controlling the potential of the second common bit line to be the precharge potential; and, making the potential of the first common bit line be a low potential or a high potential through charge sharing and sense amplification processing, depending on the data to be written in the write operation or the data to be read out in the read operation;

[0108] For the even-numbered memory layer groups, controlling the potential of the first common bit line to be the precharge potential; and, making the potential of the second common bit line be a low potential or a high potential through charge sharing and sense amplification processing, depending on the data to be written in the write operation or the data to be read out in the read operation.

[0109] Wherein, the low potential < the precharge potential < the high level.

[0110] In this way, for the first chip 20, assuming that the selected local bit lines in a memory layer group are sense amplified through the first common bit line on one side along the first direction, then the selected local bit lines in the adjacent memory layer group must be sense amplified through the second common bit line on the other side along the first direction, that is, the two adjacent common bit lines in the third direction will not be sense amplified simultaneously, so that the coupling situation of the adjacent common bit lines is significantly weakened, and the sense amplification margin is improved.

[0111] In another embodiment of the present disclosure, an electronic device is further provided. The electronic device includes a memory as Figure 4 shown. The memory includes a first chip 20 and a second chip 30 stacked along a first direction. The first chip 20 includes a plurality of memory array slices 21, and each memory array slice includes a plurality of memory layer groups (such as Figure 4 210o, 210e... in) stacked in sequence along a third direction; each memory layer group has a plurality of local bit lines extending along the first direction, and the plurality of local bit lines are arranged in sequence along a second direction. The first side (such as Figure 4 the left side in) of each memory layer group has a first common bit line 220, and the second side (such as Figure 4On the right side in [description] has a second common bit line 230. Each memory layer group further includes a plurality of bit line selectors Se and a plurality of precharge switches Eq, and each local bit line corresponds to a separate bit line selector Se and a separate precharge switch Eq. For the sake of convenience of description, the plurality of memory layer groups are numbered along the third direction. In the odd-numbered memory layer groups 210o, each local bit line is coupled to its respective first common bit line 220 via its respective bit line selector Se, and each local bit line is coupled to its respective second common bit line 230 via its respective precharge switch Eq; in the even-numbered memory layer groups 210o, each local bit line is coupled to its respective first common bit line 220 via its respective precharge switch Eq, and each local bit line is coupled to its respective second common bit line 230 via its respective bit line selector.

[0112] In this way, for the first chip 20, assuming that the selected local bit line in a memory layer group is sensed and amplified through the first common bit line on one side along the first direction, the selected local bit line in the adjacent memory layer group must be sensed and amplified through the second common bit line on the other side along the first direction, that is, the two adjacent common bit lines in the third direction will not be sensed and amplified simultaneously, so that the coupling situation of the adjacent common bit lines is significantly weakened, improving the sensing and amplification margin.

[0113] It should be noted that in this article, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including that element.

[0114] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0115] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.

Claims

1. A memory, characterized in that, The memory includes a first chip, the first chip includes a plurality of memory array slices, and each of the memory array slices includes a plurality of memory layer groups stacked in sequence along a third direction; each of the memory layer groups has a plurality of local bit lines extending along a first direction, and the plurality of local bit lines are arranged in sequence along a second direction; a first common bit line is provided on a first side of each of the memory layer groups, a second common bit line is provided on a second side of each of the memory layer groups, the first side and the second side are opposite to each other along the first direction, the first direction and the second direction intersect, and the third direction is perpendicular to the first direction and perpendicular to the second direction; Each of the memory layer groups further includes a plurality of bit line selectors and a plurality of precharge switches; the plurality of memory layer groups are numbered along the third direction: In the memory layer groups with odd numbers, each of the local bit lines is coupled to its respective first common bit line via its respective bit line selector, and each of the local bit lines is coupled to its respective second common bit line via its respective precharge switch; In the memory layer groups with even numbers, each of the local bit lines is coupled to its respective first common bit line via its respective precharge switch, and each of the local bit lines is coupled to its respective second common bit line via its respective bit line selector.

2. The memory according to claim 1, wherein A first step contact structure is further provided on a first side of the first common bit line, a second step contact structure is further provided on a second side of the second common bit line, and both the first step contact structure and the second step contact structure are connected to a sense amplification region; The first common bit line of the memory layer groups with odd numbers is connected to the first step contact structure, and the second common bit line of the memory layer groups with even numbers is connected to the second step contact structure.

3. The memory according to claim 2, wherein both the first step contact structure and the second step contact structure include multiple levels of steps, each first common bit line of the memory layer groups with odd numbers is coupled to a sense amplifier in the sense amplification region via a step of the first step contact structure; each second common bit line of the memory layer groups with even numbers is coupled to a sense amplifier in the sense amplification region via a step of the second step contact structure.

4. The memory according to claim 2, wherein for the first step contact structure, a plurality of consecutive levels of steps form a step group, and the plurality of step groups are arranged at intervals along the second direction; for the second step contact structure, a plurality of consecutive levels of steps form a step group, and the plurality of step groups are arranged at intervals along the second direction.

5. The memory according to claim 2, wherein The memory further includes a second chip, the first chip and the second chip are stacked along the third direction, and the first chip and the second chip are bonded and connected; The sense amplification region is located in the second chip.

6. The memory according to claim 5, wherein each of the memory array slices further includes a plurality of local word lines, and each of the local word lines penetrates through a plurality of memory layer groups along the third direction.

7. The memory according to claim 6, characterized in that, The memory further includes a plurality of common word lines extending in a second direction, and a plurality of the local word lines aligned in the second direction are coupled to the same common word line.

8. The memory according to claim 7, characterized in that, The memory layer group further includes a plurality of memory cells, and each memory cell is respectively connected to one of the local bit lines and one of the local word lines; The memory is configured to, during a read operation or a write operation, for the selected memory cell, control the bit line selector of the local bit line connected thereto to be in an on state, and control the precharge switch of the local bit line connected thereto to be in an off state; for the unselected memory cell, control the bit line selector of the local bit line connected thereto to be in an off state, and control the precharge switch of the local bit line connected thereto to be in an on state.

9. The memory according to any one of claims 1-8, wherein In the odd-numbered memory layer groups, each of the precharge switches is located on a third side of the corresponding local bit line, and each of the bit line selectors is located on a fourth side of the corresponding local bit line; the third side and the fourth side are opposite to each other in the second direction; In the even-numbered memory layer groups, each of the precharge switches is located on a fourth side of the corresponding local bit line, and each of the bit line selectors is located on a third side of the corresponding local bit line.

10. The memory according to claim 9, wherein Both the bit line selector and the precharge switch are CMOS switches.

11. A bit line control method, characterized in that, Applied to the memory according to any one of claims 1-10, the method includes: Based on an address signal, selecting a plurality of local bit lines aligned in a third direction in a target memory array slice; In the odd-numbered memory layer groups, controlling the selected local bit lines to be electrically connected to a first common bit line of the memory layer group to which they belong, and controlling the unselected local bit lines to be electrically connected to a second common bit line of the memory layer group to which they belong; and, in the even-numbered memory layer groups, controlling the selected local bit lines to be electrically connected to the second common bit line of the memory layer group to which they belong, and controlling the unselected local bit lines to be electrically connected to the first common bit line of the memory layer group to which they belong.

12. The bit line control method according to claim 11, wherein, The method further includes: Controlling the bit line selector of the selected local bit line to be in an on state, and the precharge switch of the selected local bit line to be in an off state, so that the selected local bit lines in the odd-numbered memory layers are electrically connected to the first common bit line, and the selected local bit lines in the even-numbered memory layers are electrically connected to the second common bit line; Controlling the bit line selector of the unselected local bit line to be in an off state, and the precharge switch of the unselected local bit line to be in an on state, so that the unselected local bit lines in the odd-numbered memory layers are electrically connected to the second common bit line, and the unselected local bit lines in the even-numbered memory layers are electrically connected to the first common bit line.

13. The bit line control method according to claim 11, wherein The method further includes: For the odd-numbered storage layer groups, control the potential of the second common bit line to be the pre-charge potential; and, make the potential of the first common bit line be a low potential or a high potential through charge sharing and sense amplification processing; For the even-numbered storage layer groups, control the potential of the first common bit line to be the pre-charge potential; and, make the potential of the second common bit line be a low potential or a high potential through charge sharing and sense amplification processing; Wherein, the low potential < the pre-charge potential < the high level.

14. An electronic device, characterized in that, The electronic device includes the memory according to any one of claims 1-10.

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