Storage device and storage system

Abstract

The invention relates to a storage device and a storage system. A memory device includes at least one bank including a first sub-bank and a second sub-bank disposed in a word line direction. The first sub-bank may store normal data and may be connected to a plurality of first word lines, and the second sub-bank may store metadata corresponding to the normal data and may be connected to a plurality of second word lines, metadata for normal data corresponding to each of the first word lines may be stored in each of the second word lines respectively corresponding to the first word lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0108499 filed in the Korean Intellectual Property Office on August 18, 2023, and Korean Patent Application No. 10-2024-0022920 filed in the Korean Intellectual Property Office on February 16, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present application relates to the field of semiconductors, and in particular, to a storage device and a storage system. Background Art

[0004] Storage devices are used to store data and are classified into volatile storage devices and nonvolatile storage devices. Volatile storage devices lose their stored data when their power supply is interrupted. Dynamic random access memory (DRAM) is a volatile storage device used in various fields such as mobile systems, servers, and graphics devices.

[0005] A storage device may store metadata, and a method is needed to efficiently allocate resources of the storage device to the metadata. Summary of the invention

[0006] In general, in some aspects, the present disclosure is directed to a storage device for reducing an area increase caused by allocation of metadata or reducing a row hammer effect for accessing metadata.

[0007] According to some embodiments, the present disclosure is directed to a storage device including at least one storage body, the at least one storage body including a first sub-storage body and a second sub-storage body arranged in a word line direction. The first sub-storage body can store normal data and can be connected to a plurality of first word lines, the second sub-storage body can store metadata corresponding to the normal data and can be connected to a plurality of second word lines, and metadata for the normal data corresponding to each first word line can be stored in each second word line corresponding to the first word line respectively.

[0008] According to some embodiments, the present disclosure is directed to a storage device, the storage device comprising: at least one storage body, including at least a first sub-storage body and a second sub-storage body arranged in a word line direction; a first row decoder connected to the first sub-storage body through a plurality of first word lines; and a second row decoder connected to the second sub-storage body through a plurality of second word lines. Based on the first row decoder selecting a single first word line from the first word lines to write normal data into the first sub-storage body, the second row decoder can select a single second word line corresponding to the single first word line from the second word lines to write metadata corresponding to the normal data.

[0009] According to some embodiments, the present disclosure is directed to a storage system, including: a storage device, the storage device including at least one storage body, the at least one storage body including at least a first sub-storage body and a second sub-storage body arranged in a word line direction; and a storage controller configured to control the storage device. The first sub-storage body can store normal data and can be connected to a plurality of first word lines, the second sub-storage body can store metadata corresponding to the normal data and can be connected to a plurality of second word lines, and metadata for the normal data corresponding to each first word line can be stored in each second word line corresponding to the first word line respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a diagram illustrating an example of a storage system according to some implementations.

[0012] Figure 2 is a block diagram of an example of a storage device according to some implementations.

[0013] Figure 3 is a diagram illustrating an example of a memory bank array according to some embodiments.

[0014] Figure 4 is a diagram illustrating an example of a storage device according to some embodiments.

[0015] Figure 5 is a diagram showing the Figure 4 A diagram of an example of a storage body defined in a storage device.

[0016] FIG. 6A to FIG. 6C is a diagram illustrating an example of the operation of a memory bank in a memory device according to some embodiments.

[0017] Figure 7 is a block diagram illustrating an example of a memory cell according to some embodiments.

[0018] Figure 8 is a schematic diagram showing an example of allocating column selection lines to metadata within each sub-memory bank according to some embodiments.

[0019] Fig. 9 is a diagram showing an example of allocation of word lines and column select lines in sub-banks within the same bank according to some embodiments.

[0020] Fig.10 is a diagram showing an example of allocation of word lines and column select lines in sub-banks within the same bank according to some embodiments.

[0021] Fig.11 is a diagram illustrating an example of a memory bank according to some embodiments.

[0022] Fig.12 is a diagram showing a method according to some embodiments Fig.11 FIG. 1 is an example of an area "A".

[0023] FIG. 13A to FIG. 16B is a diagram illustrating an example of allocation of CSLs during a normal data write or read operation on a single word line according to some embodiments.

[0024] Figures 17 to 20 is a diagram illustrating an example of allocation of CSLs during a normal data write or read operation on a single word line according to some embodiments.

[0025] Fig.21 is a diagram illustrating an example of a memory bank according to some embodiments.

[0026] Fig. 22 and Fig.23 is a diagram showing the Fig.21 FIG. 1 is a diagram of an example of the allocation of CSLs during a normal data write or read operation on a single word line in a memory bank structure. DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0028] Figure 1 is a diagram illustrating an example of a storage system according to some embodiments. Figure 1 In the embodiment, the storage system 10 may include a storage controller 100 and a storage device 200 .

[0029] The storage controller 100 may control the overall operation of the storage system 10 and control data exchange between the storage device 200 and a host device connected to the storage system 10. For example, the storage controller 100 may control the storage device 200 to write or read data in response to a request from the host device.

[0030] The memory controller 100 may transmit a command CMD, a clock signal CLK, an address ADDR, etc. to control the memory device 200. In addition, the memory controller 100 may provide data DQ to the memory device 200 and receive data DQ from the memory device 200.

[0031] The data DQ may include normal data and metadata. Metadata may be defined as data used to improve the performance of the storage device 200 or enhance the security of the storage device 200. In some embodiments, the metadata may include information related to the type, length, and attributes of the corresponding normal data, but the present disclosure is not limited thereto.

[0032] The storage device 200 may receive data DQ from the storage controller 100 and store the received data. In some embodiments, the storage device 200 may receive normal data from the storage controller 100, generate metadata for the normal data, and store the normal data and the metadata together. The storage device 200 may read the stored data DQ in response to a request from the storage controller 100 and send the read data to the storage controller 100.

[0033] In some embodiments, the memory device 200 may be a memory device including a volatile memory cell. For example, the memory device 200 may be one of various DRAM devices, such as a double data rate synchronous dynamic random access memory (DDR SDRAM) device, a DDR2 SDRAM device, a DDR3 SDRAM device, a DDR4 SDRAM device, a DDR5 SDRAM device, a DDR6 SDRAM device, a low power double data rate (LPDDR) SDRAM device, a LPDDR2 SDRAM device, a LPDDR3 SDRAM device, a LPDDR4 SDRAM device, a LPDDR4X SDRAM device, a LPDDR5 SDRAM device, a graphic double data rate synchronous graphic random access memory (GDDR SGRAM) device, a GDDR2 SGRAM device, a GDDR3 SGRAM device, a GDDR4 SGRAM device, a GDDR5 SGRAM device, or a GDDR6 SGRAM device.

[0034] In some embodiments, the memory device 200 may be a stacked memory device (eg, a high bandwidth memory (HBM) device, an HBM2 device, or an HBM3 device) in which DRAM dies are stacked.

[0035] In some embodiments, the storage device 200 may be a storage module (e.g., a dual in-line memory module (DIMM)). For example, the storage module may be a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM0), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), a small outline DIMM (SO-DIMM). However, this is only an example, and the storage device 200 may be other storage modules such as a single in-line memory module (SIMM).

[0036] In some implementations, the memory device 200 may be an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, a FRAM device, a PRAM device, a TRAM device, or an MRAM device.

[0037] The memory device 200 may include a memory cell array 310. The memory cell array 310 may include a plurality of memory banks Bank 1 to Bank m. Each memory bank may include a plurality of memory cells connected to a plurality of word lines WL1_0 to WL1_n and WL2_0 to WL2_n.

[0038] For ease of description, an example in which each memory bank includes a DRAM cell will be provided. However, this is only an example, and each of the plurality of memory banks Bank 1 to Bank m may be implemented to include a volatile memory cell other than a DRAM cell. In addition, each of the plurality of memory banks Bank 1 to Bank m may be implemented to include the same type of memory cells, or may be implemented to include different types of memory cells.

[0039] Each of the plurality of banks Bank 1 to Bank m may include sub-banks arranged in a word line direction. For example, the first bank Bank 1 may include a first sub-bank SB1_1 and a second sub-bank SB2_1. Similarly, the mth bank Bank m may include a first sub-bank SB1_m and a second sub-bank SB2_m.

[0040] The first sub-memory banks SB1_1 through SB1_m may constitute a first memory bank array BA1, and the second sub-memory banks SB2_1 through SB2_m may constitute a second memory bank array BA2.

[0041] In some embodiments, first metadata corresponding to first normal data stored in the first sub-storage bank SB1_1 may be stored in the second sub-storage bank SB2_1. Within the first sub-storage bank SB1_1, the region in which the first normal data is stored may be referred to as a first normal region NDR1. Within the 2_1st sub-storage bank SB2_1, the region in which the first metadata corresponding to the first normal data is stored may be referred to as a first meta region MDR1.

[0042] Similarly, second metadata corresponding to the second normal data stored in the 2_1th sub-storage bank SB2_1 may be stored in the 1_1th sub-storage bank SB1_1. Within the 21st sub-storage bank SB2_1, the area in which the second normal data is stored may be referred to as a second normal area NDR2. Within the 1_1th sub-storage bank SB1_1, the area in which the second metadata corresponding to the second normal data is stored may be referred to as a second meta area MDR2.

[0043] For example, each sub-bank within the same bank may be considered a common-side sub-bank and a meta-side sub-bank relative to an opposing sub-bank.

[0044] The 1_1th sub-memory bank SB1_1 and the 2_1th sub-memory bank SB2_1 may not share a global input / output line (GIO). Accordingly, while a data operation on the first normal data is performed in the 1_1th sub-memory bank SB1_1, a data operation on the first metadata may be performed substantially simultaneously or simultaneously in the 2_1th sub-memory bank SB2_1. Additionally, while a data operation on the second normal data is performed in the 2_1th sub-memory bank SB2_1, a data operation on the second metadata may be performed substantially simultaneously or simultaneously in the 1_1th sub-memory bank SB1_1. The data operation may include a data write operation and a data read operation, but example embodiments are not limited thereto.

[0045] Each of the first and second normal regions NDR1 and MDR2 of the 11th sub bank SB1_1 may be connected to the plurality of first word lines WL1_0 to WL1_n, and each of the first and second normal regions MDR1 and NDR2 of the 2_1st sub bank SB2_1 may be connected to the plurality of second word lines WL2_0 to WL2_n.

[0046] In some embodiments, each first metadata for the first normal data corresponding to each first word line may be stored in each second word line corresponding to each first word line. Hereinafter, for convenience, "data stored in a word line" may mean that the data is stored in a storage cell corresponding to (e.g., connected to) the word line. For example, "each first metadata for the first normal data corresponding to each first word line may be stored in each second word line corresponding to each first word line" may mean "each first metadata for the first normal data stored in a storage cell corresponding to each first word line may be stored in a storage cell corresponding to each second word line corresponding to each first word line".

[0047] For example, each of the first word lines WL1_0 to WL1_n connected to the first normal region NDR1 in which the first normal data is stored may correspond to each of the second word lines WL2_0 to WL2_n connected to the first meta region MDR1 in which the first meta data is stored.

[0048] For example, first metadata for first normal data stored in an area connected to the 1_0th word line WL1_0 may be stored in the 20th word line WL2_0 corresponding to the 1_0th word line WL1_0. Similarly, first metadata for first normal data stored in an area connected to the 1_nth word line WL1_n may be stored in the 2_nth word line WL2_n corresponding to the 1_nth word line WL1_n.

[0049] Similarly, each second metadata for the second normal data corresponding to each second word line may be stored in each first word line corresponding to each second word line.

[0050] For example, second metadata for second normal data stored in an area connected to the 2_0th word line WL2_0 may be stored in the 1_0th word line WL1_0 corresponding to the 2_0th word line WL2_0. Second metadata for second normal data stored in an area connected to the 2_nth word line WL2_n may be stored in the 1_nth word line WL1_n corresponding to the 2_nth word line WL2_n.

[0051] For example, a word line of one sub-bank and a word line of another sub-bank included in the same bank may form a word line pair.

[0052] Accordingly, metadata for normal data stored in the 1_1th sub-storage bank SB1_1 may be distributed and stored in corresponding word lines of the 2_1th sub-storage bank SB2_1, and may not be concentrated and stored in a specific word line of the 2_1th sub-storage bank SB2_1. Accordingly, metadata for normal data stored in the 2_1th sub-storage bank SB2_1 may be distributed and stored in corresponding word lines of the 1_1th sub-storage bank SB1_1, and may not be concentrated and stored in a specific word line of the 1_1th sub-storage bank SB1_1.

[0053] In some embodiments, the storage device 200 may operate in a first mode or a second mode. The first mode may be an operating mode in which metadata is input or output. The second mode may be a state in which the first mode is turned off and may correspond to a normal mode. The storage controller 100 may adjust a specific bit value of a storage space such as a mode register included in the storage device 200 to control the storage device 200 operating in the first mode or the second mode. For example, when a specific bit value is set to a first value (e.g., 1), the storage device may operate in the first mode. When a specific bit value is set to a second value (e.g., 0), the storage device may operate in the second mode.

[0054] When operating in the first mode, the storage system 10 may be configured to operate in accordance with various embodiments described below. Figures 2 to 23 ), performing a write or read operation based on the word lines and column select lines assigned to the metadata.

[0055] In the second mode, the word lines and column selection lines allocated for metadata in the first mode may also be allocated to normal data. In the second mode, the memory system 10 may activate at least a portion of the plurality of word lines included in the memory device 200 to write normal data into the memory device 200 or read normal data from the memory device 200. The operation of the memory system 10 in the second mode may follow the operation in DRAM, DDR4, SDRAM, DDR5 SDRAM, DDR6 SDRAM, LPDDR4 SDRAM, LPDDR5 SDRAM, or LPDDR6 SDRAM.

[0056] As described above, metadata may be allocated to a portion of each sub-storage bank, and normal data and metadata for normal data may be stored in different sub-storage banks, respectively. Accordingly, the chip size caused by the additional registers or lines for metadata may be reduced. In addition, when a data operation on normal data is performed in one sub-storage bank, a data operation on metadata may be performed substantially simultaneously in another sub-storage bank, and thus timing loss may be reduced. In some embodiments, metadata for normal data stored in one sub-storage bank may be distributed and stored in corresponding word lines in another sub-storage bank, and may not be concentrated and stored in specific word lines in another sub-storage bank. Accordingly, the row hammer effect caused by repeated access to specific word lines for metadata access may be reduced.

[0057] Figure 2 is a block diagram illustrating an example of a storage device according to some implementations. Figure 2 The storage device 200 may correspond to Figure 1 storage device 200.

[0058] exist Figure 2 In the embodiment, the storage device 200 may include a control logic circuit 210, an address register 220, a storage body control logic 230, a refresh control circuit 400, a row address multiplexer 240, a column address latch 250, a row decoder group 260, a column decoder group 270, a storage cell array 310, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, an error correction code (ECC) engine 350, a data input / output (I / O) buffer 320 and a row hammer management circuit 500.

[0059] The memory cell array 310 may include a plurality of memory bank arrays 310_1 to 310_n. Each of the plurality of memory bank arrays 310_1 to 310_n may include a plurality of memory cells.

[0060] Figure 1 The first memory bank array BA1 shown may correspond to Figure 2 One of the multiple memory bank arrays 310_1-310_k shown.

[0061] The row decoder group 260 may include a plurality of row decoders 260_1 to 260_n. Each of the plurality of row decoders 260_1 to 260_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 310_1 to 310_n.

[0062] The sense amplifier unit 285 may include a plurality of sense amplifiers 285_1 to 285_n. Each of the plurality of sense amplifiers 285_1 to 285_n may be connected to a corresponding bank array among the plurality of bank arrays 310_1 to 310_n.

[0063] The column decoder group 270 may include a plurality of column decoders 270_1 to 270_n. Each of the plurality of column decoders 270_1 to 270_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 310_1 to 310_n through a column selection line CSL.

[0064] In some embodiments, each of the plurality of memory bank arrays 310_1 to 310_n may include a plurality of sub-memory banks. Each memory bank may be defined as including different sub-memory banks from different memory bank arrays. For example, each of the plurality of memory bank arrays 310_1 to 310_n may include a plurality of sub-memory banks arranged in a column direction. A first memory bank may be defined as including one of the plurality of sub-memory banks of the first memory bank array 310_1 and one of the plurality of sub-memory banks of the second memory bank array 310_2. However, this is merely an example, and according to some embodiments, the number of sub-memory banks included in a memory bank may be defined in various ways.

[0065] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, provide the received row address ROW_ADDR to the row address multiplexer 240, and provide the received column address COL_ADDR to the column address latch 250. In addition, the address register 220 may provide the bank address BANK_ADDR and the row address ROW_ADDR to the row hammer management circuit 500 and the RMW driver.

[0066] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. For example, a row decoder corresponding to the bank address BANK_ADDR among the plurality of row decoders 260_1 to 260_n may be activated in response to the bank control signal. A column decoder corresponding to the bank address BANK_ADDR among the plurality of column decoders 270_1 to 270_n may be activated in response to the bank control signal.

[0067] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220 and a refresh row address REF_ADDR from the refresh control circuit 400. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to each of the plurality of row decoders 260_1 to 260_n.

[0068] The refresh control circuit 400 may sequentially increase or decrease the refresh row address REF_ADDR in the normal refresh mode in response to the refresh signal from the control logic circuit 210 .

[0069] The refresh control circuit 400 may receive a row hammer address HADDR in a row hammer refresh mode. The refresh control circuit 400 may output an address of a word line adjacent to a densely accessed word line as a refresh row address REF_ADDR based on the row hammer address HADDR.

[0070] Among the plurality of row decoders 260_1 to 260_n, a row decoder selected by the bank control logic 230 may activate a word line corresponding to a row address RA output from the row address multiplexer 240. For example, the selected row decoder may apply a word line driving voltage to a word line corresponding to the row address.

[0071] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and temporarily store the received column address COL_ADDR. For example, in the burst mode, the column address latch 250 may gradually increase the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or gradually increased column address COL_ADDR' to each of the plurality of column decoders 270_1 to 270_n.

[0072] Among the plurality of column decoders 270_1 to 270 — n , a column decoder activated by the bank control logic 230 may activate a sense amplifier corresponding to a bank address BANK_ADDR and a column address COL_ADDR through an input / output gating circuit 290 .

[0073] The input / output gating circuit 290 may include a circuit for inputting / outputting data. The input / output gating circuit 290 may include a data latch storing codewords output from the plurality of memory bank arrays 310_1 to 310_n, and a write driver writing data into the plurality of memory bank arrays 310_1 to 310_n.

[0074] In some embodiments, during a read operation, a codeword CW read from a selected memory bank array among the plurality of memory bank arrays 310_1 to 310_n may be detected by a sense amplifier corresponding to the selected memory bank array and may be stored in a data latch of the input / output gating circuit 290. The codeword CW stored in the data latch may be ECC decoded by the ECC engine 350 and provided to the data input / output buffer 320 as data DTA. The data input / output buffer 320 may generate a data signal DQ based on the data DTA and provide the data signal DQ together with the selection signal DQS to the memory controller 100.

[0075] In some embodiments, during a write operation, data DTA to be written to a selected memory bank array among the plurality of memory bank arrays 3101 to 310n may be received by the data input / output buffer 320 as a data signal DQ. The data input / output buffer 320 may convert the data signal DQ into data DTA and provide the data DTA to the ECC engine 350. The ECC engine 350 may generate a parity bit (or parity data) based on the data DTA and provide a codeword CW including the data DTA and the parity bit to the input / output gating circuit 290. The input / output gating circuit 290 may write the codeword CW to the selected memory bank array.

[0076] The data input / output buffer 320 may convert the data signal DQ into data DTA during a write operation and provide the data DTA to the ECC engine 350. The data input / output buffer 320 may convert the data DTA provided from the ECC engine 350 into the data signal DQ during a read operation.

[0077] The ECC engine 350 may perform ECC encoding on the data DTA during a write operation. The ECC engine 350 may perform ECC decoding on the codeword CW during a read operation. In addition, the ECC engine 350 may perform ECC encoding and ECC decoding on the count data CNTD provided from the row hammer management circuit 500.

[0078] The control logic circuit 210 may control the operation of the memory device 200. For example, the control logic circuit 210 may generate a control signal to control the memory device 200 to perform a write operation, a read operation, a normal refresh operation, and a row hammer refresh operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 100, and a mode register set (MRS) 212 that sets an operation mode of the memory device 200.

[0079] The command decoder 211 may decode the command CMD to generate internal command signals, such as an internal activation signal IACT, an internal precharge signal IPRE, an internal read signal IRD, and an internal write signal IWR. The command decoder 211 may decode the chip select signal and the command / address signal to generate a control signal corresponding to the command CMD.

[0080] Figure 3 is a diagram illustrating an example of a memory bank array according to some embodiments. Figure 3 The bank array 310_1 may correspond to, for example Figure 2 For ease of description, Figure 3 In the example, the first memory bank array 310_1 includes two sub-memory banks SB1_1 and SB1_2 arranged in the bit line direction. In addition, an example is also provided in which a single column selection line CSL corresponds to eight bit lines.

[0081] exist Figure 3 In the embodiment, the first memory bank array 310_1 may include a plurality of word lines WL0 to WLi, a plurality of bit lines BL0 to BLj, and a plurality of memory cells MC disposed at intersections of the word lines WL0 to WLi and the bit lines BL0 to BLj.

[0082] In some embodiments, each memory cell MC may be a DRAM cell. For example, each memory cell MC may include a cell transistor connected to a word line and a bit line, and a cell capacitor connected to the cell transistor.

[0083] A single column select line CSL may be electrically connected to a plurality of bit lines. For example, a single column select line CSL may be electrically connected to eight bit lines. In some embodiments, eight bits of data may be read from or written to a memory cell MC via a single word line and a single column select line CSL.

[0084] In some embodiments, the first memory bank array 310_1 may include a 1_1th sub-memory bank SB1_1 and a 1_2th sub-memory bank SB1_2. For example, memory cells connected to the 0th word line WL0 to the k-1th word line WLk-1 may constitute the 1_1th sub-memory bank SB1_1, and memory cells connected to the kth word line WLk to the i-th word line WLi may constitute the 1_2th sub-memory bank SB1_2. In example embodiments, the 1_1th sub-memory bank SB1_1 and the 1_2th sub-memory bank SB1_2 may correspond to different memory banks. For example, the sub-memory banks constituting a single memory bank array may correspond to different memory banks, respectively.

[0085] Figure 4 is a diagram illustrating an example of a storage device according to some embodiments. Figure 4 An example of an arrangement of a bank array and corresponding row and column decoders is shown. Figure 4 The storage device 200 may correspond to, for example, Figure 1 and Figure 3 For convenience of description, an example is provided in which the storage device 200 includes 32 memory bank arrays and a single memory bank group BG includes 4 memory bank arrays.

[0086] exist Figure 4 , the first memory bank group BG1 may include first to fourth memory bank arrays BA1 to BA4. For example, the first memory bank array BA1 and the second memory bank array BA2 may be disposed adjacent to each other on the upper portion of the substrate (not shown), and the third memory bank array BA3 and the fourth memory bank array BA4 may be disposed adjacent to each other on the lower portion of the substrate.

[0087] The first row decoder RD1 and the first column decoder CD1 may correspond to the first memory array BA1, and the second row decoder RD2 and the second column decoder CD2 may correspond to the second memory array BA2. In addition, the third row decoder RD3 and the third column decoder CD3 may correspond to the third memory array BA3, and the fourth row decoder RD4 and the fourth column decoder CD4 may correspond to the fourth memory array BA4.

[0088] The memory array, row decoder and column decoder arranged adjacent to each other may be referred to as a memory unit. For example, the first memory array BA1, the second memory array BA2, the first row decoder RD1 and the second row decoder RD2, and the first column decoder CD1 and the second column decoder CD2 may be referred to as a first memory unit BU1.

[0089] The first row decoder RD1 and the second row decoder RD2 may be disposed between the first memory array BA1 and the second memory array BA2 adjacent to each other. In addition, the third row decoder RD3 and the fourth row decoder RD4 may be disposed between the third memory array BA3 and the fourth memory array BA4 adjacent to each other. However, this is only an example, and according to some embodiments, the memory array, the row decoder, and the column decoder may be arranged in various ways.

[0090] Similarly, the second memory bank group BG2 may include a fifth memory bank array BA5 to an eighth memory bank array BA8. The fifth row decoder RD5 and the sixth row decoder RD6 may be disposed between the fifth memory bank array BA5 and the sixth memory bank array BA6 adjacent to each other, and the seventh row decoder RD7 and the eighth row decoder RD8 may be disposed between the seventh memory bank array BA7 and the eighth memory bank array BA8 adjacent to each other. Similarly, the eighth memory bank group BG8 may include the 29th memory bank array BA29 to the 32nd memory bank array BA32, and the row decoders may be disposed between the memory bank arrays adjacent to each other.

[0091] Figure 5 is a diagram showing the Figure 4 FIG. 2 is a diagram of an example of a memory bank defined in a memory device 200 of FIG. 20. For ease of description, an example is provided in which a single memory bank array includes two sub-memory banks.

[0092] exist Figure 4 and Figure 5 In the embodiment, each memory bank array may include two sub-memory banks. For example, the first memory bank array BA1 may include a 1_1th sub-memory bank SB1_1 and a 1_2th sub-memory bank SB1_2, and the second memory bank array BA2 may include a 2_1th sub-memory bank SB2_1 and a 2_2nd sub-memory bank SB2_2.

[0093] A memory bank may be defined using two sub-memory banks disposed adjacent to each other in a word line direction. For example, a first memory bank B1 may be defined to include a 1_1th sub-memory bank SB1_1 and a 2_1th sub-memory bank SB2_1, and a second memory bank B2 may be defined to include a 1_2th sub-memory bank SB1_2 and a 2_2nd sub-memory bank SB2_2.

[0094] In some embodiments, two sub-memory banks included in a single memory bank can operate independently. For example, the 1_1 sub-memory bank SB1_1 of the first memory bank B1 can be connected to the first row decoder RD1 and the first column decoder CD1, and can independently perform read and write operations. In addition, the 2_1 sub-memory bank SB2_1 of the first memory bank B1 can be connected to the second row decoder RD2 and the second column decoder CD2, and can independently perform read and write operations.

[0095] For example, the 1_2 sub-memory bank SB1_2 of the second memory bank B2 can be connected to the first row decoder RD1 and the first column decoder CD1, and can independently perform read and write operations. In addition, the 2_2 sub-memory bank SB2_2 of the second memory bank B2 can be connected to the second row decoder RD2 and the second column decoder CD2, and can independently perform read and write operations.

[0096] As described above, a memory bank may be defined as including sub-memory banks adjacent to each other in a word line direction. Accordingly, two different read or write operations may be independently performed in a single memory bank.

[0097] FIG. 6A to FIG. 6C is a diagram illustrating an example of the operation of a memory bank of a memory device according to some embodiments. For example, Fig. 6A An example of a read operation in a memory device is shown, where a single memory bank corresponds to a single memory bank array. Figure 6B and Figure 6C Shows Figure 5 An example of a read operation in a storage device 200 where a single memory bank includes two sub-memory banks.

[0098] exist Fig. 6A In the , generally, a memory bank is defined as comprising a single memory bank array. For example, Fig. 6A As shown, a first memory bank is defined as including a first memory bank array, a first row decoder, and a first column decoder, and a second memory bank may be defined as including a second memory bank array, a second row decoder, and a second column decoder.

[0099] When a read operation is performed on normal data ND and corresponding metadata MD stored in the first memory bank array, a first read operation of reading the normal data ND and a second read operation of reading the metadata MD may be sequentially performed.

[0100] In some embodiments, both the normal data ND and the metadata MD can be output to the outside through the first global I / O line GIO1. Accordingly, after performing the first read operation, the first global I / O line GIO1 should be precharged to perform the second read operation. As a result, in a general storage device, a large amount of time is required to read the normal data ND and the corresponding metadata MD.

[0101] exist Figure 6B According to example embodiments, the first memory bank B1 may be defined to include a 1_1th sub-memory bank SB1_1 and a 2_1th sub-memory bank SB2_1. In some embodiments, normal data ND may be stored in the 1_1th sub-memory bank SB1_1, and corresponding metadata MD may be stored in the 2_1th sub-memory bank SB2_1.

[0102] Since the 1_1th sub-memory bank SB1_1 is connected to the first row decoder RD1 and the first column decoder CD1, a read operation of normal data ND stored in the 1_1th sub-memory bank SB1_1 can be independently performed. In addition, since the 2_1th sub-memory bank SB2_1 is connected to the second row decoder RD2 and the second column decoder CD2, a read operation of metadata MD stored in the 2_1th sub-memory bank SB2_1 can be independently performed.

[0103] In addition, since the 1_1th sub-memory bank SB1_1 corresponds to the first global I / O line GIO1, and the 2_1th sub-memory bank SB2_1 corresponds to the second global I / O line GIO2, the normal data ND and the metadata MD can be output to the outside through the first global I / O line GIO1 and the second global I / O line GIO2, respectively. Accordingly, there is no need to precharge the global I / O lines between the read operation of the normal data ND and the read operation of the metadata MD.

[0104] As a result, the normal data ND and the metadata MD stored in the first memory bank B1 can be output simultaneously.

[0105] In some embodiments, even when the normal data ND and the metadata MD are stored in the second memory bank B2, the normal data ND and the metadata MD may be output simultaneously.

[0106] For example, Figure 6C As shown, normal data ND and metadata MD may be stored in the 1_2nd sub-bank SB1_2 and the 2_2nd sub-bank SB2_2, respectively. In some embodiments, normal data ND and metadata MD may be simultaneously output through the first global I / O line GIO1 and the second global I / O line GIO2, respectively.

[0107] exist Figure 6B and Figure 6C , an example of a read operation on normal data ND and metadata MD is described. However, it should be understood that this is only an example, and some embodiments are not limited thereto. According to some embodiments, even when normal data ND and metadata MD are stored in the first storage body B1 or the second storage body B2, a write operation on normal data ND and a write operation on metadata MD may be performed simultaneously.

[0108] Figure 7 is a block diagram illustrating an example of a memory cell according to some embodiments. Figure 7 The memory unit BU may correspond to, for example Figure 4 and Figure 5 One of the storage body units BU.

[0109] exist Figure 7In the embodiment, the memory unit BU may include first and second memory bank arrays BA1 and BA2, first and second row decoders RD1 and RD2, and first and second column decoders CD1 and CD2.

[0110] The first bank array BA1 may be connected to the first row decoder RD1 through a plurality of first word lines WL1_0 to WL1_m-1, and may be connected to the first column decoder CD1 through a plurality of first column selection lines CSL1_0 to CSL1_p-1.

[0111] The second bank array BA2 may be connected to the second row decoder RD2 through a plurality of second word lines WL2_0 to WL2_m-1, and may be connected to the second column decoder CD2 through a plurality of column selection lines CSL2_0 to CSL2_p-1.

[0112] The first memory bank B1 may include a 1_1th sub-memory bank SB1_1 included in the first memory bank array BA1, and a 2_1th sub-memory bank SB2_1 included in the second memory bank array BA2.

[0113] The 1_1 sub-memory body SB1_1 may be connected to the first row decoder RD1 through the first word lines WL1_0 to WL1_n-1, and may be connected to the first column decoder CD1 through the first column selection lines CSL1_0 to CSL1_p-1. The 2_1 sub-memory body SB2_1 may be connected to the second row decoder RD2 through the second word lines WL2_0 to WL2_n-1, and may be connected to the second column decoder CD2 through the second column selection lines CSL2_0 to CSL2_p-1. In some embodiments, n is 32k (where k is 1024), and p is 64. However, this is only an example and may vary depending on the memory capacity or required specifications.

[0114] exist Figure 7 The first normal region NDR1 may include a plurality of normal regions 1NR1_0 to NR1_n-1 corresponding to the first word lines WL1_0 to WL1_n-1, respectively. The first meta region MDR1 may include a plurality of meta regions 1MR1_0 to MR1_n-1 corresponding to the second word lines WL2_0 to WL2_n-1, respectively.

[0115] Metadata for normal data stored in one of the normal regions 1NR1_0 to NR1_n-1 may be stored in a first meta region corresponding to one of the first meta regions 1MR1_0 to MR1_n-1. For example, there may be a correspondence between each of the plurality of meta regions 1MR1_0 to MR1_n-1 and each of the plurality of first normal regions NDR1.

[0116] In some embodiments, each of the first meta regions MR1_0 through MR1_n-1 may be symmetrically disposed with respect to each corresponding first normal region of the first normal regions NR1_0 through NR1_n-1 based on the first row decoder RD1.

[0117] For example, metadata for normal data stored in the 1_0th normal region NR1_0 may be stored in a region connected to the 2_0th word line WL2_0 (e.g., the 1_0th meta region MR1_0), where the 2_0th word line WL2_0 corresponds to the 1_0th word line WL1_0. Similarly, metadata for normal data stored in the 1_n-1th normal region NR1_n-1 may be stored in the 1_n-1th meta region MR1_n-1.

[0118] According to some embodiments, write and read operations on the second word lines WL2_0 to WL2_n-1 for the first metadata may be performed in the same order as write and read operations on the first word lines WL1_0 to WL1_n-1 for the corresponding normal data. For example, write and read operations on the first normal data and the corresponding first metadata may be performed together in sequence in a direction in which the indexes of the first word line and the second word line increase (or decrease). In some embodiments, encoding of the word lines may be simplified.

[0119] In some embodiments, when a read or write operation of normal data and corresponding metadata is requested, both of two word lines forming a word line pair may be activated.

[0120] For example, when a read operation is requested for normal data stored in the 1_0th normal region NR1_0 and metadata stored in the corresponding 1_0th meta region MR1_0, the first row decoder RD1 may activate the 1_0th word line WL1_0, and the second row decoder RD2 may activate the 2_0th word line WL2_0. Then, the normal data stored in the 1_0th normal region NR1_0 corresponding to the 1_0th word line WL1_0 may be output, and the metadata stored in the 1_0th meta region MR1_0 corresponding to the 2_0th word line WL2_0 may be output.

[0121] In some embodiments, metadata for normal data stored in one sub-memory bank may be stored in a plurality of word lines corresponding to another sub-memory bank. In addition, when a read or write operation is requested for normal data and corresponding metadata, two word lines forming a word line pair may be activated together. As a result, word line coding on a sub-memory bank may be simplified.

[0122] Figure 8 is a schematic diagram showing an example of allocating column selection lines to metadata within each sub-memory bank according to some embodiments. Figure 8 The memory bank B1 may correspond to Figure 1 or Figure 7 Accordingly, the same or similar components are denoted by the same or similar reference numerals, and redundant descriptions will be omitted below.

[0123] In some embodiments, a column selection line connected to a single sub-bank may be divided and allocated to a normal data storage area and a metadata storage area for normal data in another sub-bank of the same bank.

[0124] exist Figure 8 Among the p first column selection lines CSL1_0 to CSL1_p-1 connected to the 1_1th sub-bank SB1_1, q first column selection lines CSL1_0 to CSL1_q-1 may be allocated to the first normal region NDR1, and the remaining first column selection lines CSL1_q to CSL1_p-1 may be allocated to the second meta region MDR2.

[0125] Similarly, among the p second column selection lines CSL2_0 to CSL2_p-1 connected to the 2_1-th sub memory bank SB2_1, q second column selection lines CSL2_0 to CSL2_q-1 may be allocated to the second normal region NDR2, and the remaining second column selection lines CSL2_q to CSL2_p-1 may be allocated to the first meta region MDR1. Hereinafter, the column selection lines allocated to the first and second normal regions may be referred to as normal column selection lines, and the column selection lines allocated to the first meta region and the second meta region may be referred to as meta column selection lines.

[0126] Among column selection lines connected to a single sub-bank, a ratio of normal column selection lines to meta column selection lines may be determined based on a ratio of normal data to meta data.

[0127] In some embodiments, when the ratio of normal data to metadata is k:1, k normal column select lines of one sub-bank may correspond to a single meta column select line of another sub-bank in the same bank in order of column select line indices.

[0128] For example, the first common column selection lines CSL1_0 to CSL1_k-1 may correspond to the second meta column selection line CSL2_q, and the first common column selection lines CSL1_k to CSL1_2k-1 may correspond to the second meta column selection line CSL2_q+1. Similarly, the first common column selection lines CSL1_q-k to CSL1_q-1 may each correspond to the second meta column selection line CSL2_q+r-1. However, some embodiments are not limited thereto and may vary according to the design of the storage device. For example, as long as the ratio of common column selection lines to meta column selection lines is determined based on the ratio of common data to metadata, the former and the latter may be different. In some embodiments, when the ratio of common data to metadata is k:1, k-1 common column selection lines of one sub-storage bank may correspond to a single meta column selection line of another sub-storage bank in the same storage bank in the order of the index of the column selection lines.

[0129] In some embodiments, the storage location of the metadata of the second sub-memory bank may correspond to the first word line and the first normal column selection line connected to the memory cell in which the corresponding normal data of the first sub-memory bank is stored. For example, metadata for normal data stored in the memory cell connected to the first normal column selection lines CSL1_0 to CSL1_k-1 in the 10th normal region NR1_0 may be stored in a location corresponding to the 2_0th word line WL2_0 and the second meta column selection line CSL2_q, wherein the 2_0th word line WL2_0 corresponds to the 1_0th word line WL1_0, and the second meta column selection line CSL2_q corresponds to the 1_0th column selection line CSL1_0 to the 1_k-1th column selection line CSL1_k-1.

[0130] exist Figure 7 and Figure 8 , when a read operation is requested for normal data stored in the 1_0th normal region NR1_0 and corresponding metadata stored in the 1_0th meta region MR1_0, the first row decoder RD1 may activate the 1_0th word line WL1_0, and the second row decoder RD2 may activate the 2_0th word line WL2_0. When the first column decoder CD1 activates one of the 1_0th normal column selection line CSL1_0 to the 1_k-1th normal column selection line CSL1_k-1 in a state where the word line is activated, the second column decoder CD2 may activate the second meta column selection line CSL2_q. Through such operations, when normal data corresponding to the 1_0th normal column selection line CSL1_0 to the 1_k-1th normal column selection line CSL1_k-1 is read from the normal data stored in the 1_0th normal region NR1_0, metadata assigned to the second meta column selection line CSL2_q in the metadata stored in the 1_0th meta region MR1_0 may be read.

[0131] As described above, normal data can be accessed by activating a first word line and a first normal column selection line connected to an area in which target normal data is stored, and target metadata can be accessed by activating a second word line corresponding to the first word line and a second meta column selection line corresponding to the first normal column selection line.

[0132] In some embodiments, the column selection line connected to one sub-memory bank can be divided and allocated to a normal data storage area and a metadata storage area for normal data in another sub-memory bank of the same memory bank. Accordingly, the chip size for allocating metadata can be prevented from being additionally increased, and efficient allocation of metadata can be achieved.

[0133] Relative to the first memory bank, the memory bank B1 is divided into the 1_1th sub-memory bank SB1_1 and the 2_1th memory bank SB2_1, but can be functionally operated in the same manner as a memory bank structure in which the memory bank is not divided into sub-memory banks. For example, the 1_1th sub-memory bank SB1_1 is internally connected to a plurality of first word lines WL1_0 to WL1_n-1, and the 21st sub-memory bank SB2_1 is internally connected to a plurality of second word lines WL2_0 to WL2_n-1. However, when n is 32k, the first memory bank B1 can be operated in the same manner as a single memory bank connected to a total of 62k (where k is 1024) word lines (e.g., WL_0 to WL_62k-1). The plurality of first word lines WL1_0 to WL1_32k-1 and the plurality of second word lines WL2_0 to WL2_32k-1 may respectively correspond to the 0th to 32kth word lines WL0 to WL32k-1 and the 32k+1th to WL32k to WL62k-1 of a total of 62k word lines (eg, WL_0 to WL_62k-1). Accordingly, the 1_1th sub-storage body SB1_1 connected to multiple first word lines WL1_0 to WL1_32k-1 and the 2_1th sub-storage body SB2_1 connected to multiple second word lines WL2_0 to WL2_32k-1 in the above embodiment can respectively correspond to the part connected to 32k word lines (for example, WL0 to WL32k-1) and the part connected to 32k word lines (for example, WL32 to WL62k-1) in the storage body without a sub-storage body structure.

[0134] Fig. 91 is a diagram showing an example of allocation of word lines and column selection lines in sub-banks within the same bank according to some embodiments. A description will be provided below based on a case where normal data is stored in the 1_1 sub-bank SB1_1 and corresponding metadata is stored in the 2_1 sub-bank SB2_1. However, some embodiments are also applicable even in a case where normal data is stored in the 2_1 sub-bank SB2_1 and corresponding metadata is stored in the 1_1 sub-bank SB1_1.

[0135] Fig. 9 The case where the ratio of normal data to metadata is 8:1 and the number of column select lines is 64 is shown. In some embodiments, the ratio of column select lines allocated to actual normal data to column select lines allocated to metadata can be 7: 1. This is to meet the required 7:1 ratio without additional chip size overhead.

[0136] Normal data may be stored in memory cells corresponding to the 1_0th word line WL1_0 and the 1_0th to 1_7th column selection lines CSL1_0 and CSL1_7, and metadata corresponding to the normal data may be stored in memory cells corresponding to the 2_0th word line WL2_0 and the 2_56th column selection line CSL2_56.

[0137] Normal data is stored in memory cells corresponding to the 1_0th word line WL1_0 and the 1_8th to 1_15th column selection lines CSL1_8 and CSL1_15, and metadata corresponding to the normal data may be stored in memory cells corresponding to the 2_0th word line WL2_0 and the 2_57th column selection line CSL2_57.

[0138] Similarly, normal data may be stored in storage cells corresponding to the 1_0th word line WL1_0 and the 1_48th to 1_55th column selection lines CSL1_48 to CSL1_55, and metadata corresponding to the normal data may be stored in storage cells corresponding to the 2_0th word line WL2_0 and the 2_62nd column selection line CSL2_62.

[0139] Data may not be stored in memory cells corresponding to the 2_0 th word line WL2_0 and the 2_63 th column selection line CSL2_63 .

[0140] In a similar manner, normal data may be stored in storage cells corresponding to the 1_1th word line WL1_1 and the 1_0th column selection line CSL1_0 to the 1_7th column selection line CSL1_7, and metadata corresponding to the normal data may be stored in storage cells corresponding to the 2_1th word line WL2_1 and the 2_56th column selection line CSL2_56. Similarly, normal data may be stored in storage cells corresponding to the 1_1th word line WL1_1 and the 1_48th column selection line CSL1_48 to the 1_55th column selection line CSL1_55, and metadata corresponding to the normal data may be stored in storage cells corresponding to the 2_1th word line WL2_1 and the 2_62nd column selection line CSL2_62.

[0141] Fig.10 is a diagram showing an example of allocation of word lines and column select lines in sub-banks within the same bank according to some embodiments. Fig.10 The case where the ratio of normal data to metadata is 16:1 and the number of column select lines is 64 is shown. In some embodiments, the ratio of column select lines allocated to actual normal data to column select lines allocated to metadata can be 15: 1. This is to meet the required 15:1 ratio without additional chip size overhead.

[0142] Normal data may be stored in memory cells corresponding to the 1_0th word line WL1_0 and the 1_0th to 1_14th column selection lines CSL1_0 and CSL1_14. Metadata corresponding to the normal data may be stored in memory cells corresponding to the 2_0th word line WL2_0 and the 2_60th column selection line CSL2_60.

[0143] Normal data may be stored in memory cells corresponding to the 1_0th word line WL1_0 and the 1_15th to 1_29th column selection lines CSL1_15 to CSL1_29. Metadata corresponding to the normal data may be stored in memory cells corresponding to the 2_0th word line WL2_0 and the 2_61st column selection line CSL2_61.

[0144] Similarly, normal data may be stored in storage cells corresponding to the 1_0th word line WL1_0 and the 1_45th to 1_59th column selection lines CSL1_45 to CSL1_59, and metadata corresponding to the normal data may be stored in storage cells corresponding to the 2_0th word line WL2_0 and the 2_63rd column selection line CSL2_63.

[0145] The above description is provided based on the case where the normal data is stored in the 1_1 sub-storage bank SB1_1 and the corresponding metadata is stored in the 2_1 sub-storage bank SB2_1. However, the above allocation method can also be applied to the case where the normal data is stored in the 2_1 sub-storage bank SB2_1 and the corresponding metadata is stored in the 1_1 sub-storage bank SB1_1.

[0146] Fig.11 is a diagram illustrating an example of a memory bank according to some embodiments, and Fig.12 is a diagram showing a method according to some embodiments Fig.11 FIG. 1 is an example of an area "A". Fig.11 The first memory bank B1 may correspond to Figures 1 to 8 One of the first memory banks B1 described in .

[0147] The 1_1th sub memory bank SB1_1 may be electrically connected to the first row decoder RD1 and the first column decoder CD1. The 1_1th sub memory bank SB1_1 may be connected to a plurality of word lines WL1_0 to WL1_32k-1 through the first row decoder RD1. In addition, the 1_1th sub memory bank SB1_1 may be connected to a plurality of column selection lines CSL through the first column decoder CD1.

[0148] The 2_1st sub-memory bank SB2_1 may be electrically connected to the second row decoder RD2 and the second column decoder CD2. The 2_1st sub-memory bank SB2_1 may be connected to a plurality of word lines WL2_0 to WL2_32k-1 through the second row decoder RD2. In addition, the 2_1st sub-memory bank SB2_1 may be connected to a plurality of column selection lines CSL through the second column decoder CD2.

[0149] Each of the 1_1th sub-memory body SB1_1 and the 2_1th sub-memory body SB2_1 may include a plurality of memory blocks MAT. Each of the plurality of memory blocks MAT may be connected to a portion of word lines and a portion of column selection lines CSL. Each of the plurality of memory blocks MAT may include a plurality of memory cells, and each of the plurality of memory cells may be connected to a single word line of a portion of word lines connected to the corresponding memory block MAT, and a single column selection line CSL of a portion of column selection lines connected to the corresponding memory block MAT.

[0150] The first column decoder CD1 may include a plurality of CSL blocks CB0 to CB7. Each of the plurality of CSL blocks CB0 to CB7 may be configured to select a column selection line to be activated from a plurality of column selection lines based on a column selection signal from the first column decoder CD1. Similarly, the second column decoder CD2 may include a plurality of CSL blocks CB0 to CB7. Each of the plurality of CSL blocks CB0 to CB7 may be configured to select a column selection line to be activated from a plurality of column selection lines based on a decoded column address from the second column decoder CD2. Fig.11 In the embodiment, the number of CSL blocks in each sub-storage bank is shown as 8, but some implementations are not limited thereto. In addition, each sub-storage bank may also include an error correction code (ECC) block. In some embodiments, the storage block MAT connected to the column corresponding to the ECC block may store the parity bits generated by the ECC block.

[0151] In some embodiments, each CSL block CB may correspond to two CSL groups CS. For example, the 0th CSL block CB0 may correspond to the 0th CSL group CS0 and the first CSL group CS1, and the first CSL block CB1 may correspond to the second CSL group CS2 and the third CSL group CS3. Similarly, the sixth CSL block CB6 may correspond to the twelfth CSL group CS12 and the thirteenth CSL group CS13, and the seventh CSL block CB7 may correspond to the fourteenth CSL group CS14 and the fifteenth CSL group CS15.

[0152] Each CSL group CS may include a plurality of column selection lines. For example, each CSL group CS may include 64 column selection lines, and a portion of the 64 column selection lines may be allocated to a normal data region, and another portion of the 64 column selection lines may be allocated to a metadata region.

[0153] Now it will target Fig.12 The sixth CSL block CB6 shown provides a more detailed description. The sixth CSL block CB6 may be connected to the twelfth CSL group CS12 and the thirteenth CSL group CS13. The twelfth CSL group CS12 may include the 0th column selection line CSL0 to the 63rd column selection line CSL63, and the thirteenth CSL group CS13 may include the 0th column selection line CSL0 to the 63rd column selection line CSL63. Accordingly, a total of 128 column selection lines may be connected to the sixth CSL block CB6.

[0154] When an example in which the ratio of normal data to metadata is 8:1 is provided, the 0th column selection line CSL0 to the 55th column selection line CSL55 in the twelfth CSL group CS12 may be allocated to the normal data region NDR, and the remaining 56th column selection line CSL56 to the 63rd column selection line CSL63 may be allocated to the metadata region MDR. The 0th column selection line CSL0 to the 55th column selection line CSL55 in the thirteenth CSL group CS13 may be allocated to the normal data region NDR, and the remaining 56th column selection line CSL56 to the 63rd column selection line CSL63 may be allocated to the metadata region MDR. As described above, a portion of the column selection lines in each CSL group CS may be allocated to the normal data region NRD, and another portion of the column selection lines may be allocated to the metadata region MDR.

[0155] exist Fig.11 In the embodiment, a single column selection line in a single CSL group CS can be selected and activated during one access operation. Two CSL groups CS correspond to a single CSL block CB, so that one or two column selection lines can be selected by a single CSL block CB during one access operation.

[0156] For ease of description, an example is provided where the decoded column address is "CSLx[a:b]". In some embodiments, "x" may refer to the number of the column select line, and "[a:b]" may refer to the range of the selected CSL group. The column select signal may include information related to the column address and may be generated by a column decoder.

[0157] In addition, an example is provided in which the column address decoded by the first column decoder CD1 is "CSL0[0:15]". In some embodiments, the 0th to 15th CSL groups CS0 to CS15 may be selected, and the 0th column selection line CSL0 may be selected in each of the 0th to 15th CSL groups CS15.

[0158] Since each CSL block CB corresponds to two CSL groups CS, each CSL block CB of the 11th sub-bank SB1_1 may select two 0th column selection lines CSL0. One or two column selection lines selected by each CSL block CB may be referred to as a 'CSL subset'.

[0159] For example, each CSL subset may be a group of column selection lines corresponding to a portion of a plurality of groups corresponding to a single column selection line. In some embodiments, when the ratio of normal data to metadata is k:1, a single normal column selection line may correspond to one of k CSL subsets of a single metadata column selection line. In some embodiments, when the number of CSL groups in a sub-bank is n, each of the k CSL subsets may correspond in turn to an activated column selection line in the n / k group.

[0160] For example, when the ratio of normal data to metadata is 8:1 and the number of CSL groups corresponding to a single sub-bank is 16, each CSL subset may correspond in sequence to column selection lines corresponding to two groups among the multiple groups corresponding to a single column selection.

[0161] For example, when the ratio of normal data to metadata is 16:1, and the number of CSL groups corresponding to the sub-memory bank is 16, each CSL subset may correspond in turn to a column selection line corresponding to a single group of a plurality of groups corresponding to a single column selection. However, some embodiments are not limited thereto, and may vary according to a desired ratio of normal data to metadata, and a design of a sub-memory bank.

[0162] The 0th to 55th column selection lines CSL0 to CSL55 are allocated to the normal data region NDR, so when the decoded column address is CSL0 [0:15], normal data can be input or output to the 1_1th sub-bank SB1_1.

[0163] When 8 bits correspond to one column selection line, 128 bits (8 times the number of activated CSLs) of normal data can be output or written in one word line access operation. Since the corresponding metadata is 16 bits, the corresponding metadata can be assigned to the 56th column selection line in a part of the CSL groups in the plurality of CSL groups.

[0164] For example, the second column decoder CD2 may select only a subset of the 56th column selection lines. In some embodiments, the column selection signal may be "CSL56[0:1]". In example embodiments, the 0th CSL group CS0 and the first CSL group CS1 may be selected, and the 56th column selection line CSL56 may be selected in each of the 0th CSL group CS0 and the first CSL group CS1. Since the 0th CSL block CB0 corresponds to the 0th CSL group CS0 and the first CSL group CS1, the 0th CSL block CB0 in the 2_1th sub-memory body SB2_1 may select two column selection lines CSL56.

[0165] In some embodiments, the 56th to 63rd column selection lines CSL56 to CSL63 are allocated to the metadata region MDR so that metadata can be input or output to the 2_1th sub-bank SB2_1 when the column selection signal is CSL56 [0:1].

[0166] In some embodiments, a plurality of word lines WL1_0 to WL1_32k-1 corresponding to the 1_1th sub-memory bank SB1_1 may be matched with a plurality of word lines WL2_0 to WL2_32k-1 corresponding to the 2_1th sub-memory bank SB2_1 to form a word line pair. For example, word line 1_0WL1_0 and word line 2_0WL2_0 may form a 0th word line pair, and word line 1_1WL1_1 and word line 2_1WL2_1 may form a first word line pair.

[0167] In some embodiments, metadata corresponding to normal data stored in the 1_1th sub-bank SB1_1 may be stored in the 2_1th sub-bank SB2_1, and the normal data and the metadata may correspond to the same word line pair.

[0168] For example, an example is provided in which the 1_0th word line WL1_0 and the 2_0th word line WL2_0 are selected by the first row decoder RD1 and the second row decoder RD2 , and the ratio of normal data to metadata is 8:1.

[0169] In some embodiments, when the column selection signal generated by the first column decoder CD1 is "CSL0[0:15]", the column selection signal generated by the second column decoder CD2 may be "CSL56[0:1]". In addition, when the column selection signal generated by the first column decoder CD1 is "CSL1[0:15]", the column selection signal generated by the second column decoder CD2 may be "CSL56[2:3]". In the same manner, the column selection signal generated by the first column decoder CD1 is "CSL54[0:15]", the column selection signal column address generated by the second column decoder CD2 may be "CSL56[12:13]". In addition, when the column selection signal generated by the first column decoder CD1 is "CSL55[0:15]", the column selection signal generated by the second column decoder CD2 may be "CSL62[14:15]". As a result, normal data corresponding to the 1_0th word line WL1_0 of the 1_1th sub-bank SB1_1 may be matched with metadata corresponding to the 2_0th word line WL2_0 of the 2_1th sub-bank SB2_1.

[0170] The above description is provided based on the case where the normal data is stored in the 1_1 sub-storage body SB1_1 and the corresponding metadata is stored in the 2_1 sub-storage body SB2_1. However, the above allocation method can also be applied to the case where the normal data is stored in the 2_1 sub-storage body SB2_1 and the corresponding metadata is stored in the 1_1 sub-storage body SB1_1.

[0171] According to some embodiments, some subsets of corresponding meta column selection lines may be allocated for metadata to correspond to a single common column selection line. Accordingly, resources for metadata may be allocated more efficiently.

[0172] FIG. 13A to FIG. 20 1 is a diagram showing an example of a CSL allocation relationship in each sub-storage body according to some embodiments. The following description will be provided with respect to the allocation between CSLs based on the case where normal data is stored in the 1_1th sub-storage body SB1_1 and the corresponding metadata is stored in the 2_1th sub-storage body SB2_1. However, the following description can also be applied to the case where normal data is stored in the 2_1th sub-storage body SB2_1 and the corresponding metadata is stored in the 1_1th sub-storage body SB1_1.

[0173] Fig.13A , Fig.14A , Fig.15A and FIG. 16A to FIG. 20 The first memory bank B1 shown corresponds to Fig.11 The first memory bank B1 is shown. Accordingly, the same or similar components are denoted by the same or similar reference numerals, and redundant descriptions will be omitted below.

[0174] For ease of description, an example of a column selection signal of "CSLx[a:b]" is provided. In some embodiments, "x" may represent the number of column selection lines (where x is one of 0 to 63), and "[a:b]" may represent the range of the selected CSL group. In addition, a column selection line assigned to normal data is referred to as a normal column selection line, and a column selection line assigned to metadata is referred to as a meta column selection line.

[0175] exist Fig.13A In the example, an example of performing a normal data write or read operation on a region of the 1_1th sub-bank 1SB1_1 corresponding to the 1_0th word line WL1_0 and the 0th normal column selection line CSL0 is provided.

[0176] exist Fig. 13B , the 0th common column selection line CSL0 may correspond to a subset of a portion of the 56th elementary column selection line CSL56.

[0177] Accordingly, metadata for normal data may be stored in an area corresponding to some subsets of the 2_0th word line WL2_0 corresponding to the 1_0th word line WL1_0 in the 2_1th sub-storage bank SB2_1 and the 56th meta-column selection line CSL56 corresponding to the 0th normal column selection line CSL0.

[0178] To this end, the row decoder 1RD1 may activate the 1_0 th word line WL1_0 , and the second row decoder RD2 may activate the 2_0 th word line WL2_0 .

[0179] The column selection signal of the 1_1th sub-bank SB1_1 side may be “CSL0[0:15]” The first column decoder CD1 may activate the 0th normal column selection line CSL0 of each of the 0th to 15th CSL groups CS0 to CS15 .

[0180] The second column decoder CD2 may select some subsets of the 56th elementary column selection lines CSL56 corresponding to the 0th common column selection line CSL0. In an example embodiment, a subset corresponding to the first block (e.g., CB0) may be selected. In some embodiments, the column selection signal may be "CSL56[0:1]". In some embodiments, the 0th CSL group CS0 and the first CSL group CS1 may be selected, and the 56th column selection line CSL56 may be selected in each of the 0th CSL group CS0 and the first CSL group CS1. Since the 0th CSL block CB0 corresponds to the 0th CSL group CS0 and the first CSL group CS1, the 0th CSL block CB0 of the 21st sub-storage body SB21 may activate two column selection lines CSL56.

[0181] Accordingly, normal data may be written to or read from an area corresponding to the 1_0th word line WL1_0 and the 0th normal column selection line CSL0 in the 1_1th sub-memory bank SB1_1, and metadata corresponding to the normal data may be written to or read from an area corresponding to the 2_0th word line WL2_0 and a single subset of the 56th meta-column selection line CSL56 in the 2_1th sub-memory bank SB2_1. Such normal data and metadata writing or reading operations may be performed substantially simultaneously.

[0182] exist Fig.14A , an example of performing a normal data write or read operation on a region of a 1_1th sub-bank SB1_1 corresponding to a 1_0th word line WL1_0 and a first normal column selection line CSL1 is provided.

[0183] exist Fig. 14B In the embodiment, the first common column selection line CSL1 may correspond to a subset of a portion of the 56th elementary column selection line CSL56.

[0184] Accordingly, metadata for normal data may be stored in an area within the 2_1th sub-bank SB2_1 that corresponds to some subsets of the 2_0th word line WL2_0 corresponding to the 1_0th word line WL1_0 and the 56th meta column selection line CSL56 corresponding to the first normal column selection line CSL1.

[0185] To this end, the first row decoder RD1 may activate the 1_0 th word line WL1_0 , and the second row decoder RD2 may activate the 2_0 th word line WL2_0 .

[0186] The column selection signal of the 1_1th sub-bank SB1_1 side may be “CSL1[0:15]”. The first column decoder CD1 may activate the first normal column selection line CSL1 in each of the 0th to 15th CSL groups CS0 to CS15.

[0187] The second column decoder CD2 can select some subsets of the 56th elementary column selection lines CSL56 corresponding to the 0th common column selection line CSL0. In some embodiments, a subset corresponding to a CSL block (e.g., CB1) can be selected. In some embodiments, the column selection signal can be "CSL56[2:3]". In some embodiments, the second CSL group CS2 and the third CSL group CS3 can be selected, and the 56th column selection line CSL56 can be selected in each of the second CSL group CS2 and the third CSL group CS3. Since the first CSL block CB1 corresponds to the second CSL group CS2 and the third CSL group CS3, the first CSL block CB1 of the 2_1st sub-storage body SB2_1 can activate two 56th column selection lines CSL56.

[0188] Accordingly, normal data may be written to or read from an area corresponding to the 1_0th word line WL1_0 and the first normal column selection line CSL1 in the 1_1th sub-memory bank SB1_1, and metadata corresponding to the normal data may be written to or read from an area corresponding to the 2_0th word line WL2_0 and another subset of the 56th meta-column selection lines CSL56 in the 2_1th sub-memory bank SB2_1. Such normal data and metadata writing or reading operations may be performed substantially simultaneously.

[0189] exist Fig.15A , an example of performing a normal data write or read operation on a region of the 1_1th sub-bank SB1_1 corresponding to the 1_0th word line WL1_0 and the 54th normal column selection line CSL54 is provided.

[0190] exist Fig. 15B , the 54th common column selection line CSL54 may correspond to a subset of a portion of the 62nd meta column selection line CSL62.

[0191] Accordingly, metadata for normal data may be stored in an area within the 2_2nd sub-memory bank SB2_2 corresponding to a subset of the 2_0th word line WL2_0 corresponding to the 1_0th word line WL1_0 and a portion of the 62nd meta column selection line CSL62 corresponding to the 54th normal column selection line CSL54.

[0192] To this end, the first row decoder RD1 may activate the 1_0 th word line WL1_0 , and the second row decoder RD2 may activate the 2_0 th word line WL2_0 .

[0193] The column selection signal of the 1_1th sub-bank SB1_1 side may be “CSL54[0:15]”. The first column decoder CD1 may activate the 54th column selection line CSL54 of each of the 0th to 15th CSL groups CS0 to CS15.

[0194] The second column decoder CD2 can select some subsets of the 62nd elementary column selection lines CSL62 corresponding to the 54th common column selection line CSL54. In some embodiments, a subset corresponding to a CSL block (e.g., CB6) can be selected. In some embodiments, the column selection signal can be "CSL62[12:13]". In some embodiments, the twelfth CSL group CS12 and the thirteenth CSL group CS13 can be selected, and the 62nd column selection line CSL62 can be selected in each of the twelfth CSL group CS12 and the thirteenth CSL group CS13. Since the sixth CBS block CB6 corresponds to the twelfth CSL group CS12 and the thirteenth CSL group CS13, the sixth CSL block CB6 of the 2_1st sub-storage body SB2_1 can activate two 62nd column selection lines CSL62.

[0195] Accordingly, normal data may be written to or read from an area corresponding to the 1_0th word line WL1_0 and the 54th normal column selection line CSL54 in the 1_1th sub-memory bank SB1_1, and metadata corresponding to the normal data may be written to or read from an area corresponding to the 2_0th word line WL2_0 and a single subset of the 62nd meta-column selection line CSL62 in the 2_1th sub-memory bank SB2_1. Such normal data and metadata writing or reading operations may be performed substantially simultaneously.

[0196] exist Fig.16A , an example of performing a normal data write or read operation on a region of the 1_1th sub-bank SB1_1 corresponding to the 1_0th word line WL1_0 and the 55th normal column selection line CSL55 is provided.

[0197] exist Fig. 16BIn the embodiment, the 55th common column selection line CSL55 may correspond to some subset of the 62nd element column selection line CSL62.

[0198] Accordingly, metadata corresponding to normal data may be stored in an area within the 2_2nd sub-bank SB2_2 corresponding to the 2_0th word line WL2_0 corresponding to the 1_0th word line WL1_0 and the 62nd meta column selection line CSL62 corresponding to the 55th normal column selection line CSL55.

[0199] To this end, the first row decoder RD1 may activate the 1_0 th word line WL1_0 , and the second row decoder RD2 may activate the 2_0 th word line WL2_0 .

[0200] The column selection signal of the 1_1th sub-bank SB1_1 side may be “CSL55[0:15]”. The first column decoder CD1 may activate the 55th column selection line CSL55 of each of the 0th to 15th CSL groups CS0 to CS15.

[0201] The second column decoder CD2 can select some subsets of the meta column selection lines CSL62 corresponding to the 55th normal column selection line CSL55. In some embodiments, a subset corresponding to the eighth block (e.g., CB7) can be selected. In some embodiments, the column selection signal can be "CSL62[14:15]". In some embodiments, the fourteenth CSL group CS14 and the fifteenth CSL group CS15 can be selected, and the 62nd column selection line CSL62 can be selected in each of the fourteenth CSL group CS14 and the fifteenth CSL group CS15. Since the seventh CSL block CB7 corresponds to the fourteenth CSL group CS14 and the fifteenth CSL group CS15, the seventh CSL block CB7 of the 2_1st sub-storage body SB2_1 can activate two 62nd column selection lines CSL62.

[0202] Accordingly, normal data may be written to or read from an area corresponding to the 1_0th word line WL1_0 and the 55th normal column selection line CSL55 in the 1_1th sub-memory bank SB1_1, and metadata corresponding to the normal data may be written to or read from an area corresponding to the 2_0th word line WL2_0 and another subset of the 62nd meta-column selection line CSL62 in the 2_1th sub-memory bank SB2_1. Such normal data and metadata writing or reading operations may be performed substantially simultaneously.

[0203] Figures 17 to 20 is a diagram showing an example of CSL allocation of metadata during a write or read operation of normal data for a 1_1th word line WL1_1 according to some embodiments. FIG. 13A to FIG. 16BThe described CSL allocation method for a single word line can be similarly applied to other word lines. Accordingly, for the convenience of description, redundant description will be omitted.

[0204] exist Fig.17 , an example of performing a normal data write or read operation on a region of the 1_1th sub-bank SB1_1 corresponding to the 1_1th word line WL1_1 and the 0th normal column selection line CSL0 is provided.

[0205] The metadata for normal data may be stored in an area within the 2_1th sub-memory bank SB2_1 that corresponds to some subsets of the 2_1th word line WL2_1 corresponding to the 1_1th word line WL1_1 and the 56th meta column selection line CSL56 corresponding to the 0th normal column selection line CSL0.

[0206] To this end, the first row decoder RD1 may activate the 1_1th word line WL1_1 , and the second row decoder RD2 may activate the 2_1th word line WL2_1 .

[0207] The column selection signal of the 1_1th sub-bank SB1_1 side may be 'CSL0[0:15]'. The first column decoder CD1 may activate the 0th column selection line CSL0 of each of the 0th to 15th CSL groups CS0 to CS15.

[0208] The second column decoder CD2 may select some subset of the 56th elementary column selection lines CSL56 corresponding to the 0th common column selection line CSL0. In some embodiments, the column selection signal may be "CSL56[0:1]". In some embodiments, the 0th CSL group CS0 and the first CSL group CS1 may be selected, and the 56th column selection line CSL56 may be activated in each of the 0th CSL group CS0 and the first CSL group CS1.

[0209] Accordingly, normal data can be written to or read from the area in the 1_1th sub-storage body SB1_1 corresponding to the 1_1th word line WL1_1 and the 0th normal column selection line CSL0, and metadata corresponding to the normal data can be written to or read from the area in the 2_1th sub-storage body SB2_1 corresponding to the 2_1th word line WL2_1 and a single subset of the 56th meta-column selection line CSL56.

[0210] exist Fig.18 , an example of performing a normal data write or read operation on a region of a 1_1th sub-bank SB1_1 corresponding to a 1_1th word line WL1_1 and a first normal column select line CSL1 is provided.

[0211] The metadata for normal data may be stored in an area within the 2_1th sub-memory bank SB2_1 that corresponds to a subset of the 2_1th word line WL2_1 corresponding to the 1_1th word line WL1_1 and some subsets of the 56th meta column selection line CSL56 corresponding to the first normal column selection line CSL1.

[0212] To this end, the first row decoder RD1 may activate the 1_1th word line WL1_1 , and the second row decoder RD2 may activate the 2_1th word line WL2_1 .

[0213] The column selection signal of the 1_1th sub-bank SB1_1 side may be 'CSL1[0:15]'. The first column decoder CD1 may activate the first column selection line CSL1 in each of the 0th to 15th CSL groups CS0 to CS15.

[0214] The second column decoder CD2 may select some subset of the 56th column selection lines CSL56 corresponding to the first common column selection lines CSL1. In some embodiments, the column selection signal may be "CSL56[2:3]". In some embodiments, the first CSL group CS2 and the third CSL group CS3 may be selected, and the 56th column selection line CSL56 may be activated in each of the second CSL group CS2 and the third CSL group CS3.

[0215] Accordingly, normal data can be written to or read from an area in the 1_1th sub-storage body SB1_1 corresponding to the 1_1th word line WL1_1 and the 0th normal column selection line CSL0, and metadata corresponding to the normal data can be written to or read from an area in the 2_1th sub-storage body SB2_1 corresponding to another subset of the 2_1th word line WL2_1 and the 56th meta-column selection line CSL56.

[0216] exist Fig.19 , an example of performing a normal data write or read operation on a region of the 1_1th sub-bank SB1_1 corresponding to the 1_1th word line WL1_1 and the 54th normal column selection line CSL54 is provided.

[0217] Metadata for normal data may be stored in an area within the 2_1th sub-bank SB2_1 that corresponds to some subset of the 2_1th word line WL2_1 corresponding to the 1_1th word line WL1_1 and the 62nd meta column select line CSL62 corresponding to the 54th normal column select line CSL54.

[0218] To this end, the first row decoder RD1 may activate the 1_1th word line WL1_1 , and the second row decoder RD2 may activate the 2_1th word line WL2_1 .

[0219] The column selection signal of the 1_1th sub-bank SB1_1 side may be “CSL54[0:15]”. The first column decoder CD1 may activate the 54th column selection line CSL54 of each of the 0th to 15th CSL groups CS0 to CS15.

[0220] The second column decoder CD2 may select some subset of the 62nd elementary column selection lines CSL62 corresponding to the 54th common column selection line CSL54. In some embodiments, the column selection signal may be "CSL62[12:13]". In some embodiments, the twelfth CSL group CS12 and the thirteenth CSL group CS13 may be selected, and the 62nd column selection line CSL62 of each of the twelfth CSL group CS12 and the thirteenth CSL group CS13 may be activated.

[0221] Accordingly, normal data can be written to or read from the area in the 1_1th sub-storage body SB1_1 corresponding to the 1_1th word line WL1_1 and the 54th common column selection line CSL54, and metadata corresponding to the normal data can be written to or read from the area in the 2_1th sub-storage body SB2_1 corresponding to the 2_1th word line WL2_1 and a single subset of the 62nd meta-column selection line CSL62.

[0222] exist Fig. 20 , an example of performing a normal data write or read operation on a region of the 1_1th sub-bank SB1_1 corresponding to the 1_1th word line WL1_1 and the 55th normal column selection line CSL55 is provided.

[0223] Metadata for normal data may be stored in an area within the 2_1th sub-bank SB2_1 that corresponds to a subset of the 2_1th word line WL2_1 corresponding to the 1_1th word line WL1_1 and a portion of the 62nd meta column select line CSL62 corresponding to the 54th normal column select line CSL54.

[0224] To this end, the first row decoder RD1 may activate the 1_1th word line WL1_1 , and the second row decoder RD2 may activate the 2_1th word line WL2_1 .

[0225] The column selection signal of the 1_1th sub-bank SB1_1 side may be “CSL55[0:15]”. The first column decoder CD1 may activate the 55th column selection line CSL55 of each of the 0th to 15th CSL groups CS0 to CS15.

[0226] The second column decoder CD2 may select some subset of the 62nd elementary column selection lines CSL62 corresponding to the 55th ordinary column selection lines CSL55. In some embodiments, the column selection signal may be "CSL62[14:15]". In some embodiments, the fourteenth CSL group CS14 and the fifteenth CSL group CS15 may be selected, and the 62nd column selection line CSL62 may be activated in each of the fourteenth CSL group CS14 and the fifteenth CSL group CS15.

[0227] Accordingly, normal data can be written to or read from an area in the 1_1th sub-storage body SB1_1 corresponding to the 1_1th word line WL1_1 and the 55th common column selection line CSL55, and metadata corresponding to the normal data can be written to or read from an area in the 2_1th sub-storage body SB2_1 corresponding to another subset of the 2_1th word line WL2_1 and the 62nd meta-column selection line CSL62.

[0228] According to some embodiments, some subsets of corresponding meta column selection lines may be allocated for metadata to correspond to a single normal column selection line. Accordingly, additional chip size overhead may be reduced. In some embodiments, metadata for normal data stored in a single sub-memory bank may be distributed and stored in corresponding word lines in another sub-memory bank, and may not be concentrated and stored in a specific word line in another sub-memory bank. Accordingly, a row hammer effect caused by repeatedly accessing a specific word line to access metadata may be reduced.

[0229] Fig.21 is a diagram illustrating an example of a memory bank according to some embodiments. Fig.21 The first memory bank B1 may correspond to Figures 1 to 8 One of the first memory banks B1 described in .

[0230] exist Fig.21 , the 1_1th sub-memory bank SB1_1 may be electrically connected to the first row decoder RD1 and the first column decoder CD1. The 1_1th sub-memory bank SB1_1 may be connected to a plurality of word lines WL1_0 to WL1_32k-1 through the first row decoder RD1. In addition, the 1_1th sub-memory bank SB1_1 may be connected to a plurality of CSL subsets L_CS0 to U_CSi-1 through the first column decoder CD1.

[0231] The 2_1st sub-memory bank SB2_1 may be electrically connected to the second row decoder RD2 and the second column decoder CD2. The 2_1st sub-memory bank SB2_1 may be connected to a plurality of word lines WL2_0 to WL2_32k-1 through the second row decoder RD2. In addition, the 2_1st sub-memory bank SB2_1 may be connected to a plurality of CSL subsets L_CS0 to U_CSi-1 through the second column decoder CD2.

[0232] Each of the 1_1th sub-memory bank SB1_1 and the 2_1th sub-memory bank SB2_1 may include a plurality of memory blocks MAT. A portion of word lines and a portion of column selection lines may be connected to each MAT. Each MAT includes a plurality of memory cells, and each memory cell may be connected to one of a portion of word lines connected to a corresponding memory block MAT and one of a portion of column selection lines connected to a corresponding memory block MAT.

[0233] refer to Fig.21 , each sub-bank may include a plurality of CSL blocks CB0 to CB15 and a single error correction code (ECC) block. Fig.21 , 16 CSL blocks per sub-block are shown. Each CSL block and each ECC block can be configured to select the CSL based on a column address decoded by a column decoder CD. The CSL blocks CB0 to CB15 and the ECC blocks can be arranged along the columns corresponding to the CSL. For example, among the plurality of storage blocks MAT, the storage blocks MAT connected to the columns corresponding to the ECC blocks can store parity bits generated from the ECC blocks.

[0234] In some embodiments, the ECC block may be arranged to correspond to a middle column of a plurality of columns formed by a plurality of storage bodies MAT included in a sub-storage body SB. For example, for a single sub-storage body SB, a plurality of CSL blocks CSL may be arranged symmetrically with respect to the ECC block. Accordingly, the column selection lines CSL connected to the plurality of CSL blocks CSL may also be arranged symmetrically with respect to the column selection lines CSL connected to the ECC block.

[0235] A plurality of CSL subsets L_CS0 to U_CSi-1 may be connected to a plurality of storage blocks MAT corresponding to a single CSL block. As shown, during one access, a CSL subset may be selected from a plurality of CSL subsets L_CS0 to U_CSi-1. In some embodiments, a pair of CSL subsets L_CS0 and L_CS1 to a pair of CSL subsets L_CSi-2 and L_CSi-1 (where i is a positive integer) may be selected on a first side L relative to the ECC block, and a pair of CSL subsets U_CS0 and U_CS1 to a pair of CSL subsets U_CSi-2 and U_CSi-1 may be selected on a second side U relative to the ECC block. In some embodiments, a single subset may be selected from a subset pair on the first side L, and a single subset may be selected from a subset pair on the second side U. In addition, a pair of CSL subsets M_CS0 and M_CS1 may be selected for an ECC block.

[0236] exist Fig.21In the embodiment, when each CSL is connected to 8 bit lines, 256 bits (8 bits × 32 (the number of CSLs corresponding to the CSL subset selected for the normal data)) of normal data can be output during the access of a single word line. When the ratio of normal data to metadata is 8:1, 32 bits (8 bits × 4 (the number of CSLs corresponding to the CSL subset selected for metadata)) of metadata and 16 bits of parity bits can be output. When the ratio of normal data to metadata is 16:1, 16 bits (8 bits × 2 (the number of CSLs corresponding to the CSL subset selected for metadata)) of metadata and 16 bits of parity bits can be output.

[0237] Fig. 22 and Fig.23 is a diagram showing a method for performing a Fig.21 FIG. 1 is a diagram of an example of CSL allocation during a normal data write or read operation performed on a single word line (eg, the 10th word line) in a memory bank structure of FIG.

[0238] For ease of description, an example of a column selection signal of "CSLx[a:b]" is provided. In some embodiments, "x" may refer to the number of column selection lines (where x is one of 0 to 63), and "[a:b]" may refer to the range of the selected CSL group. Column selection lines allocated to normal data are referred to as normal column selection lines, and column selection lines allocated to metadata are referred to as meta column selection lines.

[0239] exist Fig. 22 , an example of performing a normal data write or read operation on a region of the 1_1th sub-bank SB1_1 corresponding to the 1_0th word line WL1_0 and the 0th normal column selection line CSL0 is provided.

[0240] In some embodiments, the 0th normal column selection line CSL0 may correspond to some subset of the 56th meta column selection line CSL56.

[0241] Accordingly, metadata corresponding to normal data may be stored in an area corresponding to some subset of the 2_0th word line WL2_0 corresponding to the 1_0th word line WL1_0 and the 56th metal column selection line CSL56 corresponding to the 0th normal column selection line CSL0.

[0242] To this end, the first row decoder RD1 may activate the 1_0 th word line WL1_0 , and the second row decoder RD2 may activate the 2_0 th word line WL2_0 .

[0243] The column selection signal on the 1_1th sub-bank SB1_1 side may be “CSL0[0:15].” The first column decoder CD1 may activate all CSL subsets L_CS0 to U_CS15 corresponding to the 0th normal column selection line CSL0 .

[0244] The second column decoder CD2 can select some subsets of the 56th elementary column selection line CSL56 corresponding to the 0th common column selection line CSL0. In some embodiments, a subset pair corresponding to the first block of each of the first side L and the second side U can be selected. In some embodiments, the column selection signal can be "CSL56[0:1]". In some embodiments, the 56th column selection line CSL56 can be selected from the first two groups L_CS0 and L_CS1 on the first side L, and the 56th column selection line CSL56 can be selected from the first two groups U_CS0 and U_CS1 on the second side U.

[0245] Accordingly, normal data may be written to or read from an area corresponding to the 1_0th word line WL1_0 and the 0th normal column selection line CSL0 in the 1_1th sub-memory bank SB1_1, and metadata corresponding to the normal data may be written to or read from an area corresponding to the subset pair of the 2_0th word line WL2_0 and the 56th meta-column selection line CSL56 in the 2_1th sub-memory bank SB2_1. Such normal data and metadata writing or reading operations may be performed substantially simultaneously.

[0246] exist Fig.23 , an example of performing a normal data write or read operation on a region of the 1_1th sub-bank SB1_1 corresponding to the 1_0th word line WL1_0 and the 55th normal column selection line CSL55 is provided.

[0247] In some embodiments, the 55th normal column selection line CSL55 may correspond to a subset of the 62nd meta column selection line CSL62.

[0248] Accordingly, metadata for normal data may be stored in an area within the 2_2 th sub-bank SB2_2 , which corresponds to some subsets of the 2_0 th word line WL2_0 corresponding to the 1_0 th word line WL1_0 , and the 62 th meta column select line CSL62 .

[0249] To this end, the first row decoder D1 may activate the 1_0 th word line WL1_0 , and the second row decoder D2 may activate the 2_0 th word line WL2_0 .

[0250] The column selection signal on the 1_1th sub-bank SB1_1 side may be “CSL55[0:15]”. The first column decoder CD1 may activate all CSL subsets L_CS0 to U_CS15 corresponding to the 55th normal column selection line CSL55.

[0251] The second column decoder CD2 can select some subsets of the 62nd elementary column selection line CSL62 corresponding to the 0th common column selection line CSL0. In some embodiments, a subset pair corresponding to the eighth block of each of the first side L and the second side U can be selected. In some embodiments, the column selection signal can be "CSL62[14:15]". In some embodiments, the 62nd column selection line CSL62 can be selected from the two groups L_CS14 and L_CS15 on the first side L, and the 62nd column selection line CSL62 can be selected from the two groups U_CS14 and U_CS15 on the second side U.

[0252] Accordingly, normal data may be written to or read from an area corresponding to the 1_0th word line WL1_0 and the 0th normal column selection line CSL0 in the 1_1th sub-memory bank SB1_1, and metadata corresponding to the normal data may be written to or read from an area corresponding to the 2_0th word line WL2_0 and a single subset of the 62nd meta-column selection line CSL62 in the 2_1th sub-memory bank SB2_1. Such normal data and metadata writing or reading operations may be performed substantially simultaneously.

[0253] Fig. 22 and Fig.23 An example is shown in which one of the CSL subsets L_CS0 to L_CSi-1 included in the first side L and one of the CSL subsets U_CS0 to U_CSi-1 included in the second side U are sequentially selected for a meta column selection line in a CSL subset connected to a single sub-storage body SB. In some embodiments, four CSLs may be activated from a corresponding CSL group for a single meta column selection line. However, some embodiments are not limited thereto and may vary according to a desired ratio of normal data to metadata, and a structure of a sub-storage body. In some embodiments, in a CSL subset connected to a single sub-storage body SB, one of the CSL subsets L_CS0 to L_CSi-1 included in the first side L and one of the CSL subsets U_CS0 to U_CSi-1 included in the second side U may be sequentially selected from a CSL subset having a lowest index. In some embodiments, two CSLs may be activated for a single meta column selection line.

[0254] As described above, a storage device according to some embodiments may reduce an area increase caused by allocation of metadata or reduce a hammer effect of access to metadata.

[0255] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the protection claimed. In a single embodiment, specific features described in the context of independent embodiments in the present disclosure can also be implemented in combination. Conversely, various features described in the context of a single embodiment can also be implemented separately in multiple embodiments, or in appropriate sub-combinations. In addition, although features may be described above as working in certain combinations, one or more features in the combination can be deleted from the combination in some cases, and the combination can be for sub-combinations or variations of sub-combinations.

Claims

1. A storage device, comprising: at least one memory bank including a first sub-memory bank and a second sub-memory bank arranged in a word line direction, The first sub-memory bank is configured to store normal data and is connected to a plurality of first word lines. The second sub-memory bank is configured to store metadata corresponding to the normal data and is connected to a plurality of second word lines, and The metadata for the common data corresponding to each of the plurality of first word lines is configured to be stored in each of the plurality of second word lines corresponding to the plurality of first word lines, respectively.

2. The storage device according to claim 1, wherein: Based on performing a write operation or a read operation on the normal data in the first sub-storage bank, writing or reading is performed on the metadata corresponding to the normal data in the second sub-storage bank.

3. The storage device according to claim 2, in, Each of the first sub-memory bank and the second sub-memory bank is connected to p column selection lines, where p is a positive integer greater than or equal to 2. wherein a first part of the p column selection lines is allocated to a region in which the normal data of the first sub-memory bank is stored as normal column selection lines, and The second part of the p column selection lines is allocated to the area in which the metadata of the second sub-memory bank is stored as meta-column selection lines.

4. The storage device according to claim 3, in, Among the p column selection lines connected to the first sub-memory bank, the remaining column selection lines except the normal column selection lines are allocated to metadata corresponding to normal data stored in the second sub-memory bank, and Among the p column selection lines connected to the second sub-memory bank, the remaining column selection lines except the meta column selection line are allocated to normal data stored in the second sub-memory bank.

5. The storage device according to claim 3, wherein: A ratio of the normal column select lines to the meta column select lines is based on a ratio of the normal data to the meta data.

6. The storage device according to claim 5, wherein: Each of the p column selection lines corresponds to n CSL groups, n being a positive integer; and a corresponding column selection line is activated in each of the n CSL groups based on selection of a common column selection line.

7. The storage device according to claim 6, wherein: When the ratio of the normal data to the metadata is k:1, wherein each of the common column select lines corresponds to a single subset of k subsets of corresponding single element column select lines, and Each of the k subsets corresponds to column selection lines activated in a portion of CSL groups among a plurality of CSL groups corresponding to a single meta column selection line.

8. The storage device according to claim 7, wherein: Each of the k subsets corresponds in sequence to a column selection line activated in each of n / k CSL groups among the plurality of CSL groups corresponding to the single meta column selection line.

9. The storage device according to claim 8, wherein: k is 8 or 16.

10. The storage device according to claim 3, further comprising: a first row decoder and a first column decoder, the first row decoder being configured to select one of the plurality of first word lines, the first column decoder being connected to p column selection lines on one side of the first sub-memory bank; as well as a second row decoder configured to select one of the plurality of second word lines and a second column decoder connected to p column selection lines on one side of the second sub-memory bank.

11. The storage device according to claim 10, wherein: The second row decoder is configured to select a single first word line from the plurality of first word lines based on the first row decoder selecting a single second word line from the plurality of second word lines corresponding to the single first word line.

12. The storage device according to claim 11, wherein: When the ratio of the normal data to the metadata is k:1, wherein the second column decoder is configured to: select the common column selection line based on the first column decoder selecting the common column selection line, select a single subset from the k subsets of single meta column selection lines corresponding to the common column selection line, and Each of the k subsets corresponds to a column selection line activated in a portion of CSL groups among a plurality of CSL groups corresponding to a single meta column selection line.

13. The storage device according to any one of claims 1 to 12, in, The at least one memory bank is connected to a plurality of global input / output GIO lines, and The first sub-storage bank and the second sub-storage bank are connected to different GIO lines.

14. The storage device according to any one of claims 2 to 12, in, Metadata corresponding to the normal data stored in the second sub-storage volume is configured to be stored in the first sub-storage volume, and The metadata for the normal data corresponding to each second word line is configured to be stored in each first word line of the plurality of first word lines corresponding to the plurality of second word lines, respectively.

15. A storage device comprising: at least one memory bank including at least a first sub-memory bank and a second sub-memory bank arranged in a word line direction; a first row decoder connected to the first sub-memory bank via a plurality of first word lines; and A second row decoder is connected to the second sub-memory bank through a plurality of second word lines, Wherein, based on the first row decoder selecting a single first word line from the multiple first word lines to write normal data into the first sub-storage body, the second row decoder is configured to select a single second word line corresponding to the single first word line from the multiple second word lines to write metadata corresponding to the normal data.

16. The storage device according to claim 15, further comprising: a first column decoder connected to the first sub-memory bank via a plurality of first column selection lines; and The second column decoder is connected to the second sub-memory bank through a plurality of second column selection lines.

17. The storage device according to claim 16, in, A portion of the plurality of first column selection lines is configured to be allocated to a region in which the normal data is stored as a normal column selection line, and Part of the plurality of second column selection lines is configured to be allocated to the area in which the metadata is stored as a meta column selection line.

18. The storage device according to claim 17, in, When the ratio of the normal data to the metadata is k:1, Metadata for normal data corresponding to k normal column select lines corresponds to a single meta column select line, and wherein the second column decoder is configured to: select a single subset from among k subsets of single meta column selection lines corresponding to the normal column selection lines based on the first column decoder selecting the normal column selection lines, and Each of the k subsets corresponds to a column selection line configured to be activated in a portion of the CSL groups among the n CSL groups corresponding to a single meta column selection line.

19. The storage device according to claim 18, wherein: Each of the k subsets corresponds in turn to a column selection line configured to be activated in each of n / k CSL groups among the n CSL groups corresponding to the single meta column selection line.

20. A storage system comprising: A memory device, comprising at least one memory bank, the at least one memory bank comprising at least a first sub-memory bank and a second sub-memory bank arranged in a word line direction; as well as a storage controller configured to control the storage device, The first sub-memory bank is configured to store normal data and is connected to a plurality of first word lines. The second sub-memory bank is configured to store metadata corresponding to the normal data and is connected to a plurality of second word lines, and The metadata for the normal data corresponding to each first word line among the plurality of word lines is stored in each second word line among the plurality of second word lines respectively corresponding to the plurality of first word lines.

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