Refresh control circuit

Abstract

The invention provides a refresh control circuit. The refresh control circuit comprises a clock signal generator, a plurality of pulse wave number adjusters and a plurality of address counters. The clock signal generator generates a clock signal. The pulse wave number adjuster receives the clock signal, and adjusts the pulse wave number of the clock signal according to a plurality of pieces of data retention information in a time period to generate a plurality of adjusted clock signals. The address counter generates a plurality of pieces of refresh address information according to the adjusted clock signal. The refresh address information corresponds to a plurality of repositories of the memory device. The repository performs a refresh action according to the refresh address information.

Description

Technical Field

[0001] The invention relates to a refresh control circuit, and in particular to a refresh control circuit capable of improving refresh operation efficiency. Background Art

[0002] In a dynamic random access memory, the storage capacitor in the memory cell will leak over time, so it is necessary to perform a refresh operation on the memory cell regularly. The refresh operation of the dynamic random access memory can be divided into a burst refresh operation (Burst Refresh) and a distributed refresh operation (Distributed Refresh).

[0003] In a dynamic random access memory, not all memory cells have the same data retention. Therefore, if a consistent refresh frequency is used to perform refresh operations on all memory cells, many unnecessary refresh operations will inevitably occur. This will reduce the access bandwidth of the memory and increase unnecessary power consumption. Therefore, how to optimize the refresh operation of the memory is an important issue for engineers in this field. Summary of the invention

[0004] According to an embodiment of the present invention, a refresh control circuit includes a clock signal generator, a plurality of pulse quantity adjusters, and a plurality of address counters. The clock signal generator generates a clock signal. The pulse quantity adjuster is coupled to the clock signal generator. The pulse quantity adjuster receives the clock signal and adjusts the pulse quantity of the clock signal according to a plurality of data retention information in a time period to generate a plurality of adjusted clock signals respectively. The address counters are respectively coupled to the pulse quantity adjusters to generate a plurality of refresh address information according to the adjusted clock signal. The refresh address information corresponds to a plurality of storage banks of the memory device and is used to enable the storage banks to perform refresh actions respectively according to the refresh address information.

[0005] According to an embodiment of the present invention, a refresh control circuit includes a clock signal generator, a counter and a plurality of multiplexers. The clock signal generator generates a clock signal. The counter performs a counting action based on the clock signal to generate counting information having N bits, wherein N is an integer greater than 1. The multiplexers correspond to a plurality of storage bins of a memory device respectively. The multiplexers are coupled to the counters, and M bits of the N bits of the counting information are selected according to a plurality of data preservation information respectively to generate a plurality of refresh address information respectively. The refresh address information is provided to the storage bins respectively so that the storage bins perform refresh actions respectively according to the refresh address information.

[0006] Based on the above, in the refresh control circuit of the present invention, by recording the data retention information of multiple memory banks of the memory device, and adjusting the pulse number of the clock signal corresponding to the count refresh address information according to the data retention information, the frequency of each memory bank performing the refresh action can be associated with its data retention information, and the efficiency of the refresh action of the memory device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram showing a refresh control circuit according to an embodiment of the present invention;

[0008] Figure 2 A schematic diagram showing a refresh control circuit according to another embodiment of the present invention;

[0009] Figure 3 A schematic diagram showing a refresh control circuit according to another embodiment of the present invention;

[0010] Figure 4 A flow chart showing a method for generating data preservation information according to an embodiment of the present invention;

[0011] Figure 5 A schematic diagram showing a refresh control circuit according to another embodiment of the present invention;

[0012] Figure 6 Showing the present invention Figure 5 A schematic diagram of a method for generating refresh address information of a refresh control circuit according to an embodiment. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Please refer to Figure 1 , Figure 1FIG. 1 is a schematic diagram of a refresh control circuit according to an embodiment of the present invention. The refresh control circuit 100 may be applied in a memory device, wherein the memory device may be a dynamic random access memory device. The refresh control circuit 100 includes a clock signal generator 140, a plurality of pulse quantity adjusters 131-134, and a plurality of address counters 121-124. The address counters 121-124 correspond to a plurality of memory banks 111-114 of the memory device, respectively. The clock signal generator 140 is used to generate a clock signal OSC. The clock signal OSC may be used as a frequency basis for the refresh control circuit 100 to perform a refresh operation. The pulse quantity adjusters 131-134 are coupled to the clock signal generator 140 and receive the clock signal OSC provided by the clock signal generator 140. In addition, the pulse quantity adjusters 131-134 further receive data retention information DRI1-DRI4, respectively. The data retention information DRI1-DRI4 respectively indicates the data retention of the memory banks 111-114. The pulse number adjusters 131 - 134 adjust the pulse number of the clock signal OSC according to the received data retention information DRI1 - DRI4 in a time period to generate a plurality of adjusted clock signals POSC1 - POSC4 .

[0015] It should be noted that the pulse number adjusters 131 - 134 can respectively retain or reduce the pulse number of the clock signal OSC according to the data retention information DRI1 - DRI4 , and thereby generate adjusted clock signals POSC1 - POSC4 .

[0016] Taking the pulse quantity adjuster 131 as an example, when the corresponding memory bank 111 is detected to have a low data retention rate and needs to perform a relatively high-frequency refresh operation, the pulse quantity adjuster 131 can retain all the pulse numbers of the clock signal OSC in a time period to generate the corresponding adjusted clock signal POSC1. Taking the pulse quantity adjuster 132 as an example, if the data retention rate of the corresponding memory bank 112 is detected to be higher than the data retention rate of the memory bank 111, it means that the frequency of the refresh operation required by the memory bank 112 may be lower than that of the memory bank 111. Therefore, the pulse quantity adjuster 132 can reduce the number of pulses in the above time period to reduce the execution frequency of the refresh operation of the memory bank 112.

[0017] It is worth mentioning that, in this embodiment, the data preservation information DRI1-DRI4 can be obtained by the test device testing the memory banks 111-114 respectively. In this embodiment, each memory bank 111-114 can have multiple word lines. The test device can perform data preservation tests on the storage cells on the multiple word lines on each memory bank 111-114, and generate the data preservation information DRI1-DRI4 corresponding to each memory bank 111-114 according to the word line with the worst data preservation on each memory bank 111-114.

[0018] In this embodiment, the aforementioned testing device may be a testing machine outside the memory device.

[0019] On the other hand, the address counters 121-124 are respectively coupled to the pulse number adjusters 131-134 and the corresponding memory banks 111-114. The address counters 121-124 receive the adjusted clock signals POSC1-POSC4 generated by the pulse number adjusters 131-134, and perform address counting operations according to the pulses on the adjusted clock signals POSC1-POSC4. The address counters 121-124 generate refresh address information ADR1-ADR4, respectively. The memory banks 111-114 can perform data refresh operations on the storage cells of each bit line according to the refresh address information ADR1-ADR4, respectively.

[0020] In this embodiment, the address counters 121-124 can be implemented by any counting circuit known to those skilled in the art, such as a ripple counter composed of a plurality of T-type flip-flops connected in series or a synchronous counter constructed by a plurality of D-type flip-flops, without any specific limitation. In addition, the clock signal generator 140 can also be implemented by any frequency generating circuit known to those skilled in the art, without any specific limitation.

[0021] As can be seen from the above description, the refresh control circuit 100 of the embodiment of the present invention can control the counting frequency of the refresh address information ADR1-ADR4 by controlling the number of pulses of the clock signal OSC. In this way, corresponding to the memory banks 111-114 with different data preservation degrees, the refresh control circuit 100 can control the frequency of the refresh action of the memory banks 111-114 respectively by controlling the counting frequency of the refresh address information ADR1-ADR4. In this way, the refresh control circuit 100 can adjust the refresh action performed on each memory bank 111-114 according to the data preservation degree of each memory bank 111-114, thereby improving the efficiency of the refresh action.

[0022] Please refer to Figure 2 , Figure 2Schematic diagram of a refresh control circuit according to another embodiment of the present invention is shown. The refresh control circuit 200 includes a clock signal generator 240, a plurality of gate control circuits 231-234, a plurality of address counters 221-224 and a database 250. Figure 1 In this embodiment, the pulse quantity adjusters 131-134 are implemented by gate control circuits 231-234 respectively. In detail, the address counters 221-224 correspond to the plurality of memory banks 211-214 of the memory device respectively. The clock signal generator 240 is used to generate the clock signal OSC as the frequency basis for the refresh control circuit 200 to perform the refresh operation. The gate control circuits 231-234 are coupled to the clock signal generator 240 and receive the clock signal OSC provided by the clock signal generator 240.

[0023] In this embodiment, the gate control circuits 231-234 receive data retention information DRI1-DRI4, and, in a time period, the gate control circuits 231-234 respectively determine whether to shield the pulses on the clock signal OSC and the number of pulses to be shielded according to the received data retention information DRI1-DRI4, and respectively generate a plurality of adjusted clock signals POSC1-POSC4.

[0024] In this embodiment, the clock signal OSC has four pulses in a time interval, and the data retention levels of the storage banks 211-214 indicated by the data retention level information DRI1-DRI4 are arranged from low to high in the order of DRI1, DRI2, DRI3, and DRI4. The gate control circuit 231 can decide not to shield the pulse on the clock signal OSC according to the data retention level information DRI1, and make the generated adjusted clock signal POSC1 the same as the clock signal OSC. The gate control circuit 232 can decide to shield one pulse on the clock signal OSC according to the data retention level information DRI2, and make the generated adjusted clock signal POSC2 have three pulses in a time interval. The gate control circuit 233 decides to shield two pulses on the clock signal OSC according to the data retention level information DRI3, and makes the generated adjusted clock signal POSC3 have two pulses in a time interval. The gate control circuit 234 can determine to shield three pulses of the clock signal OSC according to the data preservation degree information DRI4, and make the generated adjusted clock signal POSC4 have one pulse in a time interval. In this embodiment, the data preservation degree represented by the data preservation degree information DRI1-DRI4 is positively correlated with the number of pulses of the clock signal OSC to be shielded by the corresponding gate control circuits 231-234.

[0025] On the other hand, the database 250 is coupled to the gate control circuits 231-234. The database 250 is used to store the data retention information DRI1-DRI4, and provide the data retention information DRI1-DRI4 to the gate control circuits 231-234 respectively. In this embodiment, the test device can perform a test operation on the data retention for the storage banks 211-214 of the memory device, and store the test results (data retention information DRI1-DRI4) in the database 250. The database 250 can be a non-volatile storage device, such as a read-only memory, a flash memory, or an electronic fuse circuit.

[0026] Incidentally, in this embodiment, each gate control circuit 231-234 can be implemented by using a digital circuit. For example, the gate control circuits 231-234 can receive the data preservation information DRI1-DRI4 in the form of digital codes, and determine the number of pulses in the clock signal OSC to be masked according to the data preservation information DRI1-DRI4. Each gate control circuit 231-234 can determine to mask 0 or more pulses in the clock signal OSC. In addition, each adjusted clock signal POSC1-POSC4 can have at least one pulse in a time interval.

[0027] The above time interval can be set by the designer according to actual needs without any specific restrictions.

[0028] Please refer to the following Figure 3 , Figure 3 Schematic diagram of a refresh control circuit according to another embodiment of the present invention is shown. The refresh control circuit 300 includes a clock signal generator 340, a plurality of frequency dividers 331-334, a plurality of address counters 321-324 and a database 350. Figure 1 In this embodiment, the pulse quantity adjusters 131-134 are implemented by frequency dividers 331-334 respectively. Figure 2 In the embodiment of the present invention, the refresh control circuit 300 adjusts the number of pulses of the clock signal OSC in a time interval through the frequency dividers 331-334. In detail, the frequency dividers 331-334 respectively receive the data preservation information DRI1-DRI4 provided by the database 350. The frequency dividers 331-334 set the frequency division number according to the respectively received data preservation information DRI1-DRI4, and perform the frequency division operation on the clock signal OSC. Among them, corresponding to each relatively high data preservation information DRI1-DRI4, each frequency divider 331-334 can be set to have a relatively high frequency division number. Conversely, corresponding to each relatively low data preservation information DRI1-DRI4, each frequency divider 331-334 can be set to have a relatively low frequency division number. In this embodiment, the frequency division number can be any real number greater than or equal to 1.

[0029] To further explain, when the frequency division number is larger, the number of pulses of each adjusted clock signal POSC1-POSC4 in a time interval will be smaller. In this way, the refresh address information generated by the corresponding address counters 321-324 can be reduced, and the refresh frequency of each corresponding storage memory 311-314 can be reduced. Conversely, when the frequency division number is smaller, the number of pulses of each adjusted clock signal POSC1-POSC4 in a time interval will increase. In this way, the refresh address information generated by the corresponding address counters 321-324 can be increased, and the refresh frequency of each corresponding storage memory 311-314 can be increased. In other words, the frequency division number of each frequency divider 331-334 is positively correlated with the data preservation degree represented by the corresponding data preservation degree information DRI1-DRI4.

[0030] It is worth mentioning that Figures 1 to 3 In the embodiment of the present invention, the number of storage repositories can be any number. Figures 1 to 3 The four storage libraries shown in the figure are merely illustrative examples and are not intended to limit the scope of implementation of the present invention.

[0031] Please refer to the following Figure 4 , Figure 4 A flow chart showing a method for generating data preservation information according to an embodiment of the present invention. In step S410, test information may be written to a plurality of storage units in a tested storage library. This test information may be a background pattern. Next, in step S420, a data preservation test action is performed on the tested storage library. The data preservation test action performed in step S420 may be implemented by applying any data preservation test action on a memory in the art, without any specific limitation.

[0032] In step S430, the information is read out for the storage unit in the tested storage library, and the test result is determined to be passed or failed by comparing the written information and the read information. It is worth mentioning that when the read information in step S430 is consistent with the written information, the data preservation test time can be further increased, and the step S410 is returned to perform the next data preservation test. Among them, steps S410 to S430 can be repeated multiple times, and the state of the data preservation in the tested storage library can be measured.

[0033] According to the test results, in step S440, the data preservation level of the tested storage memory can be evaluated and data preservation level information can be generated. In step S450, the data preservation level information of each corresponding storage memory can be recorded. Then, step S410 is returned to perform the data preservation level test action of the next storage memory.

[0034] The above-mentioned action flow may be executed by a testing device, and the testing device may be a testing machine outside the memory device.

[0035] Please refer to Figure 5 , Figure 5 A schematic diagram of a refresh control circuit according to another embodiment of the present invention is shown. The refresh control circuit 500 includes a clock signal generator 560, an address counter 550, multiplexers 541, 542, information transition detectors 531, 532, switches 521, 512, and an electronic fuse circuit 570. The clock signal generator 560 is used to generate a clock signal OSC. The address counter 550 is coupled to the clock signal generator 560 to perform a counting operation according to the clock signal OSC, and to generate counting information ADD having N bits, wherein N is an integer greater than 2. The multiplexers 541, 542 are coupled to the address counter 550 and receive the counting information ADD together. In addition, the multiplexers 541, 542 are coupled to the electronic fuse circuit 570 and receive the data retention information DRI1, DRI2 provided by the electronic fuse circuit 570, respectively.

[0036] In this embodiment, the multiplexers 541 and 542 may respectively select M bits of the N-bit counting information ADD according to the data retention information DRI1 and DRI2 to respectively generate the refresh address information ADR1 and ADR2.

[0037] To further illustrate, you can refer to Figure 6 The present invention shown Figure 5 A schematic diagram of a method for generating refresh address information of a refresh control circuit of an embodiment. Figure 5 In the embodiment of the present invention, the address counter 550 may generate counting information ADD having 5 bits A0 to A4 in multiple counting cycles PL (0 to 15), respectively. Bit A0 may be the least significant bit of the counting information ADD, and bit A4 may be the most significant bit of the counting information ADD. When the memory bank 511 has a relatively low data retention rate, the multiplexer 541 may select the relatively low three bits (bits A0 to A2) to generate the refresh address information ADR1 according to the corresponding data retention rate information DRI1. When the memory bank 512 has a relatively high data retention rate, the multiplexer 542 may select the relatively high three bits (bits A2 to A4) to generate the refresh address information ADR2 according to the corresponding data retention rate information DRI2.

[0038] Depend on Figure 6It can be known that the change rate of the refresh address information ADR1 can be higher than the change rate of the refresh address information ADR2. In this way, the memory bank 511 with a relatively low data retention rate can be set to perform a relatively high-frequency refresh action, and the memory bank 512 with a relatively high data retention rate can be set to perform a relatively low-frequency refresh action.

[0039] Please refer again Figure 5 On the other hand, the information change detectors 531 and 532 are coupled to the multiplexers 541 and 542, respectively. The information change detectors 531 and 532 receive the refresh address information ADR1 and ADR2 provided by the multiplexers 541 and 542, respectively. The information change detectors 531 and 532 are used to detect the change states of the refresh address information ADR1 and ADR2 to generate control signals C1 and C2, respectively. The information change detectors 531 and 532 transmit the generated control signals C1 and C2 to switches 521 and 522, respectively. The switch 521 is coupled between the multiplexer 541 and the memory bank 511, and the switch 522 is coupled between the multiplexer 542 and the memory bank 512. The switches 521 and 522 receive the control signals C1 and C2, respectively, and are opened or turned on according to the control signals C1 and C2, respectively.

[0040] In detail, taking the information change detector 531 as an example, when the information change detector 531 detects that the refresh address information ADR1 has not changed, the information change detector 531 may provide a control signal C1 to turn off the switch 521. Conversely, when the information change detector 531 detects that the refresh address information ADR1 has changed, the information change detector 531 may provide a control signal C1 to turn on the switch 521.

[0041] That is, only when the refresh address information ADR1 changes, the switch 521 can be turned on and transmit the new refresh address information ADR1 to the memory bank 511. In this way, the memory bank 511 can perform a refresh operation for the newly generated refresh address information ADR1.

[0042] In this embodiment, the information transition detectors 531 and 532 can detect whether the logic value of each bit in the refresh address information ADR1 and ADR2 has changed state, so as to detect the information change. The information transition detectors 531 and 532 can be implemented by using a detection circuit for detecting the edge of the logic value change state known to ordinary technicians in the field, without any specific restrictions. In addition, the switches 521 and 522 can be implemented by using a switch circuit known to ordinary technicians in the field, and the multiplexers 541 and 542 can be implemented by using a multiplexer circuit known to ordinary technicians in the field, without any special restrictions.

[0043] It is worth mentioning that Figure 5 In the embodiment of the present invention, the number of storage bins may be any number, and the two storage bins shown in the figure are merely examples for illustration and are not intended to limit the scope of implementation of the present invention.

[0044] In summary, the refresh control circuit of the present invention adjusts the pulse number of the clock signal used to count the refresh address according to the data retention level of the memory bank, and controls the execution frequency of the refresh action of the memory bank. In this way, memory banks with different data retention levels can execute refresh actions at different frequencies. The number of unnecessary refresh actions in the memory device is effectively reduced, and the performance of the refresh action of the memory device is improved.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A refresh control circuit, applicable to a memory device, comprising: A clock signal generator, generating a clock signal; A plurality of pulse quantity adjusters, coupled to the clock signal generator, receiving the clock signal, wherein the plurality of pulse quantity adjusters adjust the pulse quantity of the clock signal according to a plurality of data preservation degree information in a time period to generate a plurality of adjusted clock signals respectively; as well as A plurality of address counters are respectively coupled to the plurality of pulse quantity adjusters to generate a plurality of refresh address information according to the plurality of adjusted clock signals. The plurality of refresh address information corresponds to a plurality of storage bins of the memory device. The plurality of storage bins perform refresh actions according to the plurality of refresh address information.

2. The refresh control circuit according to claim 1, further comprising: The database is coupled to the plurality of pulse quantity adjusters and is used for storing the plurality of data preservation information.

3. The refresh control circuit according to claim 2, wherein a testing device tests the plurality of storage banks of the memory device and obtains the plurality of data retention information corresponding to the plurality of storage banks respectively, and the testing device stores the plurality of data retention information in the database. 4 . The refresh control circuit according to claim 2 , wherein the database is a read-only memory, a flash memory or an electronic fuse circuit.

5. The refresh control circuit according to claim 1, wherein each of the pulse quantity adjusters comprises: The gate control circuit determines the number of N pulses of the clock signal to be shielded in the time period according to the corresponding data preservation information to generate the corresponding adjusted clock signals, wherein N is an integer greater than or equal to 0.

6. The refresh control circuit according to claim 5, wherein the data retention level indicated by each piece of data retention level information is positively correlated with the number of the plurality of pulses of the clock signal to be masked by the corresponding each gate control circuit.

7. The refresh control circuit according to claim 1, wherein each of the pulse quantity adjusters comprises: The frequency divider performs frequency division on the clock signal according to the corresponding data preservation degree information, and generates the corresponding adjusted clock signals. 8 . The refresh control circuit according to claim 7 , wherein the frequency division number of each of the frequency dividers is positively correlated with the data retention level indicated by the corresponding data retention level information.

9. A refresh control circuit, applicable to a memory device, comprising: A clock signal generator, generating a clock signal; An address counter, performing a counting operation based on the clock signal to generate counting information having N bits, wherein N is an integer greater than 2; A plurality of multiplexers, corresponding to a plurality of storage banks of the memory device respectively, the plurality of multiplexers are coupled to the address counter, and respectively select M bits of the plurality of N bits of the counting information according to a plurality of data preservation information to respectively generate a plurality of refresh address information, The plurality of refresh address information are respectively provided to the plurality of memory banks, so that the plurality of memory banks perform refresh actions respectively according to the plurality of refresh address information.

10. The refresh control circuit according to claim 9, further comprising: A plurality of information change detectors are respectively coupled to the plurality of multiplexers, and respectively generate a plurality of control signals according to whether the plurality of refresh address information respectively corresponding to the plurality of refresh address information are changed; as well as A plurality of switches are respectively coupled between the plurality of multiplexers and the plurality of storage banks, and are respectively coupled to the plurality of information change detectors. Each of the switches determines whether to transmit each of the refresh address information to each of the corresponding databases according to the corresponding control signal.

11. The refresh control circuit according to claim 10, wherein when each of the information transition detectors detects that the corresponding refresh address information has transitioned, each of the control signals is generated to turn on the corresponding switches.

12. The refresh control circuit according to claim 9, further comprising: The database is coupled to the multiplexers and is used to store the multiple data preservation information.

13. The refresh control circuit of claim 12, wherein the database is an electronic fuse circuit.

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