Memory and operation method thereof, memory system and readable storage medium

Abstract

The embodiment of the invention provides a memory, an operation method of the memory, a memory system and a readable storage medium. The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit is configured to receive a programming command, a programming address, programming data and a programming confirmation command corresponding to a programming operation; after at least two times of initialization operation are carried out, programming operation is carried out on the storage unit array; wherein the process of receiving the programming command, the programming address, the programming data and the programming confirmation command corresponding to the programming operation and the process of carrying out the at least two initialization operations are at least partially overlapped in time.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory and an operating method thereof, a memory system, and a readable storage medium. Background Art

[0002] With the continuous development of semiconductor technology, the current memory manufacturing technology has gradually transitioned from a simple planar structure to a more complex three-dimensional structure, by arranging the memory cells three-dimensionally on the substrate to improve the integration density. However, before programming the memory, initialization operations need to be completed, and these initialization operations will take up programming time, thus greatly affecting the programming performance.

[0003] Therefore, there is an urgent need to improve the memory and its operation method to enhance the programming performance of the memory. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a memory and an operating method thereof, a memory system, and a readable storage medium.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a memory, the memory comprising a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit is configured as follows:

[0007] receiving a programming command, a programming address, programming data and a programming confirmation command corresponding to a programming operation;

[0008] After performing at least two initialization operations, a programming operation is performed on the memory cell array; wherein the process of receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations at least partially overlap in time.

[0009] In some embodiments, in the case of performing three initialization operations, the three initialization operations include a first initialization operation, a second initialization operation, and a third initialization operation, and the programming address and programming data corresponding to the first initialization operation and the programming operation are irrelevant; the peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a first signal generating circuit, a second signal generating circuit, and a third signal generating circuit;

[0010] The interface circuit is configured to: receive a programming command and a programming address corresponding to a programming operation;

[0011] The first signal generating circuit is configured to: send a first initialization operation signal to the micro control unit after the interface circuit receives a programming command corresponding to a programming operation;

[0012] The micro control unit is configured to: receive the first initialization operation signal and perform a first initialization operation; wherein the process of receiving a programming address corresponding to a programming operation and the process of performing the first initialization operation are executed in parallel.

[0013] In some embodiments, the second initialization operation is related to a programming address corresponding to the programming operation and is unrelated to programming data corresponding to the programming operation;

[0014] The interface circuit is further configured to: receive a programming address and programming data corresponding to a programming operation;

[0015] The second signal generating circuit is configured to: send a second initialization operation signal to the micro control unit after the interface circuit receives a programming address corresponding to a programming operation;

[0016] The micro control unit is further configured to: receive the second initialization operation signal and perform a second initialization operation; wherein the process of receiving the programming data corresponding to the programming operation and the process of performing the second initialization operation are executed in parallel.

[0017] In some embodiments, the first initialization operation includes a temperature detection operation; and the second initialization operation includes a word line voltage bias operation and a bad block detection operation.

[0018] In some embodiments, the third initialization operation is related to programming data corresponding to the programming operation;

[0019] The interface circuit is further configured to: receive programming data and a programming confirmation command corresponding to the programming operation;

[0020] The third signal generating circuit is configured to: send a third initialization operation signal to the micro control unit after the interface circuit receives the programming confirmation command;

[0021] The micro control unit is further configured to: receive the third initialization operation signal and perform a third initialization operation.

[0022] In some embodiments, the micro control unit includes a clock signal circuit;

[0023] The clock signal circuit is configured to output a transition of the clock signal during the process that the micro control unit performs the first initialization operation, the second initialization operation and the third initialization operation.

[0024] In some embodiments, in the case of performing two initialization operations, the two initialization operations include a fourth initialization operation and a third initialization operation, and the fourth initialization operation is irrelevant to programming data corresponding to the programming operation; the peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a fourth signal generating circuit and a third signal generating circuit;

[0025] The interface circuit is configured to: receive a programming command, a programming address, and programming data corresponding to a programming operation;

[0026] The fourth signal generating circuit is configured to: send a fourth initialization operation signal to the micro control unit after the interface circuit receives a programming address corresponding to a programming operation;

[0027] The micro control unit is configured to: receive a fourth initialization operation signal and perform a fourth initialization operation; wherein the process of receiving programming data corresponding to the programming operation and the process of performing the fourth initialization operation are executed in parallel.

[0028] In some embodiments, the fourth initialization operation includes a temperature detection operation, a word line voltage bias operation, and a bad block detection operation.

[0029] In some embodiments, the third initialization operation is related to programming data corresponding to the programming operation;

[0030] The interface circuit is further configured to: receive programming data and a programming confirmation command corresponding to the programming operation;

[0031] The third signal generating circuit is configured to: send a third initialization operation signal to the micro control unit after the interface circuit receives the programming confirmation command;

[0032] The micro control unit is further configured to: receive the third initialization operation signal and perform a third initialization operation.

[0033] In some embodiments, the micro control unit includes a clock signal circuit;

[0034] The clock signal circuit is configured to output a transition of the clock signal during the process of the micro control unit performing the fourth initialization operation and the third initialization operation.

[0035] In a second aspect, an embodiment of the present disclosure provides a memory system, the memory system comprising:

[0036] At least one memory as described in the above technical solution; and

[0037] A controller is coupled to the memory and configured to control the memory.

[0038] In a third aspect, an embodiment of the present disclosure provides an operating method of a memory, wherein the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the operating method includes:

[0039] receiving a programming command, a programming address, programming data and a programming confirmation command corresponding to a programming operation;

[0040] After performing at least two initialization operations, a programming operation is performed on the memory cell array; wherein the process of receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations at least partially overlap in time.

[0041] In some embodiments, in the case of performing three initialization operations, the three initialization operations include a first initialization operation, a second initialization operation, and a third initialization operation, and the programming address and programming data corresponding to the first initialization operation and the programming operation are irrelevant; the peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a first signal generating circuit, a second signal generating circuit, and a third signal generating circuit; the operation method includes:

[0042] The interface circuit receives a programming command corresponding to a programming operation;

[0043] The first signal generating circuit sends a first initialization operation signal to the micro control unit after the interface circuit receives a programming command corresponding to a programming operation;

[0044] The micro control unit receives the first initialization operation signal and performs a first initialization operation; wherein the process of receiving a programming address corresponding to the programming operation and the process of performing the first initialization operation are executed in parallel.

[0045] In some embodiments, the second initialization operation is related to a programming address corresponding to the programming operation and is unrelated to programming data corresponding to the programming operation;

[0046] After the interface circuit receives a programming command corresponding to the programming operation, the operation method further includes:

[0047] The interface circuit receives a programming address corresponding to a programming operation;

[0048] The second signal generating circuit sends a second initialization operation signal to the micro control unit after the interface circuit receives a programming address corresponding to a programming operation;

[0049] The micro control unit receives the second initialization operation signal and performs a second initialization operation; wherein the process of receiving the programming data corresponding to the programming operation and the process of performing the second initialization operation are executed in parallel.

[0050] In some embodiments, the third initialization operation is related to programming data corresponding to the programming operation;

[0051] After the interface circuit receives the programming address corresponding to the programming operation, the operation method further includes:

[0052] The interface circuit receives programming data and programming confirmation commands corresponding to the programming operation;

[0053] The third signal generating circuit sends a third initialization operation signal to the micro control unit after the interface circuit receives the programming confirmation command;

[0054] The micro control unit also receives the third initialization operation signal and performs a third initialization operation.

[0055] In some embodiments, the micro control unit includes a clock signal circuit; the operating method further includes:

[0056] The clock signal circuit outputs a transition of the clock signal during the process that the micro control unit performs the first initialization operation, the second initialization operation and the third initialization operation.

[0057] In some embodiments, in the case of performing two initialization operations, the two initialization operations include a fourth initialization operation and a third initialization operation, and the fourth initialization operation is irrelevant to programming data corresponding to the programming operation; the peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a fourth signal generating circuit and a third signal generating circuit; the operation method further includes:

[0058] The interface circuit receives a programming command and a programming address corresponding to a programming operation;

[0059] The fourth signal generating circuit sends a fourth initialization operation signal to the micro control unit after the interface circuit receives a programming address corresponding to a programming operation;

[0060] The micro control unit receives a fourth initialization operation signal and performs a fourth initialization operation; wherein the process of receiving programming data corresponding to the programming operation and the process of performing the fourth initialization operation are executed in parallel.

[0061] In some embodiments, the third initialization operation is related to programming data corresponding to the programming operation;

[0062] After the interface circuit receives the programming command and programming address corresponding to the programming operation, the operation method further includes:

[0063] The interface circuit also receives programming data and a programming confirmation command corresponding to the programming operation;

[0064] The third signal generating circuit sends a third initialization operation signal to the micro control unit after the interface circuit receives the programming confirmation command;

[0065] The micro control unit receives the third initialization operation signal and performs a third initialization operation.

[0066] In some embodiments, the micro control unit includes a clock signal circuit; the operating method further includes:

[0067] The clock signal circuit outputs a transition of the clock signal during the process that the micro control unit performs the fourth initialization operation and the third initialization operation.

[0068] In a fourth aspect, an embodiment of the present disclosure provides a readable storage medium, wherein the readable storage medium stores a computer program, and when the computer program is executed, the memory operation method as described in the above technical solution can be implemented.

[0069] The embodiment of the present disclosure provides a memory and an operation method thereof, a memory system and a readable storage medium. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit is configured to: receive a programming command, a programming address, a programming data and a programming confirmation command corresponding to a programming operation; after performing at least two initialization operations, perform a programming operation on the memory cell array; wherein the process of receiving the programming command, the programming address, the programming data and the programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations overlap at least partially in time. Compared with performing the initialization operation after receiving the programming command, the programming address, the programming data and the programming confirmation command corresponding to the programming operation, in the embodiment of the present disclosure, the process of receiving the programming command, the programming address, the programming data and the programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations overlap at least partially in time, that is, the process of receiving the programming command, the programming address, the programming data and the programming confirmation command corresponding to the programming operation and the process of performing part of the initialization operation are performed in parallel, so that the impact of the initialization operation on the programming time can be improved, thereby improving the programming performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Figure 1 A timing diagram of an operation method of a memory provided as an example;

[0071] Figure 2 Schematic diagram of a memory provided in an embodiment of the present disclosure Figure 1 ;

[0072] Figure 3 A schematic diagram of a memory including a memory cell array provided for an embodiment of the present disclosure;

[0073] Figure 4 A cross-sectional schematic diagram of a memory cell array including a memory string provided in an embodiment of the present disclosure;

[0074] Figure 5 Schematic diagram of a memory provided in an embodiment of the present disclosure Figure 2 ;

[0075] Figure 6 Schematic diagram of a memory provided in an embodiment of the present disclosure Figure 3 ;

[0076] Figure 7 A timing diagram of an operating method of a memory provided by an embodiment of the present disclosure;

[0077] Figure 8 A schematic diagram of a memory system provided by an embodiment of the present disclosure;

[0078] Fig. 9 A schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0079] Fig. 10A A schematic diagram of a memory card having a memory provided by an embodiment of the present disclosure;

[0080] Fig. 10B A schematic diagram of a solid-state drive with a memory provided for an embodiment of the present disclosure;

[0081] Fig.11 A flowchart of a method for operating a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0083] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0084] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0085] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0086] During the programming operation of a memory (e.g., a NAND memory), initialization operations need to be completed before applying a programming voltage to a memory cell, such as word line voltage bias, bad block detection, temperature detection, and calculation of related voltage and timing parameters. Since these initialization operations are necessary to realize the programming voltage waveform and need to be completed before applying the programming voltage, the programming time occupied by these initialization operations is difficult to be eliminated, thereby greatly affecting the programming performance.

[0087] refer to Figure 1 , Figure 1 The timing diagram of the operation method of the memory provided as an example. Figure 1 As shown, during the programming operation of the memory, the input type (Cycle Type) includes a programming command (Command, CMD), a programming address (Address, ADDR), programming data (Data in, DIN) and a programming confirmation command (CMD). Correspondingly, the memory chip has an input / output pin DQ[7:0] that receives the programming command (i.e., 80h), the programming address (including column addresses C1 and C2, row addresses R1, R2, R3 and R4), the programming data (including D0 to Dn) and the programming confirmation command (i.e., 10h) in sequence. The chip pin R / B_n that monitors the state of the memory chip includes a low level state and a high level state, wherein the low level state means that the memory chip is in a busy state. Figure 1 It also illustrates the time interval from inputting the programming address to inputting the programming data (Address Cycle to Data Loading time, tADL); the time interval from receiving the programming confirmation command to R / B_n being pulled down to a low level (ie, tWB) and the programming operation time (ie, tPROG).

[0088] like Figure 1As shown, the memory (for example, NAND type memory) includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit includes an interface circuit (NAND Interface, NAND_IF) and a microcontroller unit (Microcontroller Unit, MCU). The interface circuit receives the programming command (command), programming address (address) and programming data (data in) in sequence, and parses the programming command and programming address therein; after receiving the programming confirmation command (command), the interface circuit triggers (trigger) the microcontroller unit to execute the firmware (Firmmare) of the programming algorithm, thereby performing a programming operation on the memory cell array. After being triggered, the firmware of the programming algorithm first performs an initialization operation (initialize), and the initialization operation mainly includes word line voltage bias, bad block detection, temperature detection and calculation of related voltage and timing parameters, as well as processing related to user programming data, such as data preprocessing, data transmission, etc. After the initialization operation is completed, the programming operation begins, and the programming pulse (prog pulse) / verification (verify) is performed sequentially according to the Incremental Step Pulse Program (ISPP) principle until all memory cells reach the target threshold voltage required for the programming state.

[0089] From the above analysis, we can see that Figure 1 In the example of FIG. 1 , an initialization operation is performed after receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation. Only after the initialization operation is completed can the programming-verification operation be performed. In this way, the programming time occupied by the initialization operation is difficult to eliminate, thereby greatly affecting the programming performance.

[0090] In view of this, embodiments of the present disclosure provide a memory and an operating method thereof, a memory system, and a readable storage medium.

[0091] refer to Figure 2 , Figure 2 Schematic diagram of a memory provided in an embodiment of the present disclosure Figure 1 .like Figure 2 As shown, an embodiment of the present disclosure provides a memory 100, which includes a memory cell array 102 and a peripheral circuit 104 coupled to the memory cell array 102; the peripheral circuit 104 is configured as follows:

[0092] receiving a programming command, a programming address, programming data and a programming confirmation command corresponding to a programming operation;

[0093] After performing at least two initialization operations, a programming operation is performed on the memory cell array 102; wherein the process of receiving a programming command, a programming address, programming data and a programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations at least partially overlap in time.

[0094] In the embodiment of the present disclosure, the process of receiving the programming command, programming address, programming data and programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations at least partially overlap in time, that is, the process of receiving the programming command, programming address, programming data and programming confirmation command corresponding to the programming operation and the process of performing some initialization operations are executed in parallel. In this way, the impact of the initialization operation on the programming time can be improved, thereby improving the programming performance.

[0095] Exemplarily, after performing three initialization operations, the memory cell array is programmed. The three initialization operations include a first initialization operation, a second initialization operation, and a third initialization operation, wherein the process of receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation and the process of performing the first initialization operation and the second initialization operation overlap at least partially in time. In other words, the process of receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation and the process of performing the first initialization operation and the second initialization operation are performed in parallel. In this way, the impact of the initialization operation on the programming time can be improved, thereby improving the programming performance.

[0096] Exemplarily, after performing two initialization operations, the memory cell array is programmed. The three initialization operations include a fourth initialization operation and a third initialization operation, wherein the process of receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation and the process of performing the fourth initialization operation overlap at least partially in time. In other words, the process of receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation and the process of performing the fourth initialization operation are performed in parallel. In this way, the impact of the initialization operation on the programming time can be improved, thereby improving the programming performance.

[0097] refer to Figure 3 , Figure 3 A schematic diagram of a memory including a memory cell array provided in an embodiment of the present disclosure. Figure 3 As shown, the memory 100 may include a memory cell array 102 and a peripheral circuit 104 coupled to the memory cell array 102. The memory cell array 102 may be a NAND flash memory cell array, wherein the memory cells 108 are provided in the form of an array of memory strings 110, each memory string 110 being formed on a substrate ( Figure 3In some embodiments, each memory string 110 includes a plurality of memory cells 108 coupled in series and stacked vertically. Each memory cell 108 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 108. Each memory cell 108 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0098] In some embodiments, each memory cell 108 may be a single-level cell (SLC) having two possible storage states and thus may store one bit of data. For example, an SLC may have a first storage state "1" and a second storage state "0", where the threshold voltage distribution of the first storage state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second storage state "0" may correspond to a second voltage range. The first storage state is an erased state, and the second storage state is a programmed state. In some embodiments, each memory cell 108 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a triple-level cell (TLC)), or four bits of data per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC may have a first storage state "11", a second storage state "10", a third storage state "01", and a fourth storage state "00", where the threshold voltage distributions of the first, second, third, and fourth storage states correspond to the first, second, third, and fourth voltage ranges, respectively. The first storage state is an erased state, and the second, third, and fourth storage states are all programmed states. Similarly, TLC may have 8 storage states, including an erased state and 7 programmed states; QLC may have 16 storage states, including an erased state and 15 programmed states.

[0099] like Figure 3As shown, each memory string 110 may include a source select transistor (Source Selective Transistor, SST) 112 at its source terminal and a drain select transistor (Drain Selective Transistor, DST) 114 at its drain terminal. The source select transistor 112 and the drain select transistor 114 may be configured to activate the selected memory string 110 (column of the array) during read and program operations. In some embodiments, the sources of the memory strings 110 in the same memory block 106 are coupled through the same source line (Source Line, SL) 116 (e.g., a common SL). In other words, in some embodiments, all memory strings 110 in the same memory block (Block) 106 have an array common source (Array Common Source, ACS). In some embodiments, the drain of the drain select transistor 114 of each memory string 110 is coupled to a corresponding bit line (Bit Line, BL) 122, which may be connected via an output bus ( Figure 3 In some embodiments, each memory string 110 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the drain select transistor 114) or a deselection voltage (e.g., 0V) to the corresponding drain select transistor 114 via one or more drain select gate lines (DSL) 120 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the source select transistor 112) or a deselection voltage (e.g., 0V) to the corresponding source select transistor 112 via one or more source select gate lines (SSL) 118.

[0100] like Figure 3As shown, the memory string 110 can be organized into a plurality of memory blocks 106, each of which can have a source line 116 (e.g., a common SL coupled to ground). In some embodiments, each memory block 106 is a basic unit for an erase operation, that is, all memory cells 108 on the same memory block 106 are erased at the same time. In order to erase the memory cells 108 in a selected memory block, the source lines 116 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 108 of adjacent memory strings 110 can be coupled by word lines 124, which select which row of memory cells 108 is affected by the read and program operations. In some embodiments, each word line 124 is coupled to a memory page 126 of memory cells 108. Each word line 124 may include a plurality of control gates (gate electrodes) at each memory cell 108 in a corresponding memory page 126 and a gate line coupling the control gates.

[0101] It should be noted that Figure 3 The illustrated storage page is a physical page, which refers to a layer of storage cells on the physical level. The basic data unit for programming and reading operations is a logical page. For SLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 1 logical page. For MLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 2 logical pages. For TLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 3 logical pages. For QLC, each storage cell can store 1 bit of information, so that the information stored in one layer of storage cells (i.e., 1 physical page) on the physical level corresponds to the information of 4 logical pages.

[0102] refer to Figure 4 , Figure 4 A cross-sectional schematic diagram of a memory cell array including a memory string provided in an embodiment of the present disclosure. Figure 4As shown, the memory string 110 may extend vertically through the memory stack layer 130 above the substrate 128. The substrate 128 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0103] The memory stack 130 may include alternating gate conductive layers 132 and gate dielectric layers 134. The number of pairs of gate conductive layers 132 and gate dielectric layers 134 in the memory stack 130 may determine the number of memory cells 108 in the memory cell array 102. The gate conductive layers 132 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 132 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 132 includes a doped polysilicon layer. Each gate conductive layer 132 may include a control gate surrounding the memory cell 108 and may extend laterally at the top of the memory stack 130 as a drain select gate line 120, at the bottom of the memory stack 130 as a source select gate line 118, or between the drain select gate line 120 and the source select gate line 118 as a word line 124.

[0104] like Figure 4 As shown, the memory string 110 includes a channel structure extending vertically through the memory stack layer 130. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a memory layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the memory layer, and the barrier layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0105] According to some embodiments, a well (e.g., a P-well and / or an N-well) may be formed in substrate 128, and the source terminal of memory string 110 may contact the well. For example, a source line may be coupled to the well to apply an erase voltage to the well (i.e., the source of the memory string) during an erase operation. In some embodiments, the memory string further includes a channel plug at the drain terminal of memory string 110. It should be understood that although in Figure 4 Not shown, but additional components of the memory cell array 102 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0106] Return to reference Figure 3 , the peripheral circuit 104 may be coupled to the memory cell array 102 via the bit lines 122, the word lines 124, the source lines 116, the source select gate lines 118, and the drain select gate lines 120. The peripheral circuit 104 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 102 by applying a voltage signal and / or a current signal to each target memory cell 108 and sensing a voltage signal and / or a current signal from each target memory cell 108 via the bit lines 122, the word lines 124, the source lines 116, the source select gate lines 118, and the drain select gate lines 120. The peripheral circuit 104 may include various types of peripheral circuits formed using Metal Oxide Semiconductor (MOS) technology.

[0107] refer to Figure 5 , Figure 5 Schematic diagram of a memory provided in an embodiment of the present disclosure Figure 2 The following will combine Figure 5 , describes in detail the process of programming the memory cell array after performing three initialization operations.

[0108] like Figure 5 As shown, an embodiment of the present disclosure provides a memory 100, which includes a memory cell array 102 and a peripheral circuit 104 coupled to the memory cell array 102; the peripheral circuit 104 includes an interface circuit 136 and a micro control unit 138, and the interface circuit 136 includes a first signal generating circuit 140, a second signal generating circuit 142 and a third signal generating circuit 144.

[0109] In the embodiment of the present disclosure, when three initialization operations are performed, the three initialization operations include a first initialization operation, a second initialization operation, and a third initialization operation. The first initialization operation has nothing to do with the programming address and programming data corresponding to the programming operation; the second initialization operation is related to the programming address corresponding to the programming operation and has nothing to do with the programming data corresponding to the programming operation; the third initialization operation is related to the programming data corresponding to the programming operation.

[0110] Specifically, the first initialization operation and the programming address and programming data corresponding to the programming operation are irrelevant, which means that the programming address and programming data corresponding to the programming operation do not need to be used during the first initialization operation. In other words, after the interface circuit receives the programming command, the first initialization operation can be started. Exemplarily, the first initialization operation may include a temperature detection operation.

[0111] Specifically, the second initialization operation is related to the programming address corresponding to the programming operation and is not related to the programming data corresponding to the programming operation, which means that the programming address corresponding to the programming operation needs to be used during the second initialization operation, and the programming data corresponding to the programming operation does not need to be used. In other words, after the interface circuit receives the programming command and the programming address, the second initialization operation can be started. Exemplarily, the second initialization operation may include a word line voltage bias operation and a bad block detection operation.

[0112] Specifically, the third initialization operation is related to the programming data corresponding to the programming operation, which means that the programming data corresponding to the programming operation needs to be used during the third initialization operation. In other words, after the interface circuit receives the programming command, programming address, programming data, and programming confirmation command, the third initialization operation can be started. Exemplarily, the third initialization operation may include data preprocessing, data transmission, etc.

[0113] In some embodiments, when three initialization operations are performed, the three initialization operations include a first initialization operation, a second initialization operation, and a third initialization operation, and the programming address and programming data corresponding to the first initialization operation and the programming operation are irrelevant;

[0114] The interface circuit 136 is configured to: receive a programming command and a programming address corresponding to a programming operation;

[0115] The first signal generating circuit 140 is configured to: send a first initialization operation signal to the micro control unit 138 after the interface circuit 136 receives a programming command corresponding to a programming operation;

[0116] The micro control unit 138 is configured to: receive a first initialization operation signal and perform a first initialization operation; wherein the process of receiving a programming address corresponding to the programming operation and the process of performing the first initialization operation are executed in parallel.

[0117] like Figure 5 As shown, after the interface circuit 136 receives the programming command corresponding to the programming operation, it can trigger the first signal generating circuit 140 to generate a first initialization operation signal, and the first signal generating circuit 140 sends the first initialization operation signal to the micro control unit 138; the micro control unit 138 receives the first initialization operation signal and performs a first initialization operation; wherein, the process of the interface circuit 136 receiving the programming address corresponding to the programming operation and the process of the micro control unit 138 performing the first initialization operation overlap in time.

[0118] In some embodiments, the second initialization operation is related to a programming address corresponding to the programming operation and is not related to programming data corresponding to the programming operation;

[0119] The interface circuit 136 is further configured to: receive a programming address and programming data corresponding to a programming operation;

[0120] The second signal generating circuit 142 is configured to: send a second initialization operation signal to the micro control unit 138 after the interface circuit 136 receives the programming address corresponding to the programming operation;

[0121] The micro control unit 138 is further configured to: receive a second initialization operation signal and perform a second initialization operation; wherein the process of receiving the programming data corresponding to the programming operation and the process of performing the second initialization operation are executed in parallel.

[0122] like Figure 5 As shown, after the interface circuit 136 receives the programming address corresponding to the programming operation, it can trigger the second signal generating circuit 142 to generate a second initialization operation signal, and the second signal generating circuit 142 sends the second initialization operation signal to the micro control unit 138; the micro control unit 138 receives the second initialization operation signal and performs a second initialization operation; wherein, the process of the interface circuit 136 receiving the programming data corresponding to the programming operation and the process of the micro control unit 138 performing the second initialization operation overlap in time.

[0123] In some embodiments, the third initialization operation is related to programming data corresponding to the programming operation;

[0124] The interface circuit 136 is further configured to: receive programming data and a programming confirmation command corresponding to the programming operation;

[0125] The third signal generating circuit 144 is configured to: send a third initialization operation signal to the micro control unit 138 after the interface circuit 136 receives the program confirmation command;

[0126] The micro control unit 138 is further configured to receive a third initialization operation signal and perform a third initialization operation.

[0127] like Figure 5 As shown, after the interface circuit 136 receives the programming confirmation command corresponding to the programming operation, it can trigger the third signal generating circuit 144 to generate the second initialization operation signal, and the third signal generating circuit 144 sends the third initialization operation signal to the micro control unit 138; the micro control unit 138 receives the third initialization operation signal and performs the third initialization operation. After completing the first initialization operation, the second initialization operation and the third initialization operation, the programming-verification operation can be performed.

[0128] It should be noted that the process of the microcontroller performing the first initialization operation and the process of the interface circuit receiving the programming address corresponding to the programming operation overlap in time, the process of the microcontroller performing the second initialization operation and the process of the interface circuit receiving the programming data corresponding to the programming operation overlap in time, and after the microcontroller performs the third initialization operation, the programming-verification operation can be performed. In this way, the process of the microcontroller performing the first initialization operation and the second initialization operation and the process of the interface circuit receiving the programming address and programming data corresponding to the programming operation are executed in parallel, which can effectively reduce the time for the microcontroller to perform the initialization operation before performing the programming-verification operation; more specifically, the duration of the microcontroller performing the initialization operation is reduced from the sum of the durations of the first initialization operation, the second initialization operation and the third initialization operation to the duration of the third initialization operation. Therefore, the impact of the initialization operation on the programming time can be improved, thereby improving the programming performance.

[0129] In some embodiments, the microcontroller unit 138 includes a clock signal circuit;

[0130] The clock signal circuit is configured to output a transition of the clock signal during the process that the micro control unit 138 performs the first initialization operation, the second initialization operation, and the third initialization operation.

[0131] Here, the microcontroller unit can operate based on a clock signal circuit, the clock signal circuit can output a clock signal, output a transition of the clock signal in the clock signal in response to a clock enable signal, and prohibit outputting a transition of the clock signal in the clock signal in response to a clock disable signal. Wherein, the transition of the clock signal refers to the process of switching the clock signal from a low level state to a high level state, and from a high level state to a low level state.

[0132] Specifically, during the process of the microcontroller performing the first initialization operation, the second initialization operation, and the third initialization operation, the clock signal circuit will output the change of the clock signal. In addition, during the process of the microcontroller performing the programming-verification operation, the clock signal circuit will also output the change of the clock signal. Correspondingly, during the process of the interface circuit receiving the programming address corresponding to the programming operation, the microcontroller performs the first initialization operation, at which time, the clock signal circuit will output the change of the clock signal. During the process of the interface circuit receiving the programming data corresponding to the programming operation, the microcontroller performs the second initialization operation, at which time, the clock signal circuit will output the change of the clock signal. After the interface circuit receives the programming confirmation command corresponding to the programming operation, the microcontroller performs the third initialization operation and the programming-verification operation, at which time, the clock signal circuit will output the change of the clock signal.

[0133] refer to Figure 6 , Figure 6 Schematic diagram of a memory provided in an embodiment of the present disclosure Figure 3 . refer to Figure 7 , Figure 7 The timing diagram of the operation method of the memory provided by the embodiment of the present disclosure is as follows. Figure 6 and Figure 7 , describes in detail the process of programming the memory cell array after performing two initialization operations.

[0134] like Figure 6 As shown, an embodiment of the present disclosure provides a memory 100, which includes a memory cell array 102 and a peripheral circuit 104 coupled to the memory cell array 102; the peripheral circuit 104 includes an interface circuit 136 and a micro control unit 138, and the interface circuit 136 includes a fourth signal generating circuit 146 and a third signal generating circuit 144.

[0135] In the embodiment of the present disclosure, when two initialization operations are performed, the two initialization operations include a fourth initialization operation and a third initialization operation. The fourth initialization operation is irrelevant to the programming data corresponding to the programming operation; the third initialization operation is relevant to the programming data corresponding to the programming operation.

[0136] Specifically, the fourth initialization operation is independent of the programming data corresponding to the programming operation, which means that the programming address corresponding to the programming operation needs to be used in the process of performing the fourth initialization operation, and the programming data corresponding to the programming operation does not need to be used. In other words, after the interface circuit receives the programming command and the programming address, the fourth initialization operation can be started. The fourth initialization operation includes a first initialization operation that is independent of the programming address and programming data corresponding to the programming operation, and a second initialization operation that is related to the programming address corresponding to the programming operation and is independent of the programming data corresponding to the programming operation. Exemplarily, the fourth initialization operation includes a temperature detection operation, a word line voltage bias operation, and a bad block detection operation.

[0137] Specifically, the third initialization operation is related to the programming data corresponding to the programming operation, which means that the programming data corresponding to the programming operation needs to be used during the third initialization operation. In other words, after the interface circuit receives the programming command, programming address, programming data, and programming confirmation command, the third initialization operation can be started. Exemplarily, the third initialization operation may include data preprocessing, data transmission, etc.

[0138] In some embodiments, when two initialization operations are performed, the two initialization operations include a fourth initialization operation and a third initialization operation, and the fourth initialization operation is irrelevant to programming data corresponding to the programming operation;

[0139] The interface circuit 136 is configured to: receive a programming command, a programming address, and programming data corresponding to a programming operation;

[0140] The fourth signal generating circuit 146 is configured to: send a fourth initialization operation signal to the micro control unit 138 after the interface circuit 136 receives the programming address corresponding to the programming operation;

[0141] The micro control unit 138 is configured to: receive a fourth initialization operation signal and perform a fourth initialization operation; wherein the process of receiving the programming data corresponding to the programming operation and the process of performing the fourth initialization operation are executed in parallel.

[0142] like Figure 6 As shown, after the interface circuit 136 receives the programming command and programming address corresponding to the programming operation, it can trigger the fourth signal generating circuit 146 to generate a fourth initialization operation signal, and the fourth signal generating circuit 146 sends the fourth initialization operation signal to the micro control unit 138; the micro control unit 138 receives the fourth initialization operation signal and performs the fourth initialization operation (such as Figure 7 wherein the process of the interface circuit 136 receiving the programming data corresponding to the programming operation and the process of the micro control unit 138 performing the fourth initialization operation overlap in time.

[0143] Figure 7 It is shown that the interface circuit (i.e., NAND_IF) triggers the generation of the fourth initialization operation signal after receiving the row address R4, and the micro control unit receives the fourth initialization operation signal and performs the fourth initialization operation; at the same time, the interface circuit continues to receive the programming data corresponding to the programming operation. Since the interface circuit takes a long time to receive the programming data corresponding to the programming operation, the micro control unit enters an idle state after performing the fourth initialization operation to wait for the input process of the programming data to be completed.

[0144] In some embodiments, the third initialization operation is related to programming data corresponding to the programming operation;

[0145] The interface circuit 136 is further configured to: receive programming data and a programming confirmation command corresponding to the programming operation;

[0146] The third signal generating circuit 144 is configured to: send a third initialization operation signal to the micro control unit 138 after the interface circuit 136 receives the program confirmation command;

[0147] The micro control unit 138 is further configured to receive a third initialization operation signal and perform a third initialization operation.

[0148] like Figure 6 and Figure 7 As shown, after the interface circuit 136 receives the programming confirmation command corresponding to the programming operation, it can trigger the third signal generating circuit 144 to generate a second initialization operation signal, and the third signal generating circuit 144 sends the third initialization operation signal to the micro control unit 138; the micro control unit 138 receives the third initialization operation signal and performs the third initialization operation (such as Figure 7 After the fourth initialization operation and the third initialization operation are completed, a program-verification operation may be performed.

[0149] It should be noted that the process of the microcontroller performing the fourth initialization operation and the process of the interface circuit receiving the programming data corresponding to the programming operation overlap in time, and the microcontroller can perform the programming-verification operation after performing the third initialization operation. In this way, the process of the microcontroller performing the fourth initialization operation and the process of the interface circuit receiving the programming data corresponding to the programming operation are executed in parallel, which can effectively reduce the time for the microcontroller to perform the initialization operation before performing the programming-verification operation; more specifically, the duration of the microcontroller performing the initialization operation is reduced from the sum of the duration of the fourth initialization operation and the third initialization operation to the duration of the third initialization operation. Therefore, the impact of the initialization operation on the programming time can be improved, thereby improving the programming performance.

[0150] In some embodiments, the microcontroller unit 138 includes a clock signal circuit;

[0151] The clock signal circuit is configured to output a transition of the clock signal during the process that the micro control unit performs the fourth initialization operation and the third initialization operation.

[0152] like Figure 7 As shown, during the process of the microcontroller unit performing the fourth initialization operation and the third initialization operation, the clock signal circuit (i.e., MCU CLK) will output the change of the clock signal. In addition, during the process of the microcontroller unit performing the programming-verification operation, the clock signal circuit will also output the change of the clock signal. Correspondingly, during the process of the interface circuit receiving the programming data corresponding to the programming operation, the microcontroller unit performs the fourth initialization operation, at which time, the clock signal circuit will output the change of the clock signal. After the interface circuit receives the programming confirmation command corresponding to the programming operation, the microcontroller unit performs the third initialization operation and the programming-verification operation, at which time, the clock signal circuit will output the change of the clock signal.

[0153] In the above technical solution, part of the program that is not related to the user programming data is transferred to the preprocessing subroutine, that is, in the process of the interface circuit receiving the programming data corresponding to the programming operation, the microcontroller unit performs the fourth initialization operation, and the fourth initialization operation mainly includes word line voltage bias, bad block detection, temperature detection and voltage / timing parameter calculation. The execution of the preprocessing subroutine (that is, the fourth initialization operation) can be triggered after the user inputs the programming address corresponding to the programming operation. The execution of the preprocessing subroutine is executed in parallel with the input process of the programming data corresponding to the user programming operation, which can improve the influence of the time occupied by the partial initialization operation on the programming performance.

[0154] In the disclosed embodiment, a signal generating circuit is added to the interface circuit to change the execution timing and number of initialization operations. In the case of three initialization operations, the microcontroller unit can perform the first initialization operation and the second initialization operation respectively during the process of the interface circuit receiving the programming address and programming data corresponding to the programming operation; after the interface circuit receives the programming confirmation command, the microcontroller unit performs the third initialization operation. In the case of two initialization operations, the microcontroller unit can perform the fourth initialization operation during the process of the interface circuit receiving the programming data corresponding to the programming operation; after the interface circuit receives the programming confirmation command, the microcontroller unit performs the third initialization operation. In this way, the programming performance of the memory can be optimized without significantly increasing the area and cost of the memory chip.

[0155] In addition, whether to use the memory operation method provided by the embodiment of the present disclosure may be detected based on the execution timing of the initialization operation.

[0156] Exemplarily, whether to use the memory operation method provided by the embodiment of the present disclosure can be determined by detecting whether the clock signal circuit of the microcontroller outputs a change in the clock signal during the process of the interface circuit receiving the programming address and programming data corresponding to the programming operation. If the clock signal circuit of the microcontroller outputs a change in the clock signal during the process of the interface circuit receiving the programming address and programming data corresponding to the programming operation, it can be detected that the microcontroller is performing the first initialization operation and the second initialization operation. If the clock signal circuit of the microcontroller outputs a change in the clock signal during the process of the interface circuit receiving the programming data corresponding to the programming operation, it can be detected that the microcontroller is performing the fourth initialization operation.

[0157] Similarly, during the process of the interface circuit receiving the programming address and programming data corresponding to the programming operation, it can be determined whether to use the memory and its operation method provided by the embodiment of the present disclosure by detecting whether the register of the microcontroller unit is flipped. The relevant voltage / timing parameters are calculated by the transition of the clock signal output by the clock signal circuit and the register flip. The calculation of the specific voltage / timing parameters can be flexibly selected according to the actual situation, which will not be repeated here.

[0158] For example, in the word line bias voltage operation, although the bias voltage is not directly transmitted to the word line, the word line bias voltage is transmitted to the bias switch array. In the process of the interface circuit receiving the programming data corresponding to the programming operation, the voltage fluctuation of the bias switch array can be detected to determine whether to use the operation method of the memory provided by the embodiment of the present disclosure. If the voltage of the bias switch array can be detected (that is, the bias switch array is turned on) in the process of the interface circuit receiving the programming data corresponding to the programming operation, this indicates that the micro control unit is performing the second initialization operation or the fourth initialization operation.

[0159] Exemplarily, the bad block exists in the latch of the row decoder connected to the word line, and "1" is stored in the latch detected as a bad block, and "0" is stored in the latch detected as not a bad block. In the process of the interface circuit receiving the programming data corresponding to the programming operation, the read signal of the latch can be detected to determine whether to use the operation method of the memory provided by the embodiment of the present disclosure. If the read signal of the latch can be detected as "1" in the process of the interface circuit receiving the programming data corresponding to the programming operation, this indicates that the microcontroller unit has performed the second initialization operation or the fourth initialization operation, and the result of executing the bad block detection operation is stored in the latch.

[0160] For example, during the process of the interface circuit receiving the programming command, programming address and programming data corresponding to the programming operation, a reset command can be sent immediately after the process of the interface circuit receiving the programming data corresponding to the programming operation is completed to read the temperature of the temperature sensor. The temperature of the temperature sensor read at this time is compared with the temperature of the sensor before the interface circuit receives the programming command corresponding to the programming operation. If the sensor problem read twice is different, this indicates that the temperature detection (i.e., the first initialization operation or the fourth initialization operation) has been performed during the process of the interface circuit receiving the programming command, programming address and programming data corresponding to the programming operation.

[0161] In addition, the location of the microcontroller unit can be determined by observing the location of structures such as static random access memory (SRAM) and read-only memory (ROM) on the layout. The bias switch array has a large number of repeated structures, and the location of the bias switch array can also be found by observing it on the layout.

[0162] refer to Figure 8 , Figure 8 Schematic diagram of a memory system provided by an embodiment of the present disclosure. Figure 8 As shown, an embodiment of the present disclosure provides a memory system, and the above-mentioned memory system 200 includes: at least one memory 100 as described in the above-mentioned technical solution; and a controller 202 coupled to the memory 100 and configured to control the memory 100.

[0163] In some embodiments, the controller 202 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0164] In some embodiments, the controller 202 is designed to operate in a high duty cycle environment SSD or embedded Multi-Media Card (eMMC), which is used as data storage for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0165] The controller 202 may be configured to control the operation of the memory 100, such as read, erase, and program operations. The controller 202 may also be configured to manage various functions regarding data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical address to physical address conversion, wear leveling, etc. In some embodiments, the controller 202 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 100.

[0166] The controller 202 may also perform any other suitable functions, such as formatting the memory 100. The controller 202 may communicate with an external device (e.g., the host 302) according to a specific communication protocol. For example, the controller 202 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0167] The controller 202 and one or more memories 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash storage (UFS) package or eMMC package). That is, the memory system 200 can be implemented and packaged into different types of terminal electronic products.

[0168] refer to Fig. 9 , Fig. 9 Schematic diagram of an electronic device provided by an embodiment of the present disclosure. Fig. 9 As shown, an embodiment of the present disclosure provides an electronic device 300 , which includes: a memory system 200 as in the above technical solution; and a host 302 coupled to the memory system 200 .

[0169] In some embodiments, the electronic device 300 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0170] like Fig. 9 As shown, the electronic device 300 may include a host 302 and a memory system 200, wherein the memory system 200 has one or more memories 100 and a controller 202. The host 302 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host 302 may be configured to send data to the memory 100 or receive data from the memory 100.

[0171] In some embodiments, the controller 202 is coupled to the memory 100 and the host 302, and is configured to control the memory 100. The controller 202 may manage data stored in the memory 100, and communicate with the host 302.

[0172] refer to Fig. 10A , Fig. 10A Schematic diagram of a memory card with a memory provided by an embodiment of the present disclosure. Fig. 10A As shown, the controller 202 and the single memory 100 may be integrated into a memory card 204. The memory card 204 may include a Personal Computer Memory Card International Association (PCMCIA) card, a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro), an SD (e.g., SD, miniSD, microSD, SDHC) card, UFS, etc. The memory card 204 may also include a processor that connects the memory card 204 to a host (e.g., Fig. 9 A memory card connector 206 coupled to a host 302 in the memory card module.

[0173] refer to Fig. 10B , Fig. 10B A schematic diagram of a solid-state drive with a memory provided by an embodiment of the present disclosure. Fig. 10B As shown, the controller 202 and the plurality of memories 100 may be integrated into a solid-state drive 208. The solid-state drive 208 may also include a computer that connects the solid-state drive 208 to a host (e.g., Fig. 9 The solid-state drive connector 210 is coupled to the host 302 in the memory card. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 208 is greater than the storage capacity and / or operating speed of the memory card 204.

[0174] refer to Fig.11 , Fig.11 The flowchart of the operation method of the memory provided by the embodiment of the present disclosure is as follows. Fig.11 As shown, an embodiment of the present disclosure provides an operating method of a memory, wherein the memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the operating method includes:

[0175] Step S1101: receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to a programming operation;

[0176] Step S1102: After performing at least two initialization operations, perform a programming operation on the memory cell array; wherein the process of receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations at least partially overlap in time.

[0177] In the embodiment of the present disclosure, the process of receiving the programming command, programming address, programming data and programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations at least partially overlap in time, that is, the process of receiving the programming command, programming address, programming data and programming confirmation command corresponding to the programming operation and the process of performing some initialization operations are executed in parallel. In this way, the impact of the initialization operation on the programming time can be improved, thereby improving the programming performance.

[0178] In some embodiments, when performing three initialization operations, the three initialization operations include a first initialization operation, a second initialization operation, and a third initialization operation, and the programming address and programming data corresponding to the first initialization operation and the programming operation are unrelated; the peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a first signal generating circuit, a second signal generating circuit, and a third signal generating circuit; the operation method includes:

[0179] The interface circuit receives a programming command corresponding to the programming operation;

[0180] The first signal generating circuit sends a first initialization operation signal to the micro control unit after the interface circuit receives a programming command corresponding to the programming operation;

[0181] The micro control unit receives a first initialization operation signal and performs a first initialization operation; wherein the process of receiving a programming address corresponding to the programming operation and the process of performing the first initialization operation are executed in parallel.

[0182] In some embodiments, the second initialization operation is related to a programming address corresponding to the programming operation and is not related to programming data corresponding to the programming operation;

[0183] After the interface circuit receives the programming command corresponding to the programming operation, the operation method further includes:

[0184] The interface circuit receives a programming address corresponding to a programming operation;

[0185] The second signal generating circuit sends a second initialization operation signal to the micro control unit after the interface circuit receives the programming address corresponding to the programming operation;

[0186] The micro control unit receives the second initialization operation signal and performs a second initialization operation; wherein the process of receiving the programming data corresponding to the programming operation and the process of performing the second initialization operation are executed in parallel.

[0187] In some embodiments, the third initialization operation is related to programming data corresponding to the programming operation;

[0188] After the interface circuit receives the programming address corresponding to the programming operation, the operation method further includes:

[0189] The interface circuit receives programming data and programming confirmation commands corresponding to the programming operation;

[0190] The third signal generating circuit sends a third initialization operation signal to the micro control unit after the interface circuit receives the programming confirmation command;

[0191] The micro control unit also receives a third initialization operation signal and performs a third initialization operation.

[0192] In some embodiments, the micro control unit includes a clock signal circuit; the operating method further includes:

[0193] The clock signal circuit outputs the transition of the clock signal during the process that the micro control unit performs the first initialization operation, the second initialization operation and the third initialization operation.

[0194] In some embodiments, in the case of performing two initialization operations, the two initialization operations include a fourth initialization operation and a third initialization operation, and the fourth initialization operation is irrelevant to programming data corresponding to the programming operation; the peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a fourth signal generating circuit and a third signal generating circuit; the operation method further includes:

[0195] The interface circuit receives a programming command and a programming address corresponding to a programming operation;

[0196] The fourth signal generating circuit sends a fourth initialization operation signal to the micro control unit after the interface circuit receives the programming address corresponding to the programming operation;

[0197] The micro control unit receives a fourth initialization operation signal and performs a fourth initialization operation; wherein the process of receiving programming data corresponding to the programming operation and the process of performing the fourth initialization operation are executed in parallel.

[0198] In some embodiments, the third initialization operation is related to programming data corresponding to the programming operation;

[0199] After the interface circuit receives the programming command and programming address corresponding to the programming operation, the operation method further includes:

[0200] The interface circuit also receives programming data and programming confirmation commands corresponding to the programming operation;

[0201] The third signal generating circuit sends a third initialization operation signal to the micro control unit after the interface circuit receives the programming confirmation command;

[0202] The micro control unit receives the third initialization operation signal and performs a third initialization operation.

[0203] In some embodiments, the micro control unit includes a clock signal circuit; the operating method further includes:

[0204] The clock signal circuit outputs a transition of the clock signal during the process that the micro control unit performs the fourth initialization operation and the third initialization operation.

[0205] An embodiment of the present disclosure provides a readable storage medium, which stores a computer program. When the computer program is executed, the memory operation method in the above technical solution can be implemented.

[0206] In the embodiments of the present disclosure, the computer-readable storage medium may include: random access memory (Random Access Memory, RAM), memory, ROM, electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, read-only compact disks (CD-ROMs), or any other form of program code medium known in the technical field.

[0207] The embodiment of the present disclosure provides a memory and an operation method thereof, a memory system and a readable storage medium. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit is configured to: receive a programming command, a programming address, a programming data and a programming confirmation command corresponding to a programming operation; after performing at least two initialization operations, perform a programming operation on the memory cell array; wherein the process of receiving the programming command, the programming address, the programming data and the programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations overlap at least partially in time. Compared with performing the initialization operation after receiving the programming command, the programming address, the programming data and the programming confirmation command corresponding to the programming operation, in the embodiment of the present disclosure, the process of receiving the programming command, the programming address, the programming data and the programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations overlap at least partially in time, that is, the process of receiving the programming command, the programming address, the programming data and the programming confirmation command corresponding to the programming operation and the process of performing part of the initialization operation are performed in parallel, so that the impact of the initialization operation on the programming time can be improved, thereby improving the programming performance.

[0208] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0209] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory, characterized in that: The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit is configured as follows: receiving a programming command, a programming address, programming data and a programming confirmation command corresponding to a programming operation; After performing at least two initialization operations, a programming operation is performed on the memory cell array; wherein the process of receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations at least partially overlap in time.

2. The memory according to claim 1, characterized in that: In the case of performing three initialization operations, the three initialization operations include a first initialization operation, a second initialization operation, and a third initialization operation, and the programming address and programming data corresponding to the first initialization operation and the programming operation are irrelevant; the peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a first signal generating circuit, a second signal generating circuit, and a third signal generating circuit; The interface circuit is configured to: receive a programming command and a programming address corresponding to a programming operation; The first signal generating circuit is configured to: send a first initialization operation signal to the micro control unit after the interface circuit receives a programming command corresponding to a programming operation; The micro control unit is configured to: receive the first initialization operation signal and perform a first initialization operation; wherein the process of receiving a programming address corresponding to a programming operation and the process of performing the first initialization operation are executed in parallel.

3. The memory according to claim 2, characterized in that: The second initialization operation is related to a programming address corresponding to the programming operation and is unrelated to programming data corresponding to the programming operation; The interface circuit is further configured to: receive a programming address and programming data corresponding to a programming operation; The second signal generating circuit is configured to: send a second initialization operation signal to the micro control unit after the interface circuit receives a programming address corresponding to a programming operation; The micro control unit is further configured to: receive the second initialization operation signal and perform a second initialization operation; wherein the process of receiving the programming data corresponding to the programming operation and the process of performing the second initialization operation are executed in parallel.

4. The memory according to claim 3, characterized in that: The first initialization operation includes a temperature detection operation; the second initialization operation includes a word line voltage bias operation and a bad block detection operation.

5. The memory according to claim 3, characterized in that: The third initialization operation is related to the programming data corresponding to the programming operation; The interface circuit is further configured to: receive programming data and a programming confirmation command corresponding to the programming operation; The third signal generating circuit is configured to: send a third initialization operation signal to the micro control unit after the interface circuit receives the programming confirmation command; The micro control unit is further configured to: receive the third initialization operation signal and perform a third initialization operation.

6. The memory according to claim 5, characterized in that: The micro control unit includes a clock signal circuit; The clock signal circuit is configured to output a transition of the clock signal during the process that the micro control unit performs the first initialization operation, the second initialization operation and the third initialization operation.

7. The memory according to claim 1, characterized in that: In the case of performing two initialization operations, the two initialization operations include a fourth initialization operation and a third initialization operation, and the fourth initialization operation is irrelevant to programming data corresponding to the programming operation; the peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a fourth signal generating circuit and a third signal generating circuit; The interface circuit is configured to: receive a programming command, a programming address, and programming data corresponding to a programming operation; The fourth signal generating circuit is configured to: send a fourth initialization operation signal to the micro control unit after the interface circuit receives a programming address corresponding to a programming operation; The micro control unit is configured to: receive a fourth initialization operation signal and perform a fourth initialization operation; wherein the process of receiving programming data corresponding to the programming operation and the process of performing the fourth initialization operation are executed in parallel.

8. The memory according to claim 7, characterized in that: The fourth initialization operation includes a temperature detection operation, a word line voltage bias operation, and a bad block detection operation.

9. The memory according to claim 7, characterized in that: The third initialization operation is related to programming data corresponding to the programming operation; The interface circuit is further configured to: receive programming data and a programming confirmation command corresponding to the programming operation; The third signal generating circuit is configured to: send a third initialization operation signal to the micro control unit after the interface circuit receives a programming confirmation command; The micro control unit is further configured to: receive the third initialization operation signal and perform a third initialization operation.

10. The memory according to claim 9, characterized in that: The micro control unit includes a clock signal circuit; The clock signal circuit is configured to output a transition of the clock signal during the process of the micro control unit performing the fourth initialization operation and the third initialization operation.

11. A memory system, characterized in that: The memory system comprises: At least one memory as claimed in any one of claims 1 to 10; and A controller is coupled to the memory and configured to control the memory.

12. A method for operating a memory, characterized in that: The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array; the operating method includes: receiving a programming command, a programming address, programming data and a programming confirmation command corresponding to a programming operation; After performing at least two initialization operations, a programming operation is performed on the memory cell array; wherein the process of receiving a programming command, a programming address, programming data, and a programming confirmation command corresponding to the programming operation and the process of performing at least two initialization operations at least partially overlap in time.

13. The memory operation method according to claim 12, characterized in that: In the case of performing three initialization operations, the three initialization operations include a first initialization operation, a second initialization operation, and a third initialization operation, and the programming address and programming data corresponding to the first initialization operation and the programming operation are irrelevant; the peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a first signal generating circuit, a second signal generating circuit, and a third signal generating circuit; the operation method includes: The interface circuit receives a programming command corresponding to a programming operation; The first signal generating circuit sends a first initialization operation signal to the micro control unit after the interface circuit receives a programming command corresponding to a programming operation; The micro control unit receives the first initialization operation signal and performs a first initialization operation; wherein the process of receiving a programming address corresponding to the programming operation and the process of performing the first initialization operation are executed in parallel.

14. The memory operation method according to claim 13, characterized in that: The second initialization operation is related to a programming address corresponding to the programming operation and is unrelated to programming data corresponding to the programming operation; After the interface circuit receives a programming command corresponding to a programming operation, the operation method further includes: The interface circuit receives a programming address corresponding to a programming operation; The second signal generating circuit sends a second initialization operation signal to the micro control unit after the interface circuit receives a programming address corresponding to a programming operation; The micro control unit receives the second initialization operation signal and performs a second initialization operation; wherein the process of receiving the programming data corresponding to the programming operation and the process of performing the second initialization operation are executed in parallel.

15. The memory operation method according to claim 14, characterized in that: The third initialization operation is related to the programming data corresponding to the programming operation; After the interface circuit receives the programming address corresponding to the programming operation, the operation method further includes: The interface circuit receives programming data and programming confirmation commands corresponding to the programming operation; The third signal generating circuit sends a third initialization operation signal to the micro control unit after the interface circuit receives the programming confirmation command; The micro control unit also receives the third initialization operation signal and performs a third initialization operation.

16. The memory operation method according to claim 15, characterized in that: The micro control unit includes a clock signal circuit; the operation method also includes: The clock signal circuit outputs a transition of the clock signal during the process that the micro control unit performs the first initialization operation, the second initialization operation and the third initialization operation.

17. The memory operation method according to claim 12, characterized in that: In the case of performing two initialization operations, the two initialization operations include a fourth initialization operation and a third initialization operation, and the fourth initialization operation is irrelevant to programming data corresponding to the programming operation; The peripheral circuit includes an interface circuit and a micro control unit, and the interface circuit includes a fourth signal generating circuit and a third signal generating circuit; the operation method also includes: The interface circuit receives a programming command and a programming address corresponding to a programming operation; The fourth signal generating circuit sends a fourth initialization operation signal to the micro control unit after the interface circuit receives a programming address corresponding to a programming operation; The micro control unit receives a fourth initialization operation signal and performs a fourth initialization operation; wherein the process of receiving programming data corresponding to the programming operation and the process of performing the fourth initialization operation are executed in parallel.

18. The memory operation method according to claim 17, characterized in that: The third initialization operation is related to the programming data corresponding to the programming operation; After the interface circuit receives the programming command and programming address corresponding to the programming operation, the operation method further includes: The interface circuit also receives programming data and a programming confirmation command corresponding to the programming operation; The third signal generating circuit sends a third initialization operation signal to the micro control unit after the interface circuit receives the programming confirmation command; The micro control unit receives the third initialization operation signal and performs a third initialization operation.

19. The memory operating method according to claim 18, characterized in that: The micro control unit includes a clock signal circuit; the operation method also includes: The clock signal circuit outputs a transition of the clock signal during the process that the micro control unit performs the fourth initialization operation and the third initialization operation.

20. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed, the memory operation method according to any one of claims 12 to 19 can be implemented.

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