Composite current compensation in switching power converters

Abstract

A power controller includes a control loop (1200) configured to control timing of a pulse signal (1226) that activates a phase (120) of a coupled inductor voltage regulator (100) based on a current demand of a load circuit (114), and includes a transient detection circuit (400) configured to detect a transient of the pulse signal (1226) based on the current demand of the load circuit (114). The transient detection circuit is configured to determine a projected current through a compensation inductor (134) of the coupled inductor voltage regulator (100) based on a state of a phase (120) of the coupled inductor voltage regulator (100) and an operating parameter. The transient detection circuit (400) is configured to detect a transient in a current demand of the load circuit (114) based on variability of an inter-phase overlap of the pulse signal (1226). In response to detecting the transient, the transient detection circuit (400) is configured to apply a correction to the control loop (1200) that changes the timing of the pulse signal (1226) based on the projected current through the compensation inductor (134).

Description

Technical Field

[0001] Embodiments of the present disclosure relate to voltage regulators, and more particularly, to current emulation in multi-phase switching power converter topologies. Technical Background

[0002] Powerful microprocessors are required in power hungry applications such as cloud computing and artificial intelligence. For example, these processors may have stringent transient requirements with high current slew rates above 3000A / us. Multiphase buck converter designs can be used to design a power supply that meets the requested power requirements. Since board design can result in dense board structures to meet power requirements, adding more capacitors within the limited space available for board design is not a viable solution to meet these transient requirements.

[0003] Power supplies based on the trans-inductor voltage regulator (TLVR) buck converter topology can be used to reduce output capacitance while meeting higher transient requirements. Due to the nature of this circuit, the inductor current slew rate during transient loading will be much higher than a conventional voltage regulator buck converter topology. However, accurately capturing and reporting the current sense signal during transient loading transitions may lag behind the actual current level. The interaction between the controller device and the hysteretic current feedback may cause undesirable loopback issues as the current is used for control. Summary of the invention

[0004] According to one aspect of the present disclosure, a power controller includes a control loop configured to control the timing of a pulse signal that activates a phase of a coupled inductor voltage regulator based on a current demand of a load circuit, and includes a transient detection circuit configured to determine a projected current through a compensation inductor of the coupled inductor voltage regulator based on a phase state and an operating parameter of the coupled inductor voltage regulator. The transient detection circuit is configured to detect a transient in the current demand of the load circuit based on a variability in the phase-to-phase overlap of the pulse signal. In response to detecting the transient, the transient detection circuit is configured to apply a correction to the control loop that changes the timing of the pulse signal based on the projected current through the compensation inductor.

[0005] According to another aspect of the present disclosure, a method includes determining, by a control loop, a timing of a pulse signal that activates a phase of a coupled inductor voltage regulator based on a current demand of a load circuit, and determining, by a transient detection circuit, a projected current through a compensating inductor of the coupled inductor voltage regulator based on a phase state and an operating parameter of the coupled inductor voltage regulator. The method also includes monitoring, in the transient detection circuit, a variability in the phase-to-phase overlap of the pulse signal to detect a transient condition in the current demand of the load circuit, and applying, by the transient detection circuit, a correction to the control loop during at least a portion of the transient condition that changes the timing of the pulse signal based on the projected current through the compensating inductor.

[0006] According to another aspect of the present disclosure, an apparatus includes one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media. The program instructions executable by a processing system are used to direct the processing system to at least: determine a projected current through a compensating inductor of a coupled inductor voltage regulator based on a phase state of the coupled inductor voltage regulator and an operating parameter of the coupled inductor voltage regulator, and detect a transient in a current demand of a load circuit provided by the coupled inductor voltage regulator based on a variability in an overlap of phases of a pulse signal. The program instructions also direct the processing system to apply a correction to a control loop in response to detecting the transient, the correction changing the timing of the pulse signal based on the projected current through the compensating inductor.

[0007] This summary is provided to introduce a series of concepts in a simplified form, which will be further described in the detailed description below. It should be understood that this summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Many aspects of the present disclosure may be better understood with reference to the following drawings. Although several embodiments are described in conjunction with these drawings, the present disclosure is not limited to the embodiments disclosed herein. On the contrary, the purpose is to cover all alternatives, modifications and equivalents.

[0009] Figure 1 is a schematic diagram illustrating a multi-phase power converter according to an embodiment.

[0010] Figure 2 A number of waveforms showing current and voltage responses during a power change of a load circuit are shown according to an example.

[0011] Figure 3 The effect of power stage current reporting in various timing scenarios according to an embodiment is shown.

[0012] Figure 4is a schematic block diagram illustrating simulated current generation according to an embodiment.

[0013] Figure 5 A block diagram showing a method for calculating a current rate according to an embodiment is shown.

[0014] Figure 6 A block diagram showing a phase-by-phase counter for calculating emulated current is shown according to an embodiment.

[0015] Figure 7 A timing diagram showing the operation of a counter according to an embodiment is shown.

[0016] Figure 8 A timing diagram showing the operation of a counter according to an embodiment is shown.

[0017] Fig. 9 A waveform response in response to a load current increase according to an embodiment is shown.

[0018] Fig.10 A waveform response in response to a load current reduction according to an embodiment is shown.

[0019] Fig.11 is a flow chart illustrating a transient detection method according to an embodiment.

[0020] Fig.12 A control loop according to an embodiment is shown.

[0021] Fig.13 is a flow chart illustrating a method for adjusting the timing of a pulse signal according to an embodiment.

[0022] Fig.14 An example implementation of a control system according to an embodiment is shown. DETAILED DESCRIPTION

[0023] Figure 1 1 shows a schematic diagram of a multiphase power converter 100 according to an embodiment. In particular, the multiphase power converter 100 is arranged as a trans-inductor voltage regulator (TLVR) buck converter. An input voltage 110 is provided to an input node 111 coupled to a plurality of power stages 120. The first power stage 121 receives a voltage provided by the input voltage 110 and generates an output current i in response to a pulse width modulation (PWM) control of one or more power switches via a PWM control signal (PWM1) from a controller 103. ph1 The second power stage 122 also receives a voltage provided by the input voltage 110 and generates an output current i in response to PWM control of one or more power switches thereof via a PWM control signal (PWM2) from the control circuit. ph2As shown, the Nth power stage 123 is also coupled to the input node 111 to receive a voltage provided by the input voltage 110, thereby generating an output current i in response to PWM control (PWMN) of one or more power switches thereof. phN .

[0024] Reference Figure 2 , first and second graphs 200, 210 illustrate current transitions of the output current 113 provided to the load circuit 114 according to an example. As shown in the graph 200, the steady-state current undergoes an incremental change in response to an increase in the current demand of the load circuit 114, as indicated by the waveform 201, which illustrates a change in the actual current in response to the increase in the current demand. The graph 210 illustrates a decremental change in the current provided to the load circuit 114 in response to a decrease in the current demand. In one example, a pair of reported current waveforms 202, 212 associated with the actual current waveforms 210, 211, respectively, illustrate that the reported current changes more slowly than the actual current due to the manner in which the reported current is calculated. Between the first steady-state portion of the waveforms 210, 211 and the higher and lower current value steady-state portions of the waveforms 210, 221, respectively, the transient response of the reported current waveforms 202, 212 has difficulty adapting to the change in the actual current supplied to the load 114. As a result, in the graph 220 illustrating the output voltage waveform 221, first and second ringback events 222, 223 can be seen. Ringback events 222, 223 are undesirable, and embodiments of the present disclosure describe improved transient responses in reported current to reduce or eliminate concerns about Figure 2 Describe the shortcomings.

[0025] Back to Figure 1 , output current i ph1 -i phN is provided to the plurality of coupled inductors 130. Specifically, the output current i ph1 is supplied to the first coupled inductor 131, the output current i ph2 is supplied to the second coupled inductor 132, and the output current i phN is provided to the Nth coupled inductor 133. Each coupled inductor 131-133 includes a circuit configured to receive a corresponding output current i ph1 -i phN The primary winding and the secondary winding of the phase 120 are connected to each other. The primary winding is coupled to a common output node 112, which is also coupled to an output capacitor 115 and a load circuit 114. The secondary winding is coupled in series with an external compensation inductor 134. The external compensation inductor 134 couples current changes in one of the phases 120 (e.g., power stage 121) with the rest of the phases 120 (e.g., power stages 122, 123). In this way, the voltage drop in the output voltage is small.

[0026] The adder 102 is shown, which represents the actual current (eg, i ph1 、i ph2 、i phN etc.) are summed to form a single current value i sum-ACT , the current value i sum-ACT In response to the current i ph1 、i ph2 、i phN The same common output node 112 is fed to produce an output current 113 which is provided to a load circuit 114. Figure 1 In the circuit shown, no physical hardware for measuring actual current is used. Such hardware may take up valuable space on a printed circuit board (PCB) supporting the multiphase power converter 100. Instead, the multiphase power converter 100 generates emulated currents (e.g., CSP1, CSP2, CSPN, etc.) in each of the power stages 121-123 to be summed within the controller 103 (as shown by the current summer 101) to generate a summed current signal i sum , which is used by the controller 103 to generate PWM control signals PWM1, PWM2, PWMN, etc. Each emulated current generated by each power stage 121-123 represents an actual current (eg, i ph1 、i ph2 、i phN wait).

[0027] refer to Figure 3 , according to one embodiment, illustrates the effect of power stage current phase and power stage current reporting in various timing scenarios. The power stage current reporting block 300 illustrates the relationship between example current waveforms (1001-1003) experienced by the primary winding of the coupled inductors 131-133 in response to the respective PWM signals 304 transmitted to the respective power stages 121-123. During the ON pulse of the PWM signal 304, the current portion 301 illustrates the increase in current flowing through the primary winding. The reporting of the current during the rising current portion 301 is simulated within the power stage.

[0028] Each power stage 121-123 is designed to have a Toff1 time and a Toff2 time. In a single system arrangement such as a multi-phase power converter 100, the Toff1 and Toff2 times of all included power stages can be selected to be similar or substantially similar. However, one or more of the power stages 121-123 may have different Toff1 and / or Toff2 times. In one embodiment, the Toff1 and Toff2 times start in response to the falling edge of the pulse of the PWM signal 304. During the Toff1 time, the current is reduced through the primary winding of the corresponding coupled inductor 131-133 and is also simulated within the power stage. Starting from Toff1, the simulation of reducing the current ends, and the actual sensed current is reported to the controller 103. In response to reaching Toff2, the DC value of the current in the power stage is updated, while the actual current is still reported to the controller 103.

[0029] Figure 3 Current reporting examples 310 are shown in response to different off-times 305 of a PWM signal 304. A PWM signal 311 is shown corresponding to a first case example having a sufficiently fast off-time 305 such that the off-time (Toff) 305 between consecutive PWM pulses is shorter than the Toff1 time. During a first PWM pulse period corresponding to the first pulse and the first Toff time, the reported power stage current 315 accurately reflects the actual inductor current 314 experienced by the corresponding primary winding. However, subsequent PWM periods cause the reported power stage current 315 to deviate from the actual inductor current 314. As shown during a second PWM period, the shape of the reported power stage current 315 matches the shape of the actual inductor current 314. For example, the rising portions of the currents 314, 315 have the same or similar rising slopes, and the falling portions of the currents 314 and 315 have the same or similar falling slopes. However, because the Toff time is shorter than the Toff2 time, the DC value of the current in the power stage cannot be reset or updated.

[0030] In the second illustrated case example, the PWM signal 312 is shown as having a Toff time 305 that is longer than the Toff1 time but shorter than the Toff2 time. As shown, the slopes of the rising portions of the actual inductor current 316 and the reported power stage current 317 are similar to the slopes of the falling portions corresponding to the Toff1 time. The current reduction portion corresponding to the portion between the Toff1 and Toff2 times also has a matching slope. However, in response to the actual current reported after the Toff1 time, the DC value of the reported power stage current 317 matches the DC value of the actual inductor current 316. Unfortunately, the DC value of the reported power stage current 317 is not updated as in response to reaching the Toff2 time. Therefore, the beginning of each PWM cycle starting from the rising edge of the PWM pulse includes the power stage current 317 reported starting from a DC value that does not match the corresponding DC value of the actual inductor current 316.

[0031] In the third illustrated example, the PWM signal 313 is shown as having a Toff time 305 that is longer than the Toff2 time. As shown, the slopes of the rising and falling edges of the actual inductor current 318 and the reported power stage current 319 match throughout the PWM cycle. In addition, as shown, in response to reaching and exceeding the Toff2 time, the DC value of the current in the power stage is updated to substantially represent the actual inductor current 318 in each PWM cycle.

[0032] Embodiments of the present disclosure provide compensation for the difference between the actual current seen by the external compensation inductor 134 and the emulated current reported to the controller 103 from the plurality of power stages 120 .

[0033] Figure 4 A schematic block diagram of a digital simulated current generator 400 according to an example is shown. In one embodiment, the digital simulated current generator 400 is executed by the controller 103. The generator 400 includes an arithmetic logic unit (ALU) 410 that receives a plurality of system parameters 420. The system parameters 420 include a value (Vin) of an input voltage (e.g., the input voltage 110), a value (Vout) of an output voltage (e.g., at the output node 112), an inductance value (Lc) of the external compensation inductor 134, a body diode voltage value (Vdiode) of the low-side FETs of the power stages 121-123, a Vdroop adjustment value (Vdroop) for accounting for the measurement accuracy of Vdroop in the controller 103 due to bandwidth or offset conditions, etc. tune) and a conversion factor (Convfact), which may include one or more of the clock cycle at which the controller 103 is running, the digital-to-analog (DAC) conversion scale, and the current-to-voltage conversion ratio. The Lc, Vdiode, and conversion factor values ​​may be obtained from a memory such as a non-volatile memory within the controller 103. Additional system parameters may be obtained from the inputs to the controller 103, indicating the number of power stages 121-123 that are currently in an on, high state (e.g., controlling the PWM signal to be high) (K), the number of phases that the PWM is actively switching (M), and the number of phases available to the system (N).

[0034] In one embodiment, the compensation rate 421 is calculated based on the system parameter 420 according to the following formula:

[0035]

[0036] In another embodiment, the compensation rate 421 is calculated based on the system parameter 420 according to the following formula:

[0037]

[0038] Figure 5 A block diagram showing a method 500 for calculating a compensation rate based on Formula 2 according to an embodiment is shown. A first multiplier 501 receives a K value and a Vin value and multiplies them. The multiplication product is provided to a first subtractor 502 .

[0039] The N value is provided to the second multiplier 503. The second multiplier 503 also receives the Vout input, generates the product of the N and Vout inputs, and provides the product to the first adder 504. The N value is also provided to the second subtractor 505. The M value is provided to the second subtractor 505. M is subtracted from N in the second subtractor 505, which outputs the difference to the second adder 506. The adder 506 adds the Vdiode input to the NM difference and provides the sum to the first adder 504. The first adder 504 adds the N*Vout product and the (NM)*Vdiode product and provides them to the first subtractor 502 to be subtracted from the K*Vin product. The resulting difference is provided to the third multiplier 507 to be multiplied by a quotient based on the conversion factor divided by the inductance of the external compensation inductor 134. The final product generated by multiplier 507 is output as the generated Rate (compensation rate) of Formula 2.

[0040] Back to Figure 4The calculated compensation rate 421 is provided together with the input of the first off time Toff1 422 and the second off time Toff2 423 to the current calculator block 411, which has a counter dedicated to each power stage 121-123 for digitally simulating the current generated in response to the PWM signals PWM1-PWMN. Figure 6 As shown, the current calculator block 411 includes internal counters 600, 601, 602 and external counters 603, 604, 605 for determining emulated current values ​​of individual phases (eg, phase 1, phase 2, phase N) corresponding to the respective power stages 121-123. Figure 7 Example operations of the internal and external counters 600, 603 for phase 1 are shown corresponding to the operation of the power stage 121. Figure 6 and Figure 7 At the beginning of the PWM signal cycle starting from the rising edge 700 of the PWM pulse 701, the value of the internal counter 600 is copied to the external counter 603, and the counters 600, 603 begin to increment or decrement based on the compensation rate 421. The external counter 603 increments or decrements until the first off-time Toff1 422 ends, while the internal counter 600 keeps incrementing or decrementing until the second off-time Toff2 423 ends. Figure 6 As shown, external counter 603 derives its value as the simulated CSP1 value. Phase 2 to Phase N external counters 604 - 605 similarly derive the values ​​of their respective phases (eg, Phase 2 to Phase N) for further processing by digital simulated current generator 400 .

[0041] like Figure 4 As shown, the simulated CSP1 -CSPN values ​​are provided to adder 412 , which combines the simulated currents into a summed simulated current output 425 . Figure 8 Waveforms are shown for an exemplary implementation of calculating emulated currents and sums thereof based on PWM signals 800, 801, 802. Clock signal 803 provides timing for calculation of PWM signals 800-802 and outputs of digital ALU 410 (e.g., compensation rate 421 output shown), external counters 603-605, and adder 412 (e.g., summed emulated current output 425).

[0042] Each external counter 603-605 starts counting the value of the compensation rate signal 421 at the rising edge of the pulse of its respective PWM signal 800-802 and stops counting at the end of its respective Toff1 time 804-806. The first external counter 603 counts three times 3, once 5, twice 3, once 5, and another twice 3. The second external counter 604 counts once 5, twice 3, once 5, three times 3, and twice -1. The third external counter 605 counts once 5, three times 3, and five times -1. The sum of the counter values ​​during each clock cycle is shown in the summed simulated current output 425.

[0043] Back to Figure 4 The digital-to-analog converter (DAC) 413 converts the digital summed simulated current output 425 into an analog compensation signal I CE 426. As referenced Figure 2 As described above, the transient response has difficulty adapting to changes in the actual current supplied to the load 114. During such a transient event, by CE Incorporating 426 into the feedback control loop to compensate for the current reporting of the power stages 121-123 can improve current response and reduce ringback during such transient conditions. However, it is not necessary to incorporate the analog compensation signal 426 outside of transient events. Therefore, embodiments of the present disclosure contemplate detecting load current transient events for applying determined compensation during the transient period. Outside of the transient period, the compensation signal 426 is not provided to the feedback control loop.

[0044] Therefore, if Figure 4 As shown, the controller 103 also includes a transient detector block 414 configured to identify a transient in the load current to switch a compensation signal 426 into the control loop. Fig. 9 and Fig.10 Waveforms 900 , 1000 illustrating load current transient conditions are shown according to an embodiment. Fig.11 Transient detection is shown implemented by a flow chart of a process 1100 for determining a load current transient and controlling activation of a correction enable signal according to an embodiment.

[0045] Reference Figure 9-11 , the load current 910, 1010 starts in steady-state mode and transitions to a higher or lower load current at a corresponding transition event 921, 1021. During the steady-state mode, as the controller 103 generating the signals 912-914, 1012-1014 operates the multiphase power converter 100 to generate the desired load current, the overlap time t between consecutive pulses of adjacent PWM signals 912-914, 1012-1014 is OL1 922 and 1022 may be similar or may vary. For example, Fig. 9The overlap time between the continuous PWM signals (PWM1 signal 912 and PWM2 signal 913, PWM2 signal 914 and PWMN signal 914, or PWMN signal 914 and PWM1 signal 912) can be the same as Fig.10 The PWM signals (PWM 1 signal 1012 and PWM 2 signal 1013, PWM 2 signal 1013 and PWMN signal 1014, or PWMN signal 1014 and PWM 1 signal 1012) of the power stages 121-123 may be similar or may vary. In an attempt to maintain an equal degree of separation between the operations of the power stages 121-123 to optimize the current ripple in the output voltage, the controller 103 may tend to equalize the overlap time between consecutive PWM signals.

[0046] In response to a load current transient condition, where the step-up transition 921 or the step-down transition 1021 results in a change in the load current 910, 1010, the overlap time of the consecutive PWM signals 912-914, 1012-1014 will change accordingly. Fig. 9 As shown, the step-up transition 921 increases the load current demand, and the overlap time t between consecutive signals (eg, PWM1 signal 912 and PWM2 signal 913) is OL2 923, 1023 reduced. Fig.10 As shown, the step-up transition 1021 increases the load current demand, and the overlap time t between consecutive signals (eg, PWM1 signal 1012 and PWM2 signal 1013) is OL2 Increase.

[0047] In process 1100, by determining a first overlap time (eg, t OL1 ) to capture the overlapping time t OL2 With overlap time t OL1 In the second block 1102, a second overlap time (e.g., t OL2 ). If the correction enable signal (EMU_ENABLE) is not activated (block 1103), the subsequent overlap time t OL2 Overlap time t with the previous OL1 The comparison is performed (block 1104) to determine the overlap time t OL2 and t OL1 The difference between the two is large enough to indicate that a load current transient condition has occurred. OL1 and t OL2 The difference between the overlap time threshold t OL_THFor example, if the absolute value of the overlap time difference reaches or exceeds a threshold, the presence of a load current transient condition may be indicated. If so, a correction enable signal is activated at block 1105, and process 1100 returns to block 1101 to iterate another round of overlap time checking. Fig. 9 and Fig.10 The enabling of the correction enable signal (EMU_ENABLE 915, 1015) is shown at transitions 924, 1024. If the absolute value of the overlap time difference does not meet or exceed the threshold, the process 1100 returns to block 1101 to iterate another round of overlap time checking.

[0048] If the correction enable signal (EMU_ENABLE) is activated (block 1103), the overlap time t OL1 and t OL2 The difference between the steady-state condition threshold t SS_TH In one embodiment, the steady-state condition threshold is less than the overlap time threshold, and is less than or equal to the overlap time t of the steady-state condition threshold. OL1 and t OL2 The absolute value of the difference between indicates that there is no load current transition period. When the steady-state condition threshold is reached after experiencing the load current transition period, the load current transition period has ended. In block 1106, the overlap time t OL1 and t OL2 The absolute difference between the steady-state condition threshold t SS_TH If the steady-state condition is not met, the correction enable signal is not changed, and the process 1100 returns to block 1101 to iterate another round of overlap time checking. If the steady-state condition is met, the correction enable signal is disabled at block 1107, and the process 1100 returns to block 1101 to iterate another round of overlap time checking.

[0049] In alternative embodiments, transient events may be determined by measuring the on-time (Ton) of the PWM signals 912 - 914 , or may be inferred based on sudden and dramatic changes in the PWM output without DC sensing to maintain a stable output voltage.

[0050] Fig.12 FIG. 1 shows a feedback control loop 1200 for generating a PWM control signal according to an embodiment. The voltage compensation signal V comp 1201 is generated based on the sum of three signal paths within the control loop 1200. In the control loop 1200, the error amplifier 1202 subtracts the sensed output voltage from the output voltage target to generate a droop voltage 1203. The first signal path within the control loop 1200 includes a proportional path 1204, which receives the droop voltage 1203 and generates a proportional output 1205.

[0051] The second signal path within the control loop 1200 is based on receiving a signal from, for example, Figure 1 The simulated current summer 101 provides the sum of the reported currents I sum 1206. I sum 1206 is provided to an adder 1207, which is configured to modify I during a load current transient event if one exists. sum 1206. For example, the analog compensation signal I CE 426( Figure 4 ) by the simulation enable signal 427 ( Figure 4 1200. If provided, ICE 426 is modified to the DC portion of control loop 1200 by mixer 1209, which combines ICE 426 and DC emulated current gain 1210. The product of mixer 1209 and I sum 1206 is added and the sum is provided to the DC load line 1211 to produce the ideal droop value 1212. The difference signal generated by the summer 1213 of the difference between the droop voltage 1203 and the ideal droop value 1212 is provided to the integration path 1214, which creates the error voltage and adjusts V comp The set point of signal 1201 is set to generate an integrated output 1215 that drives the output voltage error to zero.

[0052] The third signal path within the control loop 1200 is based on I sum 1206. If a load current transient event is present, the DAC outputs 426 are combined in mixer 1216 to provide correction to the AC portion of the control loop 1200. Mixer 1216 combines I CE 426 and AC emulation current gain 1217. The product of mixer 1216 is combined with I sum 1206 are added to generate a current feedback output 1218.

[0053] The outputs of the three signal paths (e.g., proportional output 1205, integral output 1215, and current feedback output 1218) are combined in summer 1219 to generate a raw voltage compensation signal 1220, which is scaled by scaler 1221 to generate scaled voltage compensation signal 1201. Compensated ramp signal V RAMP 1222 has a slope proportional to the number of phases or power stages 121-123 and the switching frequency setting. In response to detecting V RAMP 1222 and V COMP1201 signals, the controller 103 generates a new clock pulse in the clock signal 1223. Based on the clock signal 1223, the phase manager 1261 within the controller 103 generates corresponding PWM signals 1262 (eg, PWM1-PWMN) for controlling the power stages 121-123.

[0054] Fig.13 is a flow chart showing a method 1300 for adjusting the timing of a pulse signal according to an embodiment. In one embodiment, the method 1300 may be combined with Fig.11 Method 1300 begins at step 1301 by establishing or controlling the timing of a pulse signal for activating a phase of a coupled inductor voltage regulator according to a current demand of a load circuit. For example, by Fig.12 The PWM control signal 1262 generated with the help of the control loop 1200 is used to control the power stages 121-123 to generate the output voltage 112. At step 1302, a projected current through the compensation inductor of the coupled inductor voltage regulator is determined based on the phase state and operating parameters of the coupled inductor voltage regulator. For example, the digital simulated current generator 400 generates the current compensation rate 421 and uses the phase-by-phase counter 411 to generate the simulated current output 426. At step 1303, the variability of the phase-to-phase overlap of the pulse signal is monitored to detect transient conditions in the current demand of the load circuit. Fig. 9 As shown, the 10 overlapping times Toff1 and Toff2 are used to detect transient entry and exit conditions in the load current demand.

[0055] If the transient entry condition is met at step 1304, corrections to the control loop are enabled at step 1306, which change the timing of the pulse signal based on the projected current through the compensation inductor. The process 1300 then returns to step 1301 for another iteration cycle. If the transient entry condition is not met at step 1304, the transient exit condition is tested at step 1305. If the transient exit condition is met, corrections to the control loop are disabled at step 1307, and the process 1300 returns to step 1301 for another iteration cycle. If the transient exit condition is not met at step 1305, the process 1300 returns to step 1303 to continue monitoring the transient exit condition. For example, if the transient exit condition is not met at step 1305, the process 1300 returns to step 1303 to continue monitoring the transient exit condition. Fig.11 As facilitated by process 1100, corrective activation and deactivation are determined based on detection of transient periods in load current.

[0056] Fig.14 An example implementation of a control system that can implement any of the control schemes discussed herein is shown. Fig.14The control system 1401 is included. The control system 1401 represents any system or collection of systems in which the various operational techniques, architectures, scenarios, and processes disclosed herein can be implemented. For example, the control system 1401 can be used to implement Figure 1 A controller or control portion of the multi-phase power converter 100, Figure 4 Digital simulation current generator 400, Fig.11 The correction enable signal is activated, Fig.14 feedback loop control or any control, transient detection or transient correction of any figure in this document.

[0057] The control system 1401 may be implemented as a single device, system or apparatus, or may be implemented as multiple devices, systems or apparatuses in a distributed manner. The control system 1401 includes, but is not limited to, a processing system 1402, a storage system 1403, software 1405, a communication interface system 1407 and a user interface system 1408. The processing system 1402 is operably coupled to the storage system 1403, the communication interface system 1407 and the user interface system 1408.

[0058] Processing system 1402 loads and executes software 1405 from storage system 1403. When executed by processing system 1402 to control the power system to affect specified load regulation, transient detection, and correction enable signal activation / enabling operations, software 1405 instructs processing system 1402 to operate as described herein for at least the various processes, operating scenarios, and sequences discussed in the above implementations. Control system 1401 may optionally include additional devices, features, or functions that are not discussed for the sake of brevity.

[0059] Processing system 1402 may include processing circuitry that retrieves and executes software 1405 from storage system 1403. Processing system 1402 may be implemented within a single processing device, but may also be distributed across multiple processing devices or subsystems that cooperate to execute program instructions. Examples of processing system 1402 include general purpose central processing units, special purpose processors, graphics processing units, programmable logic devices, field programmable logic devices, application specific integrated circuit devices, digital signal processors and discrete logic, and any other type of processing device and supporting circuitry, combination or variation thereof.

[0060] The storage system 1403 may include any tangible computer-readable storage medium that can be read by the processing system 1402 and can store the software 1405. The storage system 1403 may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, control programs, program modules or other data. Examples of storage media include random access memory, read-only memory, magnetic disks, optical disks, flash memory, virtual memory and non-virtual memory, magnetic storage media, magnetic storage devices, or any other suitable storage media. In any case, the computer-readable storage medium is not a propagated signal. In addition to computer-readable storage media, in some implementations, the storage system 1403 may also include a computer-readable communication medium through which at least some of the software 1405 can be communicated internally or externally. The storage system 1403 can be implemented as a single storage device, but it can also be implemented across multiple storage devices or subsystems that are co-located or distributed relative to each other. The storage system 1403 may include additional elements that can communicate with the processing system 1402 or possibly other systems, such as a controller.

[0061] The software 1405 may be implemented in program instructions and, when executed by the processing system 1402, may, among other things, direct the processing system 1402 to operate as described in the various operational scenarios, sequences, and processes described herein. For example, the software 1405 may include program instructions that include the power control environment 1420 to implement Fig.11 , Fig.13 1405. The software 1405 may include operations 1100, 1300 shown in or other operations discussed herein. In particular, program instructions may include various components or modules that collaborate or otherwise interact to perform various processes and operational scenarios described herein. Various components or modules may be implemented in compiled or interpreted instructions, or in some other variants or combinations of instructions. In addition to or including the power control environment 1420, the software 1405 may also include additional processes, programs or components, such as operating system software (e.g., 1421) or other application software (e.g., 1425). The software 1405 may also include firmware or some other form of machine-readable processing instructions that may be executed by the processing system 1402.

[0062] When the software 1405 is loaded into the processing system 1402 and executed, a suitable device, system or equipment (of which the control system 1401 is representative) can be converted as a whole from a general-purpose computing system to a special-purpose computing system that is customized to control the power system to affect load regulation, transient detection, feedback control loop correction operation and other control operations. In fact, the encoded software 1405 on the storage system 1403 can transform the physical structure of the storage system 1403. For example, if the computer-readable storage medium is implemented as a semiconductor-based memory, when the program instructions are encoded therein, the software 1405 can convert the physical state of the semiconductor memory, such as by converting the state of the transistors, capacitors or other discrete circuit elements that constitute the semiconductor memory. Similar transformations may also occur with respect to solid-state media, magnetic media or optical media. Other transformations of physical media are possible without departing from the scope of this specification, and the above examples are provided only to facilitate this discussion.

[0063] In one example implementation, the software 1405 includes a control process power control environment 1420, which includes an operating system 1421 and an application 1422, at least some of which represent the operating techniques, algorithms, architectures, scenarios, and processes discussed with respect to the included figures. The software 1405 may also use parameters 1410 stored by the storage system 1403. The parameters 1410 include system parameters 420, which may represent any of the programmable registers, software-defined parameters, status indicators, user-controlled feature settings, or adjustment parameters discussed herein.

[0064] Application 1422 can implement power control application 1423, which includes overlap detection service 1424, current emulation service 1425 and PWM service 1426. One or more software or firmware modules can perform the functions of these services, and these modules can provide shared or distributed functions. Overlap detection service 1424 is configured to monitor the timing overlap between pulse signals associated with the voltage conversion phase of supplying current to the load circuit. Current emulation service 1424 determines the current emulation signal based on parameter 1410.

[0065] Based on the monitored timing between the pulse signals, the overlap detection service 1424 is configured to monitor the variability of the overlap between the phases of the pulse signals to detect a transient condition in the current demand of the load circuit. Based on the monitored variability, if a transient entry condition is met, a correction to the control loop is enabled, which changes the timing of the pulse signal based on the projected current through the compensation inductor. If a transient exit condition is met, the correction to the control loop is disabled, which changes the timing of the pulse signal based on the projected current through the compensation inductor.

[0066] The current simulation service 1425 is configured to determine the counter rate based on the system parameters 420 and the power stage parameters. The current simulation service 1425 is also configured to generate a simulated current compensation signal. The PWM service 1426 can control various external circuits that mitigate or correct various undershoot or overshoot conditions and provide enhanced transient response for the power system. For example, based at least on an indication of a transient event condition, the PWM service 1426 is configured to generate a PWM control signal based on the simulated current compensation signal to increase the transient response.

[0067] The communication interface system 1407 may include communication connections and devices that allow communication with various circuit elements, such as discrete circuit elements, transistors, interface logic, A / D or D / A conversion units or electrical components through a communication link or a communication network (not shown). Examples of connections and devices that allow communication may include logic interfaces, off-chip communication elements, signal drivers, signal receivers, transceivers, network interface controllers and other communication circuits. Connections and devices may communicate through a communication medium to exchange communications with other computing systems or system networks, such as metal, glass, air or any other suitable communication medium. The communication between the control system 1401 and other elements or systems (not shown) via the communication interface system 1407 may occur on a data link, a control link, a communication link or a communication network, and according to various communication protocols, protocol combinations or variants thereof. For example, the control system 1401 may transmit control signaling through a digital communication link, and the digital communication link may include an Ethernet interface, a serial interface, a serial peripheral interface (SPI) link, an internal integrated circuit (I2C) interface, a universal serial bus (USB) interface, a UART interface, a discrete signaling or a wireless interface.

[0068] The user interface system 1408 may include an interface element to receive user or operator programmed settings for operating the power control system, such as for changing parameter 1410. The user interface system 1408 may also provide feedback to the user or operator about the current settings saved in parameter 1410. In some examples, the user interface system 1408 receives and transmits various information through the communication interface system 1407. The user interface system 1408 may include a separate user interface element, which includes a software interface such as a terminal interface, a command line interface, or an application programming interface (API). The user interface system 1408 may also include a physical user interface, such as a keyboard, a mouse, a voice input device, or a touch screen input device for receiving user input. The user interface system 1408 may include a visualization / status interface, a user command control, and telemetry, such as a user control, a start / stop control, telemetry, an operation mode control interface, a visualization interface, and a system characteristic calibration control, etc. Output devices, such as displays, speakers, network interfaces, terminal interfaces, and other types of output devices, may also be included in the user interface system 1408. The user interface system 1408 may also include associated user interface software executable by the processing system 1402 to support the various user input and output devices described above.

[0069] The techniques described in the present disclosure may also be embodied or encoded in an article comprising a non-transient computer-readable storage medium. Exemplary non-transient computer-readable storage media may include random access memory (RAM), read-only memory (ROM), programmable ROM, erasable programmable read-only memory, electrically erasable programmable ROM, flash memory, solid-state drive, hard disk, magnetic media, optical media, or any other computer-readable storage device or tangible computer-readable medium. The term "non-transient" may mean that the storage medium is not contained in a carrier or propagating signal. In some examples, a non-transient storage medium may store data that changes over time (e.g., in RAM or cache).

[0070] The functional block diagrams, operational scenarios and sequences, and flow charts provided in the accompanying drawings represent exemplary systems, environments, and methods for performing novel aspects of the present disclosure. Although the methods included herein may be in the form of functional diagrams, operational scenarios, or sequences or flow charts for ease of explanation, and may be described as a series of actions, it should be understood and appreciated that these methods are not limited by the order of actions, because accordingly, some actions may occur in different orders and / or occur simultaneously with other actions shown and described herein. For example, those skilled in the art will understand and appreciate that a method may alternatively be represented as a series of interrelated states or events, such as in a state diagram. In addition, not all behaviors shown in the method are required for novel implementations.

[0071] According to the above description, various circuit elements and interconnection architectures discussed herein are adopted. However, it should be understood that the disclosure and enhancements herein are not limited to these circuit elements and interconnection architectures. Therefore, the description and drawings contained herein depict specific implementations to teach those skilled in the art how to make and use the best options. In order to teach the principles of the invention, some traditional aspects are simplified or omitted. Those skilled in the art will understand the changes of these embodiments that fall within the scope of the present disclosure. Those skilled in the art will also understand that the above features can be combined in various ways to form a variety of implementations.

[0072] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform the following actions: (a) in the first example, device A is coupled to device B through a direct connection; or (b) in the second example, if the intervening component C does not change the functional relationship between device A and device B, device A is coupled to device B through the intervening component C, so that device B is controlled by device A through the control signal generated by device A.

[0073] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform that function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the hardware components of the device and the interconnection of the device, or a combination of both.

[0074] As used herein, the terms "terminal", "node", "interconnection", "pin" and "lead" may be used interchangeably. Unless otherwise specified, these terms are generally used to refer to an interconnection or an end point between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor elements.

[0075] Circuits or devices described herein that include certain components may also be implemented by coupling these components to the circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (such as a semiconductor die and / or integrated circuit (IC) package), and may be suitable for coupling to at least some of the passive elements and / or sources during or after manufacturing to form the structure, such as by an end user and / or a third party.

[0076] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used. For example, a p-channel field effect transistor (PFET) may be used instead of an n-channel field effect transistor (NFET) with little or no change to the circuit. In addition, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used. In addition, these devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs). In addition, reference to transistor features, such as a gate, source, or drain, does not mean that any suitable transistor technology is excluded. For example, features such as source, drain, and gate are commonly used to represent FETs, while emitters, collectors, and bases are commonly used to represent BJTs. These features may be used interchangeably herein. For example, reference to the gate of a transistor may refer to the gate of a FET or the base of a BJT, and vice versa. In some examples, a control terminal may refer to the gate of a FET or the base of a BJT. Any other suitable transistor technology may be used. Any such transistor can be used as a switch, with the gate or base or other similar feature acting as the switch select input, which can be driven to connect the source and drain (or emitter and collector, as the case may be).

[0077] When a field effect transistor (FET) is "on" (or the switch is closed) in this article, it means that the FET's conductive channel exists and drain current can flow through the FET. When a FET is "off" (or the switch is open) in this article, it means that there is no conductive channel and drain current does not flow through the FET. However, an off FET may have current flowing through the body diode of the transistor.

[0078] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to that available prior to component replacement. Unless otherwise indicated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistors shown. For example, a resistor or capacitor shown and described herein as a single component may be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0079] The use of the term "ground" in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground and / or any other form of ground connection that is applicable or suitable for the teachings of this description. In this description, unless otherwise specified, "approximately", "approximately" or "substantially" before a parameter means within the range of + / -11% of the parameter.

[0080] Modifications may be made in the described examples and other examples may be made within the scope of the claims.

Claims

1. A power controller, comprising: a control loop configured to control the timing of a pulse signal activating a phase of a coupled inductor voltage regulator based on a current demand of a load circuit; a transient detection circuit configured to determine a projected current through a compensation inductor of the coupled inductor voltage regulator based on a state of a phase of the coupled inductor voltage regulator and an operating parameter; wherein the transient detection circuit is configured to detect transients in the current demand of the load circuit based on variability in phase-to-phase overlap of the pulse signal; as well as Wherein, in response to detecting the transient, the transient detection circuit is configured to apply a correction to the control loop, the correction changing the timing of the pulse signal based on the projected current through the compensation inductor.

2. The power controller according to claim 1, wherein: The transient detection circuit is configured to enable the correction of the control loop based on the variability of the overlap indicating that the overlap increases above a first threshold, and to disable the correction of the control loop based on the variability of the overlap indicating that the overlap decreases below a second threshold after exceeding the first threshold.

3. The power controller according to claim 1, wherein: The transient detection circuit is configured to enable the correction of the control loop based on the variability of the overlap indicating that the overlap decreases below a first threshold, and disable the correction of the controller loop based on the variability indicating that the overlap increases above a second threshold after falling below the first threshold.

4. The power controller according to claim 1, wherein: The correction to the control loop includes one or more of a first correction to an AC portion of the control loop and a second correction to a DC portion of the control loop.

5. The power controller according to claim 1, wherein the transient detection circuit is configured to: determining the operating parameter of the coupled inductor voltage regulator based at least on an inductance value of the compensation inductor; The state of the phase is determined based on at least the number of the phases present and the activation state of the phase.

6. The power controller according to claim 1, wherein: The correction to the control loop includes a scaled combined rate of change of a projected current provided by each phase determined based at least in part on the operating parameter and the projected current through the compensation inductor.

7. The power controller according to claim 1, wherein: The correction to the control loop includes a load current adjustment to the control loop corresponding to a difference between a reported current demand of the load circuit and a scaled version of the projected current through the compensation inductor.

8. The power controller according to claim 1, comprising: A set of programmable registers defines at least an entry threshold and an exit threshold of the transient state.

9. A method comprising: determining, by a control loop, timing of a pulse signal activating a phase of a coupled inductor voltage regulator based on a current demand of a load circuit; determining, by a transient detection circuit, a projected current through a compensation inductor of the coupled inductor voltage regulator based on a state of the phase and an operating parameter of the coupled inductor voltage regulator; monitoring, in the transient detection circuit, variability in the phase overlap of the test pulse signal to detect a transient condition in the current demand of the load circuit; as well as During at least a portion of the transient condition, a correction is applied to the control loop by the transient detection circuit, the correction changing the timing of the pulse signal based on the projected current through the compensation inductor.

10. The method according to claim 9, further comprising: enabling, by the transient detection circuit, the correction of the control loop based on the variability of the overlap, the variability indicating that the overlap increases beyond a first threshold; as well as Based on the variability indicating the overlap decreasing below a second threshold after exceeding the first threshold, the correction of the control loop is disabled.

11. The method according to claim 9, further comprising: enabling, by the transient detection circuit, the correction of the control loop based on the variability of the overlap, the variability indicating a decrease in the overlap falling below a first threshold; as well as Based on the variability indicating the overlap increasing above a second threshold after falling below the first threshold, the correction of the control loop is disabled.

12. The method according to claim 9, wherein: The correction to the control loop includes one or more of a first correction to an AC portion of the control loop and a second correction to a DC portion of the control loop.

13. The method according to claim 9, further comprising: determining, by the transient detection circuit, the operating parameter of the coupled inductor voltage regulator based at least on an inductance value of the compensation inductor and a voltage across the compensation inductor; as well as The state of the phase is determined by the transient detection circuit based on at least the number of the phases present and the activation state of the phase.

14. The method according to claim 9, wherein: The correction to the control loop includes a scaled combined rate of change of a projected current provided by each phase determined based at least in part on the operating parameter and the projected current through the compensation inductor.

15. The method according to claim 9, wherein: The correction to the control loop includes a load current adjustment to the control loop corresponding to a difference between a reported current demand of the load circuit and a scaled version of the projected current through the compensation inductor.

16. The method according to claim 9, further comprising: A set of programmable registers is provided by the transient detection circuit, the set of programmable registers defining at least an entry threshold and an exit threshold of the transient condition.

17. An apparatus comprising: one or more computer-readable storage media; program instructions stored on the one or more computer-readable storage media, the program instructions being executable by a processing system to direct the processing system to at least: determining a projected current through a compensation inductor of a coupled inductor voltage regulator based on a state of a phase of the coupled inductor voltage regulator and an operating parameter of the coupled inductor voltage regulator; detecting a transient in a current demand of a load circuit provided by the coupled inductor voltage regulator based on variability in the phase-to-phase overlap of the pulse signal; as well as In response to detecting the transient, a correction is applied to a control loop that changes a timing of the pulse signal based on the projected current through the compensation inductor.

18. The apparatus of claim 17, comprising further instructions executable by the processing system to direct the processing system to at least: enabling the correction of the control loop based on the variability of the overlap, the variability indicating an increase in the overlap exceeding a first threshold or a decrease in the overlap falling below a second threshold; and The correction of the control loop is disabled based on the variability of the overlap, the variability indicating a decrease below a third threshold after exceeding the first threshold or an increase above a fourth threshold after falling below the second threshold.

19. The apparatus of claim 17, comprising further instructions executable by the processing system to direct the processing system to at least: determining the operating parameter of the coupled inductor voltage regulator based at least on an inductance value of the compensating inductor and a voltage across the compensating inductor; and The state of the phase is determined based on at least the number of the phases present and the activation state of the phase.

20. The device according to claim 17, wherein: The correction to the control loop includes a load current adjustment to the control loop corresponding to a difference between a reported current demand of the load circuit and a scaled version of the projected current through the compensation inductor.

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