Image sensing device and image sensing method

Abstract

The invention relates to an image sensing apparatus and an image sensing method. An image sensing apparatus includes a latch array including a first latch group, a second latch group, a first latch controller configured to generate a first latch control signal to control the first latch group, and a second latch controller configured to generate a second latch control signal to control the second latch group, the second edge of the second latch control signal occurs after the first edge of the first latch control signal.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a technology capable of reducing power consumption of an image sensing device and an imaging device including the image sensing device. Background Art

[0002] Image sensing devices are devices that capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer, and communications industries, the demand for high-performance image sensing devices is increasing in various fields such as smartphones, digital cameras, game consoles, IoT (Internet of Things), robots, surveillance cameras, and medical micro cameras.

[0003] Recently, image sensing devices for providing high-quality images have become cheaper, smaller in size, and larger in capacity. In addition, as consumer demand for energy efficiency increases, research and development is being conducted to suppress unnecessary power consumption of high-performance image sensing devices. Summary of the invention

[0004] Various embodiments of the present disclosure relate to an image sensing device designed to use a relatively small amount of power and an imaging device including the image sensing device.

[0005] According to an embodiment of the present disclosure, an image sensing device may include: a latch array, comprising: a first latch group, which is configured to store first image data corresponding to a first area of ​​a pixel array; a second latch group, which is configured to store second image data corresponding to a second area of ​​the pixel array; a first latch controller, which is configured to generate a first latch control signal to control the first latch group; and a second latch controller, which is configured to generate a second latch control signal to control the second latch group, wherein a time point at which a second edge of the second latch control signal occurs is set to lag behind a time point at which a first edge of the first latch control signal occurs.

[0006] In some embodiments, the first region may include a first column of the pixel array, and the second region may include a second column of the pixel array.

[0007] In some embodiments, the time point when the first edge occurs may refer to the time point when the first latch control signal transitions from a logic low level to a logic high level, and the time point when the second edge occurs may refer to the time point when the second latch control signal transitions from a logic low level to a logic high level.

[0008] In some embodiments, a pulse width of the first latch control signal and a pulse width of the second latch control signal may be different from each other.

[0009] In some implementations, the first latch controller and the second latch controller may be activated by the same control start signal.

[0010] In some embodiments, the first latch controller may include a plurality of signal delay units (i.e., buffer units), each signal delay unit being configured to delay the start time of an input signal; and a variable switch being configured to adjust a time point at which an edge of the first latch control signal occurs so that different pixel groups included in the first region correspond to edges generated at different time points.

[0011] In some embodiments, the variable switch may adjust the number of signal delay units corresponding to the first region in response to the classification signal, and thus may adjust a time point at which an edge of the first latch control signal occurs.

[0012] In some embodiments, a plurality of pixel groups may refer to pixel groups in which pixels electrically connected to the same analog-to-digital converter (ADC) are grouped together.

[0013] In some embodiments, a plurality of pixel groups may refer to groups in which pixels corresponding to the same color are grouped together.

[0014] According to another embodiment of the present disclosure, an image signal device may include a latch array, which includes: a first latch group, which is configured to store first image data corresponding to a first area of ​​a pixel array; and a second latch group, which is configured to store second image data corresponding to a second area of ​​the pixel array, wherein a time point for storing the second image data in the second latch group is set to lag behind a time point for storing the first image data in the first latch group.

[0015] In some embodiments, the first region may include a first column of the pixel array, and the second region may include a second column of the pixel array.

[0016] In some embodiments, the first latch group can be configured to receive a first latch control signal that determines a storage start time of the first image data, and the second latch group can be configured to receive a second latch control signal that determines a storage start time point of the second image data.

[0017] In some embodiments, the first latch group may be configured to receive a classification signal that adjusts storage start times of different data groups included in the first image data so that different data groups included in the first image data are stored at different time points.

[0018] In some embodiments, the classification signal may be configured to determine a storage start time for each of the plurality of data groups.

[0019] In some implementations, a plurality of data groups may refer to data groups that group together data blocks corresponding to the same analog-to-digital converter (ADC).

[0020] In some embodiments, the plurality of data groups may refer to data groups that group together pixel data blocks of pixels corresponding to the same color.

[0021] According to another embodiment of the present disclosure, an image sensing method may include: detecting a first edge of a first latch control signal by a first latch group included in a latch array; storing first image data corresponding to a first area of ​​a pixel array by the first latch group; detecting a second edge of a second latch control signal by a second latch group included in the latch array; and storing second image data corresponding to a second area of ​​the pixel array by the second latch group at a time point delayed than a storage time of storing the first image data.

[0022] In some embodiments, storing the first image data corresponding to the first region of the pixel array may further include: receiving a first classification signal; and receiving a second classification signal.

[0023] In some embodiments, the step of receiving the first classification signal may include storing a first data group included in the first image data in response to the first classification signal.

[0024] In some embodiments, the step of receiving the second classification signal may include storing the second data group included in the first image data at a time point delayed from another time point at which the first data group is stored.

[0025] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and descriptive and are intended to provide further description of embodiments of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features and advantageous aspects of the present disclosure will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0027] Figure 1 is a block diagram illustrating an imaging device according to some embodiments of the present disclosure.

[0028] Figure 2 Some embodiments of the present disclosure are illustrated. Figure 1 A circuit diagram of pixels included in the pixel array shown.

[0029] Figure 3 Some embodiments of the present disclosure are illustrated. Figure 1 Schematic diagram of an analog-to-digital converter (ADC).

[0030] Figure 4 Some embodiments of the present disclosure are illustrated. Figure 1 A block diagram of an example of a latch control unit and a latch array is shown.

[0031] Figure 5A Some embodiments of the present disclosure are illustrated. Figure 4 The logic circuit diagram of the latch controller is shown.

[0032] Figure 5B Some embodiments of the present disclosure are illustrated. Figure 4 Logic circuit diagram of an example of a latch controller is shown.

[0033] Figure 6 Some embodiments of the present disclosure are illustrated. Figure 5A A timing diagram of the operation of the first latch controller and the second latch controller is shown.

[0034] FIG. 7A to FIG. 7C Some embodiments of the present disclosure are illustrated. Figure 4 The structure and operation of the latch controller are shown in the logic circuit diagram and timing diagram. DETAILED DESCRIPTION

[0035] The present disclosure provides embodiments and examples of image sensing devices capable of reducing power consumption of image sensing devices and imaging devices including the image sensing devices, which can be used in a construction that substantially solves one or more technical or engineering problems and alleviates limitations or shortcomings encountered in some image sensing devices in the art. Some embodiments of the present disclosure relate to image sensing devices designed to use relatively small amounts of electricity and imaging devices including the image sensing devices. Recognizing the above problems, image sensing devices based on some embodiments of the present disclosure can provide higher quality images using relatively small amounts of electricity.

[0036] Some embodiments of the present disclosure shown in the accompanying drawings will now be described in detail. As much as possible, the same reference numerals will be used throughout the entire drawings to refer to the same or similar parts. Although the present disclosure allows for various modifications and alternative forms, its specific embodiments are shown by the accompanying drawings. However, the present disclosure should not be interpreted as being limited to the embodiments set forth herein.

[0037] In the following, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0038] Figure 1 is a block diagram illustrating an imaging device 10 according to some embodiments of the present disclosure.

[0039] Reference Figure 1 The imaging device 10 may be a device such as a digital still camera for capturing still images or a digital video camera for capturing moving images. For example, the imaging device 10 may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, a smart phone, and other similar devices. The imaging device 10 may include a device having both a lens and an image pickup element, so that the device can capture (or capture) a target object and thus can create an image of the target object.

[0040] The imaging device 10 may include an image sensing device 100 and an image signal processor (ISP) 200 .

[0041] The image sensing device 100 may be a complementary metal oxide semiconductor image sensor (CIS) for converting incident light into an electrical signal. The image sensing device 100 may include a pixel array 110, a row driver 120, a ramp generator 130, an analog-to-digital converter (ADC) 140, a column driver 170, a timing controller 180, and a latch control unit 150 and a latch array 160 included in the ADC 140. Figure 1 The components of the image sensing device 100 shown in FIG. 1 may encompass numerous other variations, substitutions, variations, alterations, and modifications.

[0042] The pixel array 110 may include a plurality of unit imaging pixels arranged in rows and columns. For example, a plurality of unit imaging pixels may be arranged in a two-dimensional pixel array including rows and columns. In another example, a plurality of unit imaging pixels may be arranged in a three-dimensional pixel array. A plurality of unit pixels may convert optical signals into electrical signals on a unit pixel basis or on a pixel group basis, wherein the unit pixels in the pixel group share at least some internal circuits. The pixel array 110 may receive a drive signal including a row selection signal, a pixel reset signal, and a transfer signal from the row driver 120. Upon receiving the drive signal, the corresponding imaging pixel in the pixel array 110 may be activated to perform operations corresponding to the row selection signal, the pixel reset signal, and the transfer signal.

[0043] The row driver 120 may activate the pixel array 110 to perform certain operations on the imaging pixels in the corresponding row based on the command and control signals provided by the controller circuit such as the timing controller 180. In some embodiments, the row driver 120 may select one or more imaging pixels arranged in one or more rows of the pixel array 110. The row driver 120 may generate a row selection signal to select one or more rows among the plurality of rows. The row driver 120 may sequentially enable a pixel reset signal for resetting the imaging pixels corresponding to at least one selected row, and a transmission signal for the pixels corresponding to the at least one selected row. Therefore, a reference signal and an image signal, which are analog signals generated by the respective imaging pixels of the selected row, may be sequentially transmitted to the ADC 140. The reference signal may be an electrical signal provided to the ADC 140 when a sensing node (e.g., a floating diffusion node) of the imaging pixel is reset, and the image signal may be an electrical signal provided to the ADC 140 when a photocharge generated by the imaging pixel is accumulated in the sensing node. The reference signal indicating the unique reset noise of each pixel and the image signal indicating the intensity of the incident light may be collectively referred to as a pixel signal as needed.

[0044] CMOS image sensors may use correlated double sampling (CDS) to remove the difference between the two samples by sampling the pixel signal twice, thereby removing undesirable pixel offset values ​​known as fixed pattern noise. In one example, correlated double sampling (CDS) may remove undesirable pixel offset values ​​by comparing the pixel output voltages obtained before and after the photocharges generated by incident light are accumulated in the sensing node, so that the pixel output voltage based only on the incident light may be measured. In some embodiments, ADC 140 may sequentially sample and hold the voltage levels of the reference signal and the image signal provided from pixel array 110 to each of the plurality of column lines.

[0045] The ramp generator 130 may generate a ramp signal required for an analog-to-digital conversion operation of the ADC 140 under the control of the timing controller 180 , and may provide the ramp signal to the ADC 140 .

[0046] ADC 140 can sample and hold pixel signals of each column output from each column line of pixel array 110, can convert the pixel signals into digital signals, and can output digital signals. In some embodiments, ADC 140 can be implemented as a ramp comparison ADC. The ramp comparison ADC can include: a comparator circuit for comparing an analog pixel signal with a ramp signal that ramps up or down; and a timer for performing counting until the voltage of the ramp signal matches the analog pixel signal.

[0047] In some embodiments, the counter included in the ADC 140 may include a latch control unit 150. The latch control unit 150 may control a time point at which the latch array 160 stores a count result generated by the counter 144. In some embodiments, the latch control unit 150 may adjust a time point of one edge of a latch control signal differently, and the latch array 160 may store the count result generated by the counter 144 at a time point of one edge of the latch control signal, and the count result stored in the latch array 160 may correspond to the ADC data output from the ADC 140. For example, the latch array 160 may store the count result generated by the counter 144 at a time point of a rising edge of the latch control signal, and the count result stored in the latch array 160 may correspond to the ADC data output from the ADC 140. In some embodiments, the rising edge may correspond to a signal from a logic low level to a logic high level.

[0048] In some embodiments, the counter included in the ADC 140 may include a latch array 160. The latch array 160 may receive image data of each column unit (i.e., data IDATA obtained by digital conversion of a pixel signal) from the ADC 140, and may temporarily save the received image data (IDATA). The latch array 160 may temporarily store the image data (IDATA) output from the ADC 140 based on a control signal of the timing controller 180. The image data temporarily stored in the latch array 160 may correspond to the ADC data output from the ADC 140.

[0049] The column driver 170 may select a column of the latch array 160 based on a control signal of the timing controller 180, may temporarily store image data (IDATA) of the selected column of the latch array 160, and may control the latch array 160 to sequentially output the temporarily stored image data (IDATA). The output image data (IDATA) may correspond to ADC data. In some embodiments, the column driver 170 may receive an address signal from the timing controller 180, and may generate a column selection signal based on the address signal to select a column of the latch array 160. As a result, the column driver 170 may temporarily store the image data (IDATA) received from the selected column of the latch array 160, and may control the temporarily stored image data (IDATA) to be output to the outside. The output image data (IDATA) may correspond to ADC data. In some embodiments, the counting result generated by the counter 144 may correspond to the image data (IDATA).

[0050] The timing controller 180 may control at least one of the row driver 120 , the ramp generator 130 , the ADC 140 , the latch array 160 , and the column driver 170 .

[0051] The timing controller 180 may provide a clock signal required for the operation of each component of the image sensing device 100, a control signal for timing control, a row address signal for selecting a row, and a column address signal for selecting a column to at least one of the row driver 120, the ramp generator 130, the ADC 140, the latch control unit 150, the latch array 160, and the column driver 170. In some embodiments, the timing controller 180 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0052] The image signal processor 200 may perform image processing of image data received from the image sensing device 100. The image signal processor 200 may reduce noise of the image data, and may perform various types of image signal processing (e.g., interpolation, synthesis, gamma correction, color filter array interpolation, color matrix, color correction, color enhancement, lens distortion correction, etc.) for image quality improvement of the image data. In addition, the image signal processor 200 may compress image data that has been created by performing image signal processing for image quality improvement, so that the image signal processor 200 may create an image file using the compressed image data. Alternatively, the image signal processor 200 may restore the image data from the image file. In this case, the scheme for compressing such image data may be a reversible format or an irreversible format. As a representative example of this compression format, in the case of using a still image, a Joint Photographic Experts Group (JPEG) format, a JPEG2000 format, etc. may be used. In addition, in the case of using a moving image, a plurality of frames may be compressed according to the Moving Picture Experts Group (MPEG) standard so that a moving image file may be created. For example, an image file may be created according to the Exchangeable Image File Format (Exif) standard.

[0053] When an error in the output signal of the ADC 140 occurs due to a delay in the latch control signal, the image signal processor 200 may perform a post-processing operation for the error. For example, when the latch control signal is delayed by the latch control unit 150 as an input to the latch array 160, an error may occur in the output signal output from the ADC 140 after first being temporarily stored in the latch array 160 of the ADC 140. In order to correct this error, the image signal processor 200 may correct the digital code input to the latch array 160 based on the delay time of the latch control signal input to the latch array 160. In some embodiments, when the error caused by the delayed latch control signal is not completely offset (or cancelled), the image signal processor 200 may correct the digital code temporarily stored in the latch array 160 based on the latch control signal and the output signal of the counter.

[0054] The image signal processor 200 may transmit image data (hereinafter referred to as “ISP image data”) on which image processing has been completed to a host device (not shown). The host device (not shown) may be a processor (e.g., an application processor) for processing the ISP image data received from the image signal processor 200, a memory (e.g., a nonvolatile memory) for storing the ISP image data, or a display device (e.g., a liquid crystal display LCD) for visually displaying the ISP image data.

[0055] In addition, the image signal processor 200 may transmit a control signal for controlling the operation (whether to operate, operation timing, operation mode, etc.) of the image sensing device 100 to the image sensing device 100 .

[0056] Figure 2 Some embodiments of the present disclosure are illustrated. Figure 1 2 is a circuit diagram of a pixel (PX) included in the pixel array 110 shown.

[0057] Reference Figure 2 , the pixel (PX) may be one of a plurality of pixels included in the pixel array 110. Although for ease of description, Figure 2 Only one pixel (PX) is shown, but other embodiments are possible, and it should be noted that other pixels may also have substantially the same structure and operation as that of the pixel (PX).

[0058] The pixel (PX) may include a photoelectric conversion element (PD), a transfer transistor (TX), a reset transistor (RX), a floating diffusion region (FD), a source follower transistor (SF), and a selection transistor (SX). Although for ease of description, Figure 2The pixel (PX) is illustrated as including only one photoelectric conversion element (PD), but other embodiments are also possible. Figure 2 The pixel (PX) of FIG. 1 may also be implemented as a shared pixel including a plurality of photoelectric conversion elements. In this case, a plurality of transfer transistors may be provided to correspond to the plurality of photoelectric conversion elements.

[0059] The photoelectric conversion element (PD) can generate and accumulate photoelectric charges corresponding to the intensity of the incident light by photoelectric conversion of the incident light. For example, the photoelectric conversion element (PD) can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0060] When the photoelectric conversion element (PD) is implemented as a photodiode, the photoelectric conversion element (PD) may be a region in which impurities of a second conductivity type (eg, N type) are doped in a substrate having a first conductivity type (eg, P type).

[0061] The transfer transistor (TX) may be connected between the photoelectric conversion element (PD) and the floating diffusion region (FD). The transfer transistor (TX) may be turned on or off in response to a transfer signal (TG), and the turned-on transfer transistor (TX) may transfer the photocharge accumulated in the photoelectric conversion element (PD) to the floating diffusion region (FD).

[0062] The reset transistor (RX) may be connected between a power supply voltage (VDD) and the floating diffusion region (FD), and may reset a voltage of the floating diffusion region (FD) to the power supply voltage (VDD) in response to a pixel reset signal (RG).

[0063] The floating diffusion region (FD) may receive photo charges from the transfer transistor (TX). The floating diffusion region (FD) may be connected to a gate of a source follower transistor (SF) and may be referred to as a sensing node.

[0064] In some embodiments, a logic high level may be a voltage level for activating (eg, turning on) a corresponding device (eg, a transistor), and a logic low level may be a voltage level for deactivating (eg, turning off) a corresponding device (eg, a transistor).

[0065] The source follower transistor (SF) can be connected between the power supply voltage (VDD) and the selection transistor (SX), can amplify the potential change of the floating diffusion area (FD) that has received the photocharge accumulated in the photoelectric conversion element (PD), and can transmit the amplified result to the selection transistor (SX).

[0066] The selection transistor (SX) can be connected between the source follower transistor (SF) and the output signal line and can be turned on by the selection control signal (SEL) so that the selection transistor (SX) can output the electrical signal received from the source follower transistor (SF) as a pixel signal (PS).

[0067] Figure 3 Some embodiments of the present disclosure are illustrated. Figure 1 A block diagram of an analog-to-digital converter (ADC) 140 is shown.

[0068] Reference Figure 3 ADC 140 may receive a ramp signal (V ramp ), a pixel signal (PS) may be received from a pixel (PX), and a ramp signal (V ramp ) and the pixel signal (PS) to generate comparison data (CDS_OUT) corresponding to the correlated double sampling (CDS) output data, so that the latch control unit 150 can generate a latch control signal (LCS) based on the comparison data (CDS_OUT). In addition, the ADC 140 can control the time point at which the counting result is stored in the storage latch array 160 based on the latch control signal (LCS), and can generate and output ADC data (ADC_OUT) based on the data stored in the latch array 160.

[0069] The ADC 140 may include a first capacitor ( C1 ) and a second capacitor ( C2 ), a comparator 142 , and a counter 144 .

[0070] The first capacitor C1 can receive the ramp signal (V ramp ), and the ramp signal (V ramp ) is sent to the comparator 142. The second capacitor C2 may receive the pixel signal (PS) and may send the pixel signal (PS) to the comparator 142.

[0071] The comparator 142 can convert the ramp signal (V ramp ) is compared with the pixel signal (PS), and comparison data (CDS_OUT) can be generated according to the comparison result, and the comparison data (CDS_OUT) can be sent to the counter 144. In some embodiments, when the ramp signal (V ramp ) is greater than the pixel signal (PS), the comparator 142 can generate a comparison data (CDS_OUT) of a logic high level. In addition, if the ramp signal (V ramp ) is less than the pixel signal (PS), the comparator 142 may generate a comparison data (CDS_OUT) of a logic low level. That is, the comparison data (CDS_OUT) may represent the ramp signal (Vramp ) and the amplitude relationship between the pixel signal (PS).

[0072] The counter 144 may be activated in response to the counter enable signal (CNT_EN). The activated counter 144 may perform counting in response to the comparison data (CDS_OUT) of the logic high level, and may output the counting result as ADC data (ADC_OUT). Here, the ADC data (ADC_OUT) may correspond to Figure 1 In some embodiments, the counter 144 may enable the latch control unit 150 to generate a latch control signal (LCS) based on the comparison data (CDS_OUT), and may store the counting result in the latch array 160 based on the latch control signal (LCS).

[0073] The latch control unit 150 may be activated in response to the latch control unit enable signal (LCU_EN), and the activated latch control unit 150 may output a latch control signal (LCS) in response to the comparison data (CDS_OUT) of a logic high level. In some embodiments, the latch control unit 150 may receive the comparison data (CDS_OUT) from the comparator 142, and may generate and output a latch control signal LCS based on the comparison data (CDS_OUT). In some embodiments, the latch control signal (LCS) may control a point in time at which a counting result is stored in the latch array, and the result stored in the latch array may correspond to the ADC data (ADC_OUT) output from the ADC 140.

[0074] Figure 4 Some embodiments of the present disclosure are illustrated. Figure 1 A block diagram of a latch control unit 150 and a latch array 160 is shown.

[0075] Reference Figure 4 , the latch control unit 150 may include latch controllers (e.g., 150-1, 150-2, and 150-n) respectively corresponding to the columns of the pixel array 110. Here, the latch array 160 may include latch groups (e.g., 160-1, 160-2, and 160-n) respectively electrically connected to the latch controllers (e.g., 150-1, 150-2, and 150-n).

[0076] Each column of the pixel array 110 may correspond to a latch controller. In some embodiments, a signal from a pixel output of a first column corresponding to a latch controller (e.g., 150-1) may be used to generate comparison data (CDS_OUT) by ADC 140. At this time, the latch controller (e.g., 150-1) may receive the generated comparison data (CDS_OUT). In some implementations, each column may correspond to a latch controller. For example, the first column of the pixel array 110 may correspond to the first latch controller 150-1, and the second column of the pixel array 110 may correspond to the second latch controller 150-2. In some other embodiments, a plurality of columns may correspond to a latch controller. For example, an odd-numbered column may correspond to the first latch controller 150-1, and an even-numbered column may correspond to the second latch controller 150-2.

[0077] The latch control unit 150 may receive a plurality of comparison data (e.g., CDS_OUT-1, CDS_OUT-2, CDS_OUT-n) respectively corresponding to the columns of the pixel array 110, and may generate and output a latch control signal (e.g., LCS1, LCS2, LCSn) based on the comparison data. For example, the first latch controller 150-1 may receive the first comparison data (CDS_OUT-1) corresponding to the first column, and may generate and output a first latch control signal (LCS1).

[0078] The latch array 160 may store the result counted by the counter 144 in response to latch control signals (e.g., LCS1, LCS2, LCSn) respectively corresponding to the columns of the pixel array 110, and the counter 144 may output a plurality of ADC data (e.g., ADC_OUT1, ADC_OUT2, ADC_OUTn) for each column based on the stored count result. For example, the first latch group 160-1 electrically connected to the first latch controller 150-1 may store the count data of the first column in the order of the digital code in response to the first latch control signal (LCS1). Here, the count data of the first column stored may correspond to the first ADC data (ADC_OUT1).

[0079] In some implementations, the first latch controller 150-1 may correspond to the first column of the pixel array 110. In the ADC 140, the comparator (eg, Figure 3 The ADC 142 may generate the first comparison data (CDS_OUT1) by comparing the pixel data of the pixels included in the first column of the pixel array 110 with the ramp signal. Additionally, in the ADC 140, the first comparison data (CDS_OUT1) may be generated by a counter (eg, Figure 3144) is converted into the first ADC data (ADC_OUT1). At this time, the first latch controller 150-1 can receive the latch control unit enable signal (LCU_EN) and the first comparison data (CDS_OUT1) to generate a first latch control signal (LCS1). The first latch group 160-1 can receive the first latch control signal (LCS1) and can store the count data of the first column at the rising edge of the first latch control signal (LCS1). The stored count data of the first column can be output as the first ADC data (ADC_OUT1).

[0080] For example, the first latch group 160-1 may include a plurality of latches (latch 1 (400-1) to latch m (400-m)). When a rising edge of the first latch control signal (LCS1) is detected, the first latch group 160-1 may store data at a first position of count data corresponding to the first column in latch 1 (400-1). When a rising edge of the first latch control signal (LCS1) is detected, the first latch group 160-1 may store data at a second position of count data of the first column in latch 2 (400-2). Similarly, data (ADC_OUT1[2]) at a third position of count data of the first column may be stored in latch 3 (400-3). The number of bits of the ADC data (ADC_OUT1) may be less than the number of latches (e.g., m) included in the latch group (e.g., 160-1). The above-described embodiment may also be applied to the second column of the pixel array 110 and the second latch group 160 - 2 corresponding to the second latch controller 150 - 2 .

[0081] In some embodiments, the count data of the first column stored in the latches (Latch 1 ( 400 - 1 ) to Latch n ( 400 - n )) of the first latch group 160 - 1 may correspond to the first ADC data (ADC_OUT1 ).

[0082] In some other embodiments, the latch array 160 may store the count results counted by the counter 144 in response to latch control signals respectively corresponding to the plurality of columns of the pixel array 110, and the counter 144 may output a plurality of ADC data for each column based on the stored count results. For example, a latch group electrically connected to the latch controller may store the count data of the plurality of columns in the order of the digital code in response to the latch control signal, and may convert the stored count data of the plurality of columns into ADC data corresponding thereto.

[0083] In some other embodiments, the first composite latch controller (not shown) may correspond to a plurality of columns of the pixel array 110. For example, a comparator (e.g., Figure 3 The ADC 142 may compare the pixel data of the pixels included in the first column and the second column of the pixel array 110 with the ramp signal, and may generate the first comparison data (CDS_OUT1) and the second comparison data (CDS_OUT2) based on the comparison result. In addition, in the ADC 140, the counter (e.g., Figure 3 144) converts the first comparison data (CDS_OUT1) into the first ADC data (ADC_OUT1), and can be obtained by a counter (for example, Figure 3 144) converts the second comparison data (CDS_OUT2) into the second ADC data (ADC_OUT2). In this case, the first composite latch controller (not shown) can receive the latch control unit enable signal (LCU_EN), the first comparison data (CDS_OUT1) and the second comparison data (CDS_OUT2), and can generate a first composite latch control signal (not shown). The first latch group 160-1 and the second latch group 160-2 can receive the first composite latch control signal (not shown), and can store the counting result corresponding to the first comparison data (CDS_OUT1) and the counting result corresponding to the second comparison data (CDS_OUT2) at the time point of the rising edge of the first composite latch control signal (not shown). In some embodiments, the counting result corresponding to the first comparison data (CDS_OUT1) and the counting result corresponding to the second comparison data (CDS_OUT2) can correspond to the first ADC data (ADC_OUT1) and the second ADC data (ADC_OUT2), respectively.

[0084] For example, the first latch group 160-1 may include a plurality of latches (latch 1 (400-1) to latch m (400-m)). When a rising edge of a first composite latch control signal (not shown) is detected, the first latch group 160-1 may store data located at a first position of count data corresponding to the first column in latch 1 (400-1). When a rising edge of a first composite latch control signal (not shown) is detected, the first latch group 160-1 may store data located at a second position of count data corresponding to the first column in latch 2 (400-2). Similarly, data located at a third position of count data corresponding to the first column (ADC_OUT1[2]) may be stored in latch 3 (400-3). In addition, the second latch group 160-2 may include a plurality of latches (latch 1 (410-1) to latch m (410-m)). When a rising edge of a first composite latch control signal (not shown) is detected, the second latch group 160-2 may store data located at a first position of count data corresponding to the second column in latch 1 (400-1). When a rising edge of a first composite latch control signal (not shown) is detected, the second latch group 160-2 may store data located at a second position of count data corresponding to the second column (ADC_OUT2[1]) in latch 2 (410-2). Similarly, data located at a third position of count data corresponding to the second column (ADC_OUT2[2]) may be stored in latch 3 (410-3). The number of bits of the first ADC data (ADC_OUT1) may be smaller than the number of latches (e.g., m) included in the latch group (e.g., 160-1), and the number of bits of the second ADC data (ADC_OUT2) may be smaller than the number of latches (e.g., m) included in the latch group (e.g., 160-2). The above embodiment can be applied not only to the third and fourth columns of the pixel array 110 corresponding to the second composite latch controller (not shown), but also to the third latch group 160 - 3 and the fourth latch group (not shown) of the pixel array 110 .

[0085] In some embodiments, the count data of the first column stored in the latches (latch 1 (400-1) to latch m (400-m)) and the count data of the second column stored in the latches (latch 1 (410-1) to latch m (410-m)) may correspond to the first ADC data (ADC_OUT1) and the second ADC data (ADC_OUT2), respectively.

[0086] Figure 5A Some embodiments of the present disclosure are illustrated. Figure 4 The logic circuit diagram of the latch controller is shown in .

[0087] Reference Figure 5A , the latch controllers (e.g., 150-1, 150-2, and 150-n) can respectively receive a latch control unit enable signal (LCU_EN) and comparison data (e.g., CDS_OUT1, CDS_OUT2, CDS_OUTn), and can respectively output latch control signals (e.g., LCS1, LCS2, LCSn). In more detail, the latch controller (150-1) can receive a latch control unit enable signal (LCU_EN) and comparison data (CDS_OUT1) to output a latch control signal (LCS1), the latch controller (150-2) can receive a latch control unit enable signal (LCU_EN) and comparison data (CDS_OUT2) to output a latch control signal (LCS2), and the latch controller (150-n) can receive a latch control unit enable signal (LCU_EN) and comparison data (CDS_OUTn) to output a latch control signal (LCSn).

[0088] The latch controller (e.g., 150-1, 150-2, 150-n) may include different logic circuit structures. In some embodiments, the latch controller (e.g., 150-1, 150-2, 150-n) may include at least one logical product element (e.g., 500, 510, 520), at least one logical non-element (e.g., 502, 512, 522), and at least one signal delay unit (e.g., 503, 513, 514, 523, 524). For example, the first latch controller 150-1 may include two logical product elements (500, 501), one logical non-element 502 and four signal delay units 503, and the second latch controller 150-2 may include two more signal delay units 514 than the first latch controller 150-1.

[0089] In some embodiments, the second edge of the second latch control signal (LCS2) may be later than the first edge of the first latch control signal (LCS1). For example, the rising edge of the second latch control signal (LCS2) may be later than the rising edge of the first latch control signal (LCS1). In some embodiments, the first edge may correspond to at least one rising edge of the first latch control signal, and the second edge may correspond to at least one rising edge of the second latch control signal.

[0090] The latch groups (e.g., 160-1, 160-2, 160-n) can store counting results corresponding to the comparison data (e.g., CDS_OUT1, CDS_OUT2, CDS_OUTn) at the time point of the rising edge of the latch control signal (e.g., LCS1, LCS2, LCSn). The counting results corresponding to the plurality of comparison data can correspond to the ADC data (e.g., ADC_OUT1, ADC_OUT2, ADC_OUTn), respectively. For example, when the rising edge of the first latch control signal (LCS1) occurs, the first latch group 160-1 can store the counting data of the first column at the corresponding bit position according to the order of the digital code, and the stored counting data of the first column can correspond to the first ADC data (ADC_OUT1).

[0091] In some embodiments, as can be seen from the first latch controller 150-1, the input terminal of the logical NOT element 502 can be connected to the output terminal of the first logical product element 500, and the output terminal of the logical NOT element 502 can be connected to the first input terminal of the second logical product element 501. In addition, the input terminal of the signal delay unit 503 can be connected to the output terminal of the first logical product element 500, and the output terminal of the signal delay unit 503 can be connected to the second input terminal of the second logical product element 501.

[0092] In some embodiments, the first latch controller 150-1 may perform the following operations. When the latch control unit enable signal (LCU_EN) is maintained at a logic high level and the first comparison data (CDS_OUT1) is changed from a logic high level to a logic low level, the output signal of the first logical product element 500 may be changed from a logic high level to a logic low level. At the same time (i.e., when the latch control unit enable signal (LCU_EN) is maintained at a logic high level and the first comparison data (CDS_OUT1) is changed from a logic high level to a logic low level), the output signal of the logical NOT element 502 may be changed from a logic low level to a logic high level. In addition, the output signal of the signal delay unit 503 may be changed from a logic high level to a logic low level at a unit time amount after the output signal of the logical NOT element 502 is changed, and the unit time amount is defined by the signal delay unit 503. In this process, since the logical NOT element 502 of the second logical product element 501 and the signal delay unit 503 simultaneously have a logic high level during the unit time amount defined by the signal delay unit 503, the first latch control signal (LCS1) can be expressed as a pulse-shaped signal with a rising edge and a falling edge. In some embodiments, the falling edge can correspond to a signal from a logic high level to a logic low level.

[0093] In some embodiments, it can be seen from the second latch controller 150-2 that, unlike the first latch controller 150-1, the input terminal of the additional signal delay unit 514 can be connected to the first logical product element 510, and the output terminal of the additional signal delay unit 514 can be connected to the input terminal of the logical NOT element 512 and the input terminal of the signal delay unit 513.

[0094] In some embodiments, the second latch controller 150-2 may perform the following operations. When the latch control unit enable signal (LCU_EN) is maintained at a logic high level and the second comparison data (CDS_OUT2) is changed from a logic high level to a logic low level, the output signal of the first logical product element 510 may be changed from a logic high level to a logic low level. After the unit time amount defined by the additional signal delay unit 514, the output signal of the logical non-element 512 may be changed from a logic low level to a logic high level. In addition, the output signal of the signal delay unit 513 may be changed from a logic high level to a logic low level at a unit time amount after the output signal of the logical non-element 512 is changed, and the unit time amount is defined by the signal delay unit 513. In this process, since the logical non-element 512 and the signal delay unit 513 have a logic high level at the same time during the unit time amount defined by the signal delay unit 513, the second latch control signal (LCS2) of the second logical product element 511 may be expressed as a pulse-shaped signal with a rising edge and a falling edge.

[0095] In some embodiments, it can be seen from the Nth latch controller (150-n) that, unlike the first latch controller 150-1, the input terminal of the additional signal delay unit 524 can be connected to the first logical product element 520, and the output terminal of the additional signal delay unit 524 can be connected to the input terminal of the logical negation element 522 and the input terminal of the signal delay unit 523. The additional signal delay unit 524 may include 2 (n-1) signal delay buffer units.

[0096] Figure 5B Some embodiments of the present disclosure are illustrated. Figure 4 The logic circuit diagram of the latch controller is shown in .

[0097] Reference Figure 5B , the latch controllers (e.g., 150-1, 150-2, 150-n) can respectively receive the latch control unit enable signal (LCU_EN) and the comparison data (e.g., CDS_OUT-1, CDS_OUT-2, CDS_OUT-n), and can respectively output latch control signals (e.g., LCS1, LCS2, LCSn).

[0098] The latch controller (e.g., 150-1, 150-2, 150-n) may include different logic circuit structures. In some embodiments, the latch controller may include at least one logical product element (e.g., 530, 531, 540, 541, 550, 551), at least one logical non-element (e.g., 532, 542, 552), and at least one signal delay unit (e.g., 533, 543, 544, 553, 554). For example, the first latch controller 150-1 may include two logical product elements (two AND gates), one logical non-element (one NOT gate) and four signal delay units (four buffer units). The second latch controller 150-2 may include four more signal delay units (four buffer units) than the first latch controller 150-1. Two of the four signal delay units (four buffer units) may be connected in series to the logical non-element (NOT gate), and the remaining two signal delay units may be connected in parallel to the logical non-element (NOT gate).

[0099] In some implementations, the second edge of the second latch control signal (LCS2) may be later than the first edge of the first latch control signal (LCS1). For example, the rising edge of the second latch control signal (LCS2) may be later than the rising edge of the first latch control signal (LCS1), and the falling edge of the second latch control signal (LCS2) may be later than the falling edge of the first latch control signal (LCS1).

[0100] The latch group (e.g., 160-1, 160-2, 160-n) can store the counting result corresponding to the comparison data (e.g., CDS_OUT1, CDS_OUT2, CDS_OUTn) at the time point of the rising edge of the latch control signal (e.g., LCS1, LCS2, LCSn). In this case, the counting result corresponding to such comparison data can correspond to the ADC data (e.g., ADC_OUT1, ADC_OUT2, ADC_OUTn). For example, when the rising edge of the first latch control signal (LCS1) occurs, the first latch group 160-1 can store the counting data of the first column at the corresponding bit position according to the order of the digital code. The stored counting data of the first column can correspond to the first ADC data (ADC_OUT1).

[0101] In some embodiments, as can be seen from the first latch controller 150-1, the input terminal of the logical NOT element 532 can be connected to the output terminal of the first logical product element 530, and the output terminal of the logical NOT element 532 can be connected to the first input terminal of the second logical product element 531. In addition, the input terminal of the signal delay unit 533 can be connected to the output terminal of the first logical product element 530, and the output terminal of the signal delay unit 533 can be connected to the second input terminal of the second logical product element 531.

[0102] In some embodiments, the first latch controller 150-1 may perform the following operations. When the latch control unit enable signal (LCU_EN) is maintained at a logic high level and the first comparison data (CDS_OUT1) is changed from a logic high level to a logic low level, the output signal of the first logical product element 530 may be changed from a logic high level to a logic low level. At the same time (i.e., when the latch control unit enable signal (LCU_EN) is maintained at a logic high level and the first comparison data (CDS_OUT1) is changed from a logic high level to a logic low level), the output signal of the logical NOT element 532 may be changed from a logic low level to a logic high level. In addition, the output signal of the signal delay unit 533 may be changed from a logic high level to a logic low level at a unit time amount after the output signal of the logical NOT element 532 is changed, and the unit time amount is defined by the signal delay unit 533. In this process, since the logical NOT element 532 and the signal delay unit 533 both have a logic high level during the unit time amount defined by the signal delay unit 533, the first latch control signal (LCS1) of the second logical product element 531 can appear as a pulse-shaped signal with a rising edge and a falling edge.

[0103] In some embodiments, it can be seen from the second latch controller 150-2 that, unlike the first latch controller 150-1, the signal delay unit 543 can include two more signal delay buffer units, the input terminal of the additional signal delay unit 544 can be connected to the first logical product element 540, and the output terminal of the additional signal delay unit 544 can be connected to the input terminal of the logical NOT element 542 and the input terminal of the signal delay unit 543.

[0104] In some embodiments, the second latch controller 150-2 may perform the following operations. When the latch control unit enable signal (LCU_EN) is maintained at a logic high level and the second comparison data (CDS_OUT2) is changed from a logic high level to a logic low level, the output signal of the first logical product element 540 may be changed from a logic high level to a logic low level. After the unit time amount defined by the additional signal delay unit 544, the output signal of the logical non-element 542 may be changed from a logic low level to a logic high level. In addition, the output signal of the signal delay unit 543 may be changed from a logic high level to a logic low level at a unit time amount after the output signal of the logical non-element 542 is changed, and the unit time amount is defined by the signal delay unit 543. In this process, since the logical non-element 542 and the signal delay unit 543 have a logic high level at the same time during the unit time amount defined by the signal delay unit 543, the second latch control signal (LCS2) of the second logical product element 541 may output a pulse-shaped signal having a rising edge and a falling edge.

[0105] In some embodiments, it can be seen from the Nth latch controller (150-n) that, unlike the first latch controller 150-1, the signal delay unit 553 may include 2(n-1) more signal delay buffer units than the first latch controller 150-1, the input terminal of the additional signal delay unit 554 may be connected to the first logical product element 550, and the output terminal of the additional signal delay unit 554 may be connected to the input terminal of the logical negation element 552 and the input terminal of the signal delay unit 553. The additional signal delay unit 554 may include 2(n-1) signal delay buffer units.

[0106] In some embodiments, the falling edge of the second latch control signal (LCS2) may be later than the falling edge of the first latch control signal (LCS1). For example, the falling edge of the output signal of the signal delay unit 543 of the second latch controller 150-2 may be later than the falling edge of the signal of the signal delay unit 533 of the first latch controller 150-1 by a delay time amount, the delay time amount being defined by two signal delay buffer units. In this case, the pulse width of the second latch control signal (LCS2) may be greater than the pulse width of the first latch control signal (LCS1).

[0107] In some embodiments, the pulse width of the first latch control signal (LCS1) or the pulse width of the second latch control signal (LCS2) may be adjusted to control the voltage level to be provided to the first latch group 160-1 or the voltage level to be provided to the second latch group 160-2. For example, when the voltage is provided to the counter 144 through the left and right ends of the counter 144, the voltage level may be reduced in response to the flow of current. As a result, the power supply voltage level may be gradually reduced from one of the latches located at both ends of the latch array 160 to the central latch (e.g., 160-2). For example, since the first latch group 160-1 has a high power supply voltage level, the first latch group 160-1 may store data even when the pulse width of the first latch control signal (LCS1) has a short pulse width. On the contrary, since the second latch group 160-2 has a low power supply voltage level, when the pulse width of the second latch control signal (LCS2) has a short pulse width, the second latch group 160-2 may not store data. In this case, when the pulse width of the first latch control signal (LCS1) is set to a small width and the pulse width of the second latch control signal (LCS2) is set to a large width, the power consumption required to operate the counter 144 can be optimized.

[0108] Figure 6 Some embodiments of the present disclosure are illustrated. Figure 5A A timing diagram of the operation of the first latch controller and the second latch controller is shown.

[0109] Reference Figure 6 , each latch control signal (e.g., LCS1, LCS2) can transition from a logic low level to a logic high level. In addition, the signal generated when each latch control signal transitions from a logic low level to a logic high level can be defined as a rising edge of the signal, and the signal generated when each latch control signal transitions from a logic high level to a logic low level can be defined as a falling edge of the signal.

[0110] When the latch control unit enable signal (LCU_EN) has a logic high level, the first comparison data (CDS_OUT1) and the second comparison data (CDS_OUT2) are simultaneously changed from a logic high level to a logic low level. Here, the rising edge or falling edge of the latch control signal (e.g., LCS1, LCS2) can be controlled by a logical NOT element (e.g., Figure 5A 502 and 512), a signal delay unit (eg, Figure 5A 503, 513 and 514), and logical product elements (e.g., Figure 5A 500, 501, 510 and 511) occur.

[0111] In some embodiments, when the latch control unit enable signal (LCU_EN) has a logic high level and the first comparison data (CDS_OUT1) has a logic high level, the terminal (A) may be connected due to a logical NOT element (eg, Figure 5A 502) has a logic low level, while the terminal (B) may be due to a logical NOT element (e.g., Figure 5A Thereafter, when the first comparison data (CDS_OUT1) changes from the logic high level to the logic low level, the terminal (A) may immediately have the logic high level. In addition, the terminal (B) may have the logic low level at a unit time amount after the terminal (A) becomes the logic high level, the unit time amount being determined by the four signal delay units (e.g., Figure 5A When the signal input to the terminal (A) and the signal input to the terminal (B) are input to the logical product element (for example, Figure 5A 501), the first latch control signal (LCS1) can be changed from a logic low level to a logic high level (i.e., changed to a rising edge) at a time point (t1) when the terminal (A) is changed to a logic high level (i.e., a rising edge), and can be changed from a logic high level to a logic low level (i.e., a falling edge) at a time point when the terminal (B) is changed to a logic low level (i.e., a falling edge).

[0112] In some embodiments, when the latch control unit enable signal (LCU_EN) has a logic high level and the second comparison data (CDS_OUT2) has a logic high level, the terminal (C) may be turned on due to a logical NOT element (eg, Figure 5A 512) has a logic low level and can be due to a logical NOT element (e.g., Figure 5A Thereafter, the terminal (C) may have a logic high level at a delay time amount after the second comparison data (CDS_OUT2) transitions from a logic high level to a logic low level, due to the two signal delay units (eg, Figure 5A 514), the delay time amount is defined by two signal delay units. In addition, the terminal (D) may have a logic low level at a delay time amount after the second comparison data (CDS_OUT2) transitions from a logic high level to a logic low level, which is defined by six signal delay units due to the two signal delay units connected in series with each other and the four signal delay units connected in series with each other. When the signal input to the terminal (C) and the signal input to the terminal (D) are input to the logical product element (e.g., Figure 5A511), the second latch control signal (LCS2) can be changed from a logic low level to a logic high level (i.e., a rising edge) at a time point (t2) when the node (C) is changed to a logic high level (i.e., a rising edge), and can be changed from a logic high level to a logic low level (i.e., a falling edge) at a time point when the node (D) is changed to a logic low level (i.e., a falling edge).

[0113] In some implementations, each latch group (e.g., Figure 4 160-1, 160-2, and 160-n) can store the counting results at the time points (e.g., t1, t2) of the rising edges of the respective latch control signals (LCS1, LCS2), and the ADC 140 can output the stored counting results as ADC data. Figure 4 , at the time point (t1) of the rising edge of the first latch control signal (LCS1), the first latch group 160-1 may include a plurality of latches (latch 1 (400-1) to latch m (400-m)). At the time point of the rising edge of the first latch control signal (LCS1), latch 1 (400-1) of the first latch group 160-1 may store data at a first position of the count data of the first column, and latch 2 (400-2) of the first latch group 160-1 may store data at a second position of the count data of the first column. Similarly, data at a third position of the count data of the first column may be stored in latch 3 (400-3). The number of bits of the ADC data (ADC_OUT1) may be less than the number of latches (e.g., m) included in the latch group (e.g., 160-1). The above-described embodiment may be applied not only to the second column corresponding to the second latch controller 150 - 2 in the pixel array 110 , but also to the second latch group 160 - 2 .

[0114] In some embodiments, the first edge of the first latch control signal (LCS1) and the second edge of the second latch control signal (LCS2) occur at different time points, so the time points at which data are stored in the respective first latch groups and second latch groups become different from each other. As a result, the peak current flowing in the imaging device 10 can be reduced.

[0115] FIG. 7A to FIG. 7C Some embodiments of the present disclosure are illustrated. Figure 4 The structure and operation of the latch controller are shown in the logic circuit diagram and timing diagram.

[0116] Reference Fig. 7A, the first latch controller 150-1 may receive the first classification signal (DCS1), the latch control unit enable signal (LCU_EN), and the first comparison data (CDS_OUT1), and may output the first latch control signal (LCS100) when the first switch 707 is closed. The first classification signal (DCS1) may be generated and provided by the timing controller 180 in response to some of the pixels corresponding to the first latch controller 150-1.

[0117] In some embodiments, the first latch controller 150-1 may include a logical product element (e.g., 700, 701), a logical negation element (e.g., 702), a switch (e.g., 707, 708, 709), and a signal delay unit (e.g., 703, 704, 705). For example, the first latch controller 150-1 may include two logical product elements (700, 701), one logical negation element 702, three switches (707, 708, 709), and a signal delay unit (703, 704, 705), and may include information about the closed state of the first switch 707 among the three switches.

[0118] In some embodiments, when the latch control unit enable signal (LCU_EN) has a logic high level and the first comparison data (CDS_OUT1) has a logic high level, the terminal (A) may have a logic low level due to the logical NOT element 702, and the terminal (B) may have a logic high level due to the logical NOT element 702. Thereafter, when the first comparison data (CDS_OUT11) transitions to a logic low level, the terminal (A) immediately has a logic high level. In addition, the terminal (B) has a logic low level at a unit time amount immediately after the terminal (A) has a logic high level, and the unit time amount is defined by 8 signal delay units due to the signal delay units (703, 704, 705). When a signal input to terminal (A) and a signal input to terminal (B) are input to the logical product element 701, the first latch control signal (LCS100) generated when the first switch 707 is closed can be changed from a logic low level to a logic high level (i.e., a rising edge) at a time point (t5) when the terminal (A) is changed to a logic high level (i.e., a rising edge), and can be changed from a logic high level to a logic low level at a time point when the terminal (B) is changed to a logic low level (i.e., a falling edge).

[0119] In some embodiments, at the time point of the rising edge of the first latch control signal (LCS100) when the first switch 707 is closed, the count data is stored in each latch. For example, at the time point (t5) of the rising edge of the first latch control signal (LCS100) when the first switch 707 is closed, the first latch group 160-1 can store the count data of the first column at the corresponding bit position according to the order of the digital code. In this case, the data stored in the first latch group 160-1 can correspond to the pixel data of the pixel corresponding to the first classification signal (DCS1).

[0120] Reference Figure 7B , the first latch controller 150-1 may receive the second classification signal (DCS2), the latch control unit enable signal (LCU_EN), and the first comparison data (CDS_OUT1), and may output the second latch control signal (LCS101) when the second switch 708 is closed. The second classification signal (DCS2) may be generated and provided by the timing controller 180 in response to some of the pixels corresponding to the first latch controller 150-1.

[0121] In some embodiments, the first latch controller 150-1 may include a logical product element (e.g., 700, 701), a logical negation element (e.g., 702), a switch (e.g., 707, 708, 709), and a signal delay unit (e.g., 703, 704, 705). For example, the first latch controller 150-1 may include two logical product elements (700, 701), one logical negation element 702, three switches (707, 708, 709), and a signal delay unit (703, 704, 705), and may include information about the closed state of the second switch 708 among the three switches.

[0122] In some embodiments, when the latch control unit enable signal (LCU_EN) has a logic high level and the first comparison data (CDS_OUT1) has a logic high level, the terminal (A) has a logic low level due to the logical NOT element 702, and the terminal (B) has a logic high level due to the logical NOT element 702. Thereafter, the terminal (A) may have a logic high level at a unit time amount after the first comparison data (CDS_OUT1) turns to a logic low level, and the unit time amount is defined by two signal delay units due to the signal delay unit 703. In addition, the terminal (B) may have a logic low level at a unit time amount after the terminal (A) becomes to have a logic high level, and the unit time amount is defined by 8 signal delay units due to the signal delay units (703, 704, 705). When a signal input to terminal (A) and a signal input to terminal (B) are input to the logical product element 701, the second latch control signal (LCS101) generated when the second switch 708 is closed can be changed from a logic low level to a logic high level (i.e., a rising edge) at a time point (t6) when the terminal (A) is changed to a logic high level (i.e., a rising edge), and can be changed from a logic high level to a logic low level (i.e., a falling edge) at a time point when the terminal (B) is changed to a logic low level (i.e., a falling edge).

[0123] In some embodiments, at the time point of the rising edge of the second latch control signal (LCS101) when the second switch 708 is closed, the count data is stored in each latch. For example, at the time point (t6) of the rising edge of the second latch control signal (LCS101) when the second switch 708 is closed, the first latch group 160-1 can store the count data of the first column at the corresponding bit position according to the order of the digital code. In this case, the data stored in the first latch group 160-1 can correspond to the pixel data of the pixel corresponding to the second classification signal (DCS2).

[0124] Reference Figure 7C , the first latch controller 150-1 may receive the third classification signal (DCS3), the latch control unit enable signal (LCU_EN) and the first comparison data (CDS_OUT1), and may output the third latch control signal (LCS110) when the third switch SW3 is closed. The third classification signal (DCS3) may be generated and provided by the timing controller 180 in response to some of the pixels corresponding to the first latch controller 150-1.

[0125] In some embodiments, the first latch controller 150-1 may include a logical product element (e.g., 700, 701), a logical negation element (e.g., 702), a switch (e.g., 707, 708, 709), and a signal delay unit (e.g., 703, 704, 705). For example, the first latch controller 150-1 may include two logical product elements (700, 701), one logical negation element 702, three switches (707, 708, 709), and a signal delay unit (703, 704, 705), and may include information about the closed state of the first switch 707 among the three switches.

[0126] In some embodiments, when the latch control unit enable signal (LCU_EN) has a logic high level and the first comparison data (CDS_OUT1) has a logic high level, the terminal (A) has a logic low level due to the logical NOT element 702, and the terminal (B) has a logic high level due to the logical NOT element 702. Thereafter, the terminal (A) may have a logic high level at a unit time amount after the first comparison data (CDS_OUT1) transitions to a logic low level, and the unit time amount is defined by four signal delay units due to the signal delay units (703, 704). In addition, the terminal (B) may have a logic low level at a unit time amount after the first comparison data (CDS_OUT1) transitions to a logic low level, and the unit time amount is defined by 8 signal delay units due to the signal delay units (703, 704, 705). When a signal input to terminal (A) and a signal input to terminal (B) are input to the logical product element 701, the third latch control signal (LCS110) generated when the third switch 709 is closed can be changed from a logic low level to a logic high level (i.e., a rising edge) at a time point (t7) when the terminal (A) is changed to a logic high level (i.e., a rising edge), and can be changed from a logic high level to a logic low level (i.e., a falling edge) at a time point when the terminal (B) is changed to a logic low level (i.e., a falling edge).

[0127] In some embodiments, at the time point of the rising edge of the third latch control signal (LCS110) when the third switch 709 is closed, the count data is stored in each latch. For example, at the time point (t7) of the rising edge of the third latch control signal (LCS110) when the third switch 709 is closed, the first latch group 160-1 can store the count data of the first column at the corresponding bit position according to the order of the digital code. In this case, the data stored in the first latch group 160-1 can correspond to the pixel data of the pixel corresponding to the third classification signal (DCS3).

[0128] In some embodiments, the composite latch controller (not shown) may output a first latch control signal (LCS100) by matching pixels belonging to a first column of the pixel array 110 to a first classification signal (DCS1), may output a second latch control signal (LCS101) by matching pixels belonging to a second column of the pixel array 110 to a second classification signal (DCS2), and may output a third latch control signal (LCS110) by matching pixels belonging to a third column of the pixel array 110 to a third classification signal (DCS3). For example, at a time point (t5) of a rising edge of the first latch control signal (LCS100) when the first switch 707 is closed and the remaining switches (708, 709) are open, the first latch group 160-1 may store count data corresponding to the first column at corresponding bit positions in the order of the digital code. At the time point (t6) of the rising edge of the second latch control signal (LCS101) when the second switch 708 is closed and the remaining switches (707, 709) are disconnected, the second latch group 160-2 can store the count data corresponding to the second column at the corresponding bit position according to the order of the digital code. In addition, at the time point (t7) of the rising edge of the third latch control signal (LCS110) when the third switch 709 is closed and the remaining switches (707, 708) are disconnected, the third latch group 160-3 can store the count data corresponding to the third column at the corresponding bit position according to the order of the digital code.

[0129] In some other embodiments, the composite latch controller (not shown) may output a first latch control signal (LCS100) by matching a plurality of pixels belonging to a first column of the pixel array 110 to a first classification signal (DCS1), may output a second latch control signal (LCS101) by matching a plurality of pixels belonging to a second column of the pixel array 110 to a second classification signal (DCS2), and may output a third latch control signal (LCS110) by matching a plurality of pixels belonging to a third column of the pixel array 110 to a third classification signal (DCS3). For example, at a time point (t5) of a rising edge of the first latch control signal (LCS100) when the first switch 707 is closed and the remaining switches (708, 709) are open, the first latch group 160-1 may store the count data corresponding to the first column at the corresponding bit position according to the order of the digital code, and the second latch group 160-2 may store the count data corresponding to the second column at the corresponding bit position according to the order of the digital code. At the time point (t6) of the rising edge of the second latch control signal (LCS101) when the second switch 708 is closed and the remaining switches (707, 709) are disconnected, the third latch group (not shown) can store the count data corresponding to the third column at the corresponding bit position according to the order of the digital code, and the fourth latch group (not shown) can store the count data corresponding to the fourth column at the corresponding bit position according to the order of the digital code. In addition, at the time point (t7) of the rising edge of the third latch control signal (LCS110) when the third switch 709 is closed and the remaining switches (707, 708) are disconnected, the fifth latch group (not shown) can store the count data corresponding to the fifth column at the corresponding bit position according to the order of the digital code, and the sixth latch group (not shown) can store the count data corresponding to the sixth column at the corresponding bit position according to the order of the digital code.

[0130] In some other embodiments, the composite latch controller (not shown) may output a first latch control signal (LCS100) by matching the pixel including the first color filter to the first classification signal (DCS1), may output a second latch control signal (LCS101) by matching the pixel including the second color filter to the second classification signal (DCS2), and may output a third latch control signal (LCS110) by matching the pixel including the third color filter to the third classification signal (DCS3). For example, at the time point (t5) of the rising edge of the first latch control signal (LCS100) when the first switch 707 is closed and the remaining switches (708, 709) are open, the first latch group 160-1 may store the count data corresponding to the pixel including the red (R) color filter in the corresponding bit position in the order of the digital code. At the time point (t6) of the rising edge of the second latch control signal (LCS101) when the second switch 708 is closed and the remaining switches (707, 709) are opened, the second latch group 160-2 can store the count data corresponding to the pixel including the green (G) filter at the corresponding bit position according to the order of the digital code. In addition, at the time point (t7) of the rising edge of the third latch control signal (LCS110) when the third switch 709 is closed and the remaining switches (707, 708) are opened, the third latch group 160-3 can store the count data corresponding to the pixel including the blue (B) filter at the corresponding bit position according to the order of the digital code.

[0131] As apparent from the above description, the image sensing device according to some embodiments of the present disclosure is capable of providing higher quality images using a relatively small amount of power.

[0132] The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized through the above description.

[0133] Although a number of exemplary embodiments have been described, it will be appreciated that modifications and enhancements to the disclosed embodiments and other embodiments may be devised based on what is described and / or illustrated in this disclosure.

[0134] CROSS-REFERENCE TO RELATED APPLICATIONS

[0135] This patent application claims priority to and the benefit of Korean Patent Application No. 10-2023-0108391, filed on August 18, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensing device, comprising: A latch array, the latch array comprising: a first latch group storing therein first image data corresponding to a first region of the pixel array; a second latch group storing therein second image data corresponding to a second region of the pixel array; a first latch controller generating a first latch control signal to control the first latch group; and a second latch controller that generates a second latch control signal to control the second latch group, The second edge of the second latch control signal occurs after the first edge of the first latch control signal.

2. The image sensing device according to claim 1, wherein: The first region includes a first column of the pixel array, and The second region includes a second column of the pixel array.

3. The image sensing device according to claim 1, wherein: The first edge occurs when the first latch control signal transitions from a logic low level to a logic high level, and The second edge occurs when the second latch control signal transitions from a logic low level to a logic high level.

4. The image sensing device according to claim 1, wherein: A pulse width of the first latch control signal and a pulse width of the second latch control signal are different from each other.

5. The image sensing device according to claim 1, wherein: The first latch controller and the second latch controller are activated by the same control start signal.

6. The image sensing device according to claim 1, wherein: The first latch controller comprises: a plurality of signal delay units, each of the plurality of signal delay units delaying a start time of an input signal; and A variable switch adjusts a time point of an edge of the first latch control signal so that different pixel groups included in the first area correspond to edges at different time points.

7. The image sensing device according to claim 6, wherein: The variable switch adjusts a time point of the edge of the first latch control signal by adjusting the number of signal delay units corresponding to the first region in response to a classification signal.

8. The image sensing device according to claim 6, wherein: Each of the plurality of pixel groups includes pixels electrically connected to the same analog-to-digital converter ADC.

9. The image sensing device according to claim 6, wherein: Each of the plurality of pixel groups includes pixels corresponding to the same color.

10. An image sensing device, the image sensing device comprising a latch array, the latch array comprising: a first latch group storing therein first image data corresponding to a first region of the pixel array; as well as a second latch group storing therein second image data corresponding to a second region of the pixel array, After the first latch group stores the first image data therein, the second latch group stores the second image data therein.

11. The image sensing device according to claim 10, wherein: The first region includes a first column of the pixel array, and The second region includes a second column of the pixel array.

12. The image sensing device according to claim 10, wherein: The first latch group also receives a first latch control signal indicating a start time point for storing the first image data, and The second latch group also receives a second latch control signal indicating a start time point for storing the second image data.

13. The image sensing device according to claim 12, wherein: The first latch group also receives a classification signal to adjust a start time point for storing a plurality of data groups included in the first image data therein, so that the first latch group stores the plurality of data groups therein at different time points.

14. The image sensing device according to claim 13, wherein: The classification signal is used to determine a starting time point for storing the plurality of data groups in the first latch group.

15. The image sensing device according to claim 13, wherein: Each of the plurality of data groups includes a data block corresponding to a same analog-to-digital converter ADC.

16. The image sensing device according to claim 13, wherein: Each of the plurality of data groups includes a block of pixel data of pixels corresponding to the same color.

17. An image sensing method, the image sensing method comprising the following steps: detecting a first edge of a first latch control signal by a first latch group included in the latch array; storing, by the first latch group, first image data corresponding to a first region of a pixel array; detecting a second edge of a second latch control signal by a second latch group included in the latch array; and Second image data corresponding to a second area of ​​the pixel array is stored by the second latch group at a time point delayed from a storage time at which the first image data is stored.

18. The image sensing method according to claim 17, wherein: The step of storing the first image data comprises the following steps: receiving a first classification signal; and A second classification signal is received.

19. The image sensing method according to claim 18, wherein: The step of storing the first image data further includes the step of storing a first data group included in the first image data in response to the first classification signal.

20. The image sensing method according to claim 18, wherein: The step of storing the first image data further includes the step of storing a second data group included in the first image data after storing the first data group in response to the second classification signal.

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