Semiconductor device and manufacturing method thereof, and electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, wherein the semiconductor device comprises: forming a hole extending in a direction perpendicular to the substrate in the stacked structure of the storage cell area, the sidewall of the hole exposing the conductive film and the first insulating film in the stacked structure; the hole on the conductive film is located within the conductive film; using the hole on the conductive film as a mask, the first insulating film in the hole is laterally etched until the second insulating film located in the first insulating film is exposed by the hole, and the second insulating film is laterally etched within the hole; a step is formed between the bottom of the second groove corresponding to the second groove in the second insulating film and the sidewall of the second insulating film exposed by the sidewall of the hole located in the conductive film.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of dynamic random access memory (DRAM) technology, the planar 1T1C structure has reached its limit. To achieve higher storage capacitors, lower leakage, and higher integration, DRAM memory is gradually developing towards a three-dimensional (3D) structure. However, the development of 3D structures has encountered various problems. As the number of stacked layers increases, the array becomes larger and denser. The presence of parasitic MOS transistors between different layers has a significant impact on the retention of the capacitor's stored charge and the overall stability of the device. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device, which can reduce parasitic capacitors and improve device performance.

[0005] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0006] Alternatingly depositing a first insulating film and a conductive film on a substrate to form a stacked structure; the conductive film comprises polysilicon;

[0007] forming a plurality of first grooves penetrating the stacked structure by patterned etching, wherein the area between adjacent first grooves is a storage unit area;

[0008] Filling the first grooves with a second insulating film, the second insulating film covering the conductive film exposed in each first groove and the sidewalls of the first insulating film; the material of the second insulating film is different from that of the first insulating film;

[0009] forming a hole extending in a direction perpendicular to the substrate in the stacked structure of the memory cell region, wherein the sidewall of the hole exposes the conductive film and the first insulating film in the stacked structure; the hole on the conductive film is located within the conductive film;

[0010] Using the hole in the conductive film as a mask, laterally etching the first insulating film in the hole until the second insulating film located in the first insulating film is exposed through the hole, and laterally etching the second insulating film in the hole to form a second groove between two adjacent conductive films;

[0011] After forming the second groove, the conductive film is laterally etched to form a first electrode and a second electrode on the conductive film, exposing the second insulating film;

[0012] A step is formed between the bottom of the second groove in the second insulating film corresponding to the second groove and the side wall of the second insulating film exposed at the side wall of the hole in the conductive film;

[0013] forming a semiconductor layer, a gate insulating layer and a gate electrode in sequence in the hole;

[0014] The parasitic semiconductor layer between each two adjacent conductive films is removed.

[0015] In one exemplary embodiment, removing the parasitic semiconductor layer includes:

[0016] removing the second insulating film between two adjacent holes by dry etching, retaining the second insulating film on the same layer as the conductive film between adjacent first grooves to expose the first insulating film, and wet etching the first insulating film to expose part of the side surface of the parasitic semiconductor layer between adjacent transistors;

[0017] removing the second insulating film on the same layer as the first insulating film by patterned wet etching to expose a portion of the side surface of the parasitic semiconductor layer between adjacent transistors, and retaining a portion of the second insulating film on the same layer as the conductive film to form an etching stop layer;

[0018] The exposed parasitic semiconductor layer is removed by patterned wet etching, and the semiconductor layer, gate insulating layer and gate electrode on the same layer as the conductive film are retained.

[0019] In an exemplary embodiment, forming a plurality of first grooves penetrating the stacked structure by patterned etching includes:

[0020] A plurality of first grooves penetrating the stack structure are formed by patterned etching, so that the first insulating film in the stack structure forms a first patterned structure; the conductive film in the stack structure forms a second patterned structure; the second patterned structure includes a bit line and a branch connected to the bit line, the bit line extends along a second direction, the branch extends along a first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects with the second direction.

[0021] In an exemplary embodiment, after filling the first groove with the second insulating film and before forming the hole, the method further includes:

[0022] By patterned dry etching, the second insulating film corresponding to the end of the branch away from the bit line is etched away to form a trench extending in a direction perpendicular to the substrate, wherein the trench exposes the branch in the corresponding area and the side surface of the first insulating film;

[0023] etching and removing the first insulating film exposed in the trench by wet selective etching to expose the side surface of the branch away from one end of the bit line;

[0024] A first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode are sequentially formed at one end of the branch away from the bit line by an atomic layer deposition method, wherein the first capacitor electrode and the second capacitor electrode form a capacitor.

[0025] In an exemplary embodiment, the memory further includes a lead region located on at least one side of the memory cell region. The method for manufacturing the semiconductor device, after removing the parasitic semiconductor layer, further includes:

[0026] The stacked structure of the lead area is formed into n steps; wherein the n steps are arranged in sequence along a direction perpendicular to the substrate, each step includes a first insulating film and a first conductive film that are stacked, the first conductive film of each step is located on the side of the first insulating film away from the substrate, and the first conductive film of each step forms a lead layer connected to the bit line of the memory cell area, wherein n is a natural number greater than 2.

[0027] In an exemplary embodiment, forming n steps in the stacked structure of the lead region includes:

[0028] forming a fifth insulating film on the first insulating film in the lead area;

[0029] forming a photoresist on the memory cell region and the lead region;

[0030] Etching the photoresist to form a first exposed area on the photoresist, wherein the first exposed area exposes the fifth insulating film at one end of the lead region;

[0031] Using a photolithography method, etching away the fifth insulating film and the first insulating film in the first exposed area to expose the nth layer of the first conductive film in the first exposed area;

[0032] Etching the photoresist along an edge of the first exposed area to form a second exposed area connected to the first exposed area, wherein the second exposed area exposes the fifth insulating film of the lead area;

[0033] By patterned dry etching, the nth layer of the first conductive film and the first insulating film of the first exposed area are etched away to expose the n-1th layer of the first conductive film of the first exposed area; the fifth insulating film and the first insulating film of the second exposed area are etched away to expose the nth layer of the first conductive film of the second exposed area, and the n-1th layer of the first conductive film of the first exposed area and the nth layer of the first conductive film of the second exposed area form a step.

[0034] The present disclosure also provides a semiconductor device manufactured by any of the above-mentioned methods for manufacturing a semiconductor device, including:

[0035] A plurality of memory cells are distributed in different layers and stacked along a direction perpendicular to the substrate; the memory cells at least include transistors;

[0036] The transistor includes a gate electrode, a semiconductor layer surrounding the sidewall of the gate electrode, and a gate insulating layer arranged between the sidewall of the gate electrode and the semiconductor layer; the semiconductor layers of the memory cells of different layers are physically disconnected along a direction perpendicular to the substrate;

[0037] word lines, running through the different layers and extending in a direction perpendicular to the substrate, connected to gate electrodes of the memory cells of the different layers;

[0038] A bit line extending in a direction parallel to the substrate and connected to at least one memory cell in the same layer;

[0039] The memory cell further includes an etch stop layer, which is disposed on a side of the semiconductor layer of the transistor and between a first electrode and a second electrode of the transistor. The etch stop layer and the first and second electrodes surround the semiconductor layer.

[0040] In an exemplary embodiment, it also includes a lead area located on at least one side of the storage cell area, the lead area includes n steps arranged in sequence along a direction perpendicular to the substrate, each step includes a first insulating film and a conductive film arranged in a stacked manner, the conductive film of each step is located on the side of the first insulating film away from the substrate, the conductive film of each step forms a lead layer, and n is a natural number greater than 2.

[0041] In an exemplary embodiment, it includes a first storage cell area and a second storage cell area arranged along a first direction, and a first lead area and a second lead area arranged along the first direction, the first lead area is located on one side of the first storage cell area in the second direction and is connected to the first storage cell area, the second lead area is located on one side of the second storage cell area in the second direction and is connected to the second storage cell area, the n steps in the first lead area are arranged in sequence along the first direction, and the n steps in the second lead area are arranged in sequence along the opposite direction of the first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects the second direction.

[0042] In an exemplary embodiment, a first memory cell region and a second memory cell region are arranged along a first direction. The first memory cell region and the second memory cell region share a lead region, and n steps of the lead region are sequentially arranged along the first direction.

[0043] In an exemplary embodiment, a first memory cell area and a second memory cell area are arranged along a first direction, the first memory cell area and the second memory cell area share a lead area, the lead area includes a first step row and a second step row, the first step row and the second step row are arranged along a second direction, the first step row includes an even-numbered step, and the even-numbered step is arranged in sequence along the opposite direction of the first direction; the second step row includes an odd-numbered step, and the odd-numbered step is arranged in sequence along the opposite direction of the first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects the second direction.

[0044] An embodiment of the present disclosure further provides an electronic device comprising any of the semiconductor devices described above.

[0045] The semiconductor device of the embodiment of the present disclosure can eliminate parasitic MOS capacitors between adjacent storage structure layers and improve device stability by spacing the semiconductor layers of storage units of different layers in a direction perpendicular to the substrate.

[0046] The manufacturing process of the semiconductor device in the embodiment of the present disclosure forms a stacked structure by using silicon oxide and polysilicon. Both silicon oxide and polysilicon are silicon-based materials. A single etching process can be used to simultaneously etch silicon oxide and polysilicon to form holes. The process is simple, and the uniformity of silicon oxide and polysilicon is good. The sidewall morphology of the hole formed by etching is smooth. In subsequent processes, there is no need to use conductive materials to replace polysilicon. Polysilicon can be etched to form two electrodes and bit lines of the transistor, which simplifies the process steps and reduces production costs.

[0047] The manufacturing process of the semiconductor device in the embodiment of the present disclosure forms a step-shaped second insulating film, so that after the second insulating film located in the film layer where the first insulating film is located is etched away, the second insulating film located corresponding to the holes in the conductive film is retained to form an etching barrier layer. The etching barrier layer can protect the semiconductor layer located in the film layer where the first conductive film is located when the semiconductor layer located in the film layer where the first insulating film is located is subsequently etched away to prevent it from being corroded by the etching solution.

[0048] The manufacturing process of the semiconductor device in the embodiment of the present disclosure forms a step-shaped hole, and when the semiconductor layer located in the film layer where the first insulating film is located is subsequently etched away, the semiconductor layer located in the film layer where the first conductive film is located is protected from being corroded by the etching solution.

[0049] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0050] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution.

[0052] Figure 1 A cross-sectional view of a semiconductor device along a direction parallel to a substrate provided for an exemplary embodiment;

[0053] Figure 2 for Figure 1 Cross-sectional view along the a-a' direction;

[0054] Figure 3 A schematic diagram of a semiconductor device after a stacked structure is formed in a manufacturing process according to an exemplary embodiment;

[0055] Figure 4a A perspective view of a semiconductor device after forming a first patterned structure and a second patterned structure during a manufacturing process of the semiconductor device according to an exemplary embodiment;

[0056] Figure 4b A schematic diagram in a direction parallel to the substrate after forming a first patterned structure and a second patterned structure during the manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0057] Figure 5a A schematic diagram of a semiconductor device after forming a first trench and a second trench during manufacturing of the semiconductor device according to an exemplary embodiment;

[0058] Figure 5b A schematic diagram of a semiconductor device after forming a third trench and a fourth trench during manufacturing of the semiconductor device according to an exemplary embodiment;

[0059] Figure 5c A schematic diagram of a semiconductor device after a capacitor is formed in a manufacturing process provided by an exemplary embodiment;

[0060] Figure 6a A schematic diagram of a semiconductor device in a manufacturing process in which a hole is formed in a direction parallel to the substrate according to an exemplary embodiment;

[0061] Figure 6b A schematic diagram of a semiconductor device in a manufacturing process in which a hole is formed in a direction perpendicular to the substrate according to an exemplary embodiment;

[0062] Figure 7a A schematic diagram of forming a step-like shape between the sidewall of the hole in the first insulating film and the sidewall of the hole in the first conductive film during the manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0063] Figure 7b A schematic diagram of etching the second insulating film during the manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0064] Figure 7c A schematic diagram of forming a second insulating film into a stepped shape during the manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0065] Figure 8 A schematic diagram of a semiconductor device after forming a semiconductor layer, a gate insulating layer, and a gate electrode during the manufacturing process of an exemplary embodiment is provided;

[0066] Figure 9a A schematic diagram of the sidewalls of a first insulating film and a first conductive film being exposed during the manufacturing process of a semiconductor device provided by an exemplary embodiment;

[0067] Figure 9b A schematic diagram of a semiconductor device after removing a first insulating film during manufacturing of the semiconductor device according to an exemplary embodiment;

[0068] Figure 9c A schematic diagram of a semiconductor device after forming an etch stop layer during manufacturing of the semiconductor device according to an exemplary embodiment;

[0069] Figure 9d A schematic diagram of a semiconductor device manufacturing process after removing the semiconductor layer, the gate insulating layer, and the gate electrode located in the first insulating film hole is provided in accordance with an exemplary embodiment;

[0070] Figure 10a A schematic diagram of a semiconductor device after a fifth insulating film is formed during the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0071] Figure 10b A schematic diagram of a semiconductor device manufacturing process after removing the fifth insulating film and the first insulating film from the first exposed region according to an exemplary embodiment;

[0072] Figure 10c A schematic diagram of a semiconductor device after forming a second exposed region and a third exposed region during a manufacturing process of the semiconductor device according to an exemplary embodiment is provided;

[0073] Figure 10d A schematic diagram of a semiconductor device after a step is formed during the manufacturing process of the semiconductor device according to an exemplary embodiment;

[0074] Figure 10e A schematic diagram of a semiconductor device after n steps are formed in a manufacturing process according to an exemplary embodiment;

[0075] Figure 11 A schematic diagram of a semiconductor device provided as an exemplary embodiment;

[0076] Figure 12 A schematic diagram of a semiconductor device provided for yet another exemplary embodiment;

[0077] Figure 13 A schematic diagram of a semiconductor device is provided for yet another exemplary embodiment. DETAILED DESCRIPTION

[0078] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is any conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0079] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0080] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0081] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0082] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0083] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0084] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0085] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0086] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0087] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0088] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0089] As used herein, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0090] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0091] Figure 1 A cross-sectional view of a semiconductor device along a direction parallel to a substrate provided for an exemplary embodiment; Figure 2 for Figure 1 The cross-sectional view in the a-a' direction. Figure 1 and Figure 2 As shown, in a direction parallel to the substrate, the semiconductor device provided by this embodiment may include: a memory cell region 100 and a peripheral circuit region 200 located on at least one side of the memory cell region 100. The memory cell region 100 may include a memory structure layer 102 and an insulating structure layer 101, which are sequentially overlapped and arranged in a direction perpendicular to the substrate, as well as word lines 40 and bit lines 30.

[0092] In an exemplary embodiment, in a direction parallel to the substrate, the memory structure layer 102 includes a plurality of memory cells arranged at intervals and a first insulating layer 71 separating the memory cells. The material of the first insulating layer 71 may be silicon nitride.

[0093] In an exemplary embodiment, the insulating structure layer 101 includes a second insulating layer 72 , and the second insulating layer 72 separates adjacent memory cells in a direction perpendicular to the substrate.

[0094] In an exemplary embodiment, the word line 40 extends in a direction perpendicular to the substrate and penetrates different memory structure layers 102 to connect to memory cells in different memory structure layers 102 .

[0095] In an exemplary embodiment, the bit line 30 extends in a direction parallel to the substrate and is located in each memory structure layer 102 . The bit line 30 is connected to at least one memory cell in the memory structure layer 102 of the same layer.

[0096] In an exemplary embodiment, the peripheral circuit region 200 includes a shared electrode region 201 and a lead region 202 that are sequentially arranged away from the memory cell region 100, and the lead region 202 is connected to the memory cell region 100 through the shared electrode region 201. The shared electrode region 201 may include a plurality of shared electrodes spaced apart in a direction perpendicular to the substrate. The lead region 202 may include a plurality of lead layers spaced apart in a direction perpendicular to the substrate. The first end of a shared electrode is connected to the bit line 30 in the corresponding memory structure layer 102, and the second end of the shared electrode is connected to the corresponding lead layer. That is, a lead layer can be connected to the bit line 30 in the corresponding memory structure layer 102 through the corresponding shared electrode to achieve signal transmission.

[0097] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate.

[0098] In an exemplary embodiment, the memory cell may include: a transistor, the transistor including a first electrode 51, a second electrode 52, a gate electrode 26, and a semiconductor layer 23 surrounding the gate electrode 26 and insulated from the gate electrode 26 by a gate insulating layer 24, the semiconductor layer 23 extending on the side wall of the gate electrode 26 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate; wherein the channel between the first electrode 51 and the second electrode 52 is a horizontal channel; the gate electrode 26 is connected to the word line 40.

[0099] A horizontal channel is a channel in which the direction of carrier transmission is in a plane parallel to the substrate, but the direction of carrier transmission is not limited to being in one direction. In practical applications, the direction of carrier transmission extends in one direction as a whole, but locally, it is related to the shape of the semiconductor layer. In other words, a horizontal channel does not mean that it must extend in one direction in the horizontal plane, and may extend in different directions. For example, when the semiconductor layer is annular, the source contact area and the drain contact area on the annular semiconductor layer are part of the annular ring. At this time, the carriers extend from the source contact area to the drain contact area in one direction as a whole, and may not be in a certain direction locally. Of course, the direction of carrier transmission in a plane parallel to the substrate is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate. This application protects the channel between the first electrode and the second electrode as a channel that is not perpendicular to the substrate.

[0100] In one exemplary embodiment, the semiconductor device provided in this embodiment may further include a via 60 (via) extending in a direction perpendicular to the substrate. Via 60 penetrates the overlapping storage structure layer 102 and the insulating structure layer 101, and exposes the sidewalls of the first electrode 51 and the second electrode 52 in the storage structure layer 102, as well as the sidewalls of the insulating structure layer 101.

[0101] In an exemplary embodiment, a semiconductor layer 23 , a gate insulating layer 24 , and a gate electrode 26 are sequentially disposed on the sidewalls of the hole 60 corresponding to the storage structure layer 102 .

[0102] In an exemplary embodiment, the semiconductor layers 23 of the transistors of the storage cells of at least some adjacent storage structure layers 102 are spaced apart in a direction perpendicular to the substrate, that is, the semiconductor layer 23 is provided on the side walls of the holes 60 corresponding to the storage structure layer 102, and the side walls of the holes 60 corresponding to the insulating structure layer 101 are the side surfaces of the insulating structure layer 101, and the semiconductor layer 23 thereon is etched away, and in a direction perpendicular to the substrate, the semiconductor layers 23 of the transistors of the storage cells of the adjacent storage structure layers 102 are disconnected at the insulating structure layer 101.

[0103] In one exemplary embodiment, the semiconductor layers 23 of the transistors of the memory cells of different memory structure layers 102 are physically disconnected in a direction perpendicular to the substrate. That is, the semiconductor layers 23 of the transistors of the memory cells of all adjacent memory structure layers 102 are physically disconnected in a direction perpendicular to the substrate, thereby eliminating parasitic MOS capacitors between all adjacent memory structure layers 102 and improving device stability.

[0104] The semiconductor device provided in this embodiment has at least partially adjacent semiconductor layers of transistors in the storage structure layer 102 spaced apart, which can reduce or eliminate at least a portion of parasitic MOS capacitors between layers and improve device stability.

[0105] In one exemplary embodiment, the semiconductor layer 23 wraps around the sidewalls of the gate electrode 26. The sidewall wrapping of the semiconductor layer 23 can be understood as partially or completely wrapping around the gate electrode 26. In some embodiments, the wrapping can be completely wrapped around the entirety of the semiconductor layer 23, where the cross-section of the wrapped semiconductor layer 23 is a closed ring. The cross-section is taken parallel to the substrate. In some embodiments, the wrapping can be partially wrapped around the gate electrode 26, where the cross-section is not closed but rather presents a ring shape. For example, a ring with an opening.

[0106] In an exemplary embodiment, the semiconductor layer 23 extends on the side wall of the gate electrode 26 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate. The semiconductor layer 23 may extend only in a direction perpendicular to the substrate, or the main body extends in a direction perpendicular to the substrate, and there may be a horizontal portion at the end extending in a horizontal direction and toward the gate electrode 26.

[0107] In an exemplary embodiment, the material of the semiconductor layer 23 may be a metal oxide, and the material of the metal oxide may be indium gallium zinc oxide (IGZO), InGaO, ITO, IZO, a metal oxide containing In and / or Sn, etc. When the metal oxide material is IGZO, the leakage current of the transistor is low (the leakage current is less than or equal to 1E-15A to 1E-10A), where 1E-15A refers to 10 to the negative 15th power amperes, and 1E-10A refers to 10 to the negative 10th power amperes, thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0108] In an exemplary embodiment, the gate insulating layer 24 surrounds the sidewalls of the gate electrode 26 . The gate insulating layer 24 is located between the gate electrode 26 and the semiconductor layer 23 . The semiconductor layer 23 is connected to the gate electrode 26 through the gate insulating layer 24 .

[0109] In an exemplary embodiment, the gate insulating layer 24 may be made of a high-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The high-K dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0110] In one exemplary embodiment, the gate insulating layers 24 of transistors in at least some adjacent storage structure layers 102 are spaced apart in a direction perpendicular to the substrate. Specifically, the gate insulating layer 24 is disposed on the sidewalls of the holes 60 corresponding to the storage structure layer 102, while the sidewalls of the holes 60 corresponding to the insulating structure layer 101 are the side surfaces of the insulating structure layer 101, on which the gate insulating layer 24 is etched away. In the direction perpendicular to the substrate, the gate insulating layers 24 of the transistors in the memory cells of the adjacent storage structure layers 102 are disconnected at the insulating structure layer 101.

[0111] In an exemplary embodiment, transistors in different memory structure layers 102 may share a word line 40 extending in a direction perpendicular to the substrate.

[0112] In one exemplary embodiment, the word line 40 is filled in the hole 60. The word line 40 is a line extending perpendicular to the substrate. The word line 40 is integrally connected to the gate electrode 26. The gate electrode 26 of the transistor in the memory structure layer 102 of a different layer can be part of the word line 40.

[0113] In an exemplary embodiment, the material composition of different regions of the word line 40 extending in a direction perpendicular to the substrate is the same, which can be understood as being formed using the same film manufacturing process. The same material composition can be understood as the same main elements tested in the material, for example, they are all made of transparent conductive materials such as metal or ITO, but the atomic number ratio of different regions is not limited.

[0114] In one exemplary embodiment, along a direction perpendicular to the substrate, the gate electrode 26 includes two end portions (a first end portion 261 and a second end portion 262) and a middle portion 263 located between the two end portions. The first end portion 261 and the second end portion 262 are located on opposite sides of the middle portion 263 in the direction perpendicular to the substrate. The orthographic projections of the first end portion 261 and the second end portion 262 on the substrate are both located within the orthographic projection of the middle portion 263 on the substrate. The side surfaces of the middle portion 263 protrude beyond the side surfaces of the first end portion 261 and the second end portion 262. The gate electrode 26 has a shape that is smaller at both ends and larger in the middle. That is, the orthographic projections of the first end portion 261 and the second end portion 262 on the substrate are both smaller than the orthographic projection of the middle portion 263 on the substrate.

[0115] In one exemplary embodiment, the first electrode 51 and the second electrode 52 of the same transistor can be located in the same storage structure layer 102. The first electrode 51 and the second electrode 52 are formed by patterning a conductive film layer, which is approximately parallel to the upper surface of the substrate. The first electrode 51 and the second electrode 52 can be provided in the same layer. That is, the first electrode 51 and the second electrode 52 can be formed simultaneously through the same patterning process, but the embodiments of the present disclosure are not limited thereto. The first electrode 51 and the second electrode 52 can be manufactured separately through different patterning processes.

[0116] In an exemplary embodiment, at least some of the memory cells in the same memory structure layer 102 form an array distributed along a first direction D1 and a second direction D2. The bit lines 30 extend along the second direction D2. The memory cells arranged along the second direction D2 form a column of transistors. The bit lines 30 are located on one side of the column of transistors in the first direction D1. The bit lines 30 are all connected to the second electrodes 52 of transistors in adjacent columns in the same memory structure layer 102. Figure 1 , each storage structure layer 102 includes at least three rows and two columns of memory cells, but the disclosed embodiments are not limited thereto. Each storage structure layer 102 may include memory cells of other numbers of rows and columns, for example, only one memory cell. The first direction D1 may be parallel to the substrate, the second direction D2 may be parallel to the substrate, and the first direction D1 and the second direction D2 may intersect. In some embodiments, the first direction D1 and the second direction D2 may be perpendicular.

[0117] In an exemplary embodiment, the bit line 30 is located between two adjacent columns of transistors in the same memory structure layer 102, and the second electrodes 52 of the transistors in the two adjacent columns are connected to the same bit line 30. The second electrodes 52 of the transistors in the two adjacent columns and the bit line 30 can be an integrated structure.

[0118] In an exemplary embodiment, at least one memory cell is disposed between an end portion of the bit line 30 and the peripheral circuit region 200 .

[0119] In an exemplary embodiment, the second electrode 52 of the transistor may be a portion of the bit line 30 connected to the second electrode 52. The second electrode 52 and the bit line 30 may both be made of polysilicon.

[0120] In an exemplary embodiment, the semiconductor device may further include a data storage element.

[0121] In an exemplary embodiment, the data storage element is, for example, a capacitor, which forms a 1T1C storage structure with a transistor. However, the present disclosure is not limited thereto, and the capacitor can form a 2T0C storage structure with other transistors, and so on.

[0122] In an exemplary embodiment, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42 , and the first capacitor electrode 41 is connected to the first electrode 51 .

[0123] In an exemplary embodiment, the first capacitor electrode 41 and the first electrode 51 may be an integrated structure, wherein both the first capacitor electrode 41 and the first electrode 51 may be made of polysilicon (poly-Si).

[0124] The polysilicon mentioned in the embodiments of the present application that plays a conductive role or is used as a wire or electrode means that the main material is polysilicon. In order to ensure its conductivity, it can be doped polysilicon, or polysilicon containing metal silicide, or polysilicon with a metal layer deposited on the surface.

[0125] In an exemplary embodiment, the second capacitor electrodes 42 of the capacitors in different storage structure layers 102 may be connected into an integrated structure, that is, the capacitors in the same column of different layers share the same plate as the second capacitor electrode 42 .

[0126] In an exemplary embodiment, the capacitor may further include a capacitor dielectric layer 43 disposed between the first capacitor electrode 41 and the second capacitor electrode 42. The capacitor dielectric layer 43 serves as a medium between the first capacitor electrode 41 and the second capacitor electrode 42.

[0127] In one exemplary embodiment, the memory cell further includes an etch stop layer 25 disposed within the memory structure layer 102. The etch stop layer 25 is disposed on the side of the semiconductor layer 23 of the transistor and between the first and second electrodes of the transistor. The etch stop layer 25 and the first and second electrodes surround the semiconductor layer. The etch stop layer 25 is used to prevent the etchant from corroding the semiconductor material within the memory structure layer 102 during the process of etching away the semiconductor material within the insulating structure layer, thereby preventing the etchant from corroding the semiconductor layer 23 within the memory structure layer 102 and ensuring the quality of the semiconductor layer 23. The etch stop layer 25 can be made of silicon nitride.

[0128] Figure 11 FIG. 1 is a schematic diagram of a semiconductor device provided by an exemplary embodiment. Figure 11 As shown, the lead region includes n steps 70 sequentially arranged along a direction perpendicular to the substrate. Each step 70 includes a first insulating film 10 and a first conductive film 11 stacked together. The first conductive film 11 of each step is located on the side of the first insulating film 10 away from the substrate, exposing the first conductive film 11 of each step. The first conductive film 11 of each step forms a lead layer. Here, n is a natural number greater than 2, such as 3, 4, 5, 6, etc.

[0129] In an exemplary embodiment, the lead region further includes a signal line 80 extending in a direction perpendicular to the substrate, and the signal line 80 is connected to each step 70 in a one-to-one correspondence.

[0130] In an exemplary embodiment, the semiconductor device includes a first memory cell region 110 and a second memory cell region 120 arranged along a first direction D1, and a first lead region 2021 and a second lead region 2022 arranged along the first direction D1, the first lead region 2021 is located on one side of the first memory cell region 110 in the second direction D2 and is connected to the first memory cell region 110, and the second lead region 2022 is located on one side of the second memory cell region 120 in the second direction D2 and is connected to the second memory cell region 120. The n steps 70 in the first lead area 2021 are arranged sequentially along the first direction D1, that is, the n-th step 70 in the first lead area 2021 is located on the side close to the second lead area 2022, and the n-1-th step 70 in the first lead area 2021 is located on the side away from the second lead area 2022; the n steps 70 in the second lead area 2022 are arranged sequentially along the opposite direction of the first direction D1, that is, the n-th step 70 in the second lead area 2022 is located on the side close to the first lead area 2021, and the n-1-th step 70 in the second lead area 2022 is located on the side away from the first lead area 2021.

[0131] Figure 12FIG. 1 is a schematic diagram of a semiconductor device provided as another exemplary embodiment. Figure 12 As shown, the semiconductor device of this embodiment is Figure 11 The semiconductor devices shown are substantially the same, except that the first memory cell region 110 and the second memory cell region 120 share a common wiring region 202. The n steps 70 in the wiring region 202 are sequentially arranged along the first direction D1.

[0132] Figure 13 FIG. 1 is a schematic diagram of a semiconductor device provided as another exemplary embodiment. Figure 13 As shown, the semiconductor device of this embodiment is Figure 11 The semiconductor devices shown are substantially the same, except that the first memory cell region 110 and the second memory cell region 120 share a common lead region 202. The lead region 202 includes a first step row 210 and a second step row 220, which are arranged along a second direction D2. The first step row 210 includes even-numbered steps 70, such as the second step 70, the fourth step 70, the sixth step 70, and so on, which are arranged in sequence opposite to the first direction D1. The second step row 220 includes odd-numbered steps 70, such as the first step 70, the third step 70, the fifth step 70, and so on, which are arranged in sequence opposite to the first direction D1.

[0133] The technical solution of this embodiment will be further illustrated below using the manufacturing process of the semiconductor device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a well-established manufacturing process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a well-established manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin layer of a material deposited on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, the "thin film" before patterning is referred to as a "thin film," and the "layer" after patterning is referred to as a "layer." The "layer" after patterning or photolithography contains at least one "pattern."

[0134] In this embodiment, each storage structure layer 102 may include multiple storage units, but the embodiments of the present disclosure are not limited thereto. Each storage structure layer 102 may include one storage unit.

[0135] In one exemplary embodiment, a process for manufacturing a semiconductor device may include:

[0136] S101) forming a stacking structure.

[0137] Forming the stack structure includes: alternately depositing a first insulating film 10 and a first conductive film 11 on the substrate to form a stack structure, wherein the film layer close to the substrate and the film layer away from the substrate in the stack structure are both the first insulating film 10, such as Figure 3 As shown ( Figure 3 The substrate is not shown). Figure 3 A schematic diagram of a semiconductor device in a manufacturing process according to an exemplary embodiment after a stacked structure is formed in a direction perpendicular to the substrate is provided.

[0138] In an exemplary embodiment, the material of the first insulating film 10 may be a low-K material, such as silicon oxide, and the material of the first conductive film 11 may include polysilicon.

[0139] The embodiment of the present application forms a stacked structure by using silicon oxide and conductive polysilicon. Both silicon oxide and polysilicon are silicon-based materials. A single etching process can be used to simultaneously etch silicon oxide and polysilicon to form holes. The process is simple, and the uniformity of silicon oxide and polysilicon is good. The sidewall morphology of the hole formed by etching is smooth. In subsequent processes, there is no need to use metal conductive materials to replace polysilicon. Polysilicon can be etched to form two electrodes and bit lines of the transistor, which simplifies the process steps and reduces production costs.

[0140] In an exemplary embodiment, the first insulating film 10 and the first conductive film 11 may be deposited by using a chemical vapor deposition method or an atomic layer deposition method.

[0141] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate.

[0142] Figure 3 The stacking structure shown in the figure includes 5 layers of first insulating films 10 and 4 layers of first conductive films 11. This is only an example. In other embodiments, the stacking structure may include more or fewer layers of first insulating films 10 and first conductive films 11 that are alternately arranged.

[0143] S102) forming a first patterned structure and a second patterned structure.

[0144] Forming the first patterned structure and the second patterned structure includes: based on the substrate formed with the aforementioned pattern, patterning the stacked structure of the memory cell area 100 through a mask to form a plurality of first grooves (which can be understood as trenches, with the bottoms of the first grooves facing the substrate) penetrating the stacked structure, with the area between adjacent first grooves being the memory cell area; causing each layer of the first insulating film 10 in the stacked structure of the memory cell area 100 to form a first patterned structure in which the first insulating films 10 are stacked on each other and distributed cyclically in sequence, and causing each layer of the first conductive film 11 in the stacked structure of the memory cell area 100 to form a second patterned structure in which the first conductive films 11 are stacked on each other and distributed cyclically in sequence; and retaining the stacked structure of the peripheral circuit area 200;

[0145] Then, the first grooves are filled with a second insulating film 12, which covers the sidewalls of the first conductive film 11 and the first insulating film 10 exposed in each first groove to isolate different devices. Figure 4a and Figure 4b As shown. Among them, Figure 4a A perspective view of a semiconductor device after forming a first patterned structure and a second patterned structure during a manufacturing process of the semiconductor device according to an exemplary embodiment; Figure 4b A schematic diagram in a direction parallel to a substrate after forming a first patterned structure and a second patterned structure during the manufacturing process of a semiconductor device provided by an exemplary embodiment is provided.

[0146] In an exemplary embodiment, the material of the second insulating film 12 may be silicon nitride having an etching selectivity ratio with the first insulating film.

[0147] In one exemplary embodiment, each layer of the second patterned structure includes a bit line 30, a plurality of first branches 21, and a plurality of second branches 22. The bit line 30 is elongated and extends along the second direction D2. The plurality of first branches 21 and the plurality of second branches 22 are also elongated and extend along the first direction D1. The plurality of first branches 21 and the plurality of second branches 22 are located on opposite sides of the bit line 30 in the first direction D1. The plurality of first branches 21 are spaced apart along the second direction D2. The first ends of the plurality of first branches 21 are perpendicularly connected to the bit line 30, and the second ends of the plurality of first branches 21 extend in a direction opposite to the first direction D1. The first ends of the plurality of second branches 22 are perpendicularly connected to the bit line 30, and the second ends of the plurality of second branches 22 extend in the first direction D1. The first branches 21 later form the first electrode 51 and the second electrode 52 of one transistor, while the second branches 22 later form the first electrode 51 and the second electrode 52 of another adjacent transistor.

[0148] S103) forming a capacitor before fabricating a semiconductor layer.

[0149] The capacitor formation includes: on the basis of the substrate formed with the aforementioned pattern, etching away the second insulating film 12 corresponding to the end of the plurality of first branches 21 away from the bit line 30 by patterned dry etching to form a first trench 13 extending in a direction perpendicular to the substrate, the first trench 13 exposes the plurality of first branches 21 in the corresponding area and the side surfaces of the multi-layer first insulating film 10, and retains the second insulating film 12 on the side of the plurality of first branches 21 away from the bit line 30, the second insulating film 12 can support the plurality of first branches 21 and prevent the plurality of first branches 21 from collapsing; etching away the second insulating film 12 corresponding to the end of the plurality of second branches 22 away from the bit line 30 to form a second trench 14 extending in a direction perpendicular to the substrate, the second trench 14 exposes the plurality of second branches 22 in the corresponding area and the side surfaces of the multi-layer first insulating film 10, and retains the second insulating film 12 on the side of the plurality of second branches 22 away from the bit line 30, the second insulating film 12 can support the plurality of second branches 22 and prevent the plurality of second branches 22 from collapsing, as shown in FIG. Figure 5a As shown;

[0150] Subsequently, the first insulating film 10 exposed by the first trench 13 is etched away by wet selective etching, and a third trench extending in a direction parallel to the substrate is formed in the region where the first insulating film 10 is etched away. The third trench and the first trench 13 surround the side surfaces of the plurality of first branches 21 away from one end of the bit line 30, exposing the side surfaces of the plurality of first branches 21 away from the end of the bit line 30. The first insulating film 10 exposed by the second trench 14 is etched away, and a fourth trench extending in a direction parallel to the substrate is formed in the region where the first insulating film 10 is etched away. The fourth trench and the second trench 14 surround the side surfaces of the plurality of second branches 22 away from one end of the bit line 30, exposing the side surfaces of the plurality of second branches 22 away from the end of the bit line 30. Figure 5b As shown;

[0151] Subsequently, by an atomic layer deposition method, the multiple first branches 21 away from one end of the bit line 30 and the multiple second branches 22 away from one end of the bit line 30 can be used as a first capacitor electrode and a capacitor dielectric layer; alternatively, a first electrode film and a capacitor dielectric layer are sequentially formed on the side of the multiple first branches 21 away from one end of the bit line 30 and the side of the multiple second branches 22 away from one end of the bit line 30, so that the first electrode film forms a first capacitor electrode, and the material of the first electrode film can be TIN; subsequently, a second electrode film is deposited to form the second capacitor electrode, and the material of the second electrode film can be TIN, and the first trench 13 and the second trench 14 are filled with polysilicon; finally, chemical mechanical polishing is used to smooth the surface of the stacked structure, as shown in FIG. Figure 5c The first capacitor electrode and the second capacitor electrode form a capacitor 15 .

[0152] In one exemplary embodiment, the material of the capacitor dielectric layer may be a high-k dielectric, such as hafnium oxide.

[0153] S104) forming holes.

[0154] The hole formation includes: etching the stacked structure by patterned dry etching on the substrate having the aforementioned pattern, thereby forming holes K1 penetrating the first insulating film 10 and the first conductive film 11 of the stacked structure, respectively. The holes K1 are located within the first insulating film 10 and the first conductive film 11, and are not located on the second insulating film. The sidewalls of the holes K1 expose the sidewalls of each of the first insulating film 10 and the first conductive film 11 in the stacked structure. The sidewalls of the first conductive film 11 are closed rings, and the sidewalls on the first conductive film do not expose the second insulating film. Figure 6a and Figure 6b As shown, the plurality of first branches 21, the plurality of second branches 22, and the bit line 30 are all provided with the hole K1. The hole K1 may extend in a direction perpendicular to the substrate. The hole K1 may or may not expose the substrate.

[0155] In an exemplary embodiment, the orthographic projection of the hole K1 on a plane parallel to the substrate may be a square or the like.

[0156] In an exemplary embodiment, the orthographic projection of the hole K1 on the substrate is located within the orthographic projection of the conductive layer 12 on the substrate. For example, the orthographic projection of the hole K1 passing through the first branch 21 on the substrate is located within the orthographic projection of the first branch 21 on the substrate, and the orthographic projection of the hole K1 passing through the second branch 22 on the substrate is located within the orthographic projection of the second branch 22 on the substrate.

[0157] S105) The sidewall of the hole is etched to form a step shape.

[0158] The step of etching the sidewall of the hole to form a step-like shape includes: on the basis of the substrate on which the aforementioned pattern is formed, using the hole of the first conductive film 11 in the aforementioned step as a mask, etching the first insulating film 10 exposed by the hole K1 in a direction away from the hole K1 by patterned wet etching, and in a second direction D2, etching away the first insulating film 10 (silicon oxide) so that the hole K1 located in the first insulating film 10 exposes the second insulating film 12 (silicon nitride), so that on a plane parallel to the substrate, the orthographic projection of the hole K1 located in the first conductive film 11 on the substrate falls within the orthographic projection of the hole K1 located in the first insulating film 10 on the substrate, and the area of ​​the orthographic projection of the hole K1 located in the first insulating film 10 on the substrate is larger than the area of ​​the orthographic projection of the hole K1 located in the first conductive film 11 on the substrate, so that the sidewall of the hole K1 located in the first insulating film 10 and the sidewall of the hole K1 located in the first conductive film 11 form a step-like shape, as shown in FIG. Figure 7a In this step, the second insulating film around the first conductive film 11 is blocked by the first conductive film and is not etched.

[0159] Subsequently, by patterned wet etching, the second insulating film 12 (silicon nitride) exposed in the hole K1 of the first insulating film 10 is etched away from the hole K1, so that the second insulating film exposed in the hole K1 of the first insulating film 10 is etched back to form a second groove, and the hole K1 in the first insulating film 10 is expanded along the second direction D2. The thickness of the bottom of the second groove is less than the thickness of the second insulating film 12 in the film layer where the first conductive film 11 is located. Figure 7b shown.

[0160] Subsequently, the first conductive film 11 exposed by the hole K1 is etched away from the hole K1 by patterned wet etching. In the second direction D2, the first conductive film 11 is removed by etching, so that the second insulating film located in the hole K1 of the first conductive film 11 is exposed, so that the multiple first branches, the multiple second branches and the bit line of the first conductive film 11 form a first electrode and a second electrode separated from each other. Since the thickness of the bottom of the second groove is less than the thickness of the second insulating film 12 located in the film layer where the first conductive film 11 is located, the bottom of the second groove and the side wall of the second insulating film 12 exposed by the side wall of the hole K1 of the first conductive film 11 form a step shape, as shown in FIG. Figure 7c As shown, the etching amount of the first conductive film 11 is less than the etching amount of the first insulating film 10, so that the orthographic projection area of ​​the hole K1 located in the first insulating film 10 on the substrate is larger than the orthographic projection area of ​​the hole K1 located in the first conductive film 11 on the substrate, thereby ensuring that the sidewalls of the hole K1 located in the first insulating film 10 and the sidewalls of the hole K1 located in the first conductive film 11 form a step shape.

[0161] S106) forming a semiconductor layer, a gate insulating layer and a gate electrode.

[0162] The formation of the semiconductor film includes: on the basis of the substrate formed with the aforementioned pattern, sequentially depositing a semiconductor film, a gate insulating film, and a second conductive film on the sidewalls of the hole K1 in the stacked structure by an atomic layer deposition method to form a semiconductor layer 23, a gate insulating layer 24, and a gate electrode 26; due to the step-like structure of the sidewalls of the hole K1, the orthographic projection area of ​​the semiconductor layer 23, the gate insulating layer 24, and the gate electrode 26 located in the hole K1 of the first insulating film 10 on the substrate is larger than the orthographic projection area of ​​the semiconductor layer 23, the gate insulating layer 24, and the gate electrode 26 located in the hole K1 of the first conductive film 11 on the substrate; and then, by chemical polishing, the semiconductor layer 23, the gate insulating layer 24, and the gate electrode 26 are smoothed, as shown in FIG. Figure 8 shown.

[0163] S107) removing the parasitic semiconductor layer between each two adjacent conductive films.

[0164] Removing the parasitic semiconductor layer between each adjacent two conductive films includes: on the basis of the substrate formed with the aforementioned pattern, etching away the second insulating film between the two adjacent holes in the memory cell area by patterned dry etching, retaining the second insulating film 12 in the same layer as the first conductive film between the adjacent first grooves, and etching away the area of ​​the second insulating film 12 to expose the sidewalls of the first insulating film 10 and the first conductive film 11 in the stacked structure, such as Figure 9a As shown; wherein, during this etching process, the peripheral circuit area can be protected from being etched by photoresist.

[0165] Subsequently, the sidewalls of the exposed first insulating film 10 are patterned wet-etched to remove the first insulating film 10 in the stacked structure, exposing the upper and lower surfaces of the first conductive film 11 and exposing the parasitic semiconductor layer in the first direction D1. The parasitic semiconductor layer is a semiconductor layer located between adjacent first conductive films 11, as shown in FIG. Figure 9b As shown; wherein, during this etching process, the peripheral circuit area can be protected from being etched by photoresist.

[0166] Subsequently, the stepped second insulating film 12 corresponding to the hole K1 is slowly etched by patterned wet etching. Due to the stepped structure of the second insulating film 12 corresponding to the hole K1, that is, the thickness of the second insulating film 12 located in the film layer where the first insulating film 10 is located (the thickness of the bottom of the second groove) is less than the thickness of the second insulating film 12 located in the film layer where the first conductive film 11 is located, in the second direction D2, after the parasitic semiconductor layer on the first insulating film 10 is exposed, a portion of the second insulating film in the same layer as the first conductive film 11 is still retained, and the retained second insulating film 12 forms an etching stopper 25, that is, the second insulating film 12 located in the film layer where the first insulating film 10 is located is completely etched away, and a portion of the second insulating film 12 located in the film layer where the first conductive film 11 is located is etched away, and a portion of the second insulating film 12 located in the film layer where the first conductive film 11 is located is retained, and the retained second insulating film 12 forms an etching stopper 25, as shown in FIG. Figure 9c shown.

[0167] Subsequently, the exposed parasitic semiconductor layer is removed by patterned wet etching. In some embodiments, the gate insulating layer exposed by the removed semiconductor layer can be further removed. Due to the step-like structure of the hole K1 and the blocking of the etching stop layer 25, during the above etching process, the etching liquid will not etch the semiconductor layer 23, the gate insulating layer and the gate electrode located in the hole K1 of the first conductive film 11, so that the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 on the same layer as the first conductive film 11 are completely retained. Figure 9d As shown. Among them, Figure 9d Only the semiconductor layer 23 is shown. Figure 9d The gate insulating layer and the gate electrode are not shown.

[0168] The solution provided in this embodiment can effectively reduce or eliminate parasitic MOS by etching away the parasitic semiconductor layer, thereby increasing device stability without affecting the effective channel length (the length of the semiconductor layer between the first electrode 51 and the second electrode 52).

[0169] The manufacturing process of the semiconductor device in the embodiment of the present disclosure forms a step-shaped second insulating film, so that after the second insulating film located in the film layer where the first insulating film is located is etched and removed, the second insulating film corresponding to the holes in the conductive film is retained to form an etching barrier layer. The etching barrier layer can protect the semiconductor layer located in the film layer where the first conductive film is located when the parasitic semiconductor layer is subsequently etched and removed, and prevent it from being corroded by the etching solution.

[0170] The manufacturing process of the semiconductor device of the embodiment of the present disclosure forms a step-shaped hole, and when the parasitic semiconductor layer is subsequently etched away, the semiconductor layer located in the film layer where the first conductive film is located is protected from being corroded by the etching solution.

[0171] S108) Filling the insulating film.

[0172] Filling the insulating film includes: on the basis of the substrate formed with the aforementioned pattern, using the atomic layer deposition method to deposit a third insulating film on the surface of the first conductive film 11, the semiconductor layer 23, the gate insulating layer 24, and the gate electrode 26, the third insulating film filling the area where the first insulating film was etched away; then, using the atomic layer deposition method, using the fourth insulating film to fill the area where the second insulating film was etched away, and covering the surface of the lead area and the shared electrode area; finally, using chemical mechanical polishing to smooth the fourth insulating film. The material of the third insulating film can be silicon oxide, and the material of the fourth insulating film can be silicon nitride.

[0173] S109) forming n steps in the lead region.

[0174] The n steps forming the lead region include:

[0175] S1091) Based on the substrate formed with the aforementioned pattern, a photolithography method is used to expose and etch the lead area, and the fourth insulating film of the lead area 202 is etched away to expose the first insulating film of the lead area 202; then, a fifth insulating film 16 is used to fill the area of ​​the lead area 202 where the fourth insulating film is etched away, and the fifth insulating film 16 is polished flat using chemical mechanical polishing, as shown in FIG. Figure 10a The material of the fifth insulating film can be silicon oxide.

[0176] S1092) forming a photoresist 17 on the memory cell region 100 and the peripheral circuit region 200, the photoresist 17 forming a rectangular first exposed region 181, the first exposed region 181 exposing the fifth insulating film at one end of the lead region 202; using a photolithography method, etching away the fifth insulating film and the first insulating film in the first exposed region 181, exposing the n-th layer of the first conductive film 11 in the first exposed region 181, as shown in FIG. Figure 10b shown.

[0177] S1093) etching the photoresist 17. While the photoresist 17 is being thinned, the photoresist 17 is etched along the edge of the first exposed area 181. The etching amount is controlled so that the photoresist 17 is etched in a direction parallel to the substrate, forming a rectangular second exposed area 182 and a rectangular third exposed area 183. The second exposed area 182 is located on a side of the first exposed area 181 in a direction opposite to the first direction D1 and is connected to the first exposed area 181. The second exposed area 182 exposes the fifth insulating film 192 of the lead area 202. The third exposed area 183 is located on a side of the first exposed area 181 in a direction opposite to the second direction D2 and is connected to the first exposed area 181. The third exposed area 183 exposes the fourth insulating film 191 of the shared electrode area 201. Figure 10c shown.

[0178] S1094) The first conductive film 11 and the first insulating film of the nth layer of the first exposed area 181 are etched away by patterned dry etching to expose the first conductive film 11 of the n-1th layer of the first exposed area 181; the fifth insulating film 192 and the first insulating film of the second exposed area 182 are etched away to expose the first conductive film 11 of the nth layer of the second exposed area 182. The first conductive film 11 of the n-1th layer of the first exposed area 181 and the first conductive film 11 of the nth layer of the second exposed area 182 form a step; due to the obstruction of the fourth insulating film 191 of the shared electrode area 201, the shared electrode area 201 is not etched during the above etching process. Figure 10d Wherein, n is a natural number greater than 2, such as 3, 4, 5, 6, etc.

[0179] In an exemplary embodiment, a polymer deposition and etching method may be used to protect the exposed sidewalls of the film layer.

[0180] S1095) Repeat step S1094) to form n steps 70 in the lead area 202, wherein the n steps 70 are sequentially arranged in a direction perpendicular to the substrate, and each step 70 includes a first insulating film 10 and a first conductive film 11 stacked together. The first conductive film 11 of each step is located on a side of the first insulating film 10 away from the substrate, so that the first conductive film 11 of each step is exposed. The first conductive film 11 of each step forms a lead layer connected to a bit line of a corresponding storage structure layer in the memory cell area, as shown in FIG. Figure 10e shown.

[0181] S1096) Filling the n steps of the lead region with a sixth insulating layer, and smoothing the sixth insulating film using chemical mechanical polishing, wherein the sixth insulating film may be made of silicon nitride.

[0182] The manufacturing method of this embodiment can be implemented using existing mature preparation equipment and is well compatible with existing preparation processes. Therefore, the process is simple to implement, easy to implement, and has high production efficiency. It has the advantages of easy process implementation, low production cost, and high yield rate.

[0183] The present disclosure also provides an electronic device comprising the semiconductor device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0184] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Alternatingly depositing a first insulating film and a conductive film on a substrate to form a stacked structure; The material of the conductive film includes polysilicon; forming a plurality of first grooves penetrating the stacked structure by patterned etching, wherein the area between adjacent first grooves is a storage unit area; Filling the first grooves with a second insulating film, the second insulating film covering the conductive film exposed in each first groove and the sidewalls of the first insulating film; the material of the second insulating film is different from that of the first insulating film; forming a hole extending in a direction perpendicular to the substrate in the stacked structure of the memory cell region, wherein the sidewall of the hole exposes the conductive film and the first insulating film in the stacked structure; The hole on the conductive film is located in the conductive film; Using the hole in the conductive film as a mask, laterally etching the first insulating film in the hole until the second insulating film located in the first insulating film is exposed through the hole, and laterally etching the second insulating film in the hole to form a second groove between two adjacent conductive films; After forming the second groove, the conductive film is laterally etched to form a first electrode and a second electrode on the conductive film, exposing the second insulating film; A step is formed between the bottom of the second groove in the second insulating film corresponding to the second groove and the side wall of the second insulating film exposed at the side wall of the hole in the conductive film; forming a semiconductor layer, a gate insulating layer and a gate electrode in sequence in the hole; The parasitic semiconductor layer between each two adjacent conductive films is removed.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Removing the parasitic semiconductor layer between two adjacent conductive films includes: removing the second insulating film between two adjacent holes by dry etching, retaining the second insulating film on the same layer as the conductive film between adjacent first grooves to expose the first insulating film, and wet etching the first insulating film to expose part of the side surface of the parasitic semiconductor layer between adjacent transistors; removing the second insulating film on the same layer as the first insulating film by patterned wet etching to expose a portion of the side surface of the parasitic semiconductor layer between adjacent transistors, and retaining a portion of the second insulating film on the same layer as the conductive film to form an etching stop layer; The exposed parasitic semiconductor layer is removed by patterned wet etching.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a plurality of first grooves penetrating the stacked structure by patterned etching includes: A plurality of first grooves penetrating the stack structure are formed by patterned etching, so that the first insulating film in the stack structure forms a first patterned structure; the conductive film in the stack structure forms a second patterned structure; the second patterned structure includes a bit line and a branch connected to the bit line, the bit line extends along a second direction, the branch extends along a first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects with the second direction.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: After filling the first groove with a second insulating film and before forming the hole, the method further includes: By patterned dry etching, the second insulating film corresponding to the end of the branch away from the bit line is etched away to form a trench extending in a direction perpendicular to the substrate, wherein the trench exposes the branch in the corresponding area and the side surface of the first insulating film; etching and removing the first insulating film exposed in the trench by wet selective etching to expose the side surface of the branch away from one end of the bit line; A first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode are sequentially formed at one end of the branch away from the bit line by an atomic layer deposition method, wherein the first capacitor electrode and the second capacitor electrode form a capacitor.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein: The memory further includes a lead region located on at least one side of the memory cell region. The method for manufacturing the semiconductor device further includes, after removing the parasitic semiconductor layer: The stacked structure of the lead area is formed into n steps; wherein the n steps are arranged in sequence along a direction perpendicular to the substrate, each step includes a first insulating film and a first conductive film that are stacked, the first conductive film of each step is located on the side of the first insulating film away from the substrate, and the first conductive film of each step forms a lead layer connected to the bit line of the memory cell area, wherein n is a natural number greater than 2.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Providing n steps to the stacked structure of the lead region includes: forming a fifth insulating film on the first insulating film in the lead area; forming a photoresist on the memory cell region and the lead region; Etching the photoresist to form a first exposed area on the photoresist, wherein the first exposed area exposes the fifth insulating film at one end of the lead region; Using a photolithography method, etching away the fifth insulating film and the first insulating film in the first exposed area to expose the nth layer of the first conductive film in the first exposed area; Etching the photoresist along an edge of the first exposed area to form a second exposed area connected to the first exposed area, wherein the second exposed area exposes the fifth insulating film of the lead area; By patterned dry etching, the nth layer of the first conductive film and the first insulating film of the first exposed area are etched away to expose the n-1th layer of the first conductive film of the first exposed area; the fifth insulating film and the first insulating film of the second exposed area are etched away to expose the nth layer of the first conductive film of the second exposed area, and the n-1th layer of the first conductive film of the first exposed area and the nth layer of the first conductive film of the second exposed area form a step.

7. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 6, comprising: A plurality of memory cells are distributed in different layers and stacked along a direction perpendicular to the substrate; the memory cells at least include transistors; The transistor includes a gate electrode, a semiconductor layer surrounding the sidewall of the gate electrode, and a gate insulating layer arranged between the sidewall of the gate electrode and the semiconductor layer; the semiconductor layers of the memory cells of different layers are physically disconnected along a direction perpendicular to the substrate; word lines, running through the different layers and extending in a direction perpendicular to the substrate, connected to gate electrodes of the memory cells of the different layers; A bit line extending in a direction parallel to the substrate and connected to at least one memory cell in the same layer; The memory cell further includes an etch stop layer, which is disposed on a side of the semiconductor layer of the transistor and between a first electrode and a second electrode of the transistor. The etch stop layer and the first and second electrodes surround the semiconductor layer.

8. The semiconductor device according to claim 7, wherein: It also includes a lead area located on at least one side of the storage cell area, the lead area includes n steps arranged in sequence along a direction perpendicular to the substrate, each step includes a first insulating film and a conductive film stacked together, the conductive film of each step is located on the side of the first insulating film away from the substrate, the conductive film of each step forms a lead layer, and n is a natural number greater than 2.

9. The semiconductor device according to claim 8, wherein It includes a first storage cell area and a second storage cell area arranged along a first direction, and a first lead area and a second lead area arranged along the first direction, the first lead area is located on one side of the first storage cell area in the second direction and is connected to the first storage cell area, the second lead area is located on one side of the second storage cell area in the second direction and is connected to the second storage cell area, the n steps in the first lead area are arranged in sequence along the first direction, and the n steps in the second lead area are arranged in sequence along the opposite direction of the first direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects the second direction.

10. The semiconductor device according to claim 8, wherein It comprises a first memory cell region and a second memory cell region arranged along a first direction, wherein the first memory cell region and the second memory cell region share a lead region, and n steps of the lead region are sequentially arranged along the first direction.

11. The semiconductor device according to claim 8, wherein The present invention comprises a first memory cell region and a second memory cell region arranged along a first direction, wherein the first memory cell region and the second memory cell region share a lead region, wherein the lead region comprises a first step row and a second step row, wherein the first step row and the second step row are arranged along a second direction, wherein the first step row comprises an even-numbered step, wherein the even-numbered step is sequentially arranged in a direction opposite to the first direction; wherein the second step row comprises an odd-numbered step, wherein the odd-numbered step is sequentially arranged in a direction opposite to the first direction, wherein the first direction and the second direction are both parallel to the substrate, and the first direction intersects the second direction.

12. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 7 to 11.

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