Storage unit, memory device and electronic device including the same

Abstract

The present application provides a memory cell, and a memory and electronic device containing the same. The memory cell includes a read transistor and a write transistor; the read transistor includes a first gate having a vertically extending first portion and a horizontally extending second portion, a first semiconductor layer surrounding the sidewalls of the first portion, and a first electrode layer, a first insulating layer, and a second electrode layer surrounding the first semiconductor layer and arranged vertically from bottom to top; the write transistor includes a second gate having a vertically extending third portion and a horizontally extending fourth portion, a second semiconductor layer surrounding the sidewalls of the third portion, and a third electrode layer, a third insulating layer, and a fourth electrode layer surrounding the second semiconductor layer and arranged vertically from bottom to top; the second portion and the second electrode layer have a first distance in the vertical direction that is less than a second distance between the fourth portion and the fourth electrode layer. The device architecture of the present application improves the capacitance of the storage node.

Description

Technical Field

[0001] The present application relates to, but is not limited to, semiconductor technology, and in particular to a storage unit and a memory and electronic device containing the same. Background Art

[0002] Conventional dynamic random access memory (DRAM) memory cells are based on a 1T1C structure consisting of a transistor and a capacitor. The transistor controls the read and write operations of information, while the capacitor stores charge information. Due to the large manufacturing area occupied by capacitors, increasing memory density presents significant process challenges, leading to increasing attention to capacitor-free memory cells. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0004] In one aspect, an exemplary embodiment of the present application provides a memory cell comprising a read transistor and a write transistor located above the read transistor;

[0005] The read transistor includes a first gate having a vertically extending first portion and a horizontally extending second portion, a first semiconductor layer surrounding a sidewall of the first portion, and a first electrode layer, a first insulating layer, and a second electrode layer surrounding the first semiconductor layer and arranged from bottom to top in a vertical direction;

[0006] The write transistor includes a second gate having a vertically extending third portion and a horizontally extending fourth portion, a second semiconductor layer surrounding a sidewall of the third portion, and a third electrode layer, a third insulating layer, and a fourth electrode layer surrounding the second semiconductor layer and arranged from bottom to top along the vertical direction;

[0007] The first gate is electrically connected to the third electrode layer;

[0008] There is a first distance between the second electrode layer and the second portion above the second electrode layer in the vertical direction, and there is a second distance between the fourth electrode layer and the fourth portion above the fourth electrode layer in the vertical direction, and the first distance is smaller than the second distance.

[0009] In an exemplary embodiment, the read transistor further includes a second insulating layer located between the second portion and the second electrode layer and extending horizontally, wherein the upper surface of the second insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor further includes a fourth insulating layer located between the fourth portion and the fourth electrode layer and extending horizontally, wherein the upper surface of the fourth insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

[0010] In an exemplary embodiment, the read transistor further includes a first gate insulating layer located between the first semiconductor layer and the first gate and isolating the first semiconductor layer from the first gate, and the write transistor further includes a second gate insulating layer located between the second semiconductor layer and the second gate and isolating the second semiconductor layer from the second gate.

[0011] In an exemplary embodiment, the read transistor also includes a horizontal extension portion of the first gate insulating layer located between the second portion and the second electrode layer, the upper surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second portion and the lower surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second electrode layer; the write transistor also includes a horizontal extension portion of the second gate insulating layer and a fourth insulating layer located between the fourth portion and the fourth electrode layer, the upper surface of the horizontal extension portion of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer.

[0012] In an exemplary embodiment, the read transistor further includes a horizontal extension of the first gate insulating layer and a second insulating layer located between the second portion and the second electrode layer, the upper surface of the horizontal extension of the first gate insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor further includes a horizontal extension of the second gate insulating layer and a fourth insulating layer located between the fourth portion and the fourth electrode layer, the upper surface of the horizontal extension of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

[0013] In an exemplary embodiment, the read transistor also includes a second insulating layer located between the second portion and the second electrode layer and arranged from bottom to top along the vertical direction, a second extension of the first semiconductor layer, and a horizontal extension of the first gate insulating layer, the upper surface of the horizontal extension of the first gate insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a fourth insulating layer located between the fourth portion and the fourth electrode layer and arranged from bottom to top along the vertical direction, a fourth extension of the second semiconductor layer, and a horizontal extension of the second gate insulating layer, the upper surface of the horizontal extension of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

[0014] In an exemplary embodiment, the material used for the first gate insulating layer and the second gate insulating layer is selected from one of silicon oxide, aluminum oxide, hafnium oxide, titanium oxide and zirconium oxide; the material used for the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are selected from silicon oxide or silicon oxynitride; and the thickness of the horizontal extension portion of the first gate insulating layer is less than the thickness of the first insulating layer and less than the thickness of the second insulating layer, and the thickness of the horizontal extension portion of the second gate insulating layer is less than the thickness of the third insulating layer or the thickness of the fourth insulating layer.

[0015] In an exemplary embodiment, the third electrode layer is a portion of a third extension portion of the second semiconductor layer.

[0016] In another aspect, an exemplary embodiment of the present application provides a memory including the above-mentioned storage unit. The memory may be, for example, a dynamic random access memory (DRAM).

[0017] In yet another aspect, an exemplary embodiment of the present application provides an electronic device including the above-mentioned memory.

[0018] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0019] The two transistors in the 2T0C memory cell of the present application are arranged in an asymmetric structure, i.e., the thickness of the insulating layer between the lateral extension of the gate of the read transistor and the read word line is less than or much less than the thickness of the insulating layer between the lateral extension of the gate of the write transistor and the write bit line. This not only greatly increases the storage node capacitance of the read transistor and improves the read performance, but also does not affect the performance of the write transistor.

[0020] The storage unit of the present application can also be configured so that the thickness of the insulating layer between the lateral extension portion of the gate of the write transistor and the write bit line remains unchanged, while the insulating layer between the lateral extension portion of the gate of the read transistor and the read word line is removed, that is, the read transistor is designed to have a structure without an insulating layer (interlayer insulating layer) between the semiconductor channel layer and the adjacent connection line. This can maximize the storage node capacitance of the read transistor and improve the reading performance.

[0021] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0023] Figure 1A A schematic diagram of a longitudinal structure of a storage unit provided in an exemplary embodiment of the present application;

[0024] Figure 1B An equivalent circuit diagram of a memory cell provided for an exemplary embodiment of the present application;

[0025] Figure 1C A schematic diagram comparing the storage node charge amounts of a memory cell provided in an exemplary embodiment of the present application and a memory cell in the prior art;

[0026] Figure 2 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0027] Figure 3 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0028] Figure 4 A schematic longitudinal structure diagram of an exemplary intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0029] Figure 5A A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0030] Figure 5BA schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of another method for manufacturing a storage unit provided in an exemplary embodiment of the present application;

[0031] Figure 6 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application; and

[0032] Figure 7 A schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step of a method for manufacturing a storage unit provided in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0033] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0034] The embodiments herein can be implemented in a variety of different forms. A person skilled in the art can easily understand that the implementation and content can be transformed into various forms without departing from the purpose and scope of this application. Therefore, this application should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other in any manner.

[0035] The scales of the figures in this application are intended to serve as a reference for actual processes, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing between them can be adjusted according to actual needs. The figures described in this application are merely schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values ​​shown in the figures.

[0036] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the words and phrases are not limited to those described in the specification and may be appropriately replaced according to the circumstances.

[0037] In this specification, unless otherwise specified or limited, the terms "disposed" and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0038] In the description of this application, ordinal numbers such as "first" and "second" are provided to avoid confusion of constituent elements, rather than to limit the quantity.

[0039] In this specification, "film" and "layer" can be interchanged. For example, "metal layer" can sometimes be replaced with "metal film".

[0040] In the description of this application, a transistor refers to a component comprising at least three terminals: a gate, a drain, and a source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In this application, the channel layer refers to the area through which the current mainly flows. In this application, the terms "channel layer" and "semiconductor layer" are interchangeable.

[0041] For memory cells without capacitors, 2T memory cells are currently mostly used. Typically, a memory cell contains two transistors, a read transistor and a write transistor, where the gate of the read transistor serves as a storage node. By storing different voltages corresponding to "1" and "0", the read transistor is controlled to be in an off or on state. According to the off and on states of the transistor, the stored information is determined to be "1" and "0". However, the applicant of this application has found that the storage capacity of this storage node needs to be improved in order to further increase the sensing margin and improve memory performance.

[0042] Therefore, an exemplary embodiment of the present application provides a memory cell, comprising a read transistor and a write transistor located above the read transistor; the read transistor comprises a first gate having a first portion extending vertically and a second portion extending horizontally, a first semiconductor layer surrounding the sidewall of the first portion, and a first electrode layer, a first insulating layer, and a second electrode layer surrounding the first semiconductor layer and arranged from bottom to top along the vertical direction; the write transistor comprises a second gate having a third portion extending vertically and a fourth portion extending horizontally, a second semiconductor layer surrounding the sidewall of the third portion, and a third electrode layer, a third insulating layer, and a fourth electrode layer surrounding the second semiconductor layer and arranged from bottom to top along the vertical direction; the first gate is electrically connected to the third electrode layer; the second electrode layer and the second portion located above the second electrode layer have a first distance in the vertical direction, the fourth electrode layer and the fourth portion located above the fourth electrode layer have a second distance in the vertical direction, and the first distance is less than the second distance.

[0043] As used in this application, "vertically extending" refers to extending along a vertical direction, which can be understood as a direction perpendicular to the substrate. Similarly, "horizontally extending" refers to extending along a horizontal direction, which can be understood as a direction parallel to the substrate.

[0044] As used in this application, the term "integrated structure" may refer to a microstructural separation between A and B, such as the absence of distinct interfaces such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integral. For example, A and B may be formed from the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0045] Figure 1A A schematic diagram of the longitudinal structure of a storage unit provided in an exemplary embodiment of the present application. Figure 1AAs shown, the present application provides an asymmetric 2TOC memory cell structure. The memory cell of the present application may include a read transistor 100 and a write transistor 200 located above the read transistor. The read transistor 100 may include a first gate 150 having a vertically extending first portion 151 and a horizontally extending second portion 152, a first semiconductor layer 130 surrounding the sidewalls of the first portion 151, and a first electrode layer 110, a first insulating layer 10, and a second electrode layer 120 surrounding the first semiconductor layer 130 and arranged from bottom to top along the vertical direction. The write transistor 200 may include a second gate 250 having a vertically extending third portion 251 and a horizontally extending fourth portion 252, a second semiconductor layer 230 surrounding the sidewalls of the third portion 251, and a third electrode layer 210, a third insulating layer 30, and a fourth electrode layer 220 surrounding the second semiconductor layer 230 and arranged from bottom to top along the vertical direction.

[0046] Figure 1A It is shown that both the first semiconductor layer 130 and the second semiconductor layer 230 are in the form of a ring channel, that is, the read transistor and the write transistor both adopt a ring channel structure.

[0047] Surrounding can be understood as partially or completely surrounding the first portion 151 of the first gate 150 or the third portion 251 of the second gate 250. In some embodiments, the surrounding can be completely surrounding as a whole, and the cross-section of the first semiconductor layer 130 or the second semiconductor layer 230 after surrounding can be a closed ring, and the ring shape is adapted to the outer contour of the cross section of the gate. Exemplarily, the cross section of the gate is, for example, a square structure. The interception direction of the cross section is intercepted along a direction perpendicular to the substrate. In some embodiments, the surrounding can be partial surrounding, and the cross section after surrounding is not closed, but presents a ring shape. For example, the cross section of the first semiconductor layer 130 or the second semiconductor layer 230 is a ring with an opening.

[0048] Figure 1A It is also shown that the third electrode layer 210 can be part of the third extension 232 of the second semiconductor layer 230, so that the third electrode layer 210 can be an integral structure with the first gate 150, or in other words, the third electrode layer 210 can be electrically connected to the first gate 150. Therefore, the present application obtains a capacitor-free memory, such as a 2TOC DRAM memory, by interconnecting the gate of the read transistor with the source or drain of the write transistor.

[0049] Figure 1AThe read transistor 100 is further shown to further include a first gate insulating layer 140 located between the first semiconductor layer 130 and the first gate 150 and isolating the first semiconductor layer 130 from the first gate 150. The write transistor 200 may further include a second gate insulating layer 240 located between the second semiconductor layer 230 and the second gate 250 and isolating the second semiconductor layer 230 from the second gate 250.

[0050] Continue to refer Figure 1A The read transistor 100 may further include a second insulating layer 20 located between the second portion 152 and the second electrode layer 120 and arranged from bottom to top along the vertical direction, a horizontally extending second extension portion 133 of the first semiconductor layer 130, and a horizontal extension portion 141 of the first gate insulating layer, wherein the upper surface of the horizontal extension portion 141 of the first gate insulating layer is in direct contact with the second portion 152 and the lower surface of the second insulating layer 20 is in direct contact with the second electrode layer 120, that is, the second portion 152 and the second electrode layer 120 include three layers in the vertical direction. The write transistor 200 may also include a fourth insulating layer 40 located between the fourth part 252 and the fourth electrode layer 220 and arranged from bottom to top along the vertical direction, a horizontally extending fourth extension portion 233 of the second semiconductor layer 230, and a horizontal extension portion 241 of the second gate insulating layer, the upper surface of the horizontal extension portion 241 of the second gate insulating layer is in direct contact with the fourth part 252 and the lower surface of the fourth insulating layer 40 is in direct contact with the fourth electrode layer 220, that is, three layers are included between the fourth part 252 and the fourth electrode layer 220 in the vertical direction.

[0051] A first distance H1 is defined in the vertical direction between the second electrode layer 120 and the second portion 152 located above the second electrode layer 120, and a second distance H2 is defined in the vertical direction between the fourth electrode layer 220 and the fourth portion 252 located above the fourth electrode layer 220. This application adjusts the thickness of the second insulating layer 20 of the read transistor and the thickness of the fourth insulating layer 40 of the write transistor so that the thickness of the second insulating layer 20 is less than or much less than the thickness of the fourth insulating layer 40. This means that the first distance H1 is less than or much less than the second distance H2, such as H1 being one-fifth, one-sixth, or one-seventh of H2. This structural design not only improves the storage node capacitance of the read transistor and enhances read performance, but also does not affect the performance of the write transistor.

[0052] As used in this application, the term "thickness" refers to the dimension of a film or a layer in a vertical direction, or refers to the total dimension of two or more films or layers in a vertical direction.

[0053] In an exemplary embodiment, the thickness of the fourth insulating layer 40 may be in a range of 50 nm to 200 nm, and the thickness of the second insulating layer 20 may be in a range of 0 to 10 nm.

[0054] In other exemplary embodiments, the read transistor 100 may further include a second insulating layer 20 located between the second portion 152 and the second electrode layer 120 and extending horizontally. The upper surface of the second insulating layer 20 is in direct contact with the second portion 152, and the lower surface of the second insulating layer 20 is in direct contact with the second electrode layer 120. That is, the second insulating layer 20 is located only between the second portion 152 and the second electrode layer 120. The second insulating layer 20 may function as a gate insulating layer. The write transistor 200 may further include a fourth insulating layer 40 located between the fourth portion 252 and the fourth electrode layer 220 and extending horizontally. The upper surface of the fourth insulating layer 40 is in direct contact with the fourth portion 252, and the lower surface of the fourth insulating layer 40 is in direct contact with the fourth electrode layer 220. That is, the fourth insulating layer 40 is located only between the fourth portion 252 and the fourth electrode layer 220. The fourth insulating layer 40 may also function as a gate insulating layer. The present application adjusts the thickness of the second insulating layer 20 of the read transistor and the thickness of the fourth insulating layer 40 of the write transistor so that the thickness of the second insulating layer 20 is smaller than or much smaller than the thickness of the fourth insulating layer 40.

[0055] In further exemplary embodiments, the read transistor 100 may further include a horizontal extension portion 141 of the first gate insulating layer located between the second portion 152 and the second electrode layer 120. The upper surface of the horizontal extension portion 141 of the first gate insulating layer is in direct contact with the second portion 152, and the lower surface of the horizontal extension portion 141 of the first gate insulating layer is in direct contact with the second electrode layer 120. That is, no second insulating layer 20 is included between the second portion 152 and the second electrode layer 120. The write transistor 200 may further include a horizontal extension portion 241 of the second gate insulating layer and a fourth insulating layer 40 located between the fourth portion 252 and the fourth electrode layer 220. The upper surface of the horizontal extension portion 241 of the second gate insulating layer is in direct contact with the fourth portion 252, and the lower surface of the fourth insulating layer 40 is in direct contact with the fourth electrode layer 220. In the present application, the thickness of the second insulating layer 20 is set to 0, that is, the read transistor does not include an insulating layer, so that the semiconductor layer / gate insulating layer of the read transistor is directly contacted and coupled with the source layer or drain layer (that is, the read word line) of the read transistor, thereby maximizing the capacitance of the storage node and enhancing the read performance of the device.

[0056] In an exemplary embodiment, the material used for the first gate insulating layer and the second gate insulating layer is selected from one of silicon oxide, aluminum oxide, hafnium oxide, titanium oxide and zirconium oxide; the material used for the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are selected from silicon oxide or silicon oxynitride; and the thickness of the horizontal extension portion of the first gate insulating layer is less than the thickness of the first insulating layer and less than the thickness of the second insulating layer, and the thickness of the horizontal extension portion of the second gate insulating layer is less than the thickness of the third insulating layer or the thickness of the fourth insulating layer.

[0057] In the present application, one of the first electrode and the second electrode in the read transistor can represent the source, and the other can represent the drain, and the position of the first electrode and the position of the second electrode can be interchanged. When determining which electrode is the source or the drain, it is related to the direction of current flow in the transistor and is not limited here. For example, the source can represent the electrode from which the current flows out, and the drain can represent the electrode into which the current flows. Similarly, one of the third electrode and the fourth electrode in the write transistor can represent the source, and the other can represent the drain, and the position of the third electrode and the position of the fourth electrode can be interchanged.

[0058] Figure 1B An equivalent circuit diagram of a memory cell provided for an exemplary embodiment of the present application. Figure 1B In the figure, SN represents a storage node, WWL, WBL, RWL, and RBL represent the write word line, write bit line, read word line, and read bit line, respectively. The first electrode of the read transistor is connected to the read bit line RBL, and the second electrode is connected to the read word line RWL. The gate of the write transistor is connected to the write word line WWL, and the fourth electrode of the write transistor is connected to the write bit line WBL. The gate of the read transistor is connected to the third electrode of the write transistor. The data "1" or "0" stored in the storage node controls the on / off state of the read transistor. The data stored in the storage node is determined to be "1" or "0" based on the on / off state of the read transistor.

[0059] The applicant notes that, since the thickness of the semiconductor layer and the gate insulating layer is typically less than 10 nm, the first distance H1 between the second electrode layer and the second portion of the gate (storage node) in a direction perpendicular to the substrate is typically determined by the thickness of the second insulating layer. The thickness of the second insulating layer of the read transistor can typically be in the range of 50 nm to 200 nm.

[0060] However, in the exemplary embodiment of the present application, the thickness of the second insulating layer of the read transistor can be set to a range of 0-10 nm, which can greatly improve the storage capacity of the storage node.

[0061] refer to Figure 1C, shows a comparison chart of simulation results of the capacitance storage capacity before and after the improvement of the memory cell structure of the present application. Figure 1C The results of the TCAD simulation test provided show that, compared with the case where the thickness of the second insulating layer of the read transistor (using oxide such as silicon oxide as an example) is 50 nm, the storage node charge is increased from approximately 1*10 -17 Increase to approximately 1*10 -15 , the charge increased by nearly 100 times.

[0062] In the embodiment of the present application, the increase in the storage capacity Cs of the storage node also helps to increase the change ΔV of the signal on the read transistor bit line BL during the charge sharing phase. BL Please refer to the following formula to understand the relationship between Cs and ΔV BL relationship.

[0063]

[0064] According to the above formula, as Cs increases, the change in the bit line voltage of the read transistor that can be sensed ΔVBL also increases during the data reading phase, that is, the range of the sensing window becomes larger, and the signal can be identified more accurately.

[0065] This application is aimed at a vertical transistor stack structure, thinning or removing the insulating layer between the read word line and the storage node, without increasing the footprint of the storage unit. On the contrary, while meeting the minimum capacitance requirement, the area of ​​the storage unit can be further reduced, thereby achieving further miniaturization of the device.

[0066] The technical solution of this application will be further illustrated below using the manufacturing process of a memory cell according to an exemplary embodiment of this application. The "patterning process" referred to in this exemplary embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a well-established manufacturing process in the relevant art. The "photolithography process" referred to in this exemplary embodiment includes film coating, mask exposure, and development, and is a well-established manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations herein. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film of a certain material deposited on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern."

[0067] In an exemplary embodiment, the manufacturing process of a memory cell may include:

[0068] S100: forming a first electrode layer, a first insulating layer, a second electrode layer, and a second insulating layer that extend horizontally and are vertically stacked.

[0069] Exemplary steps may include: forming a first electrode layer 110 of the read transistor 100 in the substrate 1 by photolithography and metallization processes, and making the upper surface of the substrate 1 and the first electrode layer 110 flush with each other by a planarization process, such as a chemical mechanical polishing (CMP) process; depositing a first insulating layer thin film on the first electrode layer 110 to form a first insulating layer 10; performing a metallization process to form a second electrode layer 120 of the read transistor 100 on the first insulating layer 10; and continuing to deposit a second insulating layer thin film on the second electrode layer 120 to form a second insulating layer 20, such as Figure 2 shown. Figure 2 This is a schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S100 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application.

[0070] In an exemplary embodiment, each insulating layer thin film may be deposited by using a chemical vapor deposition method, plasma enhanced chemical vapor deposition, atomic layer deposition (ALD) or the like.

[0071] In an exemplary embodiment, the substrate 1 may be made of an insulating material.

[0072] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of any one or more non-conductive materials selected from silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of an oxide insulating material, such as silicon dioxide (e.g., SiO2), to facilitate large-area deposition.

[0073] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of the same or different insulating materials.

[0074] In an exemplary embodiment, the metallization process can adopt a direct etch metal process or a damascene process. In an exemplary embodiment, the metallization process can adopt a variety of metals, including but not limited to tungsten, molybdenum, aluminum, copper, titanium nitride, cobalt, nickel, ruthenium and platinum, or alloys thereof.

[0075] In an exemplary embodiment, the first electrode layer 110 may be a read bit line RBL, and the second electrode layer 120 may be a read word line RWL.

[0076] S200: forming a first through-hole structure.

[0077] An exemplary step may include: forming a first through-hole structure K1 in the structure formed in the above step by a photolithography process, wherein the first through-hole structure K1 vertically extends through the second insulating layer 20, the second electrode layer 120, and the first insulating layer 10 and terminates at a side of the first electrode layer 110 close to the first insulating layer 10, such as Figure 3 shown. Figure 3 This is a schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S200 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application.

[0078] S300: forming a first semiconductor layer.

[0079] An exemplary step may include: depositing a semiconductor layer material thin film around the sidewall of the first through-hole structure K1, at the bottom of the first through-hole structure K1, and on the second insulating layer 20 to form a vertical portion 131 of the first semiconductor layer 130 extending around the sidewall of the first through-hole structure K1, and forming a first extension portion 132 of the first semiconductor layer 130 extending horizontally along the bottom of the first through-hole structure K1 and a second extension portion 133 extending horizontally along the second insulating layer 20, as shown in FIG. Figure 4 shown. Figure 4 A schematic diagram of the longitudinal structure of an exemplary intermediate product obtained in an intermediate step (ie, step S300 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application is provided.

[0080] In an exemplary embodiment, the first semiconductor layer 130 may be made of a metal oxide semiconductor material or a polycrystalline silicon material. In an exemplary embodiment, the metal oxide semiconductor material may be an amorphous or polycrystalline metal oxide semiconductor material, and the metal oxide semiconductor material has a slow corrosion rate in a weak acidic or weak alkaline solution. In an exemplary embodiment, the metal oxide semiconductor material may be an oxide of In, an oxide of Ga, an oxide of Zn, an oxide of Sn, or the like.

[0081] In an exemplary embodiment, when the first semiconductor layer 130 is made of IGZO metal oxide material, the leakage current of the transistor is small (the leakage current is less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, InGaO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a 、Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn zO a 、Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, it can be adjusted according to actual conditions.

[0082] In an exemplary embodiment, the first semiconductor layer 130 may not include the second extension portion 133 extending horizontally along the second insulating layer 20 , or the first semiconductor layer 130 may not include the first extension portion 132 extending horizontally along the bottom of the first through-hole structure K1 .

[0083] S400: forming a first gate.

[0084] An exemplary step may include: continuously depositing a dielectric layer film and a conductive film on the first semiconductor layer 130 to form a first gate insulating layer 140 and a first gate 150 (i.e., a storage node SN of the read transistor), wherein the first gate 150 includes a vertically extending first portion 151 and a horizontally extending second portion 152; then photolithography and etching to remove excess film layers, thereby forming a read transistor 100 having a vertical channel structure, as shown in FIG. Figure 5A shown. Figure 5A This is a schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S400 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application.

[0085] In an exemplary embodiment, the first gate insulating layer 140 may be a high-k dielectric layer, i.e., a dielectric layer with a K value of ≥ 3.9. The high-k dielectric layer may serve as a gate oxide. The first gate insulating layer 140 may be made of one or more of silicon dioxide (SiO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0086] In an exemplary embodiment, the first gate 150 may be made of ITO, P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0087] In an exemplary embodiment, each thin film layer may be deposited using an atomic layer deposition method.

[0088] refer to Figure 5AA second insulating layer 20 may be included between the second portion 152 of the first gate 150 and the second electrode layer 120. The thickness of the second insulating layer 20 may be in the range of 0-10 nm. A third extension 232 of the first semiconductor layer 130 and a horizontal extension 141 of the first gate insulating layer 140 may also be included between the second portion 152 of the first gate 150 and the second electrode layer 120.

[0089] Figure 5B This is a schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (i.e., step S400) of another method for manufacturing a storage unit according to an exemplary embodiment of the present application. Figure 5B The second insulating layer 20 is no longer included between the second portion 152 of the first gate 150 and the second electrode layer 120 , that is, the thickness of the second insulating layer is 0. That is, the semiconductor layer 130 is in direct contact with the second electrode layer 120 .

[0090] This application maximizes the capacitance of the storage node and improves the read rate by directly coupling the semiconductor layer of the read transistor to the source or drain (read word line) of the read transistor. Furthermore, direct contact between the semiconductor layer of the read transistor and the read word line saves a dielectric layer, thus reducing process steps, improving process efficiency, and lowering production costs.

[0091] S500: forming a fourth electrode layer and a second through-hole structure of the write transistor.

[0092] Exemplary steps may include: depositing a third insulating layer film to form a third insulating layer 30, so that the total thickness of the insulating layer meets the device contact area requirement; then performing a metallization process to form a fourth electrode layer 220 of the write transistor 200 on the third insulating layer 30; continuing to deposit a fourth insulating layer film to form a fourth insulating layer 40; and performing a photolithography process to form a second through-hole structure K2, the second through-hole structure K2 passing through the fourth insulating layer 40, the fourth electrode layer 220, and the third insulating layer 30 and terminating at the first gate 150 of the read transistor 100, as shown in FIG. Figure 6 shown. Figure 6 This is a schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S500 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application.

[0093] In an exemplary embodiment, the third insulating layer 30 and the fourth insulating layer 40 may be formed of any one or more non-conductive materials selected from the group consisting of silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). In an exemplary embodiment, the third insulating layer 30 and the fourth insulating layer 40 may be formed of an oxide insulating material, such as silicon dioxide (e.g., SiO2), to facilitate large-area deposition.

[0094] In an exemplary embodiment, the third insulating layer 30 and the fourth insulating layer 40 may be made of the same or different insulating materials.

[0095] The metallization process can be as described in the above steps.

[0096] In an exemplary embodiment, the fourth electrode layer 220 may be a write bit line WBL.

[0097] S600: forming a second gate.

[0098] Exemplary steps may include depositing a semiconductor layer material film around the sidewall of the second through-hole structure K2, at the bottom of the second through-hole structure K2, and on the fourth insulating layer 40 to form a vertical portion 231 of the second semiconductor layer 230 extending around the sidewall of the second through-hole structure K2, and forming a third extension portion 232 of the second semiconductor layer 230 extending horizontally along the bottom of the second through-hole structure K2 and a fourth extension portion 233 extending horizontally along the fourth insulating layer 40; continuing to deposit a dielectric layer film and a conductive film on the second conductor layer 230 to form a second gate insulating layer 240 and a second gate 250, the second gate 250 including a third portion 251 extending vertically and a fourth portion 252 extending horizontally; then photolithography and etching to remove excess film layers, i.e., forming a write transistor 200 with a vertical channel structure, as shown in FIG. Figure 7 shown. Figure 7 This is a schematic diagram of the longitudinal structure of an intermediate product obtained in an intermediate step (ie, step S600 ) of a method for manufacturing a storage unit according to an exemplary embodiment of the present application.

[0099] refer to Figure 7 A fourth insulating layer 40 may be included between the fourth portion 252 of the second gate 250 and the fourth electrode layer 220. The thickness of the fourth insulating layer 40 may be in the range of 50-200 nm. A fourth extension 233 of the second semiconductor layer 230 and a horizontal extension 241 of the second gate insulating layer 240 may also be included between the fourth portion 252 of the second gate 250 and the fourth electrode layer 220.

[0100] In this application, the thickness of the second insulating layer 20 between the second portion 152 of the first gate 150 of the read transistor and the second electrode layer 120 is smaller than or much smaller than the thickness of the fourth insulating layer 40 between the fourth portion 252 of the second gate 250 of the write transistor and the fourth electrode layer 220. In other words, the first distance H1 is smaller than or much smaller than the second distance H2, for example, H1 is one-fifth, one-sixth, or one-seventh of H2. This design significantly increases the storage node capacitance of the read transistor, improving read performance, while also maintaining the performance of the write transistor.

[0101] In an exemplary embodiment, the region of the second semiconductor layer 230 coupled to the second portion 152 of the first gate 150 is the third electrode layer 210 of the write transistor 200. Therefore, the first gate 150 of the read transistor 100 is electrically connected or coupled to the third electrode layer 210 of the write transistor 200.

[0102] In an exemplary embodiment, the second gate 250 of the write transistor 200 may be a write word line WWL.

[0103] In an exemplary embodiment, the second gate insulating layer 240 may be a high-k dielectric layer, i.e., a dielectric layer with a K value of ≥ 3.9. The high-k dielectric layer may serve as a gate oxide. The second gate insulating layer 240 may be made of one or more of silicon dioxide (SiO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0104] In an exemplary embodiment, the second gate 250 may be made of P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0105] In an exemplary embodiment, each thin film layer may be deposited using an atomic layer deposition method.

[0106] S700: Metallization technology is used to form connections at each end.

[0107] The exemplary embodiment of the present application further provides a memory, comprising the memory unit provided in the exemplary embodiment of the present application. The memory may be, for example, a DRAM.

[0108] An exemplary embodiment of the present application further provides an electronic device including the above-mentioned memory.

[0109] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0110] Although the embodiments disclosed in this application are as described above, the contents are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A storage unit, characterized in that: comprising a read transistor and a write transistor located above the read transistor; The read transistor includes a first gate having a vertically extending first portion and a horizontally extending second portion, a first semiconductor layer surrounding a sidewall of the first portion, and a first electrode layer, a first insulating layer, and a second electrode layer surrounding the first semiconductor layer and arranged from bottom to top in a vertical direction; The write transistor includes a second gate having a vertically extending third portion and a horizontally extending fourth portion, a second semiconductor layer surrounding a sidewall of the third portion, and a third electrode layer, a third insulating layer, and a fourth electrode layer surrounding the second semiconductor layer and arranged from bottom to top along the vertical direction; The first gate is electrically connected to the third electrode layer; There is a first distance between the second electrode layer and the second portion above the second electrode layer in the vertical direction, and there is a second distance between the fourth electrode layer and the fourth portion above the fourth electrode layer in the vertical direction, and the first distance is smaller than the second distance.

2. The storage unit according to claim 1, wherein The read transistor also includes a second insulating layer located between the second portion and the second electrode layer and extending horizontally, wherein the upper surface of the second insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a fourth insulating layer located between the fourth portion and the fourth electrode layer and extending horizontally, wherein the upper surface of the fourth insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

3. The storage unit according to claim 1, wherein The read transistor further includes a first gate insulating layer located between the first semiconductor layer and the first gate and isolating the first semiconductor layer from the first gate. The write transistor further includes a second gate insulating layer located between the second semiconductor layer and the second gate and isolating the second semiconductor layer from the second gate.

4. The storage unit according to claim 3, wherein: The read transistor also includes a horizontal extension portion of the first gate insulating layer located between the second portion and the second electrode layer, the upper surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second portion and the lower surface of the horizontal extension portion of the first gate insulating layer is in direct contact with the second electrode layer; the write transistor also includes a horizontal extension portion of the second gate insulating layer and a fourth insulating layer located between the fourth portion and the fourth electrode layer, the upper surface of the horizontal extension portion of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer.

5. The storage unit according to claim 3, wherein: The read transistor also includes a horizontal extension of the first gate insulating layer and a second insulating layer located between the second portion and the second electrode layer, the upper surface of the horizontal extension of the first gate insulating layer is in direct contact with the second portion and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a horizontal extension of the second gate insulating layer and a fourth insulating layer located between the fourth portion and the fourth electrode layer, the upper surface of the horizontal extension of the second gate insulating layer is in direct contact with the fourth portion and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer. The storage unit according to claim 3 , wherein: The read transistor also includes a second insulating layer, a second extension of the first semiconductor layer, and a horizontal extension of the first gate insulating layer, which are located between the second part and the second electrode layer and arranged from bottom to top along the vertical direction, the upper surface of the horizontal extension of the first gate insulating layer is in direct contact with the second part, and the lower surface of the second insulating layer is in direct contact with the second electrode layer; the write transistor also includes a fourth insulating layer, a fourth extension of the second semiconductor layer, and a horizontal extension of the second gate insulating layer, which are located between the fourth part and the fourth electrode layer and arranged from bottom to top along the vertical direction, the upper surface of the horizontal extension of the second gate insulating layer is in direct contact with the fourth part, and the lower surface of the fourth insulating layer is in direct contact with the fourth electrode layer, and the thickness of the second insulating layer is less than the thickness of the fourth insulating layer.

7. The storage unit according to any one of claims 4 to 6, characterized in that: The material used for the first gate insulating layer and the second gate insulating layer is selected from one of silicon oxide, aluminum oxide, hafnium oxide, titanium oxide and zirconium oxide; the material used for the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer is selected from silicon oxide or silicon oxynitride; and the thickness of the horizontal extension portion of the first gate insulating layer is less than the thickness of the first insulating layer and less than the thickness of the second insulating layer, and the thickness of the horizontal extension portion of the second gate insulating layer is less than the thickness of the third insulating layer or the thickness of the fourth insulating layer.

8. The storage unit according to claim 1, wherein: The third electrode layer is a portion of the third extension portion of the second semiconductor layer.

9. A memory, characterized in that: The method comprises the storage unit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: comprising a memory according to claim 9.

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