Memory device

Abstract

The invention provides a memory device. The memory device comprises a peripheral substrate and an array substrate. The peripheral substrate includes a page buffer and a high voltage processing circuit and has a peripheral substrate area. The array substrate comprises an array. The array substrate and the peripheral substrate are stacked on each other, and the circuit distribution area of the high-voltage processing circuit accounts for less than 10% of the area of the peripheral substrate.

Description

Technical Field

[0001] An embodiment of the present invention relates to a memory device. Background Art

[0002] As chip size becomes smaller and the operating speed becomes faster, the chip is more likely to generate high heat during operation. Therefore, how to dissipate the high heat generated during chip operation is one of the main issues for technicians in this technical field. Summary of the invention

[0003] The present invention relates to a memory device to improve the above-mentioned known problems.

[0004] According to one embodiment of the present invention, a memory device is provided. The memory device includes a peripheral substrate and an array substrate. The peripheral substrate includes a page buffer and a first high voltage processing circuit and has a peripheral substrate area. The array substrate includes an array. The array substrate and the peripheral substrate are stacked on each other, and a first circuit distribution area of ​​the first high voltage processing circuit occupies less than 10% of the peripheral substrate area.

[0005] According to another embodiment of the present invention, a memory device is provided. The memory device includes a peripheral substrate, an array substrate and a high voltage processing substrate. The peripheral substrate includes a page buffer. The array substrate includes an array. The high voltage processing substrate includes a high voltage processing circuit. The array substrate, the peripheral substrate and the high voltage processing substrate are stacked on each other, and the peripheral substrate does not have any high voltage processing circuit.

[0006] According to another embodiment of the present invention, a memory device is provided. The memory device includes a circuit board, a high voltage processing substrate, a peripheral substrate and an array substrate. The peripheral substrate includes a page buffer. The high voltage processing substrate includes a high voltage processing circuit and has a high voltage processing substrate area. The array substrate includes an array. The array substrate and the peripheral substrate are stacked on the circuit board, and the high voltage processing substrate is arranged side by side on the circuit board, and a high voltage processing circuit area of ​​the high voltage processing circuit accounts for more than 90% of the area of ​​the high voltage processing substrate.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A side view of a memory device in accordance with an embodiment of the present invention is shown.

[0009] Figure 1B Shows Figure 1A A top view of a peripheral substrate and an array substrate of a memory device.

[0010] Figure 2A A side view of a memory device according to another embodiment of the present invention is shown.

[0011] Figure 2B Shows Figure 2A A top view of a peripheral substrate, an array substrate, and a high voltage processing substrate of a memory device.

[0012] Figure 3A A side view of a memory device according to another embodiment of the present invention is shown.

[0013] Figure 3B Shows Figure 3A A top view of a peripheral substrate, an array substrate, and a high voltage processing substrate of a memory device.

[0014] Figure 4A A side view of a memory device according to another embodiment of the present invention is shown.

[0015] Figure 4B Shows Figure 4A A top view of a peripheral substrate, an array substrate, and a high voltage processing substrate of a memory device.

[0016] Figure 5A A cross-sectional view of a memory device according to another embodiment of the present invention is shown.

[0017] Figure 5B A cross-sectional view of a memory device according to another embodiment of the present invention is shown.

[0018] Fig. 6A A top view of a memory device according to another embodiment of the present invention is shown.

[0019] Figure 6B Shows Fig. 6A A cross-sectional view of the memory device along direction 6A-6B'.

[0020] Fig. 7A A top view of a memory device according to another embodiment of the present invention is shown.

[0021] Figure 7B Shows Fig. 7A A cross-sectional view of the memory device along direction 7A-7B'.

[0022] Fig. 8A A top view of a memory device according to another embodiment of the present invention is shown.

[0023] Figure 8B Shows Fig. 8A A cross-sectional view of the memory device along direction 8A-8B'.

[0024] Description of reference numerals:

[0025] 100, 200, 300, 400, 500, 500', 600, 700, 800: memory device

[0026] 110, 210, 410, 510, 510': Peripheral substrate

[0027] 111, 211: Page Buffer

[0028] 112, 212: First high voltage processing circuit

[0029] 113, 232, 332: Low voltage input contacts

[0030] 114, 233, 333: High voltage input contacts

[0031] 120, 220, 520, 520': Array substrate

[0032] 121, 221: Array

[0033] 230, 330, 530, 530': High voltage processing substrate

[0034] 231, 331: The third high voltage processing circuit

[0035] 334, 511: Contact

[0036] 510v, 530v: conductive hole

[0037] 511', 521', 522', 531': pads 640: solder wire

[0038] 750, 850: Circuit board

[0039] A 110 , A2 10 :Peripheral substrate area

[0040] A 112 , A2 12 :The first circuit distribution area

[0041] A 120 , A2 20 : Array substrate area

[0042] A2 30 :High voltage processing substrate area

[0043] A2 31 , A 331 :The third circuit distribution area

[0044] LV: Low Voltage

[0045] HV: High Voltage DETAILED DESCRIPTION

[0046] Please refer to Figure 1A-1B , Figure 1A 1 shows a side view of a memory device 100 according to an embodiment of the present invention, and Figure 1B Shows Figure 1A FIG. 1 is a top view of a peripheral substrate 110 and an array substrate 120 of a memory device 100. The memory device 100 is, for example, a flash memory, such as a NAND memory.

[0047] like Figure 1B As shown, the memory device 100 includes a peripheral substrate 110 and an array substrate 120. The peripheral substrate 110 includes at least one page buffer 111 and a first high voltage processing circuit 112 and has a peripheral substrate area A. 110 The array substrate 120 includes an array 121. The array substrate 120 and the peripheral substrate 110 are stacked on each other, and the first circuit distribution area A of the first high voltage processing circuit 112 is 112 Occupies surrounding substrate area A 110 10% or less, such as 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10% or a real number between the above two ratios. Compared with the page buffer 111, the first high voltage processing circuit 112 and the array 121 formed on the same substrate, since the array 121 of the present embodiment is moved to the array substrate 120, the peripheral substrate 110 can free up a larger space to form a larger page buffer 111. The larger page buffer 111 can provide more temporary storage space for data reading and can meet the requirements of higher operating speed. In addition, the peripheral substrate 110 and the array substrate 120 can be manufactured separately, which can simplify the overall process and / or circuit design complexity of the memory device 100.

[0048] The term "array" herein includes, for example, a "memory structure". The term "area" herein refers to, for example, a "top-view area".

[0049] The substrate of the peripheral substrate 110 and the substrate of the array substrate 120 are, for example, silicon wafers. The circuits on the peripheral substrate 110 and the array substrate 120 are, for example, formed by semiconductor processes.

[0050] like Figure 1AAs shown, the peripheral substrate 110 further includes at least one low voltage input contact 113 and at least one high voltage input contact 114. The low voltage input contact 113 is used to receive a set of or more low voltages LV between 1.8 volts (V) and 5V, and the high voltage input contact 114 is used to receive a high voltage HV equal to or higher than 5V. Since the memory device 100 can directly receive the high voltage HV and reduce the load of the first high voltage processing circuit 112 boosting (for example, simplifying the circuit design, reducing the occupied space, etc.), the first circuit distribution area A of the first high voltage processing circuit 112 is 112 Occupies surrounding substrate area A 110 The ratio can be reduced (compared to the case where the peripheral substrate 110 does not receive the high voltage HV).

[0051] The “contact point” herein refers to various input / output contacts such as a conductive pad, a conductive bump, and a conductive pillar.

[0052] The "high voltage processing circuit" herein is used, for example, to increase a low voltage to a high voltage, for example, to the operating voltage of the array, such as 30 V. Specifically, the high voltage processing circuit is, for example, a charge pumping circuit, a word line decoder, a word line switch, or other circuits capable of converting or processing high and low voltages.

[0053] like Figure 1B As shown, the peripheral substrate 110 includes circuits other than the array. In other words, the peripheral substrate 110 does not include the array, and all circuits other than the array can be formed on the peripheral substrate 110. The peripheral substrate 110 and the array substrate 120 can be connected by face-to-face cu-cu hybrid bonding and through-silicon vias (TSV) (similar to Figure 5A In other embodiments, the peripheral substrate 110 and the array substrate 120 may be connected vertically by hybrid bonding, wherein hybrid bonding is, for example, forming metal pads for connection on the peripheral substrate 110 and the array substrate 120, and electrically connecting the peripheral substrate 110 and the array substrate 120 by the metal pads.

[0054] like Figure 1B As shown, the array substrate 120 has an array substrate area A 120In this embodiment, the array substrate 120 does not include a second high voltage processing circuit. In another embodiment, the array substrate 120 may include a second high voltage processing circuit having a second circuit distribution area, wherein the second circuit distribution area occupies an area A of the array substrate. 120 Since the memory device 100 can directly receive the high voltage HV, the proportion of the second high voltage processing circuit in the array substrate 120 can be reduced or even eliminated.

[0055] Please refer to Figure 2A-2B , Figure 2A 2 shows a side view of a memory device 200 according to another embodiment of the present invention, and Figure 2B Shows Figure 2A FIG. 2 is a top view of a peripheral substrate 210, an array substrate 220, and a high voltage processing substrate 230 of a memory device 200. The memory device 200 is, for example, a flash memory, such as a NAND memory.

[0056] like Figure 2A As shown, the memory device 200 includes a peripheral substrate 210, an array substrate 220, and a high voltage processing substrate 230. The array substrate 220, the peripheral substrate 210, and the high voltage processing substrate 230 are stacked on each other. One of the array substrate 220, the peripheral substrate 210, and the high voltage processing substrate 230 can be disposed between the other two of the array substrate 220, the peripheral substrate 210, and the high voltage processing substrate 230. The substrate of the peripheral substrate 210, the substrate of the array substrate 220, and the substrate of the high voltage processing substrate 230 are, for example, silicon wafers. The circuits on the peripheral substrate 210, the array substrate 220, and the high voltage processing substrate 230 are formed using semiconductor processes.

[0057] like Figure 2B As shown, the peripheral substrate 210 includes a page buffer 211 and has a peripheral substrate area A. 210 The array substrate 220 includes an array 221. The first circuit distribution area A of the first high voltage processing circuit 212 212 Occupies surrounding substrate area A 210 , such as 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10% or a real number between the above two ratios. Compared with the page buffer 211, the first high voltage processing circuit 212 and the peripheral substrate 210 formed on the same substrate, since the array 221 of the present embodiment is moved to the array substrate 220, the peripheral substrate 210 can free up a larger space to form a larger page buffer 211. The larger page buffer 211 can provide more temporary storage space for data reading and can meet the requirements of higher operating speed. In addition, the peripheral substrate 210, the array substrate 220 and the high voltage processing substrate 230 are manufactured separately, which can simplify the overall process and circuit design complexity of the memory device 200.

[0058] like Figure 2B As shown, the peripheral substrate 210 includes circuits other than the array. In other words, the peripheral substrate 210 does not include the array, and all circuits other than the array can be formed on the peripheral substrate 210. The peripheral substrate 210, the array substrate 220, and the high voltage processing substrate 230 can be connected by at least one silicon through hole (similar to Figure 5A In other embodiments, the peripheral substrate 210, the array substrate 220 and the high voltage processing substrate 230 may be connected vertically by hybrid bonding, wherein the hybrid bonding may be, for example, formed on the two substrates respectively with metal pads for docking, and the two substrates may be electrically connected and signal connected by the metal pads.

[0059] like Figure 2B As shown, the array substrate 220 has an array substrate area A 220 In this embodiment, the array substrate 220 does not include a second high voltage processing circuit. In another embodiment, the array substrate 220 may include a second high voltage processing circuit having a second circuit distribution area, wherein the second circuit distribution area occupies an area A of the array substrate. 220 Since the memory device 200 can receive the high voltage HV, the proportion of the second high voltage processing circuit in the array substrate 220 can be reduced or even eliminated.

[0060] like Figure 2B As shown, the high voltage processing substrate 230 includes a third high voltage processing circuit 231, at least one low voltage input contact 232 and at least one high voltage input contact 233. The low voltage input contact 232 is used to receive a low voltage LV lower than 5V, and the high voltage input contact 233 is used to receive a high voltage HV equal to or higher than 5V. The memory device 200 can selectively receive the high voltage HV. In this embodiment, the third circuit distribution area A of the third high voltage processing circuit 231 is 231 The high voltage processing substrate area A of the high voltage processing substrate 230 is occupied 230 90% or more, for example, 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 98%, 100% or a real number between the above two ratios. In this embodiment, even if the high voltage input contact 233 is omitted, the third circuit distribution area A of the third high voltage processing circuit 231 is 231 The high voltage processing substrate area A of the high voltage processing substrate 230 is occupied 230 Therefore, there is enough space to form a boost circuit, which can increase the low voltage LV to the high voltage HV in the high voltage processing substrate 230.

[0061] In this embodiment, most of the high voltage processing circuits of the memory device 200 are configured on the high voltage processing substrate 230 , so the overall thermal management of the memory device 200 can be performed solely on the high voltage processing substrate 230 , which is beneficial to the heat dissipation rate of the memory device 200 .

[0062] Please refer to Figure 3A-3B , Figure 3A 2 shows a side view of a memory device 300 according to another embodiment of the present invention, and Figure 3B Shows Figure 3A FIG. 3 is a top view of a peripheral substrate 210, an array substrate 220, and a high voltage processing substrate 330 of a memory device 300. The memory device 300 is, for example, a flash memory, such as a NAND memory.

[0063] like Figure 3B As shown, the memory device 300 includes a peripheral substrate 210, an array substrate 220, and a high voltage processing substrate 330. The array substrate 220, the peripheral substrate 210, and the high voltage processing substrate 330 are stacked on each other. One of the array substrate 220, the peripheral substrate 210, and the high voltage processing substrate 330 can be arranged between the other two of the array substrate 220, the peripheral substrate 210, and the high voltage processing substrate 330. The substrate of the peripheral substrate 210, the substrate of the array substrate 220, and the substrate of the high voltage processing substrate 330 are, for example, silicon wafers. The circuits on the peripheral substrate 210, the array substrate 220, and the high voltage processing substrate 330 are formed using semiconductor processes.

[0064] The memory device 300 of the embodiment of the present invention includes the same or similar technical features (structure, connection relationship, etc.) as the memory device 200, except that the size (eg, top view area) of the high voltage processing substrate 330 of the memory device 300 is smaller.

[0065] The peripheral substrate 210, the array substrate 220 and the high voltage processing substrate 330 can be connected by at least one silicon through hole (similar to Figure 5A In other embodiments, the peripheral substrate 210, the array substrate 220 and the high voltage processing substrate 330 may be connected vertically by hybrid bonding, wherein the hybrid bonding may be, for example, formed on the two substrates respectively with metal pads for docking, and the two substrates may be electrically connected and signal connected by the metal pads.

[0066] like Figure 3BAs shown, the high voltage processing substrate 330 includes a third high voltage processing circuit 331, at least one low voltage input contact 332 and at least one high voltage input contact 333. The low voltage input contact 332 is used to receive a low voltage LV lower than 5V, and the high voltage input contact 333 is used to receive a high voltage HV equal to or higher than 5V. In this embodiment, the third circuit distribution area A of the third high voltage processing circuit 331 is 331 The high voltage processing substrate area A of the high voltage processing substrate 330 is occupied 320 %, for example, 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 98%, 100% or a real number between the above two ratio values. In this embodiment, since the memory device 300 can directly receive the high voltage HV and reduce the load of the third high voltage processing circuit 331 boosting (for example, simplifying the circuit design, reducing the occupied space, etc.), the size of the high voltage processing substrate 330 can be reduced.

[0067] Please refer to Figures 4A to 4B , Figure 4A 4 shows a side view of a memory device 400 according to another embodiment of the present invention, and Figure 4B Shows Figure 4A FIG. 4 is a top view of a peripheral substrate 410, an array substrate 220, and a high voltage processing substrate 330 of a memory device 400. The memory device 400 is, for example, a flash memory, such as a NAND memory.

[0068] like Figure 4A As shown, the memory device 400 includes a peripheral substrate 410, an array substrate 220, and a high voltage processing substrate 330. The peripheral substrate 410, the array substrate 220, and the high voltage processing substrate 330 are stacked on each other. One of the peripheral substrate 410, the array substrate 220, and the high voltage processing substrate 330 can be disposed between the other two of the peripheral substrate 410, the array substrate 220, and the high voltage processing substrate 330. The substrate of the peripheral substrate 410, the substrate of the array substrate 220, and the substrate of the high voltage processing substrate 330 are, for example, silicon wafers. The circuits on the peripheral substrate 410, the array substrate 220, and the high voltage processing substrate 330 are, for example, formed using semiconductor processes.

[0069] The memory device 400 of the embodiment of the present invention includes the same or similar technical features (structure, connection relationship, etc.) as the memory device 300 , except that the first high voltage processing circuit 212 may be omitted from the peripheral substrate 410 .

[0070] like Figure 4BAs shown, the high voltage processing substrate 330 includes a third high voltage processing circuit 331, at least one low voltage input contact 332 and at least one high voltage input contact 333. The low voltage input contact 332 is used to receive a low voltage LV lower than 5V, and the high voltage input contact 333 is used to receive a high voltage HV equal to or higher than 5V. In this embodiment, the third circuit distribution area A of the third high voltage processing circuit 331 is 331 The high voltage processing substrate area A of the high voltage processing substrate 330 is occupied 320 %, for example, 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 98%, 100% or a real number between the above two ratio values. In this embodiment, since the memory device 400 can directly receive the high voltage HV and reduce the load of the third high voltage processing circuit 331 boosting (for example, simplifying the circuit design, reducing the occupied space, etc.), the size of the high voltage processing substrate 330 can be reduced.

[0071] The peripheral substrate 410, the array substrate 220 and the high voltage processing substrate 330 can be connected by at least one silicon through hole (similar to Figure 5A In other embodiments, the peripheral substrate 410, the array substrate 220 and the high voltage processing substrate 330 may be connected vertically by hybrid bonding, wherein the hybrid bonding may be, for example, formed on the two substrates respectively with metal pads for docking, and the two substrates may be electrically connected and signal connected by the metal pads.

[0072] Please refer to Figure 5A , which shows a cross-sectional view of a memory device 500 according to another embodiment of the present invention. The memory device 500 is, for example, a flash memory, such as a NAND memory. The memory device 500 includes a peripheral substrate 510, an array substrate 520, and a high voltage processing substrate 530. The peripheral substrate 510, the array substrate 520, and the high voltage processing substrate 530 are stacked on each other. One of the peripheral substrate 510, the array substrate 520, and the high voltage processing substrate 530 can be disposed between the other two of the peripheral substrate 510, the array substrate 520, and the high voltage processing substrate 530.

[0073] like Figure 5A As shown, in this embodiment, the peripheral substrate 510 includes the same or similar technical features as the peripheral substrates of other embodiments of this invention, which will not be described in detail here. The array substrate 520 includes the same or similar technical features as the array substrates of other embodiments of this invention, which will not be described in detail here. The high voltage processing substrate 530 includes the same or similar technical features as the high voltage processing substrates of other embodiments of this invention, which will not be described in detail here.

[0074] like Figure 5A As shown, in this embodiment, one of the peripheral substrate 510, the array substrate 520 and the high voltage processing substrate 530 includes at least one conductive hole, and the conductive hole electrically connects the other of the peripheral substrate 510, the array substrate 520 and the high voltage processing substrate 530. For example, Figure 5A As shown, the peripheral substrate 510 has at least one conductive hole 510v, and the high voltage processing substrate 530 has at least one conductive hole 530v, and the conductive hole 510v electrically connects the array substrate 520 and the conductive hole 530v of the high voltage processing substrate 530. The conductive hole herein is, for example, a through-silicon via (TSV).

[0075] Please refer to Figure 5B , which shows a cross-sectional view of a memory device 500' according to another embodiment of the present invention. The memory device 500' is, for example, a flash memory, such as a NAND memory. The memory device 500' includes a peripheral substrate 510', an array substrate 520', and a high voltage processing substrate 530'. The peripheral substrate 510', the array substrate 520', and the high voltage processing substrate 530' are stacked on each other. One of the peripheral substrate 510', the array substrate 520', and the high voltage processing substrate 530' can be configured between the other two of the peripheral substrate 510', the array substrate 520', and the high voltage processing substrate 530'.

[0076] and Figure 5A Unlike the memory device 500 of the present embodiment, the two substrates of the memory device 500' of the present embodiment can be connected by hybrid bonding. For example, the peripheral substrate 510' includes at least one pad 511' and at least one pad 512', wherein the pad 511' and the pad 512' are respectively formed on two opposite sides of the array substrate 510'. The array substrate 520' includes at least one pad 521'. The high voltage processing substrate 530' includes at least one pad 531'. The pad 512' of the peripheral substrate 510' and the pad 521' of the array substrate 520' are connected by hybrid bonding, while the pad 511' of the peripheral substrate 510' and the pad 531' of the high voltage processing substrate 530' are connected by hybrid bonding. In addition, the aforementioned pads are, for example, metal pads.

[0077] Please refer to Figures 6A-6B , Fig. 6A 2 shows a top view of a memory device 600 according to another embodiment of the present invention, and Figure 6B Shows Fig. 6A 6 is a cross-sectional view of a memory device 600 along direction 6A-6B'. The memory device 600 is, for example, a flash memory, such as a NAND memory.

[0078] like Fig. 6A and 6BAs shown, the memory device 600 includes a peripheral substrate 210, an array substrate 220, a high voltage processing substrate 330 and at least one bonding wire 640. In this embodiment, the peripheral substrate 210 is disposed between the array substrate 220 and the high voltage processing substrate 330, but this is not intended to limit the embodiment of the present invention. 330 The peripheral substrate area A is smaller than the peripheral substrate 210. 210 , and the bonding wire 640 connects the high voltage processing substrate 330 and the peripheral substrate 210 .

[0079] Please refer to Figures 7A-7B , Fig. 7A 2 shows a top view of a memory device 700 according to another embodiment of the present invention, and Figure 7B Shows Fig. 7A 7 is a cross-sectional view of a memory device 700 along direction 7A-7B'. The memory device 700 is, for example, a flash memory, such as a NAND memory.

[0080] like Fig. 7A and 7B As shown, the memory device 700 includes a peripheral substrate 510, an array substrate 520, a high voltage processing substrate 330, at least one bonding wire 640 and a circuit board 750. In this embodiment, the peripheral substrate 510 and the array substrate 520 are stacked on the circuit board 750, and the high voltage processing substrate 330 is configured on the circuit board 750, wherein a stacked structure composed of the peripheral substrate 510 and the array substrate 520 and the high voltage processing substrate 330 are arranged side by side on the circuit board 750. The peripheral substrate 510 includes at least one contact 511, which is exposed from the peripheral substrate 510 and faces upward. The high voltage processing substrate 330 includes at least one contact 334, which is exposed from the high voltage processing substrate 330 and faces upward. The bonding wire 640 connects the exposed contact 334 of the high voltage processing substrate 330 and the exposed contact 511 of the peripheral substrate 510.

[0081] Please refer to Figures 8A-8B , Fig. 8A 8 shows a top view of a memory device 800 according to another embodiment of the present invention, and Figure 8B Shows Fig. 8A 8 is a cross-sectional view of a memory device 800 along direction 8A-8B'. The memory device 800 is, for example, a flash memory, such as a NAND memory.

[0082] like Fig. 8A and 8BAs shown, the memory device 800 includes a peripheral substrate 510, an array substrate 520, a high voltage processing substrate 330 and a circuit board 850. In this embodiment, the peripheral substrate 510 and the array substrate 520 are stacked on the circuit board 850, and the high voltage processing substrate 330 is configured on the circuit board 850, wherein a stacked structure composed of the peripheral substrate 510 and the array substrate 520 and the high voltage processing substrate 330 are arranged side by side on the circuit board 850. The peripheral substrate 510 includes at least one conductive hole 510v, which is electrically connected to the circuit board 850 downward. The high voltage processing substrate 330 includes at least one contact 334, which is electrically connected to the circuit board 850 downward. In this way, the aforementioned stacked structure and the high voltage processing substrate 330 are electrically connected through the circuit board 850.

[0083] In summary, an embodiment of the present invention proposes a memory device, which includes a page buffer, a high voltage processing circuit and an array, wherein the page buffer, most of the high voltage processing circuit and the array can be formed on different substrates respectively. Compared with the page buffer, the high voltage processing circuit and the array formed on the same substrate, since the array of the present embodiment is moved to the array substrate, the peripheral substrate can free up a larger space to form a larger page buffer. The larger page buffer can provide more data for reading and can provide the demand for higher operating speed. In addition, the peripheral substrate and the array substrate are made separately, which can simplify the overall process and / or circuit design complexity of the memory device. In another embodiment, at least two of the peripheral substrate, the array substrate and the high voltage processing substrate are stacked on each other into a stacked structure and configured on a circuit board, and the other of the peripheral substrate, the array substrate and the high voltage processing substrate is configured side by side with the stacked structure on the circuit board. In addition, the aforementioned stacked structure and the other can be electrically connected through a welding wire; or, the aforementioned stacked structure and the other are electrically connected through a circuit board (the welding wire can be omitted).

[0084] In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person skilled in the art in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention, and shall not be limited by the embodiments of the present invention, but shall still be within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached claims.

Claims

1. A memory device, comprising: A peripheral substrate including a page buffer and a first high voltage processing circuit and having a peripheral substrate area; and An array substrate (Array substrate), comprising an array; The array substrate and the peripheral substrate are stacked on each other, and a first circuit distribution area of ​​the first high voltage processing circuit occupies less than 10% of the area of ​​the peripheral substrate.

2. The memory device according to claim 1, wherein the array substrate has an array substrate area and includes a second high voltage processing circuit, and a second circuit distribution area of ​​the second high voltage processing circuit occupies less than 1% of the array substrate area. 3 . The memory device according to claim 1 , further comprising a high voltage processing substrate, wherein the array substrate, the peripheral substrate and the high voltage processing substrate are stacked on each other. 4 . The memory device according to claim 3 , wherein the high voltage processing substrate comprises a high voltage input contact, the high voltage input contact being configured to receive a voltage equal to or higher than 5V. 5 . The memory device according to claim 1 , wherein the peripheral substrate further comprises a high voltage input contact, the high voltage input contact being configured to receive a voltage equal to or higher than 5V.

6. The memory device of claim 1 , further comprising: a circuit board; a high voltage processing substrate; The peripheral substrate and the high voltage processing substrate are arranged side by side on the circuit board.

7. The memory device of claim 6, wherein the high voltage handling substrate is disposed on the circuit board with a contact.

8. A memory device comprising: a peripheral substrate including a page buffer; An array substrate comprises an array; as well as a high voltage handling substrate including a high voltage handling circuit; The array substrate, the peripheral substrate and the high voltage processing substrate are stacked on each other, and the peripheral substrate does not have any high voltage processing circuit.

9. The memory device according to claim 8, wherein the high voltage processing substrate further comprises a high voltage input contact, the high voltage input contact being used to receive a voltage equal to or higher than 5V.

10. A memory device comprising: a circuit board; a peripheral substrate including a page buffer; A high voltage processing substrate including a high voltage processing circuit and having a high voltage processing substrate area; as well as An array substrate comprises an array; The array substrate and the peripheral substrate are stacked on the circuit board, and the high voltage processing substrate is configured on the circuit board. The area of ​​a high voltage processing circuit of the high voltage processing circuit occupies more than 90% of the area of ​​the high voltage processing substrate.

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