Semiconductor device and radio frequency switch device

Abstract

The invention relates to the technical field of semiconductor devices, and discloses a semiconductor device and a radio frequency switch device. The buried oxide layer is formed on the surface of one side of the substrate layer; the active layer is formed on the surface of one side, far away from the substrate layer, of the buried oxide layer, and a plurality of shallow trench isolation structures and active regions between the adjacent shallow trench isolation structures are formed in the active layer; the main tube gate structure is formed on one side surface, far away from the buried oxide layer, of the at least one active region; wherein the thickness of the active region is # imgabs0 # to # imgabs1 # and / or, the active region comprises a body region located in the middle region, a source-drain region located between the body region and the shallow trench isolation structure, and an optimization region located between the body region and the upper surface of the active region, the optimization region is further in contact with the source-drain region, and the doping concentration of the optimization region is higher than 5E14 / cm < 3 >. According to the invention, the parasitic capacitance Coff of the MOS tube can be reduced, and the FOM of the MOS tube can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a radio frequency switch device. Background Art

[0002] Silicon On Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a semiconductor device based on an SOI substrate. MOSFET (MOS tube for short) that utilizes the properties of SOI materials can reduce parasitic capacitance, increase switching speed, and reduce leakage current, thereby reducing energy consumption. It has been widely used in high-performance computing, communication systems, automotive electronics, aerospace, and medical equipment.

[0003] RF switch devices include multiple SOI MOS tubes. The performance and reliability of RF switch devices can be evaluated by parameters such as Figure of Merit (FOM), reverse bias voltage (RFBV) and electrostatic discharge (ESD) capability. However, when optimizing the performance of RF switch devices by adjusting parameters such as the doping concentration of the active region of the SOI MOS tube, FOM, RFBV and ESD may increase or decrease at the expense of each other, and the three parameters cannot be well taken into account, which affects the performance optimization results of the RF switch devices. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor device and a radio frequency switch device to improve the problem that the three parameters of FOM, RFBV and ESD cannot be well taken into account, which affects the performance optimization result of the radio frequency switch device.

[0005] In a first aspect, the present application provides a semiconductor device, the semiconductor device comprising:

[0006] substrate layer;

[0007] A buried oxide layer is formed on a surface of one side of the substrate layer;

[0008] An active layer is formed on a surface of the buried oxide layer away from the substrate layer, wherein a plurality of shallow trench isolation structures and active regions between adjacent shallow trench isolation structures are formed in the active layer;

[0009] A main gate structure is formed on a surface of at least one active region away from the buried oxide layer;

[0010] The thickness of the active region is to and / or,

[0011] The active area includes a body area located in the middle area, a source and drain area located between the body area and the shallow trench isolation structure, and an optimized area located between the body area and the upper surface of the active area. The optimized area is also in contact with the source and drain area. The doping concentration of the optimized area is higher than 5E14 / cm3.

[0012] The semiconductor device provided in this embodiment controls the thickness of the active layer used to form the main tube to to And / or controlling the doping concentration of the optimized area to above 5E14 / cm3 can specifically optimize the key parameters corresponding to the semiconductor device serving as the main tube, avoiding affecting the key parameters corresponding to the semiconductor device serving as the pull-down tube, so that the RF switch device including semiconductor devices of various configuration types can take into account the three parameters of FOM, RFBV and ESD capability, thereby improving the performance of the RF switch device.

[0013] Furthermore, the doping concentration of the optimized region ranges from 5E14 / cm3 to 2E15 / cm3.

[0014] This embodiment uses an ultra-shallow junction (lower injection energy than conventional) implantation process to increase the doping concentration of the optimized area, which can reduce the on-resistance, thereby improving the FOM of the main tube, and can also reduce the leakage current I in the off state. off , thereby improving the supervisor’s RFBV.

[0015] Further, the doping material of the optimized region is phosphorus or arsenic;

[0016] When the doping material in the optimized region is arsenic, the implantation energy ranges from 0.5keV to 4keV;

[0017] When the doping material of the optimized region is phosphorus, the implantation energy ranges from 1 keV to 10 keV.

[0018] Furthermore, the semiconductor device further comprises:

[0019] A pull-down transistor gate structure is formed on a side surface of at least one active region away from the buried oxide layer;

[0020] The source region under the pull-down transistor gate structure and the drain region under the main transistor gate structure are connected by metal; or, the drain region under the pull-down transistor gate structure and the source region under the main transistor gate structure are connected by metal;

[0021] The thickness of the active region under the pull-down gate structure is greater than the thickness of the active region under the main gate structure; or the doping concentration of the optimized region under the pull-down gate structure is less than the doping concentration of the optimized region under the main gate structure.

[0022] Furthermore, the doping concentration of the optimized area below the pull-down tube gate structure ranges from 1E13 / cm3 to 5E14 / cm3.

[0023] In this embodiment, increasing the injection energy of the optimized region (deep junction) and reducing the doping concentration of the optimized region can reduce the gate induced drain leakage current GIDL, thereby improving the RFBV of the pull-down tube. At the same time, the junction area of ​​the optimized region and the gate oxide layer can be increased, thereby increasing the ESD leakage area and improving the ESD capability of the pull-down tube.

[0024] Furthermore, the doping material of the optimized area below the pull-down tube gate structure is arsenic or phosphorus;

[0025] When the doping material of the optimized area below the pull-down tube gate structure is arsenic and the injection energy ranges from 20keV to 40keV, the doping concentration of the optimized area below the pull-down tube gate structure ranges from 1E14 / cm3 to 5E14 / cm3;

[0026] When the doping material of the optimized area under the pull-down tube gate structure is arsenic and the injection energy ranges from 15keV to 25keV, the doping concentration of the optimized area under the pull-down tube gate structure ranges from 5E13 / cm3 to 2E14 / cm3;

[0027] When the doping material of the optimized area below the pull-down tube gate structure is phosphorus and the injection energy ranges from 15keV to 30keV, the doping concentration of the optimized area below the pull-down tube gate structure ranges from 1E13 / cm3 to 1E14 / cm3.

[0028] In this embodiment, the doping concentration of the optimized area is controlled at 5E13 / cm 3 To 2E14 / cm 3 Between, the RFBV and ESD capabilities can be above the standard values.

[0029] Furthermore, the doping concentration of the body region ranges from 3E12 / cm3 to 5E12 / cm3.

[0030] In this embodiment, reducing the doping concentration of the body region can make the pull-down tube easier to open, so that it is easier to discharge when an ESD phenomenon occurs, thereby protecting the pull-down tube and preventing the pull-down tube from being burned.

[0031] In a second aspect, the present application provides a radio frequency switching device, which includes the semiconductor device provided by any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

[0034] Figure 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

[0035] Figure 3 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention;

[0036] Figure 4 is a schematic flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention;

[0037] Figures 5 to 18 is a structural schematic diagram of a method for preparing a semiconductor device according to an embodiment of the present invention;

[0038] Fig.19 is a circuit diagram of a radio frequency switch device according to an embodiment of the present invention;

[0039] Fig. 20 is a simulation diagram of a semiconductor device according to an embodiment of the present invention.

[0040] Figure numerals: 111, substrate layer; 112, buried oxide layer; 113, active layer; 1131, active area; 1132, shallow trench isolation structure; 1133, body region; 1134, source and drain region; 1135, optimization region; 1136, channel; 1137, shallow trench; 114, trapping layer; 121, main gate structure; 122, gate oxide layer; 123, side wall isolation structure; 1231, first side wall isolation structure; 1232, second side wall isolation structure; 130, oxide layer; 140, photoresist layer; 141, window; 150, polysilicon; 160, photoresist mask layer. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0042] The semiconductor device provided by the present invention may be a SOI MOS tube, and the semiconductor device is used to form a radio frequency switch device.

[0043] In order to facilitate understanding, some concepts involved in the present invention are first explained.

[0044] (1) RF switching devices

[0045] RF switching devices are key components used in wireless communications, radar systems, satellite communications, test and measurement, and other RF (Radio Frequency) and microwave applications. The function of RF switching devices is to switch signals between different RF paths to achieve signal routing, selection or isolation to meet the RF system's signal processing requirements. The frequency range of RF switching devices can be from hundreds of megahertz to tens of gigahertz.

[0046] The radio frequency switch device may include multiple MOS tubes. The configuration types of the MOS tubes may include main tubes (series tubes) and pull-down tubes (shunt tubes). The configuration types are classified based on the connection method and working principle of the MOS tubes in the circuit.

[0047] A Series tube refers to a switch tube (MOS tube) connected in series in the signal path. When the Series tube is turned on, it allows the radio frequency signal to pass between the input and output ends, forming a low-impedance path; when the Series tube is turned off (cut off), it prevents the signal from passing, forming a high-impedance state, thereby interrupting the signal transmission.

[0048] Shunt tube refers to a switch tube (MOS tube) connected in parallel between the signal path and the ground (or reference point). When the Shunt tube is turned on, the signal path and the ground are short-circuited to form a low impedance state, thereby preventing the signal from passing; when the Shunt tube is turned off, it does not affect the signal path and allows the signal to be transmitted freely. Shunt tubes are often used to bypass or select signals. When a signal does not want to pass through a certain signal path, a Shunt tube can be used to short-circuit the signal to the ground.

[0049] The performance indicators for designing RF switching devices (evaluating the performance and reliability of RF switching devices) include parameters such as figure of merit (FOM), reverse bias voltage (RFBV) and electrostatic discharge (ESD) capability. When designing and selecting RF switching devices, these indicators need to be considered according to specific application requirements to ensure that the device can operate stably and reliably within the specified frequency range and power level.

[0050] (2) Figure of merit (FOM)

[0051] FOM is a comprehensive indicator to measure the performance of RF switching devices. FOM can be determined by the following formula (1):

[0052] FOM=R on ×C off (1)

[0053] Among them, R on Indicates the on-resistance, that is, the resistance when the MOS tube is turned on, C off Represents the parasitic capacitance when the MOS tube is turned off.

[0054] FOM can reflect the efficiency and isolation performance of RF switch devices. The smaller the FOM value, the better the efficiency and isolation performance. Specifically, the smaller the FOM value, the better the R on and C off Smaller, R on The smaller the value, the lower the insertion loss when conducting. off The smaller the value, the higher the isolation when turned off.

[0055] (3) Reverse bias voltage (RFBV)

[0056] RFBV refers to the maximum reverse voltage that the RF switch device can withstand in the off state. When the MOS tube is in the off mode, the two ends may be subjected to high voltage. RFBV reflects the voltage limit at which the RF switch device can work normally without damage. RFBV is crucial for selecting the appropriate MOS tube when designing RF switch devices to ensure that the MOS tube can work stably and reliably under various working conditions. The higher the RFBV, the higher the voltage resistance of the RF switch device, which can ensure the stability of the RF switch device in a high-voltage environment.

[0057] (4) Electrostatic discharge (ESD) capability

[0058] ESD capability refers to the tolerance of RF switch devices to electrostatic discharge. During production and use, RF switch devices may be subjected to electrostatic discharge, resulting in device performance degradation or even damage. ESD capability reflects the maximum electrostatic discharge energy that RF switch devices can withstand without permanent damage. Good ESD capability is a necessary condition to ensure that RF switch devices can work stably in complex environments, especially in high-static environments or frequently plugged-in interfaces. The higher the ESD capability, the higher the tolerance of the RF switch device to electrostatic discharge.

[0059] ESD performance can be evaluated by the current value of the Human Body Model (HBM) or the Transmission Line Pulse (TLP). Among them, the HBM test usually uses a 150pF capacitor and a 2000Ω resistor in series to simulate the conditions of human body electrostatic discharge to evaluate the anti-static ability of RF switching devices under human body contact discharge. TLP generates an adjustable pulse current with a very fast rise time to simulate the small gap discharge inside the integrated circuit or between the pins (the discharge may be caused by a machine, human body or other objects) to evaluate the anti-static ability of RF switching devices.

[0060] When optimizing the performance of RF switch devices by adjusting parameters (such as doping concentration), the three parameters of FOM, RFBV and ESD capability are inversely proportional and are traded off against each other. It is difficult to take all three parameters into account, which affects the performance of RF switch devices.

[0061] In view of this, the present invention provides a semiconductor device, which thins the active layer used to form the main tube, controls the thickness of the active layer to be below 750 angstroms, reduces the FOM value, and specifically optimizes the key parameters of the main tube, thereby improving the performance of the radio frequency switch device formed by the semiconductor device.

[0062] The semiconductor device provided by the present invention is described in detail below with reference to the accompanying drawings.

[0063] For example, Figure 1 As shown, the semiconductor device provided by the present invention includes a substrate layer 111 , a buried oxide layer 112 , an active layer 113 and a main gate structure 121 .

[0064] The buried oxide layer 112 is disposed on one side surface of the substrate layer 111, for example, Figure 1 As shown, the buried oxide layer 112 is disposed on the upper surface of the substrate layer 111. The active layer 113 is disposed on the side surface of the buried oxide layer 112 away from the substrate layer 111, for example, Figure 1As shown, the active layer 113 is disposed on the upper surface of the buried oxide layer 112. Figure 1 In the perspective (side perspective), the substrate layer 111, the buried oxide layer 112 and the active layer 113 are stacked from bottom to top.

[0065] Specifically, the substrate layer (Handle wafer) 111 can be a conventional semiconductor substrate such as silicon (Si) or germanium (Ge), and can have a certain type of doping, the material of the buried oxide layer (Buried Oxide, BOX) 112 can be silicon dioxide (SiO2), and the active layer 113 can be formed based on single crystal silicon.

[0066] In one example, a substrate layer 111, a buried oxide layer 112, and an active layer 113 can be formed based on an SOI substrate. The SOI substrate can be composed of a three-layer structure, with a top layer of single crystal silicon, an insulating layer (usually silicon dioxide SiO2) in the middle, and a silicon substrate at the bottom. Single crystal silicon can be called top silicon (Top Silicon, Tsi), which is used to form the active area of ​​the switching device. The SOI substrate can significantly reduce parasitic capacitance, increase the switching speed of the device, and reduce leakage current, thereby reducing energy consumption.

[0067] The active layer 113 includes an active region 1131 and a shallow trench isolation (STI) structure 1132 surrounding the active region 1131. Specifically, the active layer 113 can form at least one active region 1131, each active region 1131 can form a semiconductor device, and the shallow trench isolation structure 1132 is used to separate multiple active regions 1131. For example, Figure 1 As shown, the region between the two shallow trench isolation structures 1132 forms an active region 1131 .

[0068] Exemplarily, the shallow trench isolation structure 1132 includes a shallow trench formed on the active layer 113 and an insulating material (such as silicon dioxide, etc.) filled in the shallow trench. The shallow trench isolation structure 1132 is used to isolate adjacent MOS tubes or other active areas to avoid current or signal crosstalk and ensure the independence of each transistor unit.

[0069] The main gate structure 121 is formed on a surface of at least one active region away from the buried oxide layer 112, wherein a gate oxide layer 122 is disposed between the main gate structure 121 and the corresponding active region. Figure 1 As shown, the gate oxide layer 122 is located on the upper surface of the active region 1131 , and the main gate structure 121 is located on the upper surface of the gate oxide layer 122 .

[0070] Specifically, the gate oxide layer (Gate Oxide) 122 is an insulating layer, which can be composed of silicon dioxide, and is used to prevent current from flowing directly from the main gate structure 121 into the active layer 113. It also serves as a dielectric, so that the gate voltage can control the charge distribution in the semiconductor. The main gate structure 121 can be composed of materials such as polysilicon (Poly Silicon), metal or metal silicide. The main gate structure 121 controls the MOS tube to turn on or off (cut off) by applying voltage. When the gate voltage is higher than the threshold voltage, a conductive channel is formed in the active layer 113, allowing current to flow from the source region to the drain region; when the gate voltage is lower than the threshold voltage, the channel is closed, preventing current from flowing.

[0071] Specifically, the key parameter of the semiconductor device formed by the main gate structure 121 is FOM. At this time, the thickness of the active layer 113 can be set at to That is, the thickness of the active layer 113 is less than or equal to The thickness of the active layer 113 is greater than or equal to To optimize the key parameters FOM of semiconductor devices in a targeted manner.

[0072] In one example, the thickness of the active layer 113 may be or wait.

[0073] In the related art, the thickness of the active layer 113 is generally In this embodiment, by reducing the thickness of the active layer 113, the junction capacitance between the source and drain regions and the body region can be reduced, thereby reducing the parasitic capacitance C of the MOS tube. off , effectively reducing the FOM of the MOS tube.

[0074] Specifically, this embodiment is determined through experiments that the thickness of the active layer 113 is In contrast, the thickness of the active layer 113 is set to When the junction capacitance between the source-drain region and the body region is reduced by about 35%, C off The thickness of the active layer 113 is set to When the junction capacitance between the source-drain region and the body region decreases by about 20%, C off The thickness of the active layer 113 is set to When the junction capacitance between the source-drain region and the body region is reduced by about 14%, C off It has decreased by about 3%.

[0075] See also Fig. 20, under different thicknesses of the active layer 113 (Topsilicon), under the same RFBV scenario, the corresponding FOM values ​​of the supervisor are different. More specifically, referring to Table 1 below, it can be seen that the thickness of the active layer 113 (Topsilicon) is When compared with the active layer 113 (Topsilicon) with a thickness of Its FOM value is significantly reduced and RFBV is significantly improved.

[0076] Table 1 FOM and RFBV at different active layer thickness and length (Length)

[0077]

[0078] The semiconductor device provided in this embodiment controls the thickness of the active layer used to form the main tube to to It can optimize the key parameters of the main tube in a targeted manner to avoid affecting the key parameters of the pull-down tube, so that the RF switch device formed by the semiconductor device can take into account the three parameters of FOM, RFBV and ESD capability, thereby improving the performance of the RF switch device.

[0079] Furthermore, if Figure 2 As shown, the active region includes a body region 1133, two source and drain regions 1134 and two optimized regions 1135. The body region 1133 may be located in the middle region, the source and drain regions 1134 are located between the body region 1133 and the shallow trench isolation structure 1132, the optimized region 1135 is located between the body region 1133 and the upper surface of the source and drain regions 1134, and the optimized region 1135 is also in contact with the source and drain regions 1134. It can also be said that the two optimized regions 1135 are located at the two ends of the side of the body region 1133 away from the buried oxide layer 112, the two source and drain regions 1134 are respectively located at the two ends of the body region 1133, and the two source and drain regions 1134 are respectively located at the two ends of the two optimized regions 1135.

[0080] For example, Figure 2 As shown, one optimization region 1135 is located at the left end of the body region 1133 and close to the upper surface of the body region 1133, and the other optimization region 1135 is located at the right end of the body region 1133 and close to the upper surface of the body region 1133, that is, one optimization region 1135 is located at the upper left end of the body region 1133, and the other optimization region 1135 is located at the upper right end of the body region 1133, and the body region 1133 located between the two optimization regions 1135 forms a channel 1136; a source and drain region 1134 is located at the left end of the body region 1133 and one optimization region 1135, and the other source and drain region 1134 is located at the right end of the body region 1133 and the other optimization region 1135.

[0081] The doping concentration of the source and drain regions 1134 is greater than the doping concentration of the optimized region 1135 to ensure good ohmic contact between the source and drain regions 1134 and the channel 1136, reduce the source-drain resistance, and improve the driving capability and switching speed of the transistor.

[0082] The source and drain regions 1134 refer to the source region or drain region of the MOS transistor. One of the two source and drain regions 1134 refers to the source region, and the other refers to the drain region. The source region and the drain region are usually heavily doped N-type or P-type semiconductor regions, which are used to provide or receive carriers (electrons or holes), thereby forming a current path when the transistor is working. Among them, the conductivity type (N-type or P-type) of the source region and the drain region depends on the type of the MOS transistor (N-type MOS transistor or P-type MOS transistor).

[0083] The optimized region 1135 refers to a lightly doped N-type or P-type semiconductor region near the gate in the body region 1133, which is used to alleviate the electric field concentration in the high electric field region (the channel region near the source and drain regions), thereby reducing the generation of hot carriers, reducing the damage caused by the hot carrier effect, and improving the reliability and service life of the transistor, as well as improving the short channel effect, preventing a sharp drop in the threshold voltage (Vth), and maintaining the performance and stability of the transistor.

[0084] The gate oxide layer 122 covers a portion of the optimized area 1135, for example, Figure 2 As shown, the length of the gate oxide layer 122 in the horizontal direction is greater than the horizontal distance between the two ends of the two optimized areas 1135 that are close to each other, and the length of the gate oxide layer 122 in the horizontal direction is less than the horizontal distance between the two ends of the two optimized areas 1135 that are far away from each other, so that the gate oxide layer 122 covers part of the optimized area 1135.

[0085] Exemplarily, the number of active areas can be one or more. When the number of active areas is more than one, a portion of the active areas can be used to form the main pipe gate structure 121, and a portion of the active areas can be used to form the pull-down pipe gate structure, that is, the active layer is not only used to form the main pipe, but also to form the pull-down pipe.

[0086] In one example, the semiconductor device provided by the present invention further includes a pull-down transistor gate structure, which is formed on a surface of at least one active region away from the buried oxide layer 112. The pull-down transistor gate structure is not shown in the figure, and the pull-down transistor gate structure is similar to the main transistor gate structure, and a gate oxide layer is also provided between the pull-down transistor gate structure and the corresponding active region.

[0087] The source region under the pull-down tube gate structure and the drain region under the main tube gate structure are connected by metal, or the drain region under the pull-down tube gate structure and the source region under the main tube gate structure are connected by metal. The doping concentration of the optimized region 1135 in the active region forming the main tube and the doping concentration of the optimized region 1135 in the active region forming the pull-down tube may be the same or different. By adjusting the doping concentration of the optimized region 1135, the key parameters of the main tube and the pull-down tube can be optimized in a targeted manner.

[0088] In one example, the thickness of the active region under the pull-down tube gate structure is greater than the thickness of the active region under the main tube gate structure, or the doping concentration of the optimized region under the pull-down tube gate structure is less than the doping concentration of the optimized region under the main tube gate structure. Specifically, when the active layer is used to form the main tube, the key parameter is FOM. At this time, the doping concentration of the optimized region 1135 is set to the first preset interval, and the FOM is optimized in a targeted manner; when the active layer forms a pull-down tube, the key parameters are RFBV and ESD capability. At this time, the doping concentration of the optimized region 1135 is set to the second preset interval, and the RFBV and ESD capability are optimized in a targeted manner.

[0089] The main tube and the pull-down tube adopt differentiated process solutions and optimize their respective key parameters, so that the RF switch device formed based on the semiconductor device can take into account the three parameters of FOM, RFBV and ESD capability, thereby improving the performance of the RF switch device. Among them, the first preset interval and the second preset interval can be determined by the staff based on experiments.

[0090] The doping concentration of the optimized region of the present invention is described below.

[0091] For example, Figure 2 As shown in the figure, no matter whether the active area forms a main tube or a pull-down tube, the doping concentration of the optimized area can be in the range of 5E14 / cm 3 To 2E15 / cm 3 ,However, the doping concentration of the main tube optimization region is greater than the doping concentration of the pull-down tube optimization region.

[0092] That is, the doping concentration in the optimized area can be 5E14 / cm 3 To 2E15 / cm 3 For example, the doping concentration in the optimized region can be 5E14 / cm 3 、6E14 / cm 3 、7E14 / cm 3 、9E14 / cm 3 , 1E15 / cm 3 or 2E15 / cm 3 .

[0093] The doping material of the optimized area may be arsenic (As), and the value range of the injection energy may be 0.5 kiloelectron volts (keV) to 4keV. The value range of the injection energy of 0.5keV to 4keV may be understood as the injection energy may be any value between 0.5keV and 4keV, for example, the injection energy may be 0.5keV, 1keV, 1.5keV, 2.2keV, 3.6keV or 4keV, etc. The injection energy affects the length (height) of the optimized area in the vertical direction. The greater the injection energy, the greater the length of the optimized area in the vertical direction. The value range of the injection energy in this embodiment is smaller than the value range of the conventional injection energy.

[0094] Compared with the doping of the optimized area in the related art, this embodiment uses an ultra-shallow junction (lower injection energy than conventional) implantation process to increase the doping concentration of the optimized area, which can reduce the on-resistance and thus reduce the FOM of the main tube. In addition, using an ultra-shallow junction (lower injection energy) implantation process to increase the doping concentration of the optimized area can also reduce the leakage current I in the off state. off , thereby improving the supervisor’s RFBV.

[0095] It should be understood that the leakage current I in the off state off and gate induced drain leakage current (GIDL) are the two main factors affecting RFBV. off The smaller the GIDL current is, the better the RFBV is.

[0096] Specifically, this embodiment has determined through experiments that, compared with conventional implantation energy (e.g., 10 keV), adjusting the implantation energy to 1 keV can make R on 5% lower than the conventional doping concentration (e.g. 1E14 / cm 3 ) compared to the doping concentration of 1E15 / cm 3 , which can make R on Reduce by 5%, adjust the implantation energy to 1keV and the doping concentration to 1E15 / cm 3 When compared with the conventional method, R on Reduced by 10%.

[0097] Exemplarily, this embodiment does not specifically limit the doping material of the optimized region, as long as the optimized region can form a semiconductor region of a specific conductivity type (N-type or P-type). For example, the doping material of the optimized region can also be phosphorus (P), in which case the injection energy can range from 1keV to 10keV, for example, the injection energy of the optimized region can be 1keV, 2keV, 2.4keV, 5keV, 5.5keV, 6keV, 8keV or 10keV, etc. This embodiment takes the conductivity type of the optimized region as N-type as an example, but is not limited thereto.

[0098] It should be noted that, in the case where the active region forms a main tube, the thickness of the active layer 113 can be set to to At the same time, the doping concentration of the optimized area corresponding to the main gate structure 121 is set to 5E14 / cm 3 To 2E15 / cm 3 That is, the FOM of the main tube can be optimized by reducing the thickness of the active layer 113 or increasing the doping concentration of the optimized area by using an ultra-shallow junction implantation process, or both methods can be used simultaneously to optimize the FOM of the main tube.

[0099] For example, when the active layer is also used to form a pull-down tube, the doping concentration of the optimized region corresponding to the pull-down tube gate structure may be in the range of 1E14 / cm 3 To 5E14 / cm 3 , that is, the doping concentration of the optimized area corresponding to the pull-down tube gate structure can be 1E14 / cm 3 To 5E14 / cm 3 For example, the doping concentration of the optimized region corresponding to the pull-down transistor gate structure can be 1E14 / cm 3 , 2E14 / cm 3 、3E14 / cm 3 or 5E14 / cm 3 At this time, the doping material of the optimized region corresponding to the pull-down tube gate structure may be arsenic, and the value range of the injection energy may be 20 keV to 40 keV.

[0100] Among them, the injection energy value range of 20keV to 40keV can be understood as the injection energy can be any value between 20keV and 40keV, for example, the injection energy can be 20keV, 25keV, 30keV, 32keV, 36keV or 40keV, etc.

[0101] In this embodiment, compared with conventional methods, the injection energy of the optimized region is increased (deep junction) and the doping concentration of the optimized region is reduced, which can reduce the gate induced drain leakage current GIDL, thereby improving the RFBV of the pull-down tube. At the same time, the junction area of ​​the optimized region and the gate oxide layer can be increased, thereby increasing the ESD leakage area and improving the ESD capability of the pull-down tube.

[0102] Specifically, this embodiment is determined by experiments to be different from conventional (implantation energy 10keV, doping concentration 1E14 / cm 3 ), by increasing the injection energy of the optimized area and reducing the doping concentration, the gate induced drain leakage current GIDL can be reduced by about 50% to 60%.

[0103] For example, the doping concentration of the optimized region corresponding to the pull-down transistor gate structure may also be in the range of 1E13 / cm 3 To 1E14 / cm 3 That is, the doping concentration of the optimized area corresponding to the pull-down tube can be 1E13 / cm 3 To 1E14 / cm 3 For example, the doping concentration in the optimized region can be 1E13 / cm 3 、3E13 / cm 3 、5E13 / cm 3 、8E13 / cm 3 or 1E14 / cm 3 At this time, the doping material of the optimized area corresponding to the pull-down tube may be phosphorus, and the value range of the injection energy may be 15 keV to 30 keV.

[0104] Among them, the value range of the injection energy is 15keV to 30keV, which can be understood as the injection energy can be any value between 15keV and 30keV, for example, the injection energy can be 15keV, 20keV, 24keV, 28keV or 30keV, etc.

[0105] In this embodiment, compared with conventional methods, the injection energy of the optimized region is increased (deep junction) and the doping concentration of the optimized region is reduced, which can reduce the gate induced drain leakage current GIDL, thereby improving the RFBV of the pull-down tube. At the same time, the junction area of ​​the optimized region and the gate oxide layer can be increased, thereby increasing the ESD leakage area and improving the ESD capability of the pull-down tube.

[0106] Specifically, this embodiment is determined by experiments to be different from conventional (implantation energy 10keV, doping concentration 1E14 / cm 3 ), by increasing the injection energy of the optimized area and reducing the doping concentration, the gate induced drain leakage current GIDL can be reduced by about 50% to 60%.

[0107] For example, in order to better balance the RFBV and ESD capabilities of the pull-down tube, the doping concentration of the optimized region corresponding to the pull-down tube gate structure may be in the range of 5E13 / cm 3 To 2E14 / cm 3 For example, the doping concentration of the optimized area corresponding to the pull-down transistor gate structure can be 5E13 / cm 3 、8E13 / cm 3 、9E13 / cm 3 , 1E14 / cm 3 or 2E14 / cm 3 At this time, the doping material of the optimized area corresponding to the pull-down tube may be arsenic, and the value range of the injection energy may be 15 keV to 25 keV.

[0108] Among them, the value range of the injection energy is 15keV to 25keV, which can be understood as the injection energy can be any value between 15keV and 25keV, for example, the injection energy can be 15keV, 16keV, 18keV, 20keV or 25keV, etc.

[0109] Specifically, this embodiment is determined by experiments to be different from conventional (implantation energy 10keV, doping concentration 1E14 / cm 3 ), the implantation energy of the optimized area is controlled between 15keV and 25keV, and the doping concentration of the optimized area is controlled at 5E13 / cm 3 To 2E14 / cm 3 The TLP can stably exceed the 2000V standard (typical data 5000V~6000V), and the RFBV obtained by the typical test structure can reach above 4.5V, making the RFBV and ESD capabilities above the standard values.

[0110] When the active layer is also used to form a pull-down tube, in order to improve the ESD capability of the semiconductor device, in some examples, the doping concentration of the body region corresponding to the pull-down tube gate structure can be in the range of 3E12 / cm 3 To 5E12 / cm 3 That is, the doping concentration of the body region can be 3E12 / cm 3 To 5E12 / cm 3 For example, the doping concentration of the body region can be 3E12 / cm 3 、4E12 / cm 3 、4.5E12 / cm 3 or 5E12 / cm 3 Etc. Meanwhile, the doping material of the body region corresponding to the pull-down tube gate structure may be boron (B) or boron dioxide (BF2).

[0111] In this embodiment, compared with the conventional doping concentration of the body region, the doping concentration of the body region is reduced, which can make the pull-down tube easier to open, so that it is easier to discharge when an ESD phenomenon occurs, thereby protecting the pull-down tube and preventing the pull-down tube from being burned.

[0112] For example, when the active layer is also used to form a pull-down tube, limiting the thickness of the active layer 113 to less than 750 angstroms can also reduce the leakage current I in the off state. off , improve the breakdown voltage of short channel devices and enhance the RFBV of semiconductor devices.

[0113] Specifically, the doping concentration of the optimized area below the pull-down transistor gate structure can be in the range of 1E13 / cm 3 To 5E14 / cm 3 .

[0114] Furthermore, if Figure 1 and Figure 2 As shown, in some optional embodiments, the semiconductor device further includes spacer isolation structures 123 located at both ends of the main gate structure 121 and at both ends of the gate oxide layer 122, and the sum of the thicknesses of the two spacer isolation structures 123 ranges from 100nm to 280nm. That is, the sum of the thicknesses of the two spacer isolation structures 123 can be any value between 100nm and 280nm, for example, the sum of the thicknesses of the two spacer isolation structures 123 can be 100nm, 150nm, 180nm, 200nm or 280nm, etc.

[0115] In this embodiment, the sum of the thicknesses of the two sidewall isolation structures is controlled to be between 100 nm and 280 nm, which can reduce leakage current and further improve the RFBV of the semiconductor device.

[0116] Exemplarily, the spacer spacer 123 may include a polysilicon oxide layer and a silicon oxide layer, or the spacer spacer 123 may include a polysilicon oxide layer and a silicon nitride (SiN) layer.

[0117] In an example, the spacer isolation structure 123 may be composed of two first spacer isolation structures 1231 and two second spacer isolation structures 1232 . In this case, the sum of the thicknesses of the two first spacer isolation structures 1231 ranges from 100 nm to 280 nm.

[0118] In some optional embodiments, such as Figure 3 As shown, the semiconductor device further includes a trapping layer 114, which is disposed between the substrate layer 111 and the buried oxide layer 112. Figure 3In the perspective (side perspective), the substrate layer 111, the trapping layer 114, the buried oxide layer 112 and the active layer 113 are stacked from bottom to top.

[0119] Specifically, the trapping layer 114 is composed of a material having trap energy levels, such as silicon nitride, etc. The trap energy levels can capture electrons or holes. When the semiconductor device is a MOS tube, the trap energy levels in the trapping layer 114 can capture charge carriers from the substrate, thereby reducing charge accumulation in the gate oxide layer and improving the reliability of the semiconductor device.

[0120] This embodiment also provides a method for preparing a semiconductor device. Figure 4 is a schematic flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention, such as Figure 4 As shown, the method comprises the following steps:

[0121] Step S401, providing a semiconductor substrate.

[0122] Exemplarily, the semiconductor substrate may be an SOI substrate.

[0123] In some embodiments, Figure 5 As shown, the semiconductor substrate includes a substrate layer 111, a buried oxide layer 112 and an active layer 113 stacked from bottom to top.

[0124] In some other optional embodiments, Figure 6 As shown, the semiconductor substrate includes a substrate layer 111, a trapping layer 114, a buried oxide layer 112 and an active layer 113 stacked from bottom to top.

[0125] Step S402, when the thickness of the active layer is greater than or equal to In the case of , the active layer is oxidized to form an oxide layer on the active layer to consume silicon in the active layer.

[0126] Exemplarily, after obtaining the semiconductor substrate, if the thickness of the active layer 113 is greater than or equal to The active layer is oxidized by chemical deposition process or furnace tube to form a Figure 7 An oxide layer 130 is shown.

[0127] Specifically, during the oxidation process, the silicon in the active layer reacts with the oxidant to generate an oxide layer 130, which consumes the silicon in the active layer, causing the thickness of the active layer to gradually decrease, wherein the thickness of the oxide layer and the thickness of the consumed silicon are approximately 1:0.55.

[0128] Step S403, removing the oxide layer to make the thickness of the active layer to

[0129] Specifically, after the oxide layer is formed, the oxide layer may be removed by chemical etching or physical etching, etc. For example, chemical reagents such as hydrofluoric acid (HF) may be used to etch silicon oxide to remove the oxide layer.

[0130] In some optional embodiments, the method for preparing a semiconductor device further comprises: when the thickness of the active layer is less than In the case of silicon, silicon is grown on the surface of the active layer away from the buried oxide layer, so that the thickness of the active layer after growth is in the range of to

[0131] Specifically, silicon can be grown on the surface of the active layer away from the buried oxide layer by chemical vapor deposition or epitaxy.

[0132] That is, after obtaining the semiconductor substrate, if the thickness of the active layer is greater than the target thickness (eg ), then execute step S402 and step S403 to make the thickness of the active layer reach the target thickness; if the thickness of the active layer is less than the target thickness, then grow silicon on the surface of the active layer away from the buried oxide layer so that the thickness of the active layer after growth reaches the target thickness.

[0133] Step S404, etching the active layer to form a plurality of shallow trenches on the active layer.

[0134] Specifically, after the active layer reaches the target thickness, a photoresist (PR) may be coated on the active layer to form a photoresist layer, and then the photoresist layer is exposed and developed. Figure 8 A plurality of windows 141 are formed on the photoresist layer 140 , wherein the positions of the plurality of windows 141 are defined as the positions of the shallow trench isolation structures 1132 .

[0135] Afterwards, the patterned photoresist layer is used as a mask to etch from the active layer to the buried oxide layer to form a Fig. 9 The shallow groove 1137 shown. Etching can be performed by conventional etching processes in the art, such as dry etching, and the etching gas can be one or a mixture of chlorine (Cl2), trifluoromethane (CHF3) or nitrogen (N2). The shallow groove 1137 formed by etching can be a groove that is wide at the top and narrow at the bottom, which helps to more evenly distribute the stress caused by thermal cycles and mechanical stress in the manufacturing process, reduce cracks and fractures caused by stress concentration, and improve the reliability of the device.

[0136] Step S405 , filling the plurality of shallow trenches with insulating material to form a plurality of shallow trench isolation structures, and forming active regions between the shallow trench isolation structures.

[0137] Specifically, after forming the shallow trench 1137, an insulating material such as silicon oxide may be filled in the shallow trench 1137 by chemical vapor deposition or thermal oxidation growth to form a Fig.10 A plurality of shallow trench isolation structures 1132 are shown, and the area surrounded by the shallow trench isolation structures 1132 is the active area 1131 .

[0138] Step S406, growing silicon dioxide on the surface of the active layer away from the buried oxide layer to form a gate oxide layer.

[0139] Exemplarily, a gate oxide layer may be formed on a surface of the active layer away from the buried oxide layer by chemical vapor deposition or physical vapor deposition.

[0140] Step S407, growing polysilicon on a surface of the gate oxide layer away from the active layer.

[0141] Specifically, a gate oxide layer may be deposited on a surface of the gate oxide layer away from the active layer. Fig.11 The polysilicon 150 is shown. The deposition method may be chemical vapor deposition, magnetron sputtering, physical vapor deposition or atomic layer deposition.

[0142] Step S408, etching the polysilicon to form a main gate structure to prepare a semiconductor device.

[0143] The semiconductor device is any one of the semiconductor devices provided in the above embodiments.

[0144] Specifically, after forming polysilicon, a photoresist is spin-coated on the polysilicon 150 to form a photoresist layer, and a non-gate region is exposed through exposure and development steps, such as Fig.12 As shown, the main gate structure 121 area is covered by photoresist; the exposed non-gate area is etched to form Fig.13 The main gate structure shown in FIG. 1 is a main gate structure shown in FIG. 1. At the same time, the uncovered gate oxide layer under the polysilicon 150 is also etched away. The above etching method can be a dry etching, a wet etching, or a combination of dry etching and wet etching. After the etching is completed, the photoresist layer is removed by an ashing process.

[0145] In other embodiments, the main gate structure may also be made of a metal gate, for example, a metal material with a small thermal expansion coefficient such as nickel, molybdenum or tungsten.

[0146] For example, the main gate structure can be as follows Fig.14 As shown in the T-shape, it can also be Fig.15 As shown in FIG. 1 , the semiconductor device is in an I-shape (or H-shape). When the main gate structure is in an I-shape, the layout of the semiconductor device can be as follows: Fig.16 shown.

[0147] In some optional embodiments, after forming the main gate structure, the method for preparing the semiconductor device further includes: forming a sidewall isolation structure at both ends of the main gate structure and the gate oxide layer, wherein the thickness of the two sidewall isolation structures is in the range of 100nm to 280nm.

[0148] Specifically, the steps of forming a sidewall isolation structure at both ends of the main gate structure and the gate oxide layer include: forming a silicon dioxide layer at both ends of the main gate structure and the gate oxide layer through a dry oxygen or wet oxygen oxidation process; growing silicon nitride (or silicon oxide) on the surface of the silicon dioxide layer away from the end face of the main gate structure through chemical vapor deposition; and etching the silicon nitride (or silicon oxide) to form a sidewall isolation structure.

[0149] Exemplarily, the active region includes a body region, two source and drain regions and two optimized regions, the two optimized regions are located at the two ends of a side of the body region away from the buried oxide layer, the two source and drain regions are respectively located at the two ends of the body region, and the two source and drain regions are respectively located at the two ends of the two optimized regions, the doping concentration of the source and drain regions is greater than the doping concentration of the optimized regions, and the doping concentration of the optimized regions is determined based on the configuration type of the semiconductor device.

[0150] Specifically, Fig.17 As shown, after forming the first sidewall isolation structure 1231, a photoresist is spin-coated on the active layer to form a photoresist layer, and the photoresist layer is exposed and developed to form a Fig.17 The patterned photoresist mask layer 160 shown in FIG. 1 is provided with an opening of the patterned photoresist mask layer 160 exposing the optimized area and the source / drain area. Under the protection of the patterned photoresist mask layer, ion implantation is performed at a preset position of the optimized area based on doping parameters to form the optimized area. After the optimized area is formed, a deposition process is performed to form a Fig.18 The second sidewall isolation structure 1232 is shown, and then, based on the doping parameters, ion implantation is performed on the preset positions of the source and drain regions to form the source and drain regions, and then the patterned photoresist mask layer 160 is removed to form the Figure 3 The semiconductor device shown.

[0151] The present invention also provides a radio frequency switch device, comprising the semiconductor device provided by any of the above embodiments.

[0152] Among them, multiple main tubes are connected in series, the source of the main tube at the head end is connected to the RF signal transmitting end, and the source of the main tube at the tail end is connected to the RF signal receiving end; the source of the pull-down tube is grounded, and the drain of the pull-down tube is connected to the RF signal transmitting end or the RF signal receiving end. The gates of multiple main tubes and the gates of the pull-down tubes are all connected to the RF signal control end to control the main tubes and the pull-down tubes to be turned on or off.

[0153] Exemplarily, the circuit diagram of the RF switch device can be as follows: Fig.19 As shown, Fig.19 Take the example that the radio frequency switch device includes four semiconductor devices, but it is not limited to this.

[0154] Specifically, Fig.19 As shown, the first semiconductor device M1 and the second semiconductor device M2 are main tubes, the third semiconductor device M3 and the fourth semiconductor device M4 are pull-down tubes, the source of the first semiconductor device M1 is connected to the RF signal transmitting end (TX), the drain of the first semiconductor device M1 is connected to the drain of the second semiconductor device M2, the source of the second semiconductor device M2 is connected to the RF signal receiving end (RX), and the drain of the first semiconductor device M1 and the drain of the second semiconductor device M2 are also connected to the antenna (ANT) to receive external signals. The gate of the first semiconductor device M1 is connected in series with a first resistor R G1 Then connected to the RF signal control terminal (not shown in the figure), the gate of the second semiconductor device M2 is connected in series with a second resistor R G2 Then connect it to the RF signal control terminal.

[0155] The drain of the third semiconductor device M3 is connected to the radio frequency signal transmitting end (TX), the source of the third semiconductor device M3 is grounded, and the gate of the third semiconductor device M3 is connected in series with a third resistor R G3 Then connected to the RF signal control terminal, the drain of the fourth semiconductor device M4 is connected to the RF signal receiving terminal (RX), the source of the fourth semiconductor device M4 is grounded, and the gate of the fourth semiconductor device M4 is connected in series with a fourth resistor R G4 Then connect it to the RF signal control terminal.

[0156] Exemplarily, the radio frequency switch device may be a single-pole multi-throw switch.

[0157] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0158] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0159] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0160] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0161] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0162] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the present invention.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate layer; A buried oxide layer is formed on one side surface of the substrate layer; An active layer is formed on a surface of the buried oxide layer away from the substrate layer, wherein a plurality of shallow trench isolation structures and active regions between adjacent shallow trench isolation structures are formed in the active layer; A main gate structure is formed on a surface of at least one of the active regions away from the buried oxide layer; Wherein, the thickness of the active region is to and / or, The active area includes a body area located in the middle area, a source and drain area located between the body area and the shallow trench isolation structure, and an optimized area located between the body area and the upper surface of the active area. The optimized area is also in contact with the source and drain area, and the doping concentration of the optimized area is higher than 5E14 / cm3.

2. The semiconductor device according to claim 1, wherein: The doping concentration of the optimized area ranges from 5E14 / cm 3 To 2E15 / cm 3 .

3. The semiconductor device according to claim 1, wherein: The doping material of the optimized area is phosphorus or arsenic; When the doping material of the optimized region is arsenic, the injection energy ranges from 0.5keV to 4keV; When the doping material of the optimized region is phosphorus, the injection energy ranges from 1 keV to 10 keV.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The semiconductor device further comprises: A pull-down transistor gate structure is formed on a surface of at least one side of the active region away from the buried oxide layer; The source region under the pull-down transistor gate structure and the drain region under the main gate structure are connected by metal; or, the drain region under the pull-down transistor gate structure and the source region under the main gate structure are connected by metal; The thickness of the active area below the pull-down tube gate structure is greater than the thickness of the active area below the main tube gate structure; or the doping concentration of the optimized area below the pull-down tube gate structure is less than the doping concentration of the optimized area below the main tube gate structure.

5. The semiconductor device according to claim 4, characterized in that The doping concentration of the optimized area below the pull-down tube gate structure is in the range of 1E13 / cm 3 To 5E14 / cm 3 .

6. The semiconductor device according to claim 5, characterized in that The doping concentration of the optimized area below the pull-down tube gate structure is in the range of 1E14 / cm 3 To 5E14 / cm 3 .

7. The semiconductor device according to claim 6, characterized in that The doping material of the optimized area below the pull-down tube gate structure is arsenic, and the value range of the injection energy is 20keV to 40keV.

8. The semiconductor device according to claim 5, characterized in that The doping concentration of the body region is in the range of 3E12 / cm 3 To 5E12 / cm 3 .

9. The semiconductor device according to claim 8, characterized in that The doping material of the body region is boron or boron dioxide.

10. A radio frequency switch device, characterized in that: The radio frequency switching device comprises the semiconductor device according to any one of claims 1 to 9.

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