Light emitting diode with improved reliability and preparation method thereof

Abstract

The invention provides a light emitting diode with improved reliability and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The light-emitting diode comprises an epitaxial layer, an insulating layer, a first electrode and a second electrode, the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are stacked in sequence, a groove exposing the first semiconductor layer is formed in the surface of the second semiconductor layer, the insulating layer is at least located on the surface of the second semiconductor layer, and the insulating layer comprises a first through hole exposing the second semiconductor layer and a plurality of second through holes; the first through holes and the second through holes are arranged at intervals, and the multiple second through holes surround the groove and are arranged at intervals; the first electrode is at least located in the groove and electrically connected with the first semiconductor layer, the second electrode is located on the side, away from the epitaxial layer, of the insulating layer, and the insulating layer is electrically connected with the second semiconductor layer through the first through hole and the second through hole. The embodiment of the invention can improve the reliability of the light-emitting diode.

Description

Technical Field

[0001] The present disclosure relates to the technical field of optoelectronic manufacturing, and in particular to a light emitting diode with improved reliability and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a very influential new product in the optoelectronics industry. It has the characteristics of small size, long service life, rich colors and low energy consumption. It is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.

[0003] In the related art, a light-emitting diode includes an epitaxial layer, an insulating layer, a first electrode, and a second electrode. The epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence. The surface of the second semiconductor layer has a groove exposing the first semiconductor layer. The insulating layer is at least located on the surface of the second semiconductor layer. The first electrode is located in the groove and is electrically connected to the first semiconductor layer. The second electrode is located on the surface of the insulating layer and is electrically connected to the second semiconductor layer through a through hole penetrating the insulating layer.

[0004] In order to test the electrical over stress (EOS) performance of the light-emitting diode, a negative pulse voltage or pulse current is usually applied to the light-emitting diode instantaneously. During the test, the current density near the first electrode is the largest, so the current injected from the first electrode will preferentially flow into the through hole on the insulating layer closest to the first electrode through the epitaxial layer, resulting in an excessive instantaneous current at the through hole on the insulating layer closest to the first electrode, thereby burning out the light-emitting diode. Summary of the invention

[0005] The disclosed embodiment provides a light emitting diode with improved reliability and a method for manufacturing the same, which can improve the problem of burning out the light emitting diode due to excessive instantaneous current when testing electrical overstress performance, thereby improving the reliability of the light emitting diode. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes: an epitaxial layer, an insulating layer, a first electrode, and a second electrode; the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, the surface of the second semiconductor layer has a groove exposing the first semiconductor layer, the insulating layer is at least located on the surface of the second semiconductor layer, the insulating layer includes a first through hole and a plurality of second through holes exposing the second semiconductor layer, the first through hole and the second through holes are arranged at intervals, and the plurality of second through holes surround the groove and are arranged at intervals; the first electrode is at least located in the groove and is electrically connected to the first semiconductor layer, the second electrode is located on a side of the insulating layer away from the epitaxial layer, and the insulating layer is electrically connected to the second semiconductor layer through the first through hole and the second through hole.

[0007] In an implementation of the present disclosure, the sum of radial cross-sectional areas of the plurality of second through holes is greater than or equal to an area where the first electrode contacts the first semiconductor layer.

[0008] In another implementation of the present disclosure, a width of a radial cross section of the second through hole is greater than a width of a radial cross section of the first through hole.

[0009] In another implementation of the present disclosure, the maximum distance from the area where the first electrode contacts the first semiconductor layer to the second through hole is less than or equal to 15 μm.

[0010] In another implementation of the present disclosure, the plurality of second through holes include at least one surrounding through hole group, each of the surrounding through hole groups includes a plurality of second through holes uniformly distributed circumferentially with the geometric center of the groove as the midpoint, and different surrounding through hole groups are concentrically distributed.

[0011] In another implementation of the present disclosure, the radial cross-section of the second through hole is circular, elliptical or polygonal.

[0012] In another implementation of the present disclosure, a width of a radial cross section of the second through hole is 4 μm to 10 μm.

[0013] In another implementation of the present disclosure, the insulating layer includes an insulating buffer layer and an insulating reflective layer sequentially stacked on the second semiconductor layer, and the first through hole and the second through hole both penetrate the insulating reflective layer and the insulating buffer layer.

[0014] In another implementation of the present disclosure, the light-emitting diode further includes: a transparent conductive layer, a metal reflective layer, an insulating protective layer and a first passivation layer, the transparent conductive layer is located on the second semiconductor layer, and the insulating layer covers the transparent conductive layer, and the first through hole and the second through hole both expose the transparent conductive layer; the metal reflective layer is located on a surface of the insulating reflective layer away from the epitaxial layer, and is connected to the transparent conductive layer through the first through hole and the second through hole; the insulating protective layer and the first passivation layer are sequentially stacked on a surface of the insulating reflective layer away from the epitaxial layer, the insulating protective layer covers the metal reflective layer, the first passivation layer has a via hole that exposes the metal reflective layer and the bottom of the groove respectively, the first electrode and the second electrode are both located on a surface of the first passivation layer away from the epitaxial layer, the first electrode is connected to the first semiconductor layer through the via hole, and the second electrode is connected to the metal reflective layer through the via hole.

[0015] On the other hand, an embodiment of the present disclosure provides a method for preparing a light-emitting diode, the method comprising: forming an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, the surface of the second semiconductor layer having a groove exposing the first semiconductor layer; forming an insulating layer at least on the surface of the second semiconductor layer, the insulating layer comprising a first through hole and a plurality of second through holes exposing the second semiconductor layer, the first through hole and the second through holes being arranged at intervals, and the plurality of second through holes being arranged at intervals around the groove; making a first electrode and a second electrode, the first electrode being located in the groove and electrically connected to the first semiconductor layer, the second electrode being located on a side of the insulating layer away from the epitaxial layer, and the insulating layer being electrically connected to the second semiconductor layer through the first through hole and the second through hole.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode provided in the embodiment of the present disclosure is provided with a first through hole and a second through hole arranged at intervals on the insulating layer, wherein the second through holes are arranged at intervals around the groove of the epitaxial layer. The first electrode is electrically connected to the first semiconductor layer in the groove, and the second electrode is above the insulating layer and electrically connected to the second semiconductor layer through the first through hole and the second through hole.

[0018] When a negative pulse voltage is applied to the light-emitting diode, the current injected from the first electrode will be evenly distributed to each second through hole surrounding the groove, so that the larger instantaneous current can be split into different second through holes, allowing each second through hole to flow into a relatively small current. Therefore, the problem of the current concentration effect causing the explosion point in the related art, where the current injected from the first electrode directly flows into a single through hole near the first electrode, is avoided, thereby improving the problem of excessive instantaneous current at the through hole near the first electrode burning the light-emitting diode, and improving the EOS performance of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 is a top view of a light emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 2 yes Figure 1 An AA cross-sectional view is provided;

[0022] Figure 3 is a partial schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0023] Figure 4 is a partial schematic diagram of another light emitting diode provided by an embodiment of the present disclosure;

[0024] Figure 5 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0025] Figure 6 It is a comparison chart of the EOS performance of a light-emitting diode provided by an embodiment of the present disclosure.

[0026] The descriptions of the marks in the figure are as follows:

[0027] 10. Substrate;

[0028] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer; 24. groove;

[0029] 30. Insulating layer; 31. Insulating buffer layer; 32. Insulating reflective layer;

[0030] 301, first through hole; 302, second through hole;

[0031] 40. Transparent conductive layer;

[0032] 51. Metal reflective layer; 52. Insulation protective layer;

[0033] 61. a first passivation layer; 62. a second passivation layer;

[0034] 71. a first electrode; 72. a second electrode;

[0035] 80. Soldering pad. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0037] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] Figure 1 It is a top view of a light emitting diode provided by an embodiment of the present disclosure. Figure 2 yes Figure 1 An AA cross-section diagram is provided. Figure 1 , 2 As shown, the light emitting diode includes: an epitaxial layer 20 , an insulating layer 30 , a first electrode 71 and a second electrode 72 .

[0039] like Figure 2As shown, the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence, the surface of the second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21, the insulating layer 30 is at least located on the surface of the second semiconductor layer 23, the insulating layer 30 includes a first through hole 301 exposing the second semiconductor layer 23 and a plurality of second through holes 302, the first through hole 301 and the second through holes 302 are arranged at intervals, and the plurality of second through holes 302 surround the groove 24 and are arranged at intervals.

[0040] like Figure 2 As shown, the first electrode 71 is at least located in the groove 24 and is electrically connected to the first semiconductor layer 21 , the second electrode 72 is located on the side of the insulating layer 30 away from the epitaxial layer 20 , and the insulating layer 30 is electrically connected to the second semiconductor layer 23 through the first through hole 301 and the second through hole 302 .

[0041] The light emitting diode provided in the embodiment of the present disclosure is provided with first through holes 301 and second through holes 302 arranged at intervals on the insulating layer 30, wherein the second through holes 302 are arranged at intervals around the groove 24 of the epitaxial layer 20. The first electrode 71 is electrically connected to the first semiconductor layer 21 in the groove 24, and the second electrode 72 is above the insulating layer 30 and electrically connected to the second semiconductor layer 23 through the first through holes 301 and the second through holes 302.

[0042] When a negative pulse voltage is applied to the light-emitting diode, the current injected from the first electrode 71 will be evenly distributed to each second through hole 302 surrounding the groove 24, so that a larger instantaneous current can be split into different second through holes 302, allowing each second through hole 302 to flow with a relatively small current. Therefore, the problem of the current injected by the first electrode 71 directly flowing into a single through hole near the first electrode 71 in the related art, which causes the current concentration effect to cause a flash point, is avoided, thereby improving the problem of excessive instantaneous current at the through hole near the first electrode 71 and burning the light-emitting diode, and improving the EOS performance of the light-emitting diode.

[0043] Optionally, the sum of radial cross-sectional areas of the plurality of second through holes 302 is greater than or equal to an area where the first electrode 71 contacts the first semiconductor layer 21 .

[0044] The radial cross section of the second through hole 302 refers to a cross section in a direction perpendicular to the central axis of the second through hole 302 .

[0045] By limiting the sum of the radial cross-sectional areas of the second through holes 302 to be no less than the contact area between the first electrode 71 and the first semiconductor layer 21, when a negative pulse voltage is applied to the light-emitting diode, the current injected from the first electrode 71 will be evenly distributed to each of the second through holes 302 surrounding the groove 24, and the problem that the second through holes 302 cannot receive a large instantaneous current is not likely to occur. In other words, providing enough second through holes 302 can slowly release a large instantaneous current into multiple small currents, thereby avoiding the problem that the instantaneous current at the second through holes 302 is too large and burns the light-emitting diode.

[0046] Alternatively, if Figure 2 As shown, the width of the radial cross section of the second through hole 302 is greater than the width of the radial cross section of the first through hole 301 .

[0047] The width of the radial cross section of the second through hole 302 may refer to the maximum width or the minimum width of the radial cross section of the second through hole 302 .

[0048] By making the radial cross section of the second through hole 302 larger, the current injected from the first electrode 71 can be more easily integrated into the second through hole 302, thereby achieving the purpose of dispersing the current.

[0049] For example, the width of the radial cross section of the second through hole 302 may be 1 μm to 8 μm greater than the width of the radial cross section of the first through hole 301 .

[0050] Optionally, the width of the radial cross section of the second through hole 302 is 4 μm to 10 μm. For example, the width of the radial cross section of the second through hole 302 is 8 μm, and accordingly, the width of the radial cross section of the first through hole 301 may be 3 μm.

[0051] Optionally. Figure 2 As shown, the maximum distance from the area where the first electrode 71 contacts the first semiconductor layer 21 to the second through hole 302 is less than or equal to 15 μm.

[0052] Exemplarily, the farthest distance from the area where the first electrode 71 contacts the first semiconductor layer 21 to the second through hole 302 is 8 μm to 15 μm.

[0053] By controlling the maximum distance from the area where the first electrode 71 contacts the first semiconductor layer 21 to the second through hole 302 within the above range, it is possible to avoid the distance from the second through hole 302 to the first electrode 71 being too far, which would fail to achieve the purpose of quickly sharing the large instantaneous current injected from the first electrode 71, thereby ensuring that the instantaneous current can be evenly and quickly distributed to each adjacent second through hole 302, thereby improving the EOS performance of the light-emitting diode.

[0054] Figure 3It is a partial schematic diagram of a light emitting diode provided in an embodiment of the present disclosure. Figure 4 It is a partial schematic diagram of another light emitting diode provided in an embodiment of the present disclosure. Figure 3 and Figure 4 The diagram shows the distribution of the second through holes 302 and the first through holes 301 near the groove 24 .

[0055] Optionally, the plurality of second through holes 302 include at least one surrounding through hole group, each surrounding through hole group includes a plurality of second through holes 302 uniformly distributed circumferentially with the geometric center of the groove 24 as the midpoint, and different surrounding through hole groups are concentrically distributed.

[0056] For example, Figure 3 As shown, the plurality of second through holes 302 include a surrounding through hole group, the surrounding through hole group includes a plurality of second through holes 302 circumferentially surrounding the groove 24, and the plurality of second through holes 302 are evenly distributed circumferentially.

[0057] The interval angle between two adjacent second through holes 302 does not exceed 90°, so as to ensure that there are enough second through holes 302 arranged inside the surrounding through hole group to share the instantaneous current injected by the first electrode 71 .

[0058] For example, Figure 4 As shown, the plurality of second through holes 302 include two surrounding through hole groups, the two surrounding through hole groups are concentrically distributed, and each surrounding through hole group includes a plurality of second through holes 302 circumferentially surrounding the groove 24 .

[0059] The radial distance between two adjacent surrounding through-hole groups may be less than or equal to 8 μm, so as to ensure that the two adjacent surrounding through-hole groups are not too far apart to affect the equal distribution of the instantaneous current injected by the first electrode 71 .

[0060] For example, the aperture of the second through-hole 302 of the surrounding through-hole group close to the groove 24 may be larger than the aperture of the second through-hole 302 of the annular through-hole group far from the groove 24 .

[0061] Since the second through hole 302 closer to the groove 24 is closer to the first electrode 71, the transient current injected from the first electrode 71 can more easily enter the second through hole 302 closer to the first electrode 71. Therefore, making the aperture of the second through hole 302 closer to the groove 24 larger is conducive to quickly dissipating larger transient currents.

[0062] Optionally, the radial cross-section of the second through hole 302 is circular, elliptical or polygonal.

[0063] For example, Figure 3 , 4 As shown, the radial cross-sections of the first through hole 301 and the second through hole 302 are both circular.

[0064] Exemplarily, the second through hole 302 may also be configured as an ellipse or a polygon, which is beneficial for increasing the area of ​​the radial cross section of the second through hole 302, thereby making it easier to resolve larger transient currents.

[0065] Alternatively, if Figure 2 As shown, the insulating layer 30 includes an insulating buffer layer 31 and an insulating reflective layer 32 sequentially stacked on the second semiconductor layer 23 , and the first through hole 301 and the second through hole 302 both penetrate the insulating reflective layer 32 and the insulating buffer layer 31 .

[0066] In the disclosed embodiment, an insulating buffer layer 31 is disposed on the transparent conductive layer 40 . The insulating buffer layer 31 can isolate the transparent conductive layer 40 from contact with other film layers, so as to fully protect the transparent conductive layer 40 .

[0067] Exemplarily, the insulating buffer layer 31 may be a silicon oxide layer.

[0068] Optionally, the thickness of the insulating buffer layer 31 is less than or equal to 500 angstroms. Exemplarily, the thickness of the insulating buffer layer 31 is 300 angstroms, which can prevent the insulating buffer layer 31 from being too thick and absorbing more light, thereby affecting the brightness of the light-emitting diode.

[0069] In the disclosed embodiment, an insulating reflective layer 32 is further provided on the insulating buffer layer 31. The insulating reflective layer 32 can reflect the light emitted from the epitaxial layer 20, allowing more light to be emitted from the light emitting surface of the LED, thereby improving the brightness of the LED.

[0070] Exemplarily, the insulating reflective layer 32 may be a DBR (Distributed Bragg Reflector) layer.

[0071] The DBR layer includes a plurality of silicon oxide layers and a plurality of titanium oxide layers stacked alternately, and the thickness of the DBR layer is 3 μm to 4 μm.

[0072] Alternatively, if Figure 2 As shown, the light emitting diode further includes: a transparent conductive layer 40, a metal reflective layer 51, an insulating protective layer 52 and a first passivation layer 61, the transparent conductive layer 40 is located on the second semiconductor layer 23, and the insulating layer 30 covers the transparent conductive layer 40, and the first through hole 301 and the second through hole 302 both expose the transparent conductive layer 40.

[0073] like Figure 2 As shown, the metal reflective layer 51 is located on the surface of the insulating reflective layer 32 away from the epitaxial layer 20 , and is connected to the transparent conductive layer 40 through the first through hole 301 and the second through hole 302 .

[0074] like Figure 2 As shown, the insulating protection layer 52 and the first passivation layer 61 are sequentially stacked on the surface of the insulating reflective layer 32 away from the epitaxial layer 20, the insulating protection layer 52 covers the metal reflective layer 51, the first passivation layer 61 has via holes that expose the metal reflective layer 51 and the bottom of the groove 24 respectively, the first electrode 71 and the second electrode 72 are both located on the surface of the first passivation layer 61 away from the epitaxial layer 20, the first electrode 71 is connected to the first semiconductor layer 21 through the via hole, and the second electrode 72 is connected to the metal reflective layer 51 through the via hole.

[0075] Optionally, the transparent conductive layer 40 may be an indium tin oxide (ITO) layer or an indium zinc oxide (IZO) layer.

[0076] Exemplarily, the transparent conductive layer 40 is an indium tin oxide layer. The indium tin oxide layer has good transmittance and low resistivity. The indium tin oxide layer has low resistivity, facilitates carrier conduction, and improves injection efficiency.

[0077] Exemplarily, the transparent conductive layer 40 is an indium zinc oxide layer. The indium zinc oxide layer has good transmittance and low resistivity. The indium zinc oxide layer has low resistivity, facilitates carrier conduction, and improves injection efficiency.

[0078] Exemplarily, the thickness of the transparent conductive layer 40 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 40 is 200 angstroms.

[0079] In the embodiment of the present disclosure, the metal reflective layer 51 is provided to reflect the light emitted from the epitaxial layer 20 , so that more light is emitted from the light emitting surface of the epitaxial layer 20 , thereby improving the light emitting intensity of the light emitting diode.

[0080] At the same time, the metal reflective layer 51 is also covered with an insulating protection layer 52 to prevent the metal in the metal reflective layer 51 from migrating upward.

[0081] Using an insulating protective layer 52 to cover the metal reflective layer 51 can not only save costs, but also the insulating protective layer 52 can be made of different materials from the insulating layer 30, so that the refractive index of the insulating protective layer 52 and the insulating layer 30 is different, so that the light is reflected or refracted at the junction of the insulating protective layer 52 and the insulating layer 30, so as to avoid the light being absorbed by the metal, thereby increasing the light output of the light-emitting diode.

[0082] Optionally, the metal reflective layer 51 includes an Ag layer, a Ni layer, and a TiW layer stacked in sequence.

[0083] Since Ag has a good reflective effect, providing an Ag layer in the reflective layer can enhance the reflection of light by the reflective layer and improve the light emitting brightness of the light emitting surface of the light emitting diode.

[0084] The Ni layer has good corrosion resistance and wear resistance, and the TiW layer can be successfully deposited on other films as an adhesion layer without peeling or cracking. The alternating stacked Ni and TiW layers can act as a barrier layer to protect the silver mirror.

[0085] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0086] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0087] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0088] Optionally, the insulating protection layer 52 includes an aluminum oxide layer.

[0089] Optionally, the thickness of the insulating protective layer 52 is 500 angstroms to 1200 angstroms. The thickness of the insulating protective layer 52 cannot be set too thin to prevent the insulating protective layer 52 from failing to block the metal migration in the reflective layer, and the thickness of the insulating protective layer 52 cannot be set too thick to avoid the insulating protective layer 52 being too thick and absorbing a large amount of light.

[0090] By way of example, the thickness of the insulating protection layer 52 is 1000 angstroms.

[0091] Optionally, the first passivation layer 61 may be a silicon oxide layer.

[0092] Exemplarily, the thickness of the first passivation layer 61 is 4000 angstroms to 6000 angstroms.

[0093] Optionally, the first electrode 71 and the second electrode 72 each include a Cr layer, an Al layer, a Ti layer and a Pt layer stacked in sequence. The Cr layer is evaporated to a thickness of 1500 to 2500 angstroms. The Al layer is evaporated to a thickness of 1000 to 2500 angstroms. The Ti layer is evaporated to a thickness of 300 to 700 angstroms. The Pt layer is evaporated to a thickness of 1500 to 2500 angstroms.

[0094] Alternatively, if Figure 2 As shown, the light emitting diode may further include a second passivation layer 62 and a pad 80, wherein the second passivation layer 62 is located on the surface of the first passivation layer 61 and covers the first electrode 71 and the second electrode 72. The second passivation layer 62 has a through hole exposing the first electrode 71 and the second electrode 72, and the pad 80 is located on the surface of the second passivation layer 62 away from the epitaxial layer 20, and the pad 80 is electrically connected to the first electrode 71 and the second electrode 72 through the through hole.

[0095] Optionally, the pad 80 includes at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0096] The above metal material has good heat dissipation performance. Therefore, the pad 80 made of the above material also has good heat dissipation performance, which can improve the heat dissipation effect of the light emitting diode.

[0097] Alternatively, the pad 80 includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked in sequence.

[0098] Exemplarily, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0099] Exemplarily, the thickness of the Al layer is 10000 angstroms to 20000 angstroms. For example, the thickness of the Al layer is 15000 angstroms.

[0100] Exemplarily, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the second Ti layer is 1000 angstroms.

[0101] Exemplarily, the thickness of the Pt layer is 500 angstroms to 1500 angstroms. For example, the thickness of the Pt layer is 1000 angstroms.

[0102] Exemplarily, the thickness of the Ni layer is 60,000 angstroms to 80,000 angstroms. For example, the thickness of the Ni layer is 70,000 angstroms.

[0103] Exemplarily, the thickness of the Au layer is 1500 angstroms to 2500 angstroms. For example, the thickness of the Au layer is 2000 angstroms.

[0104] Alternatively, if Figure 2 As shown, the light emitting diode further includes a substrate 10 , and an epitaxial layer 20 is located on the surface of the substrate 10 .

[0105] Exemplarily, the substrate is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0106] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0107] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0108] In the implementation of the present disclosure, the first semiconductor layer 21 is Al x Ga 1-xN material layer, wherein X is greater than or equal to 0 and less than or equal to 1.

[0109] Exemplarily, when X is 0, the first semiconductor layer 21 is a GaN layer. For example, the first semiconductor layer 21 is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0110] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0111] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0112] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0113] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0114] Figure 5 FIG. 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 5 As shown, the preparation method comprises:

[0115] Step S11: forming an epitaxial layer.

[0116] The epitaxial layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence, and the second semiconductor layer has a groove exposing the first semiconductor layer.

[0117] Step S12: forming an insulating layer at least on the surface of the second semiconductor layer.

[0118] The insulating layer includes a first through hole exposing the second semiconductor layer and a plurality of second through holes, the first through hole and the second through holes are arranged at intervals, and the plurality of second through holes are arranged at intervals around the groove.

[0119] Step S13: manufacturing a first electrode and a second electrode.

[0120] The first electrode is located in the groove and electrically connected to the first semiconductor layer, the second electrode is located on a side of the insulating layer away from the epitaxial layer, and the insulating layer is electrically connected to the second semiconductor layer through the first through hole and the second through hole.

[0121] The light-emitting diode provided in the embodiment of the present disclosure is provided with a first through hole and a second through hole arranged at intervals on the insulating layer, wherein the second through holes are arranged at intervals around the groove of the epitaxial layer. The first electrode is electrically connected to the first semiconductor layer in the groove, and the second electrode is above the insulating layer and electrically connected to the second semiconductor layer through the first through hole and the second through hole.

[0122] When a negative pulse voltage is applied to the light-emitting diode, the current injected from the first electrode will be evenly distributed to each second through hole surrounding the groove, so that the larger instantaneous current can be split into different second through holes, allowing each second through hole to flow into a relatively small current. Therefore, the problem of the current concentration effect causing the explosion point in the related art, where the current injected from the first electrode directly flows into a single through hole near the first electrode, is avoided, thereby improving the problem of excessive instantaneous current at the through hole near the first electrode burning the light-emitting diode, and improving the EOS performance of the light-emitting diode.

[0123] The step S11 of preparing the epitaxial layer may include:

[0124] First, a substrate is provided.

[0125] The substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0126] As an example, in the embodiment of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0127] The sapphire substrate may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0128] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0129] Then, a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer are sequentially formed on the sapphire substrate by MOCVD technology.

[0130] The first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0131] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0132] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0133] Optionally, the multi-quantum well layer includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Wherein, the multi-quantum well layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0134] When growing multi-quantum well layers, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing InGaN quantum well layers, the temperature of the reaction chamber is 760°C to 780°C. When growing GaN quantum barrier layers, the temperature of the reaction chamber is 860°C to 890°C.

[0135] As an example, in the embodiment of the present disclosure, the multi-quantum well layer includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0136] Optionally, the thickness of the multi-quantum well layer may be 150 nm to 200 nm.

[0137] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0138] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0139] Then, the second semiconductor layer is etched to form a groove exposing the first semiconductor layer.

[0140] Before step S12, the method further includes: forming a transparent conductive layer on the surface of the second semiconductor layer.

[0141] Exemplarily, the transparent conductive layer is an indium tin oxide layer or an indium zinc oxide layer.

[0142] Exemplarily, the thickness of the transparent conductive layer is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer is 250 angstroms.

[0143] Step S12 may include the following steps:

[0144] First, an insulating buffer layer and an insulating reflective layer are formed on the surface of the second semiconductor layer, the surface of the transparent conductive layer and in the groove to obtain an insulating layer.

[0145] Exemplarily, the insulating buffer layer includes a silicon oxide layer.

[0146] Exemplarily, the thickness of the insulating buffer layer is 100 angstroms to 500 angstroms.

[0147] Exemplarily, the insulating reflective layer includes a DBR layer, the DBR layer includes a plurality of silicon oxide layers and a plurality of titanium oxide layers alternately stacked, and the thickness of the DBR layer is 3 μm to 4 μm.

[0148] Then, a first through hole and a second through hole exposing the transparent conductive layer are formed by etching on the surface of the insulating reflective layer.

[0149] The first through holes and the second through holes are arranged at intervals, and a plurality of second through holes surround the groove and are arranged at intervals.

[0150] Before step S13, the following steps may also be included:

[0151] First, a metal reflective layer is formed on the surface of the insulating layer, and the metal reflective layer is electrically connected to the transparent conductive layer through the first through hole and the second through hole.

[0152] Optionally, the metal reflective layer includes an Ag layer, a Ni layer and a TiW layer stacked in sequence.

[0153] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0154] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0155] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0156] Next, an insulating protective layer is formed on the surface of the insulating layer so that the insulating protective layer covers the metal reflective layer.

[0157] Optionally, the insulating protective layer includes an aluminum oxide layer. In this way, the insulating layer and the insulating protective layer can form a composite insulating layer composed of two different materials alternately stacked, so that light is reflected or refracted at the junction of two adjacent film layers, thereby increasing the amount of light output.

[0158] Optionally, the thickness of the insulating protection layer is 500 angstroms to 1200 angstroms. Exemplarily, the thickness of the insulating protection layer is 1000 angstroms.

[0159] Then, a first passivation layer is formed on the surface of the insulating protection layer and in the groove.

[0160] like Figure 1 As shown, the first passivation layer covers the insulating protection layer, and the first passivation layer has via holes that expose the metal reflective layer and the bottom of the groove respectively.

[0161] Exemplarily, the first passivation layer may be a silicon oxide layer.

[0162] Exemplarily, the thickness of the first passivation layer is 4000 angstroms to 6000 angstroms.

[0163] Step S13 may include: forming a first electrode and a second electrode on a surface of the first passivation layer.

[0164] Optionally, the first electrode is connected to the first semiconductor layer through a via hole, and the second electrode is connected to the metal reflective layer through a via hole.

[0165] Exemplarily, the metal reflective layer is connected to the second semiconductor layer, and the second semiconductor layer is a p-type layer, so the second electrode electrically connected to the metal reflective layer is a p-electrode.

[0166] Exemplarily, the first semiconductor layer is an n-type layer, and the first electrode electrically connected to the first semiconductor layer is an n-electrode.

[0167] The preparation of the electrode may specifically include: sequentially evaporating a Cr layer, an Al layer, a Ti layer and a Pt layer.

[0168] Exemplarily, the thickness of the evaporated Cr layer is 1500 angstroms to 2500 angstroms.

[0169] Illustratively, the thickness of the evaporated Al layer is 1000 angstroms to 2500 angstroms.

[0170] Among them, the Ti layer and the Pt layer are used as wrapping layers, and a thicker metal layer can be used to reduce the resistance of the electrode, and at the same time, can protect the Cr layer and the Al layer.

[0171] Illustratively, the thickness of the Ti layer evaporated is 300 angstroms to 700 angstroms.

[0172] Illustratively, the thickness of the evaporated Pt layer is 1500 angstroms to 2500 angstroms.

[0173] After step S13, the following steps may also be included:

[0174] First, a second passivation layer is formed on the surface of the first passivation layer so that the second passivation layer covers the electrode, and the second passivation layer is etched to form a through hole exposing the electrode.

[0175] Exemplarily, the second passivation layer is a DBR (Distributed Bragg Reflector) layer, and the DBR layer includes a plurality of silicon oxide layers and a plurality of titanium oxide layers, and the thickness of the DBR layer is 3 μm to 4 μm.

[0176] Next, a pad is formed on the surface of the second passivation layer, and the pad is electrically connected to the electrode through the through hole.

[0177] Optionally, the pad layer includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer and an Au layer stacked in sequence.

[0178] Exemplarily, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0179] Exemplarily, the thickness of the Al layer is 10000 angstroms to 20000 angstroms. For example, the thickness of the Al layer is 15000 angstroms.

[0180] Exemplarily, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the second Ti layer is 1000 angstroms.

[0181] Exemplarily, the thickness of the Pt layer is 500 angstroms to 1500 angstroms. For example, the thickness of the Pt layer is 1000 angstroms.

[0182] Exemplarily, the thickness of the Ni layer is 60,000 angstroms to 80,000 angstroms. For example, the thickness of the Ni layer is 70,000 angstroms.

[0183] Exemplarily, the thickness of the Au layer is 1500 angstroms to 2500 angstroms. For example, the thickness of the Au layer is 2000 angstroms.

[0184] Figure 6 is a comparison chart of the EOS performance of a light emitting diode provided by an embodiment of the present disclosure. Figure 6 As shown in the figure, the horizontal axis is the number of light-emitting diodes, and the vertical axis is the voltage that the light-emitting diodes can withstand. Figure 6 It can be known that the voltage that the light-emitting diode provided in the embodiment of the present disclosure can withstand is 20V higher than the voltage that the light-emitting diode in the related art can withstand. Therefore, the light-emitting diode provided in the embodiment of the present disclosure can improve the EOS performance of the light-emitting diode.

[0185] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: an epitaxial layer (20), an insulating layer (30), a first electrode (71) and a second electrode (72); The epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22) and a second semiconductor layer (23) which are stacked in sequence, the surface of the second semiconductor layer (23) having a groove (24) exposing the first semiconductor layer (21), the insulating layer (30) being at least located on the surface of the second semiconductor layer (23), the insulating layer (30) comprising a first through hole (301) exposing the second semiconductor layer (23) and a plurality of second through holes (302), the first through hole (301) and the second through hole (302) being arranged at intervals, and the plurality of second through holes (302) surrounding the groove (24) and being arranged at intervals; The first electrode (71) is at least located in the groove (24) and is electrically connected to the first semiconductor layer (21); the second electrode (72) is located on a side of the insulating layer (30) away from the epitaxial layer (20); and the insulating layer (30) is electrically connected to the second semiconductor layer (23) via the first through hole (301) and the second through hole (302).

2. The light emitting diode according to claim 1, characterized in that: The sum of the radial cross-sectional areas of the plurality of second through holes (302) is greater than or equal to the contact area between the first electrode (71) and the first semiconductor layer (21).

3. The light emitting diode according to claim 1, characterized in that: The width of the radial cross section of the second through hole (302) is greater than the width of the radial cross section of the first through hole (301).

4. The light emitting diode according to claim 1, characterized in that: The maximum distance from the area where the first electrode (71) contacts the first semiconductor layer (21) to the second through hole (302) is less than or equal to 15 μm.

5. The light emitting diode according to claim 1, characterized in that: The plurality of second through holes (302) include at least one surrounding through hole group, each of the surrounding through hole groups includes a plurality of second through holes (302) uniformly distributed circumferentially with the geometric center of the groove (24) as the midpoint, and different surrounding through hole groups are concentrically distributed.

6. The light emitting diode according to claim 5, characterized in that: The radial cross-section of the second through hole (302) is circular, elliptical or polygonal.

7. The light emitting diode according to any one of claims 1 to 5, characterized in that: The width of the radial cross section of the second through hole (302) is 4 μm to 10 μm.

8. The light emitting diode according to any one of claims 1 to 5, characterized in that: The insulating layer (30) comprises an insulating buffer layer (31) and an insulating reflective layer (32) which are sequentially stacked on the second semiconductor layer (23); the first through hole (301) and the second through hole (302) both penetrate the insulating reflective layer (32) and the insulating buffer layer (31).

9. The light emitting diode according to claim 8, characterized in that: The light emitting diode further comprises: a transparent conductive layer (40), a metal reflective layer (51), an insulating protective layer (52) and a first passivation layer (61); the transparent conductive layer (40) is located on the second semiconductor layer (23), the insulating layer (30) covers the transparent conductive layer (40), and the first through hole (301) and the second through hole (302) both expose the transparent conductive layer (40); The metal reflective layer (51) is located on a surface of the insulating reflective layer (32) away from the epitaxial layer (20), and is connected to the transparent conductive layer (40) through the first through hole (301) and the second through hole (302); The insulating protective layer (52) and the first passivation layer (61) are sequentially stacked on a surface of the insulating reflective layer (32) away from the epitaxial layer (20); the insulating protective layer (52) covers the metal reflective layer (51); the first passivation layer (61) has via holes respectively exposing the metal reflective layer (51) and the bottom of the groove (24); the first electrode (71) and the second electrode (72) are both located on a surface of the first passivation layer (61) away from the epitaxial layer (20); the first electrode (71) is connected to the first semiconductor layer (21) through the via hole; and the second electrode (72) is connected to the metal reflective layer (51) through the via hole.

10. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: forming an epitaxial layer, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, wherein a surface of the second semiconductor layer has a groove exposing the first semiconductor layer; forming an insulating layer at least on a surface of the second semiconductor layer, the insulating layer comprising a first through hole exposing the second semiconductor layer and a plurality of second through holes, the first through hole and the second through holes being arranged at intervals, and the plurality of second through holes being arranged at intervals around the groove; A first electrode and a second electrode are manufactured, wherein the first electrode is located in the groove and is electrically connected to the first semiconductor layer, and the second electrode is located on a side of the insulating layer away from the epitaxial layer, and the insulating layer is electrically connected to the second semiconductor layer through the first through hole and the second through hole.

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