Pattern testing method, device, equipment and medium for single crystal grains

Abstract

The present application discloses a pattern test method, device, equipment, and medium for a single crystal grain, and relates to the field of wafer testing technology. The method includes: when the first capacity to be tested of a single first crystal grain to be tested in the wafer to be tested is greater than the preset capacity threshold, obtaining the current first parameter file; the first parameter file includes: first algorithm selection information and preset difference; according to the first capacity difference and the preset difference between the first capacity to be tested and the preset capacity threshold, the first algorithm selection information is updated to obtain the second algorithm selection information and the updated second parameter file; according to the second algorithm selection information, a target pattern test algorithm is determined and started from a plurality of different candidate pattern test algorithms; according to the second parameter file and the target pattern test algorithm, the first crystal grain is pattern tested in different regions to complete the single crystal grain test. It can improve the efficiency of single crystal grain testing.

Description

Technical Field

[0001] The present application relates to the field of wafer testing technology, and in particular to a pattern testing method, device, equipment, and medium for a single crystal grain. Background Art

[0002] Usually, in the process of manufacturing chips, CP (Chip Probing) test and FT (Final Test) test are required. Among them, CP test refers to the whole wafer that has not been divided and packaged to connect the exposed chip pins to the test machine through probes after wafer manufacturing, and execute the test pattern to perform functional testing on the chip. A memory wafer (Flash Wafer) usually has hundreds of dies. After the wafer test, the defective dies are marked. When packaging the dies, usually only good dies are selected to be packaged into finished products. The defective dies are called ink dies and are discarded. Die in the semiconductor industry refers to an integrated circuit chip that has not been packaged, that is, a bare chip, wafer, etc.

[0003] At present, in the process of testing a single crystal grain, if the capacity of the single crystal grain to be tested exceeds a certain threshold, there is a problem of incomplete testing of the single crystal grain. Usually, it is necessary to modify the overall and underlying test algorithm to complete all tests on the single crystal grain whose capacity to be tested exceeds a certain threshold. However, changing the overall and underlying test algorithm to adapt to the capacity of the single crystal grain to be tested is difficult and inefficient, which also leads to low efficiency of single crystal grain testing and is difficult to apply to batch testing with changing conditions in production and manufacturing. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a pattern test method, device, equipment, and medium for single-crystal grains, which can match different target pattern test algorithms according to different single-crystal grain capacities to be tested to perform pattern tests on single-crystal grains, improve the efficiency of single-crystal grain testing, and enhance the universality of testing.

[0005] In a first aspect, an embodiment of the present application provides a pattern testing method for a single crystal grain, comprising:

[0006] Determine a first die to be tested from the wafer to be tested, and determine a first capacity to be tested of a single first die;

[0007] When the first capacity to be tested is greater than a preset capacity threshold, obtaining a current first parameter transmission file; wherein the first parameter transmission file includes: first algorithm selection information and a preset difference value; the first algorithm selection information is binary data of all 0s, and the number of bits of the binary data is the same as the current first total number of candidate pattern test algorithms;

[0008] According to a first capacity difference between the first capacity to be measured and the preset capacity threshold and the preset difference, the first algorithm selection information is updated to obtain second algorithm selection information and an updated second parameter file including the second algorithm selection information;

[0009] Run and parse the second parameter transfer file, and determine and start a target pattern test algorithm from a plurality of different candidate pattern test algorithms according to the second algorithm selection information;

[0010] According to the second parameter transfer file and the target Pattern test algorithm, Pattern test is performed on the first grain to be tested in different regions to complete the single grain test.

[0011] According to some embodiments of the present application, the updating process of the first algorithm selection information is performed according to the first capacity difference between the first capacity to be measured and the preset capacity threshold, and the preset difference, to obtain the second algorithm selection information and the updated second parameter file including the second algorithm selection information, including:

[0012] Subtracting the preset capacity threshold from the first capacity to be measured to obtain the first capacity difference;

[0013] Dividing the first capacity difference by the preset difference to obtain a quotient;

[0014] After rounding the quotient, the obtained integer is determined as the digit number;

[0015] Modify the low level value corresponding to the target number of bits in the first algorithm selection information indicated by the number of bits to a high level value to obtain updated second algorithm selection information;

[0016] Generate an updated second parameter file based on the second algorithm selection information.

[0017] According to some embodiments of the present application, the first parameter transmission file and the second parameter transmission file both include: an algorithm enable signal;

[0018] The running and parsing of the second parameter transfer file, and determining and starting a target pattern test algorithm from a plurality of different candidate pattern test algorithms according to the second algorithm selection information, includes:

[0019] Run and parse the second parameter transfer file to obtain the algorithm enable signal;

[0020] In response to the algorithm enable signal, the preconfigured LK algorithm is enabled, and a plurality of ranked candidate Pattern test algorithms are determined from the LK algorithm; wherein different candidate Pattern test algorithms are obtained based on different configurations of the capacity to be tested;

[0021] In response to a low level value in the second algorithm selection information, disabling the candidate pattern test algorithm at the corresponding sorting position;

[0022] In response to the high level value in the second algorithm selection information, the candidate Pattern test algorithm at the corresponding sorting position is determined as the target Pattern test algorithm, and the target Pattern test algorithm is started.

[0023] According to some embodiments of the present application, the method further includes:

[0024] In response to an algorithm update instruction, adding or deleting the candidate Pattern test algorithm in the LK algorithm;

[0025] Determine a second total number of the candidate Pattern test algorithms in the current LK algorithm;

[0026] Modify the first algorithm selection information according to the second total number to obtain updated first algorithm selection information; wherein the number of bits of the updated first algorithm selection information is determined by the second total number;

[0027] Generate an updated first parameter file based on the updated first algorithm selection information.

[0028] According to some embodiments of the present application, the second parameter transmission file further includes: test parameters;

[0029] The step of performing pattern testing on the first die to be tested in different regions according to the second parameter transfer file and the target pattern testing algorithm to complete single-die testing includes:

[0030] Dividing the first die to be tested into a first test area and a second test area according to a preset capacity threshold; wherein the capacity to be tested in the first test area is equal to the preset capacity threshold; and the capacity to be tested in the second test area is equal to the first capacity difference;

[0031] Based on a preset conventional test mode, performing a first test process on the first test area;

[0032] Acquire the test parameters from the second parameter transfer file, and perform a second test process on the second test area according to the target pattern test algorithm and the test parameters;

[0033] When the first test process and the second test process are completed, the Pattern test is completed.

[0034] According to some embodiments of the present application, the method further includes:

[0035] When the first capacity to be tested is less than or equal to a preset capacity threshold, determining a preset conventional Pattern test algorithm;

[0036] According to the preset conventional Pattern test algorithm, the first die is subjected to Pattern test to complete the single-die test.

[0037] According to some embodiments of the present application, after performing the Pattern test on the first die and completing the single-die test, the method further includes:

[0038] Determine a next second die to be tested from the wafer to be tested, and determine a second capacity to be tested of the single second die;

[0039] When the second capacity to be tested is greater than a preset capacity threshold, obtaining the current first parameter transmission file; wherein the first parameter transmission file includes: first algorithm selection information and a preset difference value; the first algorithm selection information is binary data of all 0s, and the number of bits of the binary data is the same as the current first total number of the candidate pattern test algorithm;

[0040] According to the second capacity difference between the second capacity to be measured and the preset capacity threshold and the preset difference, the first algorithm selection information is updated to obtain third algorithm selection information and a third parameter transmission file including the update of the third algorithm selection information;

[0041] Run and parse the third parameter transfer file, and determine and start a target pattern test algorithm from a plurality of candidate pattern test algorithms according to the third algorithm selection information;

[0042] According to the third parameter transfer file and the target Pattern test algorithm, the Pattern test is performed on the second die to be tested in different regions to complete the single-die test;

[0043] The wafer test is terminated until the Pattern test is completed on all the dies to be tested in the wafer to be tested.

[0044] In a second aspect, an embodiment of the present application provides a Pattern testing device for a single crystal grain, comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the Pattern testing method for a single crystal grain as described in any one of the embodiments of the first aspect.

[0045] In a third aspect, an embodiment of the present application provides an electronic device, comprising a Pattern testing device for a single crystal die as described in the embodiment of the second aspect.

[0046] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the Pattern testing method for a single crystal grain as described in any one of the embodiments of the first aspect.

[0047] The embodiment of the present application includes: by utilizing a pattern test device for a single crystal grain, first, determining a first crystal grain to be tested from a wafer to be tested, and determining a first capacity to be tested of the single first crystal grain; second, when the first capacity to be tested is greater than a preset capacity threshold, obtaining a current first parameter file; wherein the first parameter file includes: first algorithm selection information and a preset difference; the first algorithm selection information is binary data of all 0s, and the number of bits of the binary data is the same as the current first total number of candidate Pattern test algorithms; and then, according to the first capacity difference and the preset difference between the first capacity to be tested and the preset capacity threshold, updating the first algorithm selection information to obtain the second algorithm selection information and the first parameter file including the second algorithm selection information. The second parameter file is updated with information; then, the second parameter file is run and parsed, and a target Pattern test algorithm is determined and started from multiple different candidate Pattern test algorithms according to the second algorithm selection information; in this way, there is no need to rewrite the underlying test algorithm, but different target Pattern test algorithms are quickly and directly matched and called according to different single-crystal grain capacities to be tested, laying the foundation for Pattern testing, which is conducive to improving the efficiency of single-crystal grain testing; finally, according to the second parameter file and the target Pattern test algorithm, the first grain to be tested is pattern tested in different regions to complete the single-crystal grain test; thereby improving the efficiency of single-crystal grain testing and enhancing the universality of testing. That is to say, the embodiment of the present application can match different target Pattern test algorithms according to different single-crystal grain capacities to be tested to perform Pattern testing on single-crystal grains, thereby improving the efficiency of single-crystal grain testing and enhancing the universality of testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a structural schematic diagram of a Pattern testing system for a single crystal grain provided by an embodiment of the present application;

[0049] Figure 2 It is a schematic diagram of the steps of a Pattern testing method for a single crystal grain provided in one embodiment of the present application;

[0050] Figure 3 It is a specific schematic diagram of a target pattern test algorithm provided by an embodiment of the present application;

[0051] Figure 4 yes Figure 2 Specific step flow chart of step S140;

[0052] Figure 5 It is a schematic diagram of the hardware structure of a Pattern testing device for a single crystal grain provided in one embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0054] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0056] The present application discloses a pattern test method for a single crystal grain, a pattern test device for a single crystal grain, an electronic device and a computer-readable storage medium, and relates to the field of wafer testing technology. The method includes: when the first capacity to be tested of a single first crystal grain to be tested in the wafer to be tested is greater than a preset capacity threshold, obtaining the current first parameter file; the first parameter file includes: first algorithm selection information and a preset difference; according to the first capacity difference and the preset difference between the first capacity to be tested and the preset capacity threshold, the first algorithm selection information is updated to obtain the second algorithm selection information and the updated second parameter file; according to the second algorithm selection information, a target pattern test algorithm is determined and started from a plurality of different candidate pattern test algorithms; according to the second parameter file and the target pattern test algorithm, the first crystal grain is pattern tested in different regions to complete the single crystal grain test. It can improve the efficiency of single crystal grain testing and enhance the universality of testing.

[0057] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0058] like Figure 1 As shown, the Pattern test system for a single crystal grain includes: a host computer and a test machine, the host computer is electrically connected to the test machine, the test machine is used to load the round wafer to be tested, and the host computer is used to run the test software. The host computer and the test machine cooperate with each other to execute the Pattern test method for a single crystal grain provided by the implementation of this application, and can match different target Pattern test algorithms according to different single crystal grain capacities to be tested to perform Pattern test on the single crystal grain, thereby improving the efficiency of single crystal grain testing.

[0059] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0060] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0061] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0062] Based on the above system structure, various embodiments of the Pattern testing method for a single crystal grain of the present application are proposed below.

[0063] First, as Figure 2 As shown, the Pattern testing method for a single die may include but is not limited to steps S110 to S150.

[0064] Step S110: determining a first die to be tested from the wafer to be tested, and determining a first capacity to be tested of the single first die.

[0065] Step S120: When the first capacity to be tested is greater than the preset capacity threshold, obtain the current first parameter file; wherein the first parameter file includes: first algorithm selection information and a preset difference; the first algorithm selection information is binary data of all 0s, and the number of bits of the binary data is the same as the current first total number of the candidate Pattern test algorithm.

[0066] Step S130: updating the first algorithm selection information according to the first capacity difference between the first capacity to be measured and the preset capacity threshold and the preset difference, to obtain the second algorithm selection information and the updated second parameter file including the second algorithm selection information.

[0067] Step S140: run and parse the second parameter file, and determine and start a target Pattern test algorithm from a plurality of different candidate Pattern test algorithms according to the second algorithm selection information.

[0068] Step S150: According to the second parameter file and the target Pattern test algorithm, the Pattern test is performed on the first die to be tested in different regions to complete the single-die test.

[0069] Further explanation of step S110, wherein determining the first die to be tested from the wafer to be tested specifically includes: for the die to be tested, the host computer sends a single Die test instruction to the tester through the serial port, and the GPIO control selection chip of the tester makes a signal connection to the die to be tested; for the Die that does not need to be tested, no signal connection is made; thereby determining the first die to be tested from the wafer to be tested.

[0070] It is understandable that a Die product is composed of many blocks, and determining the first capacity to be tested of a single first die is specifically as follows: reading the number of blocks, and determining the first capacity to be tested of the single first die based on the number of blocks and the single block capacity.

[0071] Specifically, the preset capacity threshold is 3 GB, and the preset capacity threshold may also be set to other values ​​according to actual test conditions. Therefore, the embodiment of the present application does not impose any specific restrictions on the value of the preset capacity threshold.

[0072] It can be understood that the first parameter transmission file includes: first algorithm selection information, test parameters, preset difference, and algorithm enable signal. Among them, the test parameters, preset difference, and first algorithm selection information can be pre-configured respectively through the configuration interface provided by the host computer. In addition, the current first algorithm selection information can also be updated based on the second total number of candidate Pattern test algorithms in the current LK algorithm and the previous first algorithm selection information when adding or deleting candidate Pattern test algorithms in the LK algorithm; the algorithm enable signal is used to enable the pre-configured LK algorithm.

[0073] Specifically, the first algorithm selection information is binary data of all 0s, and the number of bits of the binary data is the same as the current first total number of candidate pattern test algorithms. For example, when the current first total number of candidate pattern test algorithms is 6, the first algorithm selection information is: 000000.

[0074] Specifically, the preset difference may be 0.5, 1.5, 2, 3, etc.; this application does not impose any limitation on the specific value of the preset difference.

[0075] Specifically, the test parameters include but are not limited to: test start address, test background data, and test capacity. The test start address is used to determine the position where the test starts in the crystal to be tested, and the test capacity is used to determine the test end address together with the test start address. The test background data is used in the read-write verification process of the crystal to be tested. The read-write verification process refers to: inverting the background data to obtain the write data, writing the write data into the storage space of the crystal to be tested, and then reading the write data to obtain the read-back data; verifying whether the write data is consistent with the read-back data. If they are consistent, it is determined that there is no error in the storage space of the crystal; if they are inconsistent, it is determined that there is an error in the storage space of the crystal, and the error information is recorded.

[0076] It can be understood that the difference between the first parameter file and the second parameter file is that the first algorithm selection information is different from the second algorithm selection information, and the other test parameters, preset difference values, and algorithm enable signals are the same.

[0077] Specifically, different candidate pattern test algorithms are obtained based on different configurations of the capacity to be tested.

[0078] It can be understood that the Pattern testing method provided in the embodiment of the present application is performed in the preloader stage.

[0079] The embodiment of the present application, through steps S110 to S150, utilizes a pattern test device for a single crystal grain, firstly, determines a first crystal grain to be tested from a wafer to be tested, and determines a first capacity to be tested of the single first crystal grain; secondly, when the first capacity to be tested is greater than a preset capacity threshold, obtains a current first parameter file; wherein the first parameter file includes: first algorithm selection information and a preset difference; the first algorithm selection information is binary data of all 0s, and the number of bits of the binary data is the same as the current first total number of the candidate Pattern test algorithm; and then, according to the first capacity difference and the preset difference between the first capacity to be tested and the preset capacity threshold, the first algorithm selection information is updated to obtain the second algorithm selection information and the preset difference. The second parameter file of the updated second algorithm selection information; then, the second parameter file is run and parsed, and a target Pattern test algorithm is determined and started from a plurality of different candidate Pattern test algorithms according to the second algorithm selection information; in this way, there is no need to rewrite the underlying test algorithm, but different target Pattern test algorithms are quickly and directly matched and called according to different single-crystal grain capacities to be tested, which lays the foundation for Pattern testing and is conducive to improving the efficiency of single-crystal grain testing; finally, according to the second parameter file and the target Pattern test algorithm, the first grain to be tested is subjected to Pattern testing in different regions to complete the single-crystal grain testing; thereby improving the efficiency of single-crystal grain testing and enhancing the universality of testing. That is to say, the embodiment of the present application can match different target Pattern test algorithms according to different single-crystal grain capacities to be tested to perform Pattern testing on single-crystal grains, thereby improving the efficiency of single-crystal grain testing and enhancing the universality of testing.

[0080] According to some embodiments of the present application, step S130 is further described. Step S130 updates the first algorithm selection information according to the first capacity difference and the preset difference between the first capacity to be measured and the preset capacity threshold, and obtains the second algorithm selection information and the updated second parameter file including the second algorithm selection information, including but not limited to steps S131 to S135.

[0081] Step S131: subtracting a preset capacity threshold from the first capacity to be measured to obtain a first capacity difference.

[0082] Step S132: Divide the first capacity difference by the preset difference to obtain a quotient.

[0083] Step S133: After rounding the quotient, the obtained integer is determined as the digit number.

[0084] Step S134: modify the low-level value corresponding to the target number of bits in the first algorithm selection information indicated by the bit sequence number to a high-level value to obtain updated second algorithm selection information.

[0085] Step S135: Generate an updated second parameter file according to the second algorithm selection information.

[0086] Specifically, the high level value is 1, and the low level value is 0.

[0087] Take an example to illustrate the specific process of step S131 to step S135. When the first algorithm selection information is 000000. The first capacity to be tested is 9.5GB, the preset capacity threshold is 3GB, and the preset difference is 5GB; then the first capacity difference is: 9.5-3=6.5 (GB); let the first capacity difference 6.5GB be divided by the preset difference 5GB to get the quotient 1.3, and round the quotient 1.3 to get the bit number 2; correspondingly, according to the bit number 2, the second bit in the first algorithm selection information is determined as the target bit number, and the low level value corresponding to the target bit number is modified to a high level value, and the updated second algorithm selection information is 010000.

[0088] Through step S131 to step S135, the first algorithm selection information is updated according to the capacity to be tested of the single crystal grain to obtain the second algorithm selection information, so as to quickly and directly match and call different target pattern test algorithms based on the second algorithm selection information.

[0089] According to some embodiments of the present application, the first parameter file and the second parameter file both include: an algorithm enable signal; Figure 4 , further illustrating step S140, step S140: run and parse the second parameter file, determine and start a target Pattern test algorithm from multiple different candidate Pattern test algorithms according to the second algorithm selection information, including but not limited to steps S141 to S144.

[0090] Step S141: Run and parse the second parameter file to obtain an algorithm enable signal.

[0091] Step S142: In response to the algorithm enable signal, the preconfigured LK algorithm is enabled, and a plurality of sorted candidate Pattern test algorithms are determined from the LK algorithm; wherein different candidate Pattern test algorithms are obtained based on different configurations of the capacity to be tested.

[0092] Step S143: in response to the low level value in the second algorithm selection information, disabling the candidate Pattern test algorithm at the corresponding sorting position.

[0093] Step S144: In response to the high level value in the second algorithm selection information, the candidate Pattern test algorithm at the corresponding sorting position is determined as the target Pattern test algorithm, and the target Pattern test algorithm is started.

[0094] It can be understood that LK (Little Kernel) refers to the microkernel; the LK algorithm is pre-configured, and the LK algorithm includes multiple candidate pattern test algorithms; different candidate pattern test algorithms are obtained based on different configurations of the capacity to be tested; candidate pattern test algorithms are sorted in order from small to large with reference to the capacity to be tested. For example: the capacity to be tested corresponding to candidate pattern test algorithm 1 is 3GB to 8GB, the capacity to be tested corresponding to candidate pattern test algorithm 2 is 8GB to 13GB, and so on.

[0095] For example, Figure 3 As shown, the enabling state of each candidate Pattern test algorithm is determined according to the second algorithm selection information. Specifically, when the updated second algorithm selection information is 010000, the candidate Pattern test algorithm 1, candidate Pattern test algorithm 3 to candidate Pattern test algorithm 6 in the LK algorithm are correspondingly disabled; the candidate Pattern test algorithm 2 is correspondingly determined as the target Pattern test algorithm, and the target Pattern test algorithm is started.

[0096] Through step S141 to step S144, there is no need to rewrite the underlying test algorithm. Instead, different target Pattern test algorithms are quickly and directly matched and called according to different single-crystal capacity to be tested, which lays the foundation for Pattern testing and is conducive to improving the single-crystal test efficiency.

[0097] According to some embodiments of the present application, the second parameter file also includes: test parameters; further illustrating step S150, step S150: according to the second parameter file and the target Pattern test algorithm, pattern testing is performed on the first grain to be tested in different regions to complete the single grain test, including but not limited to steps S151 to S154.

[0098] Step S151: Divide the first die to be tested into a first test area and a second test area according to a preset capacity threshold; wherein the capacity to be tested in the first test area is equal to the preset capacity threshold; and the capacity to be tested in the second test area is equal to the first capacity difference.

[0099] Step S152: performing a first test process on the first test area based on a preset conventional test mode.

[0100] Step S153: Acquire test parameters from the second parameter transfer file, and perform a second test process on the second test area according to the target Pattern test algorithm and the test parameters.

[0101] Step S154: When the first test process and the second test process are completed, the Pattern test is completed.

[0102] In one embodiment, when executing the first test process of step S152, steps S120 to S140 can be performed simultaneously to determine the target pattern test algorithm. After the first test process is completed, the second test process of step S153 is performed to improve the test efficiency of the single-die test.

[0103] In one embodiment, after executing steps S120 to S140 to determine the target pattern test algorithm, steps S152 to S153 may be executed simultaneously to improve the test efficiency of the single die test.

[0104] Through step S151 to step S154, the single-crystal test is completed on the first crystal grain in different regions, thereby improving the test efficiency of the single-crystal test.

[0105] According to some embodiments of the present application, after step S110, the Pattern test method for a single crystal grain further includes: when the first capacity to be tested is less than or equal to the preset capacity threshold, determining a preset conventional Pattern test algorithm; performing a Pattern test on the first crystal grain according to the preset conventional Pattern test algorithm to complete the single crystal grain test. In this way, for the first crystal grain whose first capacity to be tested is less than or equal to the preset capacity threshold, it is not necessary to call the target Pattern test algorithm based on the second parameter transfer file, but directly use the existing preset conventional Pattern test algorithm to perform Pattern test to complete the single crystal grain test; thereby helping to improve test efficiency.

[0106] According to some embodiments of the present application, the Pattern testing method for a single crystal grain further includes but is not limited to steps S210 to S240.

[0107] Step S210: In response to the algorithm update instruction, a candidate Pattern test algorithm is added or deleted in the LK algorithm.

[0108] Step S220: Determine the second total number of candidate Pattern test algorithms in the current LK algorithm.

[0109] Step S230: modifying the first algorithm selection information according to the second total number to obtain updated first algorithm selection information; wherein the number of bits of the updated first algorithm selection information is determined by the second total number.

[0110] Step S240: Generate an updated first parameter file according to the updated first algorithm selection information.

[0111] It is understandable that the LK algorithm can be modified, and the candidate pattern test algorithm can be customized, updated and modified. Therefore, the tester can update the LK algorithm through the configuration interface provided by the host computer. For example: add or delete candidate pattern test algorithms, or adjust the order between candidate pattern test algorithms, or modify the specific content of the pattern test algorithm.

[0112] It is understandable that when the candidate pattern test algorithm in the LK algorithm is updated, it is necessary to re-count the second total number of candidate pattern test algorithms in the current LK algorithm, thereby modifying the first algorithm selection information of the first parameter file used as the benchmark, so as to facilitate the subsequent calling of the new candidate pattern test algorithm and the new LK algorithm.

[0113] The Pattern test algorithm is further explained. Wafer testing involves leakage current testing, working current testing, etc. This type of test is mainly completed by performing multiple read and write operations on the test object. The basic statement format of the above two operations is: [command] + [address] + [data]. Among them, [command] is a read instruction or a write instruction; [address] is the addressing information that determines the location of the minimum storage unit in the storage space of the test object; [data] is the content information to be stored in the corresponding address of the Flash. At present, in CP (Chip Probing wafer test) testing, vector template Pattern is usually used to simplify the test operation. It includes the following steps: write pre-operation (such as powering on related pins, etc.) in the Pattern test algorithm, write "command + address + data" in the Pattern, and finally run the Pattern test algorithm to complete the read or write operation of the test object. Before testing, write multiple candidate Pattern test algorithms first, and save the candidate Pattern test algorithms to the internal storage space of the tester for fast reading. The Pattern test algorithm contains pre-operation, command, address and data. At this time, the address in the Pattern test algorithm is any Flash address in the die to be tested, and the data is generally set to 0. This application configures different candidate Pattern test algorithms based on different capacities to be tested.

[0114] Through step S210 to step S240, when the LK algorithm is updated, the first algorithm selection information and the first parameter file are updated in a timely manner; thereby providing reliable guarantee for subsequently matching different target pattern test algorithms according to different single-crystal test capacities.

[0115] According to some embodiments of the present application, after performing a Pattern test on the first die and completing the single-die test, the method further includes but is not limited to steps S310 to S360.

[0116] Step S310: determining a next second die to be tested from the wafer to be tested, and determining a second capacity to be tested of the single second die.

[0117] Step S320: When the second capacity to be tested is greater than the preset capacity threshold, obtain the current first parameter file; wherein the first parameter file includes: first algorithm selection information and a preset difference; the first algorithm selection information is binary data of all 0s, and the number of bits of the binary data is the same as the current first total number of the candidate Pattern test algorithm.

[0118] Step S330: updating the first algorithm selection information according to the second capacity difference between the second capacity to be measured and the preset capacity threshold and the preset difference, to obtain the third algorithm selection information and the updated third parameter file including the third algorithm selection information.

[0119] Step S340: run and parse the third parameter file, and determine and start a target Pattern test algorithm from multiple candidate Pattern test algorithms according to the third algorithm selection information.

[0120] Step S350: According to the third parameter file and the target Pattern test algorithm, the Pattern test is performed on the second die to be tested in different regions to complete the single-die test.

[0121] Step S360: Wafer testing is terminated until all the tested dies in the tested wafer have completed the Pattern test.

[0122] It is understandable that a wafer to be tested includes multiple grains to be tested, and each grain to be tested needs to be tested. Therefore, after executing steps S110 to S150, the next second grain to be tested is determined in sequence, and steps S310 to S350 are executed to complete the single grain test on the second grain. When it is determined that the second grain currently tested is not the last grain to be tested in the wafer to be tested, steps S310 to S350 are automatically repeated to complete the single grain test on the next grain to be tested; until the test of the last grain to be tested in the wafer to be tested is completed, it is determined that the Pattern test is completed for all the grains to be tested in the wafer to be tested, and the wafer test is ended; automated testing is achieved for a wafer to be tested, thereby improving the overall efficiency of the wafer test.

[0123] It is understandable that the Pattern test is performed based on the target Pattern test algorithm. Different target Pattern test algorithms will result in different specific Pattern tests. This application does not impose any specific restrictions on each candidate Pattern test algorithm; the tester can configure it according to their needs.

[0124] Through step S310 to step S360, all the dies to be tested in the wafer to be tested are automatically tested, which is beneficial to improving the efficiency of the overall wafer test.

[0125] In one embodiment, when at least two wafers to be tested are loaded on the tester, the host computer automatically continues to test the next wafer to be tested after completing the wafer test on one wafer to be tested; all test results are recorded in the host computer to facilitate testers to view the test status.

[0126] like Figure 5 As shown, Figure 5 1 is a schematic diagram of the hardware structure of a pattern test device for a single crystal grain provided by an embodiment of the present application. The present invention also provides a pattern test device for a single crystal grain, comprising:

[0127] The processor 501 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0128] The memory 502 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 502 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls and executes the Pattern test method for a single crystal grain in the embodiment of this application;

[0129] Input / output interface 503, used to implement information input and output;

[0130] Communication interface 504, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0131] A bus 505 that transmits information between various components of the device (e.g., the processor 501, the memory 502, the input / output interface 503, and the communication interface 504);

[0132] The processor 501 , the memory 502 , the input / output interface 503 and the communication interface 504 are connected to each other in communication within the device via the bus 505 .

[0133] An embodiment of the present application further provides an electronic device, comprising the Pattern testing device for a single crystal die as described above.

[0134] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned Pattern testing method for a single crystal grain is implemented.

[0135] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0136] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0137] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A Pattern testing method for a single crystal grain, characterized in that: include: Determine a first die to be tested from the wafer to be tested, and determine a first capacity to be tested of a single first die; When the first capacity to be tested is greater than a preset capacity threshold, obtaining a current first parameter transmission file; wherein the first parameter transmission file includes: first algorithm selection information and a preset difference value; the first algorithm selection information is binary data of all 0s, and the number of bits of the binary data is the same as the current first total number of candidate pattern test algorithms; According to a first capacity difference between the first capacity to be measured and the preset capacity threshold and the preset difference, the first algorithm selection information is updated to obtain second algorithm selection information and an updated second parameter file including the second algorithm selection information; Run and parse the second parameter transfer file, and determine and start a target pattern test algorithm from a plurality of different candidate pattern test algorithms according to the second algorithm selection information; According to the second parameter transfer file and the target Pattern test algorithm, Pattern test is performed on the first grain to be tested in different regions to complete the single grain test.

2. The Pattern testing method for a single crystal grain according to claim 1, characterized in that: The updating process of the first algorithm selection information according to the first capacity difference between the first capacity to be measured and the preset capacity threshold and the preset difference to obtain the second algorithm selection information and the updated second parameter file including the second algorithm selection information includes: Subtracting the preset capacity threshold from the first capacity to be measured to obtain the first capacity difference; Dividing the first capacity difference by the preset difference to obtain a quotient; After rounding the quotient, the obtained integer is determined as the digit number; Modify the low level value corresponding to the target number of bits in the first algorithm selection information indicated by the number of bits sequence to a high level value to obtain updated second algorithm selection information; Generate an updated second parameter file based on the second algorithm selection information.

3. The Pattern testing method for a single crystal grain according to claim 2, characterized in that: The first parameter transmission file and the second parameter transmission file both include: an algorithm enable signal; The running and parsing of the second parameter file, and determining and starting a target pattern test algorithm from a plurality of different candidate pattern test algorithms according to the second algorithm selection information, includes: Run and parse the second parameter transfer file to obtain the algorithm enable signal; In response to the algorithm enable signal, the preconfigured LK algorithm is enabled, and a plurality of ranked candidate Pattern test algorithms are determined from the LK algorithm; wherein different candidate Pattern test algorithms are obtained based on different configurations of the capacity to be tested; In response to a low level value in the second algorithm selection information, disabling the candidate pattern test algorithm at the corresponding sorting position; In response to the high level value in the second algorithm selection information, the candidate Pattern test algorithm at the corresponding sorting position is determined as the target Pattern test algorithm, and the target Pattern test algorithm is started.

4. The Pattern testing method for a single crystal grain according to claim 3, characterized in that: The method further comprises: In response to an algorithm update instruction, adding or deleting the candidate Pattern test algorithm in the LK algorithm; Determine a second total number of the candidate Pattern test algorithms in the current LK algorithm; Modify the first algorithm selection information according to the second total number to obtain updated first algorithm selection information; wherein the number of bits of the updated first algorithm selection information is determined by the second total number; Generate an updated first parameter file based on the updated first algorithm selection information.

5. The Pattern testing method for a single crystal grain according to claim 1, characterized in that: The second parameter transmission file also includes: test parameters; The step of performing pattern testing on the first die to be tested in different regions according to the second parameter transfer file and the target pattern testing algorithm to complete single-die testing includes: Dividing the first die to be tested into a first test area and a second test area according to a preset capacity threshold; wherein the capacity to be tested in the first test area is equal to the preset capacity threshold; and the capacity to be tested in the second test area is equal to the first capacity difference; Based on a preset conventional test mode, performing a first test process on the first test area; Acquire the test parameters from the second parameter transfer file, and perform a second test process on the second test area according to the target pattern test algorithm and the test parameters; When the first test process and the second test process are completed, the Pattern test is completed.

6. The Pattern testing method for a single crystal grain according to claim 1, characterized in that: The method further comprises: When the first capacity to be tested is less than or equal to a preset capacity threshold, determining a preset conventional Pattern test algorithm; According to the preset conventional Pattern test algorithm, the first die is subjected to Pattern test to complete the single-die test.

7. The Pattern testing method for a single crystal grain according to any one of claims 1 to 6, characterized in that: After performing the Pattern test on the first die and completing the single-die test, the method further includes: Determine a next second die to be tested from the wafer to be tested, and determine a second capacity to be tested of the single second die; When the second capacity to be tested is greater than a preset capacity threshold, obtaining the current first parameter transmission file; wherein the first parameter transmission file includes: first algorithm selection information and a preset difference value; the first algorithm selection information is binary data of all 0s, and the number of bits of the binary data is the same as the current first total number of the candidate Pattern test algorithm; According to a second capacity difference between the second capacity to be measured and the preset capacity threshold and the preset difference, the first algorithm selection information is updated to obtain third algorithm selection information and a third parameter transmission file including an update of the third algorithm selection information; Run and parse the third parameter transfer file, and determine and start a target pattern test algorithm from a plurality of candidate pattern test algorithms according to the third algorithm selection information; According to the third parameter transfer file and the target Pattern test algorithm, the Pattern test is performed on the second die to be tested in different regions to complete the single-die test; The wafer test is terminated until the Pattern test is completed on all the dies to be tested in the wafer to be tested.

8. A pattern testing device for a single crystal grain, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the Pattern testing method for a single grain as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: It comprises the Pattern testing device for a single crystal grain as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the Pattern testing method for a single crystal grain according to any one of claims 1 to 7.

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