An interrupt interval monitoring method and system suitable for a stability control device, a computer device and a storage medium

Abstract

The application discloses a kind of suitable for the interrupt interval monitoring method, system, computer equipment and storage medium of stable control device, comprising: when entering interrupt service procedure, read interrupt time Tint (k), and save interrupt time Tint (k) in annular circulation sequence;Wherein, k=0,1,2,3,…;Calculate the interrupt interval time difference ΔTintN in annular circulation sequence=Tint (k)-Tint (k-N), k≥N;Judge whether it satisfies ΔTintN≤N×Ts-δint1 Or ΔTintN≥N×Ts+δint2, wherein, δint1 And δint2 All represent positive and negative error limit set artificially, if satisfy, then think that error has been produced in interrupt service procedure interval;If not satisfied, then think that interrupt service procedure interval has not produced error;The application is checked in the sense of statistics to interrupt trigger signal by combining the absolute time of RTC chip on mainboard, and the system level monitoring of the interrupt interval of each board card in whole safety and stability control device is realized by the method that mainboard is sent message from board interrupt interval.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power systems and their automation, and particularly relates to an interruption interval monitoring method and system suitable for a stability control device, a computer device, and a storage medium. BACKGROUND

[0002] A power system safety and stability control device (hereinafter referred to as a stability control device) generally adopts a fixed time interval sampling, which is referred to as an interruption. A software sampling calculation algorithm is designed based on the fixed interruption interval sampling. Once the interruption interval is inaccurate, a large deviation will occur in the sampling calculation. In addition, a number of interruption intervals are often used in the software criterion to count time. For example, if the interruption interval is 1 ms, the software criterion considers that 10 ms has elapsed after 10 interruption intervals. Once the interruption interval is inaccurate, the delay counting will be inaccurate, which directly affects the action time of the stability control device. Since the existing processor often uses a CACHE mechanism, the CACHE needs to be reloaded when the interruption signal triggers the interruption service program, so that the interruption service program cannot be executed immediately after the interruption signal triggers. Therefore, the time difference between the moment when the interruption service program is entered and the moment when the interruption service program is entered cannot be used to determine whether the interruption interval is normal. SUMMARY

[0003] The application aims to solve the problem that the existing technology is prone to inaccurate delay counting, which directly affects the action time of the stability control device. The application provides an interruption interval monitoring method and system suitable for a power system safety and stability control device, a computer device, and a storage medium.

[0004] The technical scheme is as follows: An interruption interval monitoring method suitable for a stability control device comprises the following steps:

[0005] When the interruption service program is entered, the interruption time Tint(k) is read and saved in a circular sequence, wherein k=0, 1, 2, 3, ….

[0006] The interruption interval time difference ATintN=Tint(k)-Tint(k-N) in the circular sequence is calculated, wherein k≥N.

[0007] It is determined whether the interruption service program interval has an error or not according to whether ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2 is met, wherein δint1 and δint2 represent the positive and negative error limits set by humans. If yes, it is considered that the interruption service program interval has an error. If no, it is considered that the interruption service program interval has no error.

[0008] Further, the interruption time Tint(k) is provided by an absolute time of a clock chip.

[0009] Further, the interrupt time Tint(k) is a sampling time cached in advance.

[0010] The application further discloses an interrupt interval monitoring method suitable for the stability control device.

[0011] The main board receives a message from the slave board j, records the sending serial number Syn(j, k) and the current time value Tint(k) carried by the message, and sends the message to the master board every fixed time interval Tz(j) by the slave board j. j (k); the fixed time interval Tz(j) is generated by the timing interrupt of the slave board j;

[0012] When the sending serial number carried by the message received by the main board is Syn(j, k+Mj) and is greater than or equal to Mjs, the message time difference is calculated: ΔTz(j)Mj = Tint(k+Mj)-Tint(k); j j (k); wherein, Mj represents that Mj frames are continuously received after the first message of the slave board is received; and Mjs represents a set threshold value;

[0013] The main board judges whether ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2 is satisfied; wherein, δzj1 and δzj2 both represent positive and negative error limits artificially set; if yes, it is considered that an error occurs in the interrupt service program interval of the slave board j; and if not, it is considered that no error occurs in the interrupt service program interval of the slave board j.

[0014] The application further discloses an interrupt interval monitoring system suitable for the stability control device.

[0015] The interrupt interval monitoring main body is used for reading the interrupt time Tint(k) when entering the interrupt service program, and saving the interrupt time Tint(k) in a circular sequence; wherein, k = 0, 1, 2, 3, …; the main board calculates the interrupt interval time difference ΔTintN = Tint(k)-Tint(k-N) in the circular sequence, and k≥N; the main board judges whether ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2 is satisfied; wherein, δint1 and δint2 both represent positive and negative error limits artificially set; if yes, it is considered that an error occurs in the interrupt service program interval; and if not, it is considered that no error occurs in the interrupt service program interval.

[0016] Further, a clock chip is arranged on the interrupt interval monitoring main body; and the interrupt time Tint(k) is provided by the absolute time of the clock chip.

[0017] ​Further, the interrupt time Tint(k) is a pre-cached sampling time.The application further discloses an interrupt interval monitoring system suitable for a stability control device, which comprises a master board and a slave board.

[0018] The slave board is used for sending a message to the master board every time interval Tz(j), and each message has a sending serial number.

[0019] The master board is used for receiving a message from the slave board, recording the sending serial number Syn(j, k) and the current time value Tint(k) of the message. j When the sending serial number of the message is Syn(j, k+Mj) and is greater than or equal to Mjs, the message time difference is calculated: ΔTz(j)Mj=Tint(k+Mj)-Tint(k). j j Mj represents that Mj frames are continuously received after the first message of the slave board is received; Mjs represents a set threshold value; whether ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2 is judged; δzj1 and δzj2 both represent positive and negative error limits artificially set; if yes, it is considered that an error of the interrupt service program interval of the slave board is generated, and if not, it is considered that no error of the interrupt service program interval of the slave board is generated.

[0020] The application further discloses a computer device, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, and the processor implements the steps of the interrupt interval monitoring method disclosed above when the computer program is executed.

[0021] The application further discloses a storage medium, which stores an interrupt interval monitoring program, and the steps of the interrupt interval monitoring method disclosed above are implemented when the interrupt interval monitoring program is executed by at least one processor.

[0022] Advantages: compared with the prior art, the application has the following advantages:

[0023] (1) When the CACHE mechanism of the processor of the power system safety and stability control device causes the time interval of entering the interrupt service program to be inconsistent, the application can detect whether the interrupt interval of the whole device system is accurate, prevents the interrupt interval error caused by the hardware from causing the sampling calculation error, the logic timing error and other uncontrollable factors of the device system, and improves the reliability of the safety and stability control device.

[0024] (2) The application does not need to increase additional hardware, and the interrupt trigger signal is checked in a statistical sense by combining the absolute time of the clock chip;

[0025] (3) The method of the application can also realize the checking of the interrupt trigger signal of the sampling module in a statistical sense to complete the interrupt judgment;

[0026] (4) The method of the application realizes the interrupt judgment of each board card by sending a message to the mainboard from the board at the interrupt interval;

[0027] (5) The method of the application realizes the system-level monitoring of the interrupt interval of each board card of the whole safety and stability control device through the interrupt interval monitoring of the main CPU, DSP, sampling template and each board card. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a sampling interval and timing interval monitoring method block diagram;

[0029] Figure 2 It is an intelligent board card timing interval monitoring method block diagram. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical scheme and advantages of the application clearer, the application of the interrupt interval monitoring method, system, device and storage medium suitable for the stability control device will be further described below in combination with the drawings and examples in the application.

[0031] Example 1:

[0032] The embodiment proposes an interrupt interval monitoring method suitable for a stability control device, which is mainly composed of the following steps for the interrupt judgment of the sampling module:

[0033] After the initialization is completed, a sampling pulse Ttrip is generated every Ts time; once the rising edge of the sampling pulse Ttrip is detected, ADC sampling is performed, and the sampling result is written into the cache AdcBuf, and the time value Tadc of the RTC chip is read and written into AdcBuf at the same time;

[0034] Once the interrupt service program is entered, the time of the sampling point is recorded as Tadc(k), and Tadc(k) is saved in the ring-shaped circular sequence S.

[0035] In each interrupt service program, the time difference between the current sampling time and the sampling time before N interrupts in the ring-shaped circular sequence S is calculated: ΔTadcN=Tadc(k)-Tadc(k-N), k≥N;

[0036] If ΔTadcN≤N×Ts-δadc1 or ΔTadcN≥N×Ts+δadc2, where δadc1 and δadc2 represent positive and negative error limits set artificially, it is considered that the sampling interval has an error, the device is alarmed and locked.

[0037] The embodiment performs statistical checking on the interrupt trigger signal by combining the absolute time of the clock chip.

[0038] Embodiment 2

[0039] The embodiment proposes an interrupt interval monitoring method suitable for a stability control device, which is aimed at interrupt judgment of a main CPU or a DSP, and mainly includes the following steps:

[0040] The main CPU or the DSP reads the time of a high-precision RTC as Tint(k) when entering an interrupt service program, and saves Tint(k) in a circular sequence S.

[0041] The main CPU or the DSP calculates the time difference between the current time when entering the interrupt service program and the time when entering the interrupt service program before N interrupts in the circular sequence S: ΔTintN=Tint(k)-Tint(k-N), k≥N.

[0042] If ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2, where δint1 and δint2 represent positive and negative error limits set artificially, it is considered that the interrupt service program interval has an error, the device is alarmed and locked.

[0043] The embodiment performs statistical checking on the interrupt trigger signal by combining the absolute time of the clock chip.

[0044] Embodiment 3

[0045] The embodiment proposes an interrupt interval monitoring method suitable for a stability control device, which is aimed at interrupt judgment of an intelligent board card j, and mainly includes the following steps:

[0046] The main CPU or the DSP receives a message sent by the intelligent board card j, the message is sent at a fixed time interval Tz(j), and the fixed time interval Tz(j) is generated by a timing interrupt of the intelligent board card; each message carries a sending serial number, denoted as Syn(j, k), and the main CPU or the DSP records the current Syn(j, k) value and the time value Tint(k) of the high-precision RTC after receiving the first message sent by the intelligent board card.

[0047] Considering that the main CPU or DSP receives a possible lost packet, the judgment is set after receiving at least Mjs packets, so that the main CPU or DSP receives the sending sequence number Syn(j, k+Mj) and calculates ΔTz(j)Mj=Tint(k+Mj)-Tint(k) as soon as Syn(j, k+Mj) is greater than or equal to Mjs. If ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2, wherein δzj1 and δzj2 represent positive and negative error limits set artificially, it is considered that an error occurs in the interrupt service program interval of the intelligent board card j, the device is alarmed and locked.

[0048] The embodiment realizes the system-level monitoring of the interrupt interval of each board card in the entire safety and stability control device by combining the absolute time of the clock chip RTC and the method of sending packets from the board interrupt interval to the mainboard.

[0049] Embodiment 4:

[0050] As shown in Figure 1 The embodiment proposes an interrupt interval monitoring system suitable for a stability control device, mainly including a main CPU or DSP, a high-precision RTC, an FPGA, a high-precision timer, a sampling module, and other intelligent board cards. The system adopts time interval sampling, and the time interval is recorded as Ts. The FPGA maintains a high-precision timer, and generates a sampling pulse Ttrip every Ts time. After the initialization is completed, theoretically, the sampling time Tspl(k)=k×Ts every time, k=0, 1, 2, 3, …. The FPGA maintains a sampling module. Once the rising edge of the sampling pulse Ttrip is detected, the sampling module starts the ADC sampling, reads the sampling result of the ADC, and writes the result into the cache AdcBuf. At the same time, the time value Tadc of the RTC is read and written into the AdcBuf, waiting for the main CPU or DSP to read.

[0051] The main CPU or DSP reads the high-precision RTC time as Tint(k) as soon as it enters the interrupt service program, and saves Tint(k) in a ring-shaped circular sequence S. The main CPU or DSP reads the sampling point attached time as Tadc(k) as soon as it enters the interrupt service program, and saves Tadc(k) in the ring-shaped circular sequence S.

[0052] The main CPU or DSP calculates the time difference ATadcN=Tadc(k)-Tadc(k-N) between the current sampling time in the ring sequence S and the sampling time before N interrupts, k≥N; the time difference ATintN=Tint(k)-Tint(k-N) between the current interrupt service program entering time and the interrupt service program entering time before N interrupts, k≥N. If ATadcN≤N×Ts-δadc1 or ATadcN≥N×Ts+δadc2 (δadc1 and δadc2 are positive and negative error limits artificially set), it is considered that the sampling interval has an error, the device is alarmed and locked.

[0053] As shown in Figure 2 For other intelligent board cards of the system (assuming j), a message is designed to be sent to the main CPU or DSP at a constant time interval Tz(j) (the time interval is generated by the timing interrupt of the intelligent board card), each message carries a sending sequence number, denoted as Syn(j, k). After receiving the first message sent by the intelligent board card, the main CPU or DSP records the current Syn(j, k) value and the time value Tint(k) of the high-precision RTC. Considering that the main CPU or DSP may lose messages, it is set that at least after receiving Mjs messages, the judgment is performed. Therefore, once the sending sequence number Syn(j, k+Mj) received by the main CPU or DSP is greater than or equal to Mjs, ATz(j)Mj=Tint(k+Mj)-Tint(k) is calculated. If ATz(j)Mj≤Mj×Tz(j)-δzj1 or ATz(j)Mj≥Mj×Tz(j)+δzj2 (δzj1 and δzj2 are positive and negative error limits artificially set), it is considered that the interrupt service program interval of the other intelligent board card j in the device has an error, the device is alarmed and locked.

[0054] The embodiment realizes the system-level monitoring of the interrupt interval of each board card in the safety and stability control device by combining the absolute time of the RTC chip to statistically check the interrupt trigger signal and by sending messages from the board timing interrupt to the main board.

[0055] Embodiment 5

[0056] On the basis of embodiment 4, the embodiment proposes an interrupt interval monitoring system suitable for the stability control device, mainly including:

[0057] Suppose the sampling and timing interval are both 0.833 ms (Ts), and the external oscillator is input into the FPGA as a clock source, a 1200 Hz square wave signal is generated via the high-precision timer inside the FPGA and output to the sampling module and the timing interrupt pin of the CPU / DSP.

[0058] The sampling module generates a sampling trigger pulse of the same frequency according to the square wave signal, triggers the ADC conversion, and then reads the ADC conversion result and writes the result and the current RTC time value Tadc into the buffer AdcBuf.

[0059] After the CPU / DSP enters the timing interrupt function, the ADC conversion result and its corresponding RTC time value Tadc(k) are read, and the RTC time is read and recorded as Tint(k) using a loop sequence.

[0060] When the recorded data is greater than N points (usually N is 1200 points, i.e. 1 s), the time difference of 1200 interrupts is calculated in the timing interrupt. For the sampling interval, the time difference is ΔTadc=Tadc(k)-Tadc(k-1200), and for the timing interval, the time difference is ΔTint=Tint(k)-Tint(k-1200). In theory, ΔTadc and ΔTint should both be 1 s. Considering the existence of errors, the confidence interval can be set to 1 s±1 ms. When the time difference is less than 1 ms from 1 s, it is considered that the sampling interval and the timing interval are normal, otherwise, it is abnormal, the device is locked and an alarm is given.

[0061] Embodiment 6:

[0062] On the basis of embodiment 4, this embodiment proposes an interrupt interval monitoring system suitable for a stability control device. Taking a certain intelligent board card as an example, the timing interval of the intelligent board card is agreed to be Tz=1 ms, and a frame of message is sent to the CPU / DSP host board card every interval Tz, and the message sequence number is Syn(k). After the host receives the message, the message sequence number Syn(k) and the RTC time value Tint(k) when the message is received are recorded in the buffer. When the number of messages is greater than 1000, the time difference ΔTint=Tint(k+1000)-Tint(k) of the reception of the previous 1000 messages can be calculated in a loop. In theory, ΔTint should be 1 s. Considering the existence of errors, the confidence interval can be set to 1 s±1 ms. When the error of ΔTint from 1 s is within 1 ms, it is considered that the timing interval of the intelligent board card is normal, otherwise, it is abnormal, the device is locked and an alarm is given.

[0063] Embodiment 7:

[0064] The embodiment discloses a computer device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the steps disclosed in any one of the above embodiments when executing the computer program.

[0065] Embodiment 8:

[0066] The embodiment discloses a computer readable storage medium, which stores a computer program, and the computer program implements the steps disclosed in any one of the above embodiments when executed by a processor.

[0067] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments of the method. In the embodiments provided in the present application, any reference to memory, storage, database or other medium can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0068] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0069] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.

Claims

1. An interrupt interval monitoring method for a stability control device, characterized by: The method comprises the following steps: When entering the interrupt service procedure, the interrupt time Tint(k) is read and saved in a circular sequence; wherein k=0, 1, 2, 3, …; The interrupt interval time difference ΔTintN=Tint(k)-Tint(k-N) in the circular sequence is calculated, k≥N; It is judged whether ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2 is satisfied, wherein δint1 and δint2 represent positive and negative error limits set artificially, if satisfied, it is considered that an error is generated in the interrupt service procedure interval; if not satisfied, it is considered that no error is generated in the interrupt service procedure interval.

2. The method for monitoring the interruption interval of the stability control device according to claim 1, characterized in that: The interrupt time Tint(k) is provided by the absolute time of a clock chip.

3. The method for monitoring the interruption interval of the stability control device according to claim 1, characterized in that: The interrupt time Tint(k) is a sampling time cached in advance.

4. An interrupt interval monitoring method for a stability control device, characterized by: The method comprises the following steps: The main board receives a packet from the slave board j, records the sending sequence number Syn(j, k) and the current time value Tint carried by the packet j (k); each packet is sent by the slave board j every fixed time interval Tz(j); the fixed time interval Tz(j) is generated by the timing interrupt of the slave board j; When the mainboard receives a message with a sending serial number of Syn(j, k+Mj) greater than or equal to Mjs, the message time difference is calculated: ΔTz(j)Mj=Tint j (k+Mj)-Tint j (k); wherein Mj represents that Mj frames are received after the first message from the board is received; and Mjs represents a set threshold value. The mainboard judges whether ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2 is satisfied; wherein δzj1 and δzj2 represent positive and negative error limits set artificially; if satisfied, it is considered that an error is generated in the interrupt service procedure interval of the slave board j, if not satisfied, it is considered that no error is generated in the interrupt service procedure interval of the slave board j.

5. An interruption interval monitoring system for a stability control device, comprising: The interrupt interval monitoring subject is comprised; The interrupt interval monitoring subject is used for reading the interrupt time Tint(k) when entering the interrupt service procedure, and saving the interrupt time Tint(k) in a circular sequence; wherein k=0, 1, 2, 3, …; the mainboard calculates the interrupt interval time difference ΔTintN=Tint(k)-Tint(k-N) in the circular sequence, k≥N; the mainboard judges whether ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2 is satisfied, wherein δint1 and δint2 represent positive and negative error limits set artificially, if satisfied, it is considered that an error is generated in the interrupt service procedure interval; if not satisfied, it is considered that no error is generated in the interrupt service procedure interval.

6. The interrupt interval monitoring system for a stability control device according to claim 5, characterized by: A clock chip is arranged on the interrupt interval monitoring subject; the interrupt time Tint(k) is provided by the absolute time of the clock chip.

7. The interrupt interval monitoring system for a stability control device according to claim 5, characterized by: The interrupt time Tint(k) is a sampling time cached in advance.

8. An interruption interval monitoring system for a stability control device, comprising: The method comprises: The mainboard and the slave board; The slave board is used for sending a message to the mainboard every time interval Tz(j), and each message is provided with a sending serial number; the time interval Tz(j) is generated by the timing interrupt of the slave board; The main board is used for receiving a packet from the slave board, recording the sending serial number Syn(j, k) and the current time value Tint carried by the packet j (k); when the sending serial number carried by the packet is Syn(j, k+Mj) and is greater than or equal to Mjs, calculating the packet time difference: ΔTz(j)Mj=Tint j (k+Mj)-Tint j (k); wherein, Mj represents that Mj frames are continuously received after the first packet from the slave board is received; Mjs represents a set threshold; judging whether ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2 is satisfied; wherein, δzj1 and δzj2 both represent positive and negative error limits artificially set; if yes, it is considered that an error is generated in the interrupt service program interval of the slave board; if not, it is considered that no error is generated in the interrupt service program interval of the slave board.

9. A computer device, comprising: The computer program stored in the memory and executable on the processor is used for realizing the steps of the interrupt interval monitoring method for the stable control device according to any one of claims 1 to 3, or the interrupt interval monitoring method for the stable control device according to claim 4.

10. A storage medium, characterized by The storage medium stores an interruption interval monitoring program, and the interruption interval monitoring program, when executed by the at least one processor, implements the steps of the method for monitoring the interruption interval of the stability control device according to any one of claims 1 to 3 or claim 4.

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