A circuit for enhancing loop stability and a low-dropout linear regulator chip

Abstract

The present invention discloses a circuit for enhancing loop stability, which relates to the technical field of integrated circuits, including PMOS tubes PM1, PMOS tubes PM2, PMOS tubes PM3, PMOS tubes PM4, PMOS tubes PM5, NMOS tubes NM1, NMOS tubes NM2, NMOS tubes NM3, NMOS tubes NM4, M NMOS tubes connected in series, including NMOS tubes NM5, NMOS tubes NM6, ..., NMOS tubes NM M+4 , N series-connected NMOS tubes, including NMOS tube NM M+5 、NMOS tube NM M+6 、……、NMOS tube M M+N+4 , NMOS consumption although NMOS1, resistor R1, resistor R2, capacitor C1, current source I Q The present invention also discloses a low-dropout linear regulator chip, which is provided with the aforementioned loop stability enhancement circuit. The present invention increases the phase margin and ensures stability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a circuit for enhancing loop stability and a low-dropout linear regulator chip. Background Art

[0002] DC / DC power converters have captured a significant share of the power supply market and are widely used due to their high conversion efficiency. However, DC / DC power converters exhibit significant ripple. Therefore, low-dropout (LDO) linear regulators (LDRs) play a significant role in applications requiring low ripple. LDOs offer low power consumption, simple structure, small chip area, low noise, and high power supply rejection ratio (PSRR). However, frequency compensation is a design challenge for LDOs.

[0003] The traditional frequency compensation method is Miller compensation, in which a capacitor C is connected across the input and output of the second-stage operational amplifier A2. C , which is equivalent to placing a capacitor with a value of (1+A2)C at the input of A2 C The pole moves toward the origin, that is, the low-frequency direction, and the output pole moves away from the origin, achieving pole separation. At this time, a zero point is introduced. By adjusting the resistor R A The size of the zero point is adjusted to the appropriate position to compensate the second pole and realize loop compensation. However, when the load current fluctuates in a large range, loop oscillation may occur.

[0004] Therefore, those skilled in the art are committed to developing a circuit for enhancing loop stability and a low voltage dropout linear regulator chip. Summary of the Invention

[0005] In view of the above-mentioned defects in the prior art, the technical problem to be solved by the present invention is how to enhance loop stability.

[0006] Research has found that when the load current fluctuates greatly, the position of the pole changes. If the size of the zero-adjusting resistor can follow the change of the pole, when the load current becomes larger, the position of the zero point will also move to the high frequency, and the position of this zero point and the output pole will not be much different. This zero point can compensate for the additional phase shift caused by the output pole.

[0007] In one embodiment of the present invention, a loop stability enhancement circuit is provided, comprising a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, an NMOS transistor NM1, an NMOS transistor NM2, an NMOS transistor NM3, an NMOS transistor NM4, and M NMOS transistors connected in series, including an NMOS transistor NM5, an NMOS transistor NM6, ..., an NMOS transistor NM7, an NMOS transistor NM8, an NMOS transistor NM9, an NMOS transistor NM10, an NMOS transistor NM11, an NMOS transistor NM12, an NMOS transistor NM13, an NMOS transistor NM14, an NMOS transistor NM15, an NMOS transistor NM16, an NMOS transistor NM17, an NMOS transistor NM18, an NMOS transistor NM19, an NMOS transistor NM20, an NMOS transistor NM21 M+4 , N series-connected NMOS tubes, including NMOS tube NMM+5 、NMOS tube NM M+6 、……、NMOS tube M M+N+4 , NMOS consumption although NMOS1, resistor R1, resistor R2, capacitor C1, current source I Q ;

[0008] The sources of the PMOS transistors PM1, PM2, PM3, PM4, and PM5 are connected together to VDD, and the gates of the PMOS transistors PM1, PM2, and PM3 are connected to the drain of the PMOS transistor PM1 and the current source I Q One end of the current source I Q The other end of the PMOS transistor PM2 is grounded, the drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM2, the gate, the gates of the NMOS transistors connected in series, and the gate of the NMOS transistor NMOS1. The source of the NMOS transistor NM2 is grounded, the drain of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM5, one end of the capacitor C1, the gates of the NMOS transistors NM1, NMOS transistor NM3, and NMOS transistor NM4. The gates of the M NMOS transistors connected in series are connected to the resistor R1 and one end of the resistor R2. The source of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM6. The source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7. And so on. M+3 The source of the NMOS tube NM M+4 The drain connection of NMOS tube NM M+4 The source of the capacitor C1 is grounded, and the other end of the capacitor C1 is connected to the NMOS tube NM M+5 , the drains of NMOS tube NM3 are connected together, and the drains of NMOS tube NM M+5 The source of the NMOS tube NM M+6 The drain connection of NMOS tube NM M+6 The source of the NMOS tube NM M+7 The drain of NMOS tube M M+N+3 The source of NMOS tube M M+N+4 The drain connection of NMOS tube M M+N+4 The source of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM4, the source of the NMOS transistor NM4 is grounded, the gate and drain of the PMOS transistor PM4 are connected to the gate of the PMOS transistor PM5, and the drain of the NMOS transistor NMOS1 is connected together, the source of the NMOS transistor NMOS1 is connected to the drain of the NMOS transistor NM1, the source of the NMOS transistor NM1 is grounded, the drain of the PMOS transistor PM5 is connected to the other end of the resistor R1, and the other end of the resistor R2 is grounded;

[0009] N series-connected NMOS transistors operate in a linear region. NMOS transistors NM3 and NMOS transistor NM4 operate in a linear region. The gate voltage of the N series-connected NMOS transistors does not change with changes in the load current. When the load current is small, a zero point is provided to offset the influence of the pole. When the load current increases, the gate voltage of NMOS transistors NM3 and NMOS transistor NM4 increases accordingly. The equivalent resistance of the N series-connected NMOS transistors is connected in parallel with the equivalent resistance of NMOS transistors NM3 and NMOS transistor NM4. The position of the zero point moves toward a high frequency accordingly. Moreover, the position of the zero point and the output pole are not much different. The zero point can compensate for the additional phase shift caused by the output pole.

[0010] Optionally, in the loop stability enhancement circuit of any of the foregoing embodiments, M is greater than or equal to 8 and less than or equal to 20.

[0011] Preferably, in the loop stability enhancement circuit of the above embodiment, M is equal to 12.

[0012] Optionally, in the loop stability enhancement circuit of any of the above embodiments, a channel length of the M series-connected NMOS transistors is greater than or equal to 10 um and less than or equal to 20 um.

[0013] Preferably, in the loop stability enhancement circuit of the above embodiment, the channel length of the M series-connected NMOS transistors is equal to 15 um.

[0014] Furthermore, in the loop stability enhancement circuit of the above embodiment, the width and length of the channels of the M series-connected NMOS transistors are equal.

[0015] Optionally, in the loop stability enhancement circuit of any of the foregoing embodiments, N is greater than or equal to 6 and less than or equal to 12.

[0016] Optionally, in the loop stability enhancement circuit of any of the above embodiments, a channel length of the N series-connected NMOS transistors is greater than or equal to 10 um and less than or equal to 20 um.

[0017] Preferably, in the loop stability enhancement circuit of the above embodiment, the channel length of the N series-connected NMOS transistors is equal to 18 um.

[0018] Furthermore, in the loop stability enhancement circuit of the above embodiment, the width and length of the channels of the N series-connected NMOS transistors are equal.

[0019] Preferably, in the loop stability enhancement circuit of the above embodiment, N is equal to 8.

[0020] Optionally, in the loop stability enhancement circuit of any of the above embodiments, the channel lengths of the NMOS transistors NM3 and NMOS transistors NM4 are greater than or equal to 15 um and less than or equal to 20 um.

[0021] Preferably, in the loop stability enhancement circuit of the above embodiment, the channel length of the NMOS transistor NM3 and the NMOS transistor NM4 is equal to 18 μm.

[0022] Optionally, in the loop stability enhancement circuit of any of the above embodiments, the value of the capacitor C1 is greater than or equal to 600 fF and less than or equal to 800 fF.

[0023] Preferably, in the loop stability enhancement circuit of the above embodiment, the value of the capacitor C1 is equal to 700 fF.

[0024] Based on the above embodiment, in another embodiment of the present invention, a low voltage dropout linear regulator chip is provided, which is provided with the loop stability enhancement circuit in the above embodiment.

[0025] The present invention improves the existing technology by using N series-connected NMOS transistors operating in the linear region to replace resistors, and connecting two NMOS transistors NM3 and NM4 operating in the linear region in parallel. The gate voltages of the NMOS transistors NM3 and NM4 are voltages that follow the output load current transformation, and the zero points generated by their equivalent resistances follow the load current frequency compensation. When the load current changes, the positions of the zero points and the poles change, thereby increasing the phase margin and ensuring stability.

[0026] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic structural diagram illustrating a conventional frequency compensation circuit according to an exemplary embodiment;

[0028] Figure 2 is a schematic structural diagram illustrating a circuit for enhancing loop stability according to an exemplary embodiment;

[0029] Figure 3 FIG. 1 is a schematic diagram illustrating the structure of a low-dropout linear regulator chip according to an exemplary embodiment. DETAILED DESCRIPTION

[0030] The following describes several preferred embodiments of the present invention with reference to the accompanying drawings to make its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0031] In the drawings, components with identical structures are denoted by the same reference numerals, and components with similar structures or functions are denoted by similar reference numerals. The size and thickness of each component shown in the drawings are arbitrary and are not limited by the present invention. To enhance clarity, the thickness of components in some places in the drawings is schematically exaggerated.

[0032] The traditional frequency compensation circuit is Miller compensation, such as Figure 1 As shown, a capacitor C is connected across the input and output of the second stage operational amplifier A2. C , which is equivalent to placing a capacitor with a value of (1+A2)C at the input of A2 C The pole moves toward the origin, that is, the low-frequency direction, and the output pole moves away from the origin, achieving pole separation. At this time, a zero point is introduced. By adjusting the resistor R A The zero point is adjusted to the appropriate position to compensate for the second pole and achieve loop compensation. However, when the load current fluctuates widely, loop oscillation may occur.

[0033] This embodiment designs a circuit to enhance loop stability, such as Figure 2 As shown, it includes: PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, M NMOS tubes connected in series, including NMOS tube NM5, NMOS tube NM6, ..., NMOS tube NM M+4 , N series-connected NMOS tubes, including NMOS tube NM M+5 、NMOS tube NM M+6 、……、NMOS tube M M+N+4 , NMOS consumption although NMOS1, resistor R1, resistor R2, capacitor C1, current source I Q ; Wherein M is equal to 12, the channel length of the 12 NMOS tubes connected in series is equal to 15um, and the width and length of the channel of the 12 NMOS tubes connected in series are equal; N is equal to 8, the channel length of the 8 NMOS tubes connected in series is equal to 18um, and the width and length of the channel of the 8 NMOS tubes connected in series are equal; the value of capacitor C1 is equal to 700fF.

[0034] The sources of the PMOS transistors PM1, PM2, PM3, PM4, and PM5 are connected together to VDD, and the gates of the PMOS transistors PM1, PM2, and PM3 are connected to the drain of the PMOS transistor PM1 and the current source I Q One end of the current source I QThe other end of the PMOS transistor is grounded, the drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM2, the gate, the gates of the eight NMOS transistors connected in series, and the gate of the NMOS transistor NMOS1. The source of the NMOS transistor NM2 is grounded, the drain of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM5, one end of the capacitor C1, the gates of the NMOS transistors NM1, NMOS transistor NM3, and NMOS transistor NM4. The gates of the twelve NMOS transistors connected in series are connected to the resistors R1 and R2. The source of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM6. The source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7. And so on. 15 The source of the NMOS tube NM 16 The drain connection of NMOS tube NM 16 The source of the capacitor C1 is grounded, and the other end of the capacitor C1 is connected to the NMOS tube NM 17 , the drains of NMOS tube NM3 are connected together, and the drains of NMOS tube NM 17 The source of the NMOS tube NM 18 The drain connection of NMOS tube NM 18 The source of the NMOS tube NM 19 The drain of NMOS tube M M23 The source of NMOS tube M 24 The drain of the NMOS tube M24 is connected, the source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM4, the source of the NMOS tube NM4 is grounded, the gate and drain of the PMOS tube PM4 are connected to the gate of the PMOS tube PM5, and the drain of the NMOS tube NMOS1 is connected together, the source of the NMOS tube NMOS1 is connected to the drain of the NMOS tube NM1, the source of the NMOS tube NM1 is grounded, the drain of the PMOS tube PM5 is connected to the other end of the resistor R1, and the other end of the resistor R2 is grounded.

[0035] To verify the practical effect of this embodiment, eight NMOS transistors connected in series are operated in a linear region, and NMOS transistors NM3 and NMOS transistors NM4 are operated in a linear region. The gate voltage of the eight NMOS transistors connected in series does not change with changes in the load current. When the load current is small, a zero point is provided to offset the influence of the pole. When the load current increases, the gate voltage of NMOS transistors NM3 and NM4 increases accordingly. The equivalent resistance of the eight NMOS transistors connected in series is connected in parallel with the equivalent resistance of NMOS transistors NM3 and NM4, and the position of the zero point moves toward a high frequency. The position of the zero point is also close to that of the output pole. The zero point can compensate for the additional phase shift caused by the output pole.

[0036] When the load current changes from 1mA to 300mA, the position of the pole changes. At this time, the value of the equivalent zero adjustment resistor of NMOS tube NM3 and NMOS tube NM4 also changes accordingly. When the load current gradually increases, the position of the zero point also moves to the high frequency, and the position of this zero point is not much different from the position of the output pole. This zero point can compensate for the additional phase shift caused by the output pole, ensuring loop stability and preventing oscillation.

[0037] Based on the above embodiment, in another embodiment of the present invention, Figure 3 As shown, a low voltage dropout linear regulator chip is provided, and the low voltage dropout linear regulator chip is provided with the loop stability enhancement circuit in the above embodiment.

[0038] The above describes in detail the preferred embodiments of the present invention. It should be understood that those skilled in the art can make numerous modifications and variations based on the concepts of the present invention without inventive effort. Therefore, any technical solutions that can be derived by those skilled in the art through logical analysis, reasoning, or limited experimentation based on the concepts of the present invention and the prior art should be within the scope of protection defined by the claims.

Claims

1. A circuit for enhancing loop stability, characterized in that: include: PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, M NMOS tubes connected in series, including NMOS tube NM5, NMOS tube NM6, ..., NMOS tube NM M+4 , N series-connected NMOS tubes, including NMOS tube NM M+5 、NMOS tube NM M+6 、……、NMOS tube M M+N+4 , NMOS consumption although NMOS1, resistor R1, resistor R2, capacitor C1, current source I Q ; The sources of the PMOS transistors PM1, PM2, PM3, PM4, and PM5 are connected together to VDD, and the gates of the PMOS transistors PM1, PM2, and PM3 are connected to the drain of the PMOS transistor PM1 and the current source I Q One end of the current source I Q The other end of the NMOS transistor is grounded, the drain of the PMOS transistor PM2 is connected to the drain and gate of the NMOS transistor NM2, the gates of the NMOS transistors connected in series, and the gate of the NMOS transistor NMOS1; the source of the NMOS transistor NM2 is grounded; the drain of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM5, one end of the capacitor C1, the gates of the NMOS transistor NM1, the NMOS transistor NM3, and the NMOS transistor NM4; the gates of the M NMOS transistors connected in series are connected to one end of the resistor R1 and the resistor R2; the source of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM6; the source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7; and so on. M+3 The source of the NMOS tube NM M+4 The drain of the NMOS tube NM M+4 The source of the capacitor C1 is grounded, and the other end of the capacitor C1 is connected to the NMOS tube NM M+5 , the drains of the NMOS tube NM3 are connected together, and the NMOS tube NM M+5 The source of the NMOS tube NM M+6 The drain of the NMOS tube NM M+6 The source of the NMOS tube NM M+7 The drain of the NMOS tube M M+N+3 The source of the NMOS tube M M+N+4 The drain of the NMOS tube M M+N+4 The source of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM4, the source of the NMOS transistor NM4 is grounded, the gate and drain of the PMOS transistor PM4 are connected to the gate of the PMOS transistor PM5, and the drain of the NMOS power transistor NMOS1 are connected together, the source of the NMOS power transistor NMOS1 is connected to the drain of the NMOS transistor NM1, the source of the NMOS transistor NM1 is grounded, the drain of the PMOS transistor PM5 is connected to the other end of the resistor R1, and the other end of the resistor R2 is grounded.

2. The loop stability enhancement circuit according to claim 1, wherein: The M is greater than or equal to 8 and less than or equal to 20.

3. The loop stability enhancement circuit according to claim 2, wherein: The channel length of the M series-connected NMOS tubes is greater than or equal to 10 um and less than or equal to 20 um.

4. The loop stability enhancement circuit according to claim 3, wherein: The width and length of the channels of the M series-connected NMOS transistors are equal.

5. The loop stability enhancement circuit according to claim 1, wherein: The N is greater than or equal to 6 and less than or equal to 12.

6. The loop stability enhancement circuit according to claim 5, wherein: The channel length of the N series-connected NMOS tubes is greater than or equal to 10 μm and less than or equal to 20 μm.

7. The loop stability enhancement circuit according to claim 5, wherein: The width and length of the channels of the N series-connected NMOS transistors are equal.

8. The loop stability enhancement circuit according to claim 1, wherein: The channel lengths of the NMOS transistor NM3 and the NMOS transistor NM4 are greater than or equal to 15 μm and less than or equal to 20 μm.

9. The loop stability enhancement circuit according to claim 1, wherein: The value of the capacitor C1 is greater than or equal to 600fF and less than or equal to 800fF.

10. A low voltage dropout linear regulator chip, characterized in that: Provide a loop stability enhancement circuit as described in any one of claims 1-9.

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