Clock control module, storage device and data sampling method thereof, and storage medium

Abstract

The invention discloses a clock control module, a storage device, a data sampling method of the storage device and a storage medium. The storage device comprises a memory and a controller, the controller comprises a clock control module, the clock control module is connected with the memory, the clock control module is configured to generate a sampling clock according to a system clock, and the sampling clock is used for sampling output data of the memory to obtain sampling data, adjusting the generated sampling clock according to the matching condition of the sampling data and the output data until the sampling data is matched with the output data; and the main control module is connected with the memory and the clock control module, and the main control module is configured to sample the output data of the memory by using the adjusted sampling clock. By means of the mode, it can be ensured that the Flash controller accurately samples the data, and therefore the performance of the Flash controller is improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a clock control module, a storage device and a data sampling method thereof, and a storage medium. Background Art

[0002] Flash memory is a form of electronically erasable programmable read-only memory that allows the memory to be erased or written multiple times during operation.

[0003] Generally, when sampling the data outputted by the Flash memory using a clock, the correct data may not be sampled due to the difference between the sampling clock and the clock received inside the Flash memory, or the difference between different sampling clocks, or the difference in the frequency of the sampling clock. Therefore, how to ensure the accurate sampling of the data outputted by the Flash memory has become an urgent problem to be solved. Summary of the invention

[0004] To solve the above problems, the present application provides a clock control module, a storage device and a data sampling method thereof, and a storage medium, which can ensure that the Flash controller accurately samples the data, thereby improving the performance of the Flash controller.

[0005] The first technical solution adopted in the present application is: providing a clock control module for adjusting the sampling clock of the storage device; the clock control module is configured to match the sampling data and output data of the storage device and determine the adjustment step of the sampling clock; wherein the sampling data is obtained by sampling the output data of the storage device according to the sampling clock.

[0006] Among them, the clock control module includes: a training unit, which is configured to determine sampling data and output data; and is used to match the sampling data and the output data, and determine the adjustment step of the sampling clock according to the matching result, so that the sampling data obtained by sampling according to the sampling clock adjusted by the adjustment step matches the output data.

[0007] The training unit is configured to determine the matching result between the sampled data and the output data according to whether the values ​​of corresponding preset bits of the sampled data and the output data match.

[0008] In which, the training unit is configured to perform the following operations: in response to the sampling data obtained by sampling in the current cycle period and the output data matching, determine the adjusted sampling clock; or in response to the sampling data obtained by sampling in the current cycle period and the output data not matching, use the adjusted delay step to perform sampling in the next cycle period until the sampling data and the output data match.

[0009] The second technical solution adopted in the present application is: providing a storage device, including a memory and a controller, wherein the controller is connected to the memory, and the controller includes: a clock control module, connected to the memory, the clock control module is configured to match the sampling data and output data of the storage device, and determine the adjustment step of the sampling clock; wherein the sampling data is obtained by sampling the output data of the storage device according to the sampling clock; a main control module, connected to the memory and the clock control module, and the main control module is configured to use the adjusted sampling clock to sample the output data of the memory.

[0010] Among them, the clock control module includes: a training unit, which is configured to determine sampling data and output data; and is used to match the sampling data and the output data, and determine the adjustment step of the sampling clock according to the matching degree, so that the sampling data obtained by sampling according to the sampling clock adjusted by the adjustment step matches the output data.

[0011] The training unit is configured to determine the matching degree between the sampled data and the output data according to whether the values ​​of corresponding preset bits of the sampled data and the output data match.

[0012] In which, the training unit is configured to perform the following operations: in response to the sampling data obtained by sampling in the current cycle period and the output data matching, determine the adjusted sampling clock; or in response to the sampling data obtained by sampling in the current cycle period and the output data not matching, use the adjusted delay step to perform sampling in the next cycle period until the sampling data and the output data match.

[0013] The third technical solution adopted in the present application is: providing a method for sampling data from a storage device, wherein the storage device includes a memory and a controller, and the method includes: the controller matches the sampled data and output data of the storage device; according to the matching result of the sampled data and the output data, adjusting the sampling clock to match the sampled data and the output data; sampling the output data of the memory using the adjusted sampling clock; wherein the sampled data is obtained by sampling the output data of the storage device according to the sampling clock.

[0014] Wherein, according to the matching result of the sampled data and the output data, the sampling clock is adjusted to make the sampled data and the output data match, including: in response to the sampled data sampled in the current cycle period matching the output data, determining the adjusted sampling clock; or in response to the sampled data sampled in the current cycle period not matching the output data, sampling in the next cycle period using the adjusted delay step until the sampled data and the output data match.

[0015] In which, in response to the sampling data obtained by sampling in the current cycle period matching the output data, determining the adjusted sampling clock includes: in response to the sampling data and the output data matching for the first time, determining the delay step of the current cycle period as the minimum delay step; in response to the sampling data and the output data matching for the last time, determining the delay step of the current cycle period as the maximum delay step; and determining the adjusted sampling clock according to the minimum delay step and the maximum delay step.

[0016] The fourth technical solution adopted in the present application is: to provide a computer-readable storage medium, in which program data is stored, and when the program data is executed, it is used to implement the above-mentioned data sampling method.

[0017] The present application provides a clock control module, a storage device and a data sampling method thereof, and a storage medium. The storage device includes a memory and a controller, and the controller includes: a clock control module, connected to the memory, the clock control module is configured to generate a sampling clock according to the system clock, use the sampling clock to sample the output data of the memory to obtain the sampling data, and adjust the generated sampling clock according to the matching of the sampling data and the output data until the sampling data and the output data match; a main control module, connected to the memory and the clock control module, the main control module is configured to sample the output data of the memory using the adjusted sampling clock. Through the above method, since the controller takes into account the matching of the sampling data and the output data when adjusting the phase of the sampling clock, sampling the output data of the memory using the adjusted sampling clock can ensure that the Flash controller can accurately sample the data; in addition, in the adjustment process of the sampling clock, a cyclic adjustment (self-training) method is adopted to realize the automation and efficiency of the sampling clock adjustment, thereby improving the performance of the Flash controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0019] Figure 1 is a structural schematic diagram of an embodiment of a storage device provided by the present application;

[0020] Figure 2 It is a timing diagram of sampling Flash output data using a clock signal in an embodiment provided by the present application;

[0021] Figure 3is a schematic diagram of the structure of a controller in an embodiment provided by the present application;

[0022] Figure 4 It is a flow chart of an embodiment of a data sampling method provided by the present application;

[0023] Figure 5 This is a schematic diagram of the communication data waveform based on the SPI interface provided by the present application;

[0024] Figure 6 This is a flow chart of another embodiment of the data sampling method provided by the present application.

[0025] Figure 7 is a timing diagram of the sampling clock provided by the present application;

[0026] Figure 8 It is a structural schematic diagram of an embodiment of a computer-readable storage medium provided by the present application;

[0027] Fig. 9 It is a structural diagram of an embodiment of a clock control module provided in the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0029] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0030] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of an embodiment of a storage device provided in the present application. The storage device 100 includes a memory 10 and a controller 20.

[0032] Optionally, the storage device 100 can be integrated into various memory cards such as personal computer memory card international association (PCMCIA or PC), compact Flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC), secure digital memory card (SD), universal Flash storage (UFS) and solid state drives (SSD).

[0033] The controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0034] Alternatively, the controller 20 is configured for operation in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablet computers, laptop computers, and enterprise storage arrays.

[0035] Alternatively, the controller 20 is configured to manage the data stored in the memory 10 and communicate with an external device (e.g., a host) according to a specific communication protocol. The communication protocol includes at least one of a USB protocol, a SPI (Serial Peripheral Interface) protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small drive interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a firewire protocol.

[0036] The controller 20 may also be configured to control the operation of the memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 may also be configured to process error correction codes regarding data read from or written to the memory 10. The controller 20 may also perform any other suitable functions, such as formatting the memory 10.

[0037] It can be understood that in one embodiment, the memory 10 in the storage device 100 is a Flash chip. Flash chips can be divided into BPI (Boot Parallel Interface) and SPI (Serial Peripheral Interface). In this article, SPI Flash is used as an example for explanation. In the related art, the Flash chip is generally operated through the SPI interface. This Flash chip using the SPI interface is generally called SPI Flash. Due to the low cost, high reliability and easy integration of SPI Flash, more and more SoC (System on Chip) chips choose to package SPI Flash with SoC together, and the important bridge for communication between SoC and SPI Flash is the controller 20, that is, the Flash controller.

[0038] Currently, the maximum clock frequency supported by SPI Flash is generally around 100MHz. In the process of designing the interaction logic between the Flash controller and SPI Flash, an important consideration is to ensure that the Flash controller can communicate normally with the SPI Flash under the fastest possible Flash clock. However, simply increasing the clock frequency output to the SPI Flash is unreliable. This is because the transmission delay caused by the connection wires of the SoC and SPI Flash, as two chips sealed together, will be so large that it cannot be easily ignored. When the clock frequency of the SPI Flash is increased, if the Flash controller still uses the default sampling time point, it may not be able to sample the correct data.

[0039] In one embodiment, if Figure 2 As shown, Figure 2 This is a timing diagram of sampling Flash output data using a clock signal in an embodiment provided by the present application, wherein the input clock clk1 is a clock signal waveform diagram input by the Flash controller to the SPI Flash, the internal clock clk2 is a clock signal waveform diagram received inside the SPI Flash, and the output data data is a SPI Flash output signal waveform diagram.

[0040] In one embodiment, the frequencies of the input clock clk1 and the internal clock clk2 are equal, and the internal clock clk2 is delayed compared to the input clock clk1. When the Flash controller samples the output data data of the SPI Flash, an edge detection technique is generally used to sample data at the rising edge or falling edge of the input clock clk1. Therefore, the input clock clk1 here can also be called a sampling clock.

[0041] In one embodiment, the SPI Flash generates output data data after a first time interval (CLQX) of the falling edge of the internal clock clk2, and reaches stability after a second time interval (CLQV) of the falling edge. The Flash controller samples the output data data of the SPI Flash at the rising edge of the input clock (also called sampling clock) clk1; since the internal clock clk2 of the SPI Flash is delayed compared to the input clock clk1, and the time (CLQV) from the falling edge of the internal clock clk2 corresponding to different SPI Flashes to the valid output data data may be different, which may result in failure to sample the correct output data data.

[0042] Specifically, the SPI Flash generates output data data at the falling edge of the internal clock clk2. After a period of time CLQV, the output data data is stable. After the next falling edge of the internal clock clk2 arrives, the output data data starts to flip after a period of time CLQX. Then, for a clock cycle Tclk of the internal clock clk2, the unstable time window of the output data data is CLQV-CLQX, and the stable time window of the output data data is Tclk-(CLQV-CLQX). Further, the Flash controller receives the output data data, and then samples the output data data at the rising edge of the input clock clk1. If the sampling point (i.e., the rising edge of the input clock clk1) falls during the unstable period of the output data data, the sampled data obtained by sampling may be incorrect (inconsistent with the output data data). The flipping of the output data data refers to: the flipping of the bit in the bit width of the output data data; wherein the bit width of the output data data may include multiple bits, and one or more of the bits remain unchanged and the other bits change during the flipping. The change means that the bit changes from 0 to 1 or from 1 to 0.

[0043] In one embodiment, the frequencies of the input clock clk1 and the internal clock clk2 are equal. The higher the frequencies of the input clock clk1 and the internal clock clk2, the smaller the clock period Tclk, the smaller the stable time window Tclk-(CLQV-CLQX) of the output data data, the greater the possibility that the sampling point falls in the unstable time window CLQV-CLQX of the output data data, and the higher the possibility that the sampled data is incorrect. At this time, if you want to sample the correct data in the stable time window Tclk-(CLQV-CLQX), you can reduce the frequency of the input clock clk1, so that the stable time window Tclk-(CLQV-CLQX) of the output data data becomes larger; and reducing the frequency of the input clock clk1 also reduces the operating frequency of the Flash controller, reducing the performance of the Flash controller.

[0044] An embodiment of the present application proposes a clock control module for adjusting a sampling clock of a storage device; the clock control module is configured to use the sampling clock to sample output data of the storage device to obtain sampling data, and to match the sampling data with the output data to determine a delay step of the sampling clock.

[0045] It should be noted that the clock control module in the embodiment of the present application can be either a program, code or instruction, or a chip or circuit for executing the program, code or instruction.

[0046] For details, please refer to Fig. 9 As shown, the clock control module 22 may include: a training unit 222, wherein the training unit 222 is configured to determine sampling data and output data; and to compare the sampling data and the output data to determine the matching degree between the sampling data and the output data, and to determine the delay step of the sampling clock according to the matching degree, so that the sampling data obtained by sampling according to the sampling clock adjusted by the delay step matches the output data.

[0047] Among them, Fig. 9 As shown, the clock control module 22 may further include: an adjusting unit 221, wherein the adjusting unit 221 is configured to determine an adjusted sampling clock using a delay step and a system clock.

[0048] It can be understood that the system clock SCLK can be a clock signal generated by the SoC. Similarly, the controller 20 can input the system clock SCLK into the memory 10 as the input clock clk1.

[0049] In this embodiment of the present application, the matching result between the sampled data and the output data can be determined based on whether the values ​​of the corresponding preset bits of the sampled data and the output data match.

[0050] The present application embodiment proposes a controller 20, such as Figure 3 As shown, Figure 3 2 is a schematic diagram of the structure of a controller 20 in an embodiment provided in the present application. The controller 20 includes a main control module 21, a clock control module 22 and a cache module 23.

[0051] The clock control module 22 is used to generate a sampling clock RXCLK according to the input system clock SCLK, and use the sampling clock RXCLK to sample the output data data of the memory 10, and then continuously adjust the sampling clock RXCLK according to the matching of the sampled data obtained by sampling and the original output data data, until the sampled data obtained by sampling can match the original output data, and further obtain the sampling clock RXCLK when the sampled data matches the original output data. The clock control module 22 is also used to input the adjusted sampling clock RXCLK to the main control module 21, and the main control module 21 performs subsequent sampling of the output data data based on the sampling clock RXCLK, as well as other operations.

[0052] It can be understood that the system clock SCLK can be a clock signal generated by the SoC. Similarly, the controller 20 can input the system clock SCLK as the input clock clk1 to the memory 10, wherein the input clock clk1; the memory 10 generates output data data based on the internal clock clk2. However, due to the delay of the interface, the internal clock clk2 received by the memory 10 is delayed compared to the input clock clk1.

[0053] The cache module 23 is used for data caching, especially for caching of sending data. For example, when the controller 20 needs to write data into the memory 10, the controller 20 obtains the data to be written from the SoC, and can cache the data in the cache module 23, and then the main control module 21 writes the cached data into the memory 10. Optionally, the cache module 23 can be a Tx FIFO (First Input First Output), and the FIFO memory is a first-in-first-out dual-port buffer, that is, the first data entering it is removed first, one of which is the input port of the memory, and the other port is the output port of the memory.

[0054] Optionally, the clock control module 22 specifically includes a delay unit 221 , a training unit 222 and a cache unit 223 .

[0055] The delay unit 221 is used to receive the system clock SCLK and the delay step step sent by the training unit 222, and use the delay step step to delay the system clock SCLK to obtain the delayed sampling clock RXCLK, and send the sampling clock RXCLK to the training unit 222. The training unit 222 is used to sample the output data data of the memory 10 using the sampling clock RXCLK, and then match and compare the sampled data obtained by sampling with the original output data data. Specifically, when the sampled data obtained by sampling does not match the original output data data, the training unit 222 adjusts the output delay step step, for example, the delay step step increases or decreases by one unit, so that the delay unit 221 delays the system clock SCLK according to the new delay step to obtain a new sampling clock RXCLK, and the training unit 222 uses the new sampling clock RXCLK to sample the output data of the memory 10, and then matches the obtained sampled data with the original output data, and so on. The cycle is repeated until the obtained sampled data can match the original output data, and the process is terminated.

[0056] It can be understood that the delay unit 221 is used to insert a certain buffer between the system clock SCLK and the sampling clock RXCLK, and the buffer is used to control the delay level so that the sampling clock RXCLK has a certain phase delay relative to the system clock SCLK. Optionally, the delay unit 221 can be a delay locked loop (DLL). In one embodiment, the DLL can be implemented by a digital circuit. The DLL includes a delay module and a control module. The output clock (sampling clock RXCLK) of the delay module is obtained by delaying the input clock (system clock SCLK). The control module adjusts the delay amount of the delay module according to the feedback signal (the feedback signal is determined by the output clock) and the input step step.

[0057] It can be understood that the sampling data has the same frequency as the original output data data, but the phase may be inconsistent. Therefore, the training unit 222 is used to match the phase of the sampling data with the original output data data. Optionally, in one embodiment, the matching of the sampling data and the output data is determined by detecting the levels of the sampling data and the output data data. For example, if the sampling data and the output data data are both "1" or "0", it is determined that the sampling data and the output data match; if the sampling data is "1" and the output data data is "0", or if the sampling data is "0" and the output data data is "1", it is determined that the sampling data and the output data do not match.

[0058] The cache unit 223 is used for data caching, especially for receiving data. For example, when the controller 20 needs to read data in the memory 10, the controller 20 samples the output data data of the memory 10, and can cache the data in the cache unit 223 and then send it to the SoC. Optionally, the cache unit 223 can be an Rx FIFO (First Input First Output). The FIFO memory is a first-in-first-out dual-port buffer, that is, the first data entering it is removed first, one of which is the input port of the memory, and the other port is the output port of the memory.

[0059] Different from the prior art, the storage device provided by the embodiment of the present disclosure includes a memory and a controller, and the controller includes: a clock control module, connected to the memory, the clock control module is configured to generate a sampling clock according to the system clock, use the sampling clock to sample the output data of the memory to obtain the sampling data, and adjust the generated sampling clock according to the matching of the sampling data and the output data until the sampling data and the output data match; a main control module, connected to the memory and the clock control module, the main control module is configured to use the adjusted sampling clock to sample the output data of the memory. In the above manner, since the controller takes into account the matching of the sampling data and the output data when adjusting the phase of the sampling clock, sampling the output data of the memory using the adjusted sampling clock can ensure that the Flash controller can accurately sample the data; in addition, in the process of adjusting the sampling clock, a cyclic adjustment (self-training) method is adopted to realize the automation and efficiency of the sampling clock adjustment, thereby improving the performance of the Flash controller.

[0060] See below Figure 4 , Figure 4 1 is a flow chart of an embodiment of a data sampling method provided by the present application. The execution subject of the method is the controller 20, and specifically includes:

[0061] Step S41: Match the sampled data and output data of the storage device.

[0062] The sampled data is obtained by sampling the output data of the storage device according to the sampling clock.

[0063] The system clock SCLK is generally provided by a clock circuit, which is a circuit composed of an oscillator (signal source), a timer wake-up device, a frequency divider, etc. Common signal sources include crystal oscillators and RC oscillators. In one embodiment, the above-mentioned clock circuit is integrated into a SoC, and the SoC is connected to a controller 20, and the controller 20 is connected to a memory 10 to provide the system clock SCLK to the controller 20 and the memory 10.

[0064] In one embodiment, referring to the above Figure 3 In an embodiment, the training unit 222 outputs a delay step, the delay unit 221 delays the system clock SCLK based on the delay step to obtain the sampling clock RXCLK, and the training unit 222 receives the delayed sampling clock RXCLK output by the delay unit 221.

[0065] Optionally, in one embodiment, the initial delay step (also referred to as the initial delay step) step may be 0 or any preset value.

[0066] The sampling clock RXCLK is obtained by delaying the system clock SCLK by an initial delay step length step.

[0067] Optionally, in one embodiment, step S42 may specifically include: latching the DLP data in the output data data of the memory 10, and then sampling the DLP data to obtain sampled data.

[0068] like Figure 5 As shown, Figure 5 1 is a schematic diagram of a communication data waveform based on an SPI interface provided by the present application. The communication data using the SPI interface includes serial input data DI (from the memory 10 to the controller 20) and serial output data DO (from the controller 20 to the memory 10). Therefore, the present embodiment needs to sample the serial input data DI. In one embodiment, the serial input data DI includes a command field CMD, a normal address field ADD, a virtual address field DUMMY, and a data field HZ, wherein the data field HZ includes DLP data. The present embodiment latches and samples the DLP data.

[0069] It can be understood that starting from the initial step size, each time the step size is adjusted, the system clock SCLK needs to be delayed based on the adjusted step size to obtain the adjusted sampling clock RXCLK, and then the output data data is sampled using the adjusted sampling clock RXCLK.

[0070] Step S42: According to the matching result of the sampled data and the output data, the sampling clock is adjusted to make the sampled data and the output data match.

[0071] Optionally, in one embodiment, whether the sampled data and the output data match is determined by detecting the levels of the sampled data and the output data data. For example, if the sampled data and the output data data are both "1" or "0", it is determined whether the values ​​of the corresponding preset bits of the sampled data and the output data match; if the corresponding preset bits, the sampled data is "1" and the output data data is "0", or the sampled data is "0" and the output data data is "1", it is determined that the sampled data and the output data do not match.

[0072] Optionally, in one embodiment, step 43 may be specifically as follows: in response to the sampling data sampled in the current cycle period matching the output data, determining an adjusted sampling clock; or when the sampling data sampled in the current cycle period does not match the output data, generating a new delay step for the next cycle period until the sampling data and the output data match.

[0073] It can be understood that the above method adopts a self-loop training method. Specifically, when the sampling data and the output data match for the first time, the delay step of the current cycle is determined to be the minimum delay step. When the sampling data and the output data match for the last time, the delay step of the current cycle is determined to be the maximum delay step. The adjusted sampling clock is determined based on the minimum delay step and the maximum delay step.

[0074] Step S43: Sample the output data of the memory using the adjusted sampling clock.

[0075] The data sampling method provided in this embodiment includes: matching the sampled data and output data of the storage device; adjusting the sampling clock according to the matching result of the sampled data and the output data so that the sampled data and the output data match; sampling the output data of the storage device using the adjusted sampling clock; wherein the sampled data is obtained by sampling the output data of the storage device according to the sampling clock. In the above manner, since the controller takes into account the matching of the sampled data and the output data when adjusting the phase of the sampling clock, sampling the output data of the storage device using the adjusted sampling clock can ensure that the Flash controller can accurately sample the data; in addition, in the process of adjusting the sampling clock, a cyclic adjustment (self-training) method is adopted to realize the automation and efficiency of the sampling clock adjustment, thereby improving the performance of the Flash controller.

[0076] In all embodiments of the present application, if it is in the first sampling process, the sampling clock can be determined based on the system clock and the initial delay step; then matching is performed, and if it does not match, the sampling clock is redetermined after adjusting the delay step, and sampling is performed again, and matching is performed again so that the sampled data matches the output data. In an embodiment of the present application, the initial delay step can be the minimum delay step; and the step when the sampled data matches the output data is the maximum delay step. It should be noted that if the initial delay step is able to achieve matching of the sampled data with the output data, then the minimum delay step and the maximum delay step are the same. The above steps can be applied to all embodiments of the present application and will not be repeated later.

[0077] See below Figure 6 , Figure 6 2 is a flow chart of another embodiment of the data sampling method provided by the present application. The execution subject of the method is the training unit 222, which specifically includes:

[0078] Step S61: outputting a delay step length, so that the delay unit performs delay processing on the system clock based on the delay step length to obtain a sampling clock, and receiving the sampling clock output by the delay unit.

[0079] Step S62: The training unit samples the output data of the memory using the sampling clock to obtain sampled data.

[0080] Step S63: The training unit matches the sampled data and the output data to determine whether the sampled data and the output data are matched for the first time; if so, execute step S64, if not, execute step S65.

[0081] It can be understood that since the output data data has a stable time window Tclk-(CLQV-CLQX) and an unstable time window CLQV-CLQX, two situations may occur in the process of continuously adjusting the sampling clock RXCLK: one is that the sampled data obtained after the output data is sampled for the first time using the initial sampling clock can match the output data; the other is that one or more mismatches may occur, and the first match occurs after adjusting the delay step, and then continuous matches occur. Here, it is necessary to record the relevant data when the first match occurs (the relevant data includes but is not limited to: the current sampling clock or the current delay step).

[0082] Step S64: Determine that the current delay step is the minimum delay step a, and jump to step S67.

[0083] In one embodiment, if the sampled data and the output data data match for the first time after at least one mismatch, it means that the current sampling clock RXCLK can be used to sample the output data data, and the sampled data is accurate. At this time, the current delay step is recorded as the minimum delay step a.

[0084] In another embodiment, when the initial delay step is not adjusted, the sampled data obtained based on the current sampling clock RXCLK and the output data data have matched, and any one of the following three methods can be used for processing:

[0085] The first method: record the initial delay step length as the minimum delay step length a. It can be understood that the first method will reduce the range between the minimum delay step length a and the subsequently determined maximum delay step length b, but the sampling of the output data data can still be achieved.

[0086] The second method: still using the above-mentioned step adjustment method, after the sampling data obtained by the sampling clock RXCLK determined by the initial delay step matches the output data data, after multiple matches and multiple mismatches, the first match occurs again, indicating that the current sampling clock RXCLK can be used to sample the output data data, and the sampled data is accurate. At this time, the current delay step is recorded as the minimum delay step a.

[0087] The third method: when adjusting the delay step, the adjustment accuracy is set to a negative number, that is, the system clock SCLK is delayed in the opposite direction.

[0088] Step S65: Determine whether the sampled data and the output data are matched for the last time; if so, execute step S66; if not, execute step S67.

[0089] It can be understood that since the output data data has a stable time window Tclk-(CLQV-CLQX) and an unstable time window CLQV-CLQX, continuous mismatches generally occur in the process of continuously adjusting the sampling clock RXCLK, and then after the first match, continuous matches occur again. In step S63, the relevant data of the first match is recorded, and here the relevant data of the last match needs to be recorded.

[0090] Step S66: Determine the current delay step length as the maximum delay step length b.

[0091] It can be understood that, in general, after the first match between the sampled data and the output data data, the results of data acquisition obtained by adjusting the sampling clock after the step size is adjusted for several subsequent times are still that the sampled data and the output data data can match. However, as the delay step size gradually increases, the sampled data and the output data may not match. At this time, the maximum delay step size b is recorded.

[0092] In one implementation of the present application, the minimum delay step a and the maximum delay step b can determine the lower threshold value and the upper threshold value of the delay step; the delay step between the lower threshold value and the upper threshold value can achieve sampling data that matches the output data data.

[0093] Step S67: Control the delay step to increase by one unit and jump to step S61.

[0094] When the judgment result of step S63 is yes and the judgment result of step S65 is no, this step S67 is executed. Optionally, a step length p can be preset as a unit, that is, increasing one unit means increasing the step length p, for example, p=10ps, specifically, the initial delay step length is 0ps, the delay step length after the first increase of one unit is 0+1*p, the delay step length after the second increase of two units is 0+2*p, and the delay step length after the nth increase of two units is 0+n*p.

[0095] Optionally, in one embodiment, a coarse adjustment and a fine adjustment may be used when adjusting the step size. Specifically, two different step sizes may be set to increase the accuracy: p1 and p2, where p1 is greater than p2.

[0096] Specifically, the initial delay step is 0ps. When the sampled data obtained by sampling the sampling clock RXCLK corresponding to the delay step of 0ps does not match the output data data, the delay step after the first increase by one unit is 0+1*p1. After the first increase, if the sampled data obtained by sampling the sampling clock RXCLK corresponding to the delay step 0+1*p1 still does not match the output data data, the step size continues to be increased to 0+2*p1, 0+3*p1...0+n*p1. After the mth increase, if the sampling data obtained by sampling the sampling clock RXCLK corresponding to the delay step 0+m*p1 and the output data data still match, then return to the previous delay step: 0+(m-1)*p1, and start step adjustment based on p2 on the basis of 0+(m-1)*p1. At this time, 0+(m-1)*p1 can be regarded as the initial delay step, and then continue to use 0+(m-1)*p1+1*p2, 0+(m-1)*p1+2*p2...0+(m-1)*p1+n*p2 to adjust the step size, so as to determine the first match or the last match.

[0097] Step S68: Determine the final delay step length according to the minimum delay step length and the maximum delay step length.

[0098] Among them, any value between the minimum delay step a and the maximum delay step b can be determined as the final delay step. Theoretically, the result of data sampling by the sampling clock RXCLK obtained by delaying the system clock SCLK based on any value between the minimum delay step a and the maximum delay step b is accurate.

[0099] Optionally, in one embodiment, the middle value between the minimum delay step a and the maximum delay step b is taken as the final delay step, that is, (a+b) / 2.

[0100] Specifically, combined Figure 3 , Figure 6 and Figure 7 , Figure 7 It is a timing diagram of the sampling clock provided in the present application, wherein the delay unit 221 delays the system clock SCLK according to the delay step n*p sent by the training unit 222 to obtain the sampling clock RXCLK, the initial value of n is 0, and in each subsequent step adjustment, n increases by 1, p is the adjustment accuracy, p is a positive number indicating forward movement, and p is a negative number indicating backward movement, for example, p = 10ns.

[0101] The training unit 222 uses the sampling clock RXCLK to sample the output data data of the memory 10. When the sampled data does not match the original output data data, the delay step n*p=(n+1)p is used to adjust the sampling clock RXCLK, and then the output data data of the memory 10 is sampled again using the new sampling clock RXCLK; when the sampled data matches the original output data data for the first time, the training unit 222 records the delay coefficient n=a corresponding to the current sampling clock RXCLK_min; when the sampled data matches the original output data for the last time, the training unit 222 records the delay coefficient n=b corresponding to the current sampling clock RXCLK_max, and then obtains the optimal delay step value based on (ba) / 2*p, thereby obtaining the optimal sampling clock RXCLK_better.

[0102] The training unit 222 inputs the sampling clock RXCLK_better to the main control module 21 , and the main control module 21 uses the sampling clock RXCLK_better to perform subsequent work, such as performing regular sampling on the output data of the memory 10 .

[0103] See also Figure 8 , Figure 8 It is a structural diagram of an embodiment of a computer-readable storage medium provided by the present application. The computer-readable storage medium 81 stores program data 82. When the program data 82 is executed by the processor, it is used to implement the following method: matching the sampling data and output data of the storage device; adjusting the sampling clock according to the matching result of the sampling data and the output data so that the sampling data and the output data match; sampling the output data of the memory using the adjusted sampling clock; wherein the sampling data is obtained by sampling the output data of the storage device according to the sampling clock.

[0104] Among them, the memory or computer-readable storage medium in the above embodiments can be a medium that can store program data, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or it can also be a server that stores the program data. The server can send the stored program data to other devices for execution, or it can also execute the stored program data by itself.

[0105] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0106] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0107] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0108] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A clock control module, used to adjust the sampling clock of a storage device, characterized in that: The clock control module is configured to match the sampling data and output data of the storage device and determine the adjustment step of the sampling clock; wherein the sampling data is obtained by sampling the output data of the storage device according to the sampling clock.

2. The clock control module according to claim 1, characterized in that: The clock control module comprises: A training unit, wherein the training unit is configured to determine the sampling data and the output data; and to match the sampling data and the output data, and determine the adjustment step of the sampling clock according to the matching result, so that the sampling data obtained by sampling according to the sampling clock adjusted by the adjustment step matches the output data.

3. The clock control module according to claim 2, characterized in that: The training unit is configured to determine a matching result between the sampled data and the output data according to whether values ​​of corresponding preset bits of the sampled data and the output data match.

4. The clock control module according to claim 2, characterized in that: The training unit is configured to perform the following operations: In response to the sampling data obtained by sampling in the current cycle period matching the output data, determining the adjusted sampling clock; or In response to the sampled data obtained by sampling in the current cycle not matching the output data, sampling is performed in the next cycle using the adjusted delay step until the sampled data matches the output data.

5. A storage device, comprising a memory and a controller, wherein: The controller is connected to the memory, and is characterized in that the controller includes: A clock control module connected to the memory, the clock control module is configured to match the sampling data and output data of the storage device to determine the adjustment step of the sampling clock; wherein the sampling data is obtained by sampling the output data of the storage device according to the sampling clock; A main control module is connected to the memory and the clock control module, and the main control module is configured to sample the output data of the memory using the adjusted sampling clock.

6. The storage device according to claim 5, characterized in that: The clock control module comprises: A training unit, wherein the training unit is configured to determine the sampling data and the output data; and to match the sampling data and the output data, and determine the adjustment step of the sampling clock according to the matching degree, so that the sampling data obtained by sampling according to the sampling clock adjusted by the adjustment step matches the output data.

7. The storage device according to claim 6, characterized in that: The training unit is configured to determine a matching degree between the sampled data and the output data according to whether values ​​of corresponding preset bits of the sampled data and the output data match.

8. The storage device according to claim 6, characterized in that: The training unit is configured to perform the following operations: In response to the sampling data obtained by sampling in the current cycle period matching the output data, determining the adjusted sampling clock; or In response to the sampled data obtained by sampling in the current cycle not matching the output data, sampling is performed in the next cycle using the adjusted delay step until the sampled data matches the output data.

9. A method for sampling data in a storage device, wherein: The storage device includes a memory and a controller, and the method includes: The controller matches the sampled data and the output data of the storage device; According to the matching result between the sampled data and the output data, the sampling clock is adjusted so that the sampled data and the output data match; Sampling the output data of the memory using the adjusted sampling clock; The sampled data is obtained by sampling the output data of the storage device according to a sampling clock.

10. The method according to claim 9, characterized in that The step of adjusting the sampling clock according to the matching result between the sampling data and the output data so as to make the sampling data and the output data match each other includes: In response to the sampling data obtained by sampling in the current cycle period matching the output data, determining the adjusted sampling clock; or In response to the sampled data obtained by sampling in the current cycle not matching the output data, sampling is performed in the next cycle using the adjusted delay step until the sampled data matches the output data.

11. The method according to claim 10, characterized in that In response to the sampling data obtained by sampling in the current cycle matching the output data, determining the adjusted sampling clock includes: In response to the first match between the sampled data and the output data, the delay step of the current cycle is determined to be the minimum delay step. In response to the last match between the sampled data and the output data, the delay step of the current cycle is determined to be the maximum delay step. The adjusted sampling clock is determined based on the minimum delay step and the maximum delay step.

12. A computer-readable storage medium, characterized in that: The computer storage medium stores program data, which, when executed, is used to implement the method according to any one of claims 9 to 11.

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