Memory control circuit and operating method thereof

Abstract

The invention discloses a memory control circuit and an operation method thereof, and relates to the technical field of memory control. The memory control circuit comprises a data buffer circuit, a data holding circuit and a control circuit. The data buffer circuit is used for storing data read from a memory, wherein the memory comprises a plurality of memory banks and a plurality of channels corresponding to the plurality of memory banks. A data retention circuit is connected with the plurality of channels. The control circuit is configured to control the data holding circuit not to gate a target channel corresponding to a storage library identification code and hold target data on the target channel in the target channel when the storage capacity of the data buffer circuit is full based on the storage library identification code originating from a data reading instruction; and when the storage capacity is not full, controlling the data holding circuit to gate the target channel so as to read the target data on the target channel to the data buffer circuit.

Description

Technical Field

[0001] The present application relates to the field of memory control technology, and in particular to a memory control circuit and an operation method thereof. Background Art

[0002] In the process of designing electronic systems such as chips, if the processing circuit used for high-speed computing needs to access the memory, it usually uses the chip bus to do so. Since the chip bus may not be able to directly access the memory, the electronic system will set up a memory control circuit as an interface between the processing circuit and the memory to achieve the purpose of access through data format conversion.

[0003] When the memory returns data, the temporary storage circuit set in the memory control circuit will first store it temporarily, and then the processing circuit will read it further. However, if the temporary storage circuit has a large depth, it will often increase the area of ​​the circuit. If the temporary storage circuit has a small depth, it will easily reduce the data throughput and transmission efficiency. Summary of the invention

[0004] Based on the problems of the prior art, one of the objectives of the present application is to provide a memory control circuit and an operation method thereof to improve the prior art.

[0005] The present application includes a memory control circuit, including: a data buffer circuit, a data holding circuit and a control circuit. The data buffer circuit is used to store data read from a memory, wherein the memory includes a plurality of storage banks and a plurality of channels corresponding to the plurality of storage banks. The data holding circuit is connected to the plurality of channels. The control circuit is configured to: based on a storage bank identification code derived from a data read instruction, when the storage capacity of the data buffer circuit is full, control the data holding circuit to not select the target channel corresponding to the storage bank identification code and to keep the target data on the target channel in the target channel; and when the storage capacity is not full, control the data holding circuit to select the target channel to read the target data on the target channel to the data buffer circuit.

[0006] The present application also includes a memory control circuit operation method, which is applied to the memory control circuit, including: the control circuit determines whether the storage capacity of the data buffer circuit is full, wherein the data buffer circuit is used to store data read from the memory, and the memory includes multiple storage libraries and multiple channels corresponding to the multiple storage libraries; the control circuit controls the data holding circuit connected to the multiple channels to not select the target channel corresponding to the storage library identification code and to maintain the target data on the target channel in the target channel based on the storage library identification code derived from the data read instruction when the storage capacity is full; and the control circuit controls the data holding circuit to select the target channel to read the target data on the target channel to the data buffer circuit when the storage capacity is not full.

[0007] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram showing an electronic system in one embodiment of the present application;

[0009] Figure 2 A block diagram showing a memory control circuit in one embodiment of the present application;

[0010] Figure 3 A flowchart showing a memory control circuit operation method in an embodiment of the present application; and

[0011] Figure 4 A flow chart showing a memory control circuit operation method according to another embodiment of the present application.

[0012] 100: Electronic system;

[0013] 110: processing circuit;

[0014] 120: memory control circuit;

[0015] 130: memory circuit;

[0016] 140: first interface;

[0017] 150: second interface;

[0018] 160A~160D: storage library;

[0019] 170A~170D: storage unit;

[0020] 200: identification code buffer circuit;

[0021] 210: Conversion and analysis circuits;

[0022] 220: data buffer circuit;

[0023] 230: data holding circuit;

[0024] 240: control circuit;

[0025] 300: Memory control circuit operation method;

[0026] S310-S350: steps;

[0027] 400: Memory control circuit operation method;

[0028] S410-S430: steps;

[0029] BID: repository identification number;

[0030] CDA: Correspondence Data;

[0031] CHA~CHD: channel;

[0032] DRC: data read command;

[0033] ITS: interrupt signal;

[0034] MRC: memory read command;

[0035] SDA: storage data;

[0036] SID: repository identifier. DETAILED DESCRIPTION

[0037] The technical terms used in the following descriptions refer to the customary terms in the technical field. If some of the terms are explained or defined in this specification, the interpretation of the terms shall be based on the explanation or definition in this specification.

[0038] An object of the present application is to provide a memory control circuit and an operation method thereof. When the storage capacity of a data buffer circuit is full, the data returned by the memory circuit is stored in a channel corresponding to a data retention circuit. By using the memory circuit's own channel to retain the data to be read, the depth of the data buffer circuit can be reduced, thereby reducing the circuit area, and maintaining a higher data throughput and transmission performance.

[0039] Please refer to Figure 1 , shows a block diagram of an electronic system 100 according to an embodiment of the present application. The electronic system 100 includes a processing circuit 110 , a memory control circuit 120 and a memory circuit 130 .

[0040] The processing circuit 110 may be, for example, an image signal processor (ISP) or other types of processing circuits, and may communicate with the memory control circuit 120 via the first interface 140. In one embodiment, the first interface 140 is an advanced extensible interface (AXI), an advanced peripheral bus (APB), or an advanced high-performance bus (AHB).

[0041] The memory circuit 130 may be, for example, a static random access memory (SRAM), and may communicate with the memory control circuit 120 through the second interface 150 .

[0042] In one embodiment, the memory circuit 130 has a plurality of memory banks 160A-160D, each memory bank having a corresponding identification code.

[0043] exist Figure 1 In the example shown, the memory circuit 130 includes four memory banks 160A-160D, each memory bank having a corresponding identification code, such as identification codes numbered 0, 1, 2, and 3 in sequence.

[0044] Each memory bank 160A-160D includes a plurality of memory cells arranged in an array, that is, each memory bank is a memory cell array. A memory cell may be the smallest storage unit in the memory circuit 130. Figure 1 In the example shown, the storage library 160A includes four storage units 170A-170D.

[0045] The memory control circuit 120 receives the data read command DRC from the processing circuit 110 , retrieves the data DAT requested by the data read command DRC from the memory circuit 130 , and transmits the data DAT back to the processing circuit 110 to complete the data read operation.

[0046] Please refer to Figure 2 , shows a block diagram of a memory control circuit 120 in an embodiment of the present application. The memory control circuit 120 includes: an identification code buffer circuit 200, a conversion and analysis circuit 210, a data buffer circuit 220, a data holding circuit 230 and a control circuit 240.

[0047] The conversion and analysis circuit 210 receives the data read command DRC from the processing circuit 110. The conversion and analysis circuit 210 analyzes the data read command DRC to generate a storage bank identification code BID and stores it in the identification code buffer circuit 200. The identification code buffer circuit 200 has a preset storage capacity and can store multiple storage bank identification codes BID. In one embodiment, the number of multiple storage bank identification codes BID that can be stored in the identification code buffer circuit 200 is less than or equal to the number of multiple channels of the memory circuit 130, so that the characteristics of the multiple channels of the memory circuit 130 for temporarily storing data can be fully utilized to save the cache space of the memory control circuit 120. The identification code buffer circuit 200 can be specifically a first-in-first-out (FIFO) cache circuit. The conversion and analysis circuit 210 also performs format conversion on the data read command DRC to generate a corresponding memory read command MRC and transmit it to the memory circuit 130.

[0048] Since the processing circuit 110 and the memory circuit 130 use different communication interfaces, the conversion and analysis circuit 210 converts the format of the data read command DRC from the first interface 140 to the second interface 150, so that the memory circuit 130 can receive the format-converted memory read command MRC to read data accordingly.

[0049] The bank identifier BID is included in the data read command DRC and the converted memory read command MRC, and can be used to indicate which bank 160A-160D of the memory circuit 130 is to be accessed by the command. The memory circuit 130 can retrieve data from the bank corresponding to the bank identifier BID.

[0050] For example, if the value of the memory bank identification code BID is 0, the memory circuit 130 can determine that the corresponding memory bank is the memory bank 160A, and then retrieve the data DAT from at least one storage unit in the memory bank 160A.

[0051] The memory circuit 130 includes a plurality of channels CH (such as channels CHA to CHD), and the plurality of channels CH correspond to the memory banks one by one. In practice, the channel CH may be a data bus of the memory bank. It is well known to those skilled in the art that when the memory circuit 130 receives a first read request, it retrieves the requested first data from a corresponding memory bank and places the first data on the channel of the memory bank (such as switching the output enable to a low voltage level state) to wait for the read circuit, such as the memory control circuit 120 of the present application, to obtain the first data from the corresponding channel; when the memory circuit 130 receives a second read request to retrieve the second data from the memory bank again, it responds to the second read request to retrieve the second data and places the second data on the channel, and at this time, the first data previously placed on the channel is updated and replaced by the second data. It can be understood that the channel CH itself can temporarily store the data retrieved from the corresponding memory bank.

[0052] The data holding circuit 230 is connected to the memory circuit 130. Specifically, the data holding circuit 230 is connected to a plurality of channels CH, and generates an interrupt signal ITS to notify the control circuit 240 that there is data waiting to be written into the data buffer circuit 220 when it is known that the corresponding channel of the memory circuit 130 has data. In one example, the identification code buffer circuit 200 is a FIFO buffer circuit. After responding to the interrupt signal ITS, the control circuit 240 reads a storage bank identification code SID (e.g., a current identification code) from the identification code buffer circuit 200, and determines the corresponding channel of the storage bank identification code SID accordingly to read the data placed on the corresponding channel. In an optional example, the interrupt signal ITS includes storage bank information such as the storage bank information identification code BID, and the control circuit 240 responds to the interrupt signal ITS to determine whether the storage bank identification code SID consistent with the storage bank identification code is stored in the identification code buffer circuit 200. If it is stored, the control circuit 240 performs relevant operations to read the data placed on the corresponding channel. In another example, the control circuit 240 may first obtain a storage bank identification code SID (e.g., any one of a plurality of identification codes) from the identification code buffer circuit 200, and confirm the channel CH corresponding to the storage bank identification code SID, and wait for the interrupt signal ITS sent back by the data holding circuit 230 to inform that the channel CH has been set with data to be read. The control circuit 240 responds to the interrupt signal ITS to determine whether the storage capacity of the data buffer circuit 220 is full.

[0053] When the storage capacity of the data buffer circuit 220 is full, the control circuit 240 controls the data holding circuit 230 to not select the corresponding channel and to hold the corresponding data on the corresponding channel in the corresponding channel.

[0054] In one embodiment, the data holding circuit 230 is a multiplexer. When the storage capacity of the data buffer circuit 220 is full, the control circuit 240 controls the data holding circuit 230 to not enable the corresponding channel to keep the corresponding data to be read on the corresponding channel. Specifically, the data holding circuit 230 can not enable the channel by maintaining the voltage level on the corresponding channel. For example, if the channel corresponding to the storage bank identification code SID is the channel CHA, the corresponding data CDA to be read will be kept on the channel CHA by the data holding circuit 230 maintaining the voltage level on the channel CHA.

[0055] Since the corresponding data CDA is still kept on the corresponding channel and has not been actually read, the control circuit 240 controls the identification code buffer circuit 200 to continue storing the memory bank identification code SID.

[0056] When the storage capacity of the data buffer circuit 220 is not full, the control circuit 240 controls the data holding circuit 230 to select the corresponding channel to transmit the corresponding data from the corresponding channel to the data buffer circuit 220 for storage, and controls the identification code buffer circuit 200 to remove the storage bank identification code SID.

[0057] Specifically, the control circuit 240 controls the data holding circuit 230 to select the channel CHA according to the memory bank identification code SID, so as to read the corresponding data CDA from the channel CHA and store it in the data buffer circuit 220 .

[0058] After the corresponding data CDA has been stored in the data buffer circuit 220, the control circuit 240 controls the identification code buffer circuit 200 to remove the corresponding storage bank identification code SID. It is understandable that the removal includes, but is not limited to, updating the storage bank identification code BID.

[0059] Furthermore, the data SDA is stored in the data buffer circuit 220 and can be accessed by the processing circuit 110. The data buffer circuit 220 removes the data SDA stored in the data buffer circuit 220 after the processing circuit 110 retrieves the data SDA.

[0060] When the memory circuit 130 receives the first data read request and the second data read request corresponding to the same memory bank in succession, the first data corresponding to the first read request on the channel will be replaced by the second data requested by the second read request. In order to prevent the data requested by the next data read instruction DRC of the same memory bank from overwriting the data requested by the previous data read instruction DRC but stored on the channel CH and not actually read to the data buffer circuit 220, after the conversion and analysis circuit 210 analyzes the data read instruction DRC and generates the memory bank identification code BID, the control circuit 240 can determine whether the memory bank identification code BID is the same as any memory bank identification code SID stored in the identification code buffer circuit 200, and accordingly control the conversion and analysis circuit 210 whether to perform format conversion processing on the data read instruction DRC.

[0061] For example, if the conversion and analysis circuit 210 analyzes a data read command DRC and obtains a code value of the memory bank identification code BID of 0, and the control circuit 240 also identifies a memory bank identification code SID in the identification code buffer circuit 200 and the code value is also 0, it means that the corresponding channel CHA still stores the data requested by the previous data read command DRC but the data has not been read to the data buffer circuit 220. At this time, the control circuit 240 controls the conversion and analysis circuit 210 not to store the memory bank identification code BID in the identification code buffer circuit 200, and not to perform format conversion on the data read command DRC, so as not to transmit the corresponding memory read command MRC to the memory circuit 130.

[0062] On the contrary, if the conversion and analysis circuit 210 analyzes a data read command DRC and obtains a code value of the bank identification code BID of 0, but the control circuit 240 does not identify the bank identification code SID with a code value of 0 in the identification code buffer circuit 200, this scenario indicates that the previous data of the channel CHA have been read to the data buffer circuit 220. At this time, the control circuit 240 controls the conversion and analysis circuit 210 to store the bank identification code BID in the identification code buffer circuit 200, performs format conversion on the data read command DRC and transmits it to the memory circuit 130, so that the memory circuit 130 places the requested data in the corresponding channel and performs subsequent operations.

[0063] When the storage capacity of the data buffer circuit is full, the memory control circuit of the present application maintains the data returned by the memory circuit on the corresponding channel connected to the data holding circuit. By using the memory circuit's own channel to maintain the data to be read, the depth of the data buffer circuit can be reduced, thereby reducing the circuit area, and maintaining a higher data throughput and transmission efficiency.

[0064] In one embodiment, in order to achieve the best resource utilization, the depth of the identification code buffer circuit 200 is equal to the number of the storage bank identification codes. Under such a configuration, it is possible to avoid the situation where the storage mechanism of all channels cannot be used when the depth of the identification code buffer circuit 200 is less than the number of the storage bank identification codes, and it is also possible to avoid the waste of resources caused by the depth of all the identification code buffer circuits 200 not being used when the depth of the identification code buffer circuit 200 is greater than the number of the storage bank identification codes.

[0065] Please refer to Figure 3 , a flow chart of a memory control circuit operation method 300 in an embodiment of the present application is shown. The memory control circuit operation method 300 includes the following steps.

[0066] In step S310 , the control circuit 240 controls the conversion and analysis circuit 210 to analyze the data read command DRC in response to the received data read command DRC to generate a bank identification code BID and store it in the identification code buffer circuit 200 , and converts the data read command DRC into a memory read command MRC and transmits it to the memory circuit 130 .

[0067] In step S320 , the control circuit 240 responds to the interrupt signal sent by the data holding circuit 230 , and reads the memory bank identification code SID from the identification code buffer circuit 200 to determine the corresponding target channel.

[0068] In step S330, the control circuit 240 determines whether the storage capacity of the data buffer circuit 220 is full. If yes, the process proceeds to step S340; if no, the process proceeds to step S350.

[0069] In step S340 , the control circuit 240 controls the data holding circuit 230 to not select the target channel and to hold the target data on the target channel in the target channel.

[0070] In step S350 , the control circuit 240 controls the data holding circuit 230 to select the target channel and transmit the target data from the target channel to the data buffer circuit 220 for storage.

[0071] Please refer to Figure 4 , a flow chart of a memory control circuit operation method 400 in another embodiment of the present application is shown. The memory control circuit operation method 400 includes the following steps.

[0072] In step S410, upon receiving the data read command DRC, the control circuit 240 determines whether the storage capacity of the data buffer circuit 220 is full. If yes, the process proceeds to step S420; if no, the process proceeds to step S430.

[0073] In step S420 , the control circuit 240 controls the data holding circuit 230 connected to the plurality of channels to not select the target channel corresponding to the bank identification code BID and to hold the target data on the target channel in the target channel when the storage capacity is full based on the bank identification code BID from the data read command DRC.

[0074] In step S430 , the control circuit 240 controls the data holding circuit 230 to select the target channel to read the target data on the target channel to the data buffer circuit 220 when the storage capacity is not full.

[0075] In summary, the memory control circuit and its operating method in the present application save the data returned by the memory circuit on the channel corresponding to the data holding circuit when the storage capacity of the data buffer circuit is full. By using the memory circuit's own channel to hold the data to be read, the depth of the data buffer circuit can be reduced, thereby reducing the circuit area, and maintaining a higher data throughput and transmission performance.

[0076] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.

Claims

1. A memory control circuit, characterized in that: include: a data buffer circuit for storing data read from a memory, wherein the memory includes a plurality of memory banks and a plurality of channels corresponding to the plurality of memory banks; a data holding circuit connected to the plurality of channels; and A control circuit is configured to: Based on a memory bank identification code from a data read instruction, when a storage capacity of the data buffer circuit is full, the data holding circuit is controlled not to select a target channel corresponding to the memory bank identification code and to hold a target data on the target channel in the target channel; as well as When the storage capacity is not full, the data holding circuit is controlled to enable the target channel so as to read the target data on the target channel to the data buffer circuit.

2. The memory control circuit according to claim 1, wherein: The data holding circuit generates an interrupt signal when it is known that the target data is placed in the target channel. The control circuit identifies whether a storage capacity of the data buffer circuit is full in response to the interrupt signal.

3. The memory control circuit according to claim 1, wherein: The device further comprises an identification code buffer circuit, and the control circuit reads the storage bank identification code from the identification code buffer circuit.

4. The memory control circuit according to claim 3, wherein: The control circuit will remove the target data on the target channel from the identification code buffer circuit after reading it into the data buffer circuit.

5. The memory control circuit according to claim 1, wherein: It also includes an identification code buffer circuit, which has a storage capacity for storing multiple storage library identification codes. The data holding circuit generates an interrupt signal when it is known that the target data is placed in the target channel. The control circuit determines whether the storage library identification code is stored in the identification code buffer circuit in response to the interrupt signal.

6. The memory control circuit according to claim 1, wherein: It also includes an identification code buffer circuit, which has a storage capacity to store multiple storage library identification codes, the number of the multiple storage library identification codes is less than or equal to the number of the multiple channels, and the storage library identification code is one of the multiple storage library identification codes.

7. The memory control circuit according to claim 6, wherein: It also includes a conversion and analysis circuit for parsing the data read instruction to generate the repository identification code. When the repository identification code and any of the multiple repository identification codes stored in the identification code buffer circuit are different, the control circuit controls the conversion and analysis circuit to store the repository identification code in the identification code buffer circuit, and controls the conversion and analysis circuit to convert the data read instruction into a memory read instruction.

8. The memory control circuit according to claim 6, wherein: The control circuit reads the target data on the target channel to the data buffer circuit to update the storage bank identification code in the identification code buffer circuit.

9. A memory control circuit operation method, characterized in that: Applicable to a memory control circuit, comprising: A control circuit determines whether a storage capacity of a data buffer circuit is full, wherein the data buffer circuit is used to store data read from a memory, the memory including a plurality of memory banks and a plurality of channels corresponding to the plurality of memory banks; The control circuit controls a data holding circuit connected to the plurality of channels to not select a target channel corresponding to the memory bank identification code and to hold a target data on the target channel in the target channel based on a memory bank identification code from a data read instruction when the storage capacity is full; and When the storage capacity is not full, the control circuit controls the data holding circuit to select the target channel so as to read the target data on the target channel to the data buffer circuit.

10. The memory control circuit operation method according to claim 9, wherein: Also includes: The data holding circuit generates an interrupt signal when it is known that the target data is placed in the target channel; as well as The control circuit responds to the interrupt signal to identify whether a storage capacity of the data buffer circuit is full.

11. The memory control circuit operation method according to claim 9, wherein: The memory control circuit also includes an identification code buffer circuit, which has a storage capacity to store multiple storage library identification codes, the number of the multiple storage library identification codes is less than or equal to the number of the multiple channels, and the storage library identification code is one of the multiple storage library identification codes.

12. The memory control circuit operation method according to claim 11, wherein: Also includes: Parsing the data read instruction by a conversion and parsing circuit to generate the memory bank identification code; as well as When any of the multiple storage bank identification codes stored in the storage bank identification code and the identification code buffer circuit are different, the control circuit controls the conversion and analysis circuit to store the storage bank identification code in the identification code buffer circuit, and controls the conversion and analysis circuit to convert the data read instruction into a memory read instruction.

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