Data processing method and device

Abstract

The invention provides a data processing method and device, relates to the field of communication, and aims to improve the timeliness of fault prediction of high-risk hardware, improve the response speed of hardware fault prediction, reduce the probability of hardware faults and improve the stability and reliability of the hardware. In the method, a first device obtains log information of first hardware, and the first hardware comprises a plurality of pieces of hardware; the first device obtains a historical probability of fault occurrence of each hardware in the first hardware; the first device sorts the first hardware according to the size of the historical probability to obtain a sorting result, and when the historical probability is higher, the sorting of the first hardware corresponding to the sorting result is higher; and the first device analyzes the log information according to the sorting result from front to back so as to predict the probability that each piece of hardware in the first hardware has the fault.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communications, and in particular, to a data processing method and device. Background Art

[0002] At present, hardware failures often occur in large-scale data centers, which leads to a decrease in the stability and reliability of servers and even the entire network infrastructure. Hardware failure is the main cause of server crashes. Whether hardware failures can be accurately predicted in advance has become one of the important issues that the industry needs to study and solve in the cloud computing era. Traditional hardware failure prediction systems predict hardware failures based on system logs of hardware such as memory and hard disks. Generally, hardware with a higher probability of failure is called high-risk hardware. Since high-risk hardware failures account for a high proportion of all hardware failures, predicting the failure probability of high-risk hardware is of great significance to improving the response speed of system prediction.

[0003] In order to predict hardware failures, we can first obtain the error characteristics of the device to be predicted that has multiple hardware correctable errors in the current time window; then aggregate the error characteristics to obtain the aggregated error characteristics; and then predict whether the device to be predicted will have uncorrectable errors based on the aggregated error characteristics, that is, predict whether a hardware failure will occur. However, the amount of data in large-scale data centers is large, and it takes a long time to predict whether uncorrectable errors will occur, resulting in poor timeliness in the prediction of high-risk hardware failures.

[0004] Therefore, how to improve the timeliness of fault prediction for high-risk hardware is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present application provides a data processing method and device, which can find high-risk hardware by sorting the historical probabilities of failure of different hardware, and then analyze the hardware logs in order from front to back according to the sorting results, that is, give priority to predicting the probability of failure of high-risk hardware, thereby improving the timeliness of failure prediction of high-risk hardware, improving the response speed of hardware failure prediction, reducing the probability of hardware failure, and improving the stability and reliability of hardware.

[0006] The first aspect of the present application provides a data processing method, which is executed by a first device, or the method is executed by some components (such as a processor, a chip or a chip system, etc.) in the first device, or the method can also be implemented by a logic module or software that can realize all or part of the functions of the first device. In the first aspect and its possible implementation, the data processing method is described as being executed by the first device, the first device obtains log information of the first hardware, and the first hardware includes multiple hardware; the first device obtains the historical probability of each hardware in the first hardware failing; the first device sorts the first hardware according to the size of the historical probability to obtain a sorting result, and when the historical probability is larger, the corresponding first hardware is ranked higher in the sorting result; the first device analyzes the log information according to the order from front to back of the sorting result to predict the probability of each hardware in the first hardware failing.

[0007] In the first aspect, the first device needs to predict the probability of the first hardware failing. To this end, the first device first obtains the log information of the first hardware, wherein the first hardware is the sum of multiple hardware, and then obtains the historical probability of each hardware failing in the first hardware. For example, the historical probability can be the probability of hardware failing obtained in the previous round of prediction, or the probability of hardware failing obtained based on historical data analysis. Then the first hardware is sorted according to the size of the historical probability, wherein the larger the historical probability, the higher the ranking of the corresponding first hardware, that is, the hardware with the highest ranking is high-risk hardware. Then the first device analyzes the log information according to the order of the sorting result from front to back to predict the probability of each hardware in the first hardware failing. Therefore, in this application, the probability of high-risk hardware failing is analyzed first. In this application, the priority of high-risk hardware failure analysis is increased, thereby improving the timeliness of failure prediction of high-risk hardware, improving the response speed of hardware failure prediction, reducing the probability of hardware failure, and improving the stability and reliability of hardware.

[0008] Optionally, the first hardware includes: a hard disk, a disk, a memory, an optical module, a central processing unit (CPU), i.e., a graphics processing unit (GPU), a tensor processing unit (TPU) or a neural network processing unit (NPU).

[0009] Optionally, the first hardware may be the hardware of the second device, and the second device may be a server, for example, a physical server or a cloud server. Figure 1In the system shown, the second device may be server 105 , server 103 and / or server 104 .

[0010] In an optional implementation manner of the first aspect, the first hardware is a memory.

[0011] Based on the above implementation, this solution can be applied to the scenario of memory fault prediction, which can improve the priority of high-risk memory prediction and improve the timeliness of high-risk memory fault prediction.

[0012] Optionally, the log information in this application is an exemplary term and can be replaced by any possible term, such as system log, hardware log, etc.

[0013] Optionally, the first device may obtain log information of the first hardware from a storage location on the cloud.

[0014] Optionally, the fault in the present application is an uncorrectable error. When a fault occurs, the server where the first hardware is located will stop or interrupt operation.

[0015] Optionally, the first device may obtain a maintenance order of the first hardware, which records hardware failure information, and based on this, the historical probability of failure of each hardware in the first hardware may be calculated.

[0016] In an optional implementation of the first aspect, the historical probability is a probability obtained by analyzing the log information according to the sorting result in the previous i rounds, where i is a positive integer.

[0017] Based on the above implementation, the analysis results of the previous round can be reused, and the historical probability of the first module can be determined without adding new modules, which occupies less computing power resources.

[0018] Optionally, if the hardware appears for the first time, the default probability value P is set.

[0019] In an optional implementation of the first aspect, the first hardware includes multiple hardware sets, and for each of the hardware sets, the first device sorts the first hardware according to the size of the historical probability of each hardware in the hardware set.

[0020] Based on the above implementation, the first hardware can be divided into multiple hardware sets, and then the hardware can be sorted according to the size of the historical probability of the hardware in each hardware set, that is, each hardware set is sorted separately. Through this distributed sorting method, the efficiency of sorting the hardware can be improved, thereby improving the efficiency of hardware fault analysis.

[0021] Optionally, the first hardware may be divided into multiple hardware sets according to the number of resource pools.

[0022] Optionally, the first device may analyze the log information with the aid of a neural network model.

[0023] In an optional implementation of the first aspect, the first device analyzes the log information for each of the hardware sets according to the order from front to back in the ordering result.

[0024] Based on the above implementation, by dividing the hardware into multiple hardware sets and analyzing the log information of the hardware in each hardware set respectively, the efficiency of hardware analysis can be improved through this distributed analysis method, thereby improving the efficiency of hardware fault analysis.

[0025] In an optional implementation of the first aspect, the first device analyzes the log information of each hardware in the hardware set in parallel according to the sorting result from front to back.

[0026] Based on the above implementation, the hardware in each hardware set can be analyzed in parallel to predict the probability of hardware failure in each hardware set, so that the resources in the first device can be used to analyze the logs of the hardware in different hardware sets respectively.

[0027] The second aspect of the present application provides a communication device, which includes an acquisition module, a sorting module and an analysis module, and is used to perform all or part of the operations of the first aspect. The communication device can be a server, or a partial component of the server for performing related operations, such as a line card, an interface board, etc., or a chip system for performing related operations, and the chip system can include one or more chips. When the communication device is a chip system, the acquisition module can be, for example, an interface circuit of the chip, and the processing unit can be, for example, a processing circuit of the chip.

[0028] For example, when the communication device is the first device in the first aspect, the acquisition module is used to obtain the log information of the first hardware, which includes multiple hardware; obtain the historical probability of failure of each hardware in the first hardware; the sorting module is used to sort the first hardware according to the size of the historical probability to obtain a sorting result, when the historical probability is larger, the corresponding log information is ranked higher in the sorting result; the analysis module is used to analyze the log information according to the order of the sorting result from front to back to predict the probability of failure of each hardware in the first hardware.

[0029] In an optional implementation of the second aspect, the first hardware includes multiple hardware sets, and the sorting module is specifically used to: for each of the hardware sets, sort the first hardware according to the size of the historical probability of each hardware in the hardware set.

[0030] In an optional implementation of the second aspect, the analysis module is specifically used to: For each of the hardware sets, the log information is analyzed according to the order from front to back in the ordering result.

[0031] In an optional implementation of the second aspect, the analysis module is specifically used to: The log information of each hardware in the hardware set is analyzed in parallel in a descending order according to the sorting result.

[0032] In an optional implementation of the second aspect, the historical probability is a probability obtained by analyzing the log information in the first i rounds in a descending order according to the sorting result, where i is a positive integer.

[0033] In an optional implementation of the second aspect, the first hardware is a memory.

[0034] In a third aspect, an embodiment of the present application provides a communication device, comprising: a processor, the processor is coupled to a memory, the memory is used to store instructions, when the instructions are executed by the processor, the processor implements the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0035] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed, the computer executes the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0036] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, it enables the computer to execute the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0037] In a sixth aspect, an embodiment of the present application provides a chip, comprising: a processor, the processor is coupled to a memory, the memory is used to store instructions, and when the instructions are executed by the processor, the chip implements the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0038] Among them, the technical effects brought about by any implementation method of the second to sixth aspects can refer to the technical effects brought about by the above-mentioned first aspect and its implementation method, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A system architecture diagram provided for an embodiment of the present application; Figure 2 A flowchart of a method 200 provided in an embodiment of the present application; Figure 3 A schematic diagram of a log analysis process of a method 200 provided in an embodiment of the present application; Figure 4 A schematic diagram of the relationship between a hardware set and a resource pool provided in an embodiment of the present application; Figure 5 A schematic diagram of a reasoning process provided in an embodiment of the present application; Figure 6 A schematic diagram of an embodiment provided for the present application; Figure 7 A schematic diagram of the structure of a communication device provided in an embodiment of the present application; Figure 8 Another structural diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0041] References to "one embodiment" or "some embodiments" etc. described in this application mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the application.

[0042] The various embodiments in the present application can be reasonably combined to a certain extent. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in the present specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways.

[0043] The terms "system" and "network" in the embodiments of the present application can be used interchangeably. "Including" means "including but not limited to". When A includes multiple elements or situations, A can be one or more of the elements or situations. For example, if A includes B or C, then A can be B, A can be C, and A can also be B and C. "At least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, "at least one of A, B and C" includes A, B, C, AB, AC, BC or ABC. Also, unless otherwise specified, ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish multiple objects and are not used to limit the order, timing, priority or importance of multiple objects.

[0044] It can be understood that in this application, "indication" can include direct indication, indirect indication, explicit indication, implicit indication. When describing that a certain indication information is used to indicate A, it can be understood that the indication information carries A, directly indicates A, or indirectly indicates A.

[0045] The following are some terms related to the embodiments of the present application for explanation.

[0046] 1. Data Center A data center is a facility designed to house a large number of networked computer devices that work together to process, store, and transmit data. In modern society, most high-tech companies rely on data centers to provide online services such as websites, applications, and cloud services. It can be said that data centers are the core hubs of the Internet. Data centers are physical locations that bring together a large number of computers and network equipment to improve the efficiency of data processing and reduce costs associated with storage, bandwidth, etc.

[0047] In the business world, data centers are an integral part of business operations. They support critical business applications such as customer relationship management, enterprise resource planning, and supply chain management systems. In addition, data centers are also the cornerstone of modern technology trends such as digital transformation, big data analytics, and the Internet of Things.

[0048] On a technical level, data centers are the foundation of cloud computing services, making software as a service, platform as a service, and infrastructure as a service possible. With the popularity of mobile devices and the deployment of 5G networks, the role of data centers in processing and distributing massive amounts of data has become increasingly prominent.

[0049] The application of data centers is becoming more and more extensive, and the demand for improving the performance of data centers is increasing.

[0050] 2. Correctable Errors Correctable errors are errors that can be detected and corrected by the server platform. Correctable errors can be caused by both soft and hard errors and will not disrupt the operation of the server.

[0051] As DRAM-based memories shrink in geometry to increase capacity, an increasing number of correctable errors are expected as a natural part of uniform scaling. In addition, the number of error-generating phenomena is expected to increase due to various other DRAM scaling factors.

[0052] There is a growing consensus in the server industry that some correctable errors are unavoidable and do not necessarily warrant replacing a memory module. Continuing to operate a system reporting correctable errors without rebooting to self-heal does not significantly increase the risk of uncorrectable errors occurring, which can result in unplanned downtime.

[0053] 3. Uncorrectable Errors Uncorrectable errors are multi-bit errors that cannot be corrected by the server platform. These errors can be caused by any combination of soft or hard errors, but are usually caused by multiple hard errors.

[0054] Uncorrectable errors can be classified as: 1. detectable and consumed, 2. detectable and unconsumed, 3. silent and consumed, 4. silent and unconsumed, where consumed errors refer to whether the data has been loaded into the CPU execution path. Unconsumed errors are usually discovered during memory patrol scrubs, but may also be discovered during CPU prefetches. Detectable errors refer to errors that can be detected by the CPU's Error Checking and Correcting (ECC) scheme. Silent errors refer to errors that require the problematic cache execution to meet a very specific bit error pattern, thereby bypassing the CPU's ECC scheme.

[0055] 4. Neural Network Model A neural network model is a model composed of different layers, each of which performs a specific function, thereby realizing layer-by-layer abstraction and processing of input data. A neural network can usually include: an input layer, a hidden layer, or an output layer. A neural network can include multiple hidden layers, and the number of hidden layers depends on the network complexity of the neural network model. The following is a detailed introduction to the input layer, hidden layer, and output layer of a neural network: A. The input layer of a neural network is the first layer of the neural network. In a neural network, each neuron in the input layer corresponds to a feature in the input data. The number of neurons in the input layer depends on the number of features in the input data. For example, in an image classification task, each pixel is a neuron in the input layer. The function of the input layer is to convert the input data into a format that can be processed by the neural network, such as converting image data into vector form. The output of the input layer is the input passed to the next layer of neurons, which can be a hidden layer or an output layer.

[0056] B. The hidden layer of a neural network is one or more layers located between the input layer and the output layer. Its function is to convert the input data into a higher-level feature representation. The number of neurons and the way they are connected in different hidden layers can be different, depending on the specific neural network architecture. The number of hidden layers in a neural network can be 0 or any positive integer. And with the continuous development of the model, the number of layers and hidden layers in the neural network is also increasing. The introduction of hidden layers allows the network to represent complex nonlinear functions and solve problems that linear models cannot handle. Hidden layers mainly include: convolutional layers, fully connected layers, pooling layers, normalized exponential layers or activation layers. The input of the hidden layer is the output of the neurons in the previous layer, where the previous layer can be the input layer or the previous hidden layer. The output of the hidden layer is the input passed to the next layer of neurons, where the next layer can be the next hidden layer or the output layer.

[0057] C. The output layer of the neural network is the last layer in the neural network. Its output is the prediction or classification result of the neural network for the input data. The design of the output layer needs to be adjusted according to the specific task to adapt to different application scenarios.

[0058] The following is an example of the system architecture on which the embodiments of the present application are based.

[0059] To facilitate understanding of the embodiments of the present application, Figure 1 A possible, non-limiting system schematic is shown. Figure 1 The system 100 shown includes: server 101, storage node 102, server 105, server 103 and server 104.

[0060] Optionally, server 101 is a server for operation and maintenance, and can be used to manage server 105, server 103 and server 104. For example, it can be used to predict whether server 105, server 103 and server 104 will have hardware failures, and to report alarms and perform corresponding management when memory failures are predicted.

[0061] Optionally, the storage node 102 may be a storage location on the cloud, and may be used for analyzing logs of servers such as server 105, server 103, and server 104. For example, the storage node 102 may be a disk for distributed storage.

[0062] Optionally, the above-mentioned servers 105, 103 and 104 can be physical servers, and the log information of servers 105, 103 and 104 can be stored in storage node 102, and servers 105, 103 and 104 can be managed through server 101.

[0063] For example, the above-mentioned servers 105, 103 and 104 can store the hardware log information in the storage node 102, and then the server 101 obtains the log information from the storage node 102, and then analyzes the log information to predict whether a hardware failure will occur. If a hardware failure occurs, an alarm is issued.

[0064] At present, hardware failures often occur in large-scale data centers, which leads to a decrease in the stability and reliability of servers and even the entire network infrastructure. Hardware failure is the main cause of server crashes. Whether hardware failures can be accurately predicted in advance has become one of the important issues that the industry needs to study and solve in the cloud computing era. Traditional hardware failure prediction systems predict hardware failures based on system logs of hardware such as memory and hard disks. Generally, hardware with a higher probability of failure is called high-risk hardware. Since high-risk hardware failures account for a high proportion of all hardware failures, predicting the failure probability of high-risk hardware is of great significance to improving the response speed of system prediction.

[0065] In order to predict hardware failures, we can first obtain the error characteristics of the device to be predicted that has multiple hardware correctable errors in the current time window; then aggregate the error characteristics to obtain the aggregated error characteristics; and then predict whether the device to be predicted will have uncorrectable errors based on the aggregated error characteristics, that is, predict whether a hardware failure will occur. However, the amount of data in large-scale data centers is large, and it takes a long time to predict whether uncorrectable errors will occur, resulting in poor timeliness in the prediction of high-risk hardware failures.

[0066] Therefore, how to improve the timeliness of fault prediction for high-risk hardware is a technical problem that needs to be solved urgently.

[0067] In order to solve the above technical problems, the present application proposes a data processing method 200. In the method 200, the first device needs to predict the probability of the first hardware failing. To this end, the first device first obtains the log information of the first hardware, wherein the first hardware is the sum of multiple hardware, and then obtains the historical probability of each hardware failing in the first hardware. For example, the historical probability can be the probability of hardware failing obtained by the previous round of prediction, or the probability of hardware failing obtained by analyzing historical data. Then, the first hardware is sorted according to the size of the historical probability, wherein the larger the historical probability, the higher the ranking of the corresponding first hardware, that is, the hardware with the highest ranking is high-risk hardware. Then, the first device analyzes the log information according to the order of the sorting result from front to back to predict the probability of each hardware in the first hardware failing. Therefore, the probability of high-risk hardware failing is analyzed first in the present application. The priority of high-risk hardware failure analysis is increased in the present application, thereby improving the timeliness of failure prediction of high-risk hardware, improving the response speed of hardware failure prediction, reducing the probability of hardware failure, and improving the stability and reliability of hardware.

[0068] Combine the following Figure 2 The method 200 provided in the embodiment of the present application is specifically described. Optionally, when Figure 2 The method shown is applied to Figure 1 The system shown in Figure 2 The first device in may be server 101 . Figure 2 The method is illustrated by taking the first device as the execution subject of the interaction diagram as an example, but the present application does not limit the execution subject of the interaction diagram. For example, the first device in S201-S204 and related implementations can also be replaced by a chip, a chip system, or a processor that supports the first device to implement the method, and can also be replaced by a logic module or software that can implement all or part of the functions of the first device.

[0069] like Figure 2 As shown, the method 200 provided in the embodiment of the present application includes the following steps: S201, a first device obtains log information of a first hardware; The first hardware includes multiple hardware.

[0070] It should be noted that the above-mentioned first device can be a server, for example, a cloud server, a physical server, etc. A typical application scenario of the present application is that the first device is a server in a data center.

[0071] Optionally, the first hardware includes: a hard disk, a disk, a memory, an optical module, a CPU, a GPU, a TPU or an NPU.

[0072] Optionally, the first hardware may be the hardware of the second device, and the second device may be a server, for example, a physical server or a cloud server. Figure 1 In the system shown, the second device may be server 105 , server 103 and / or server 104 .

[0073] In an optional implementation, the first hardware is a memory.

[0074] Based on the above implementation, this solution can be applied to the scenario of memory fault prediction, which can improve the priority of high-risk memory prediction and improve the timeliness of high-risk memory fault prediction.

[0075] It should be noted that a typical application scenario of the present application is for predicting memory failures, but the present application can also be applied to predicting failures of other hardware, such as optical modules, CPUs and other hardware.

[0076] Optionally, the log information in this application is an exemplary term and can be replaced by any possible term, such as system log, hardware log, etc.

[0077] Optionally, the first device may obtain log information of the first hardware from a storage location on the cloud.

[0078] S202, the first device obtains a historical probability of failure of each hardware in the first hardware; It is understandable that the so-called historical probability refers to the historical probability of hardware failure obtained before the execution of the current round of S203 and S204, for example, it can be the historical probability of hardware failure obtained in the previous round of analysis.

[0079] Optionally, the fault in the present application is an uncorrectable error. When a fault occurs, the server where the first hardware is located will stop or interrupt operation.

[0080] The present application provides a variety of optional methods for obtaining the historical probability of each hardware failure in the first hardware, which are as follows: For example, the first device may obtain a maintenance order for the first hardware, which records hardware failure information, and based on this, the historical probability of failure of each hardware in the first hardware may be calculated.

[0081] Based on the above implementation, the historical probability of each hardware failure can be obtained through the maintenance order, so that the hardware can be sorted according to the historical probability.

[0082] For another example, the historical probability is the probability obtained by analyzing the log information according to the sorting result in the previous i rounds, where i is a positive integer.

[0083] Based on the above implementation, the analysis results of the previous round can be reused, and the historical probability of the first module can be determined without adding new modules, which occupies less computing power resources.

[0084] Optionally, after the following S203 and S204 are executed in the previous round, the probability of the failure occurring in each hardware of the first hardware predicted in step S204 can be used as the historical probability of this round.

[0085] Optionally, if the hardware appears for the first time, the default probability value P is set.

[0086] S203, the first device sorts the first hardware according to the magnitude of the historical probability to obtain a sorting result; Among them, when the historical probability is greater, the corresponding first hardware is ranked higher in the sorting result.

[0087] For example, the first hardware includes hardware 1 and hardware 2. The historical probability of hardware 1 failing is 0.3, and the historical probability of hardware 2 failing is 0.4. Then, hardware 2 is ranked before hardware 1.

[0088] In an optional implementation, the first hardware includes multiple hardware sets, and for each of the hardware sets, the first device sorts the first hardware according to the historical probability of each hardware in the hardware set.

[0089] Based on the above implementation, the first hardware can be divided into multiple hardware sets, and then the hardware can be sorted according to the size of the historical probability of the hardware in each hardware set, that is, each hardware set is sorted separately. Through this distributed sorting method, the efficiency of sorting the hardware can be improved, thereby improving the efficiency of hardware fault analysis.

[0090] For example, the first hardware is 100 memory bars, and the first hardware may include 4 hardware sets, each of which includes 25 memory bars.

[0091] Optionally, the first hardware may be divided into multiple hardware sets according to the number of resource pools.

[0092] For example, the first hardware is 50 memory bars, and the first device has a total of 10 resource pools. Then, the first hardware can be divided into 10 hardware sets, and each hardware set includes 5 memory bars.

[0093] S204: The first device analyzes the log information in order from front to back according to the sorting result to predict the probability of the failure occurring in each hardware in the first hardware.

[0094] It is understandable that before performing fault prediction analysis on the log information, the present application first sorts the hardware according to its historical probability, so that hardware with a high probability of failure, that is, high-risk hardware, is sorted higher, and the probability of failure of high-risk hardware is analyzed first, which increases the priority of high-risk hardware in fault analysis, thereby allowing for more timely prediction of whether high-risk hardware will fail.

[0095] Optionally, the first device may analyze the log information with the aid of a neural network model.

[0096] In an optional implementation, the first device analyzes the log information for each hardware set according to the order from front to back in the ordering result.

[0097] Based on the above implementation, by dividing the hardware into multiple hardware sets and analyzing the log information of the hardware in each hardware set respectively, the efficiency of hardware analysis can be improved through this distributed analysis method, thereby improving the efficiency of hardware fault analysis.

[0098] For example, see Figure 3 ,exist Figure 3 The first hardware in the hardware set includes hardware set 1 and hardware set 2. Hardware set 1 includes hardware m1, hardware m2, hardware m3 and hardware m4. Hardware set 2 includes hardware m5, hardware m6, hardware m7 and hardware m8. When sorting, hardware set 1 and hardware set 2 are sorted respectively. Hardware set 1 is sorted according to the historical probability of hardware failure. The sorting result is: hardware m2->hardware m1->hardware m3->hardware m4. Therefore, when analyzing the log information of the hardware in hardware set 1, hardware failures are analyzed first. The log information of hardware m2 is analyzed first, and then the log information of hardware m1 is analyzed, and then the log information of hardware m3 is analyzed, and finally the log information of hardware m4 is analyzed. Among them, the hardware set 2 is sorted according to the size of the historical probability of hardware failure, and the sorting result is: hardware m8->hardware m6->hardware m7->hardware m5. When analyzing the log information of the hardware in hardware set 2, the log information of hardware m8 is analyzed first, and then the log information of hardware m6 is analyzed, and then the log information of hardware m7 is analyzed, and finally the log information of hardware m5 is analyzed.

[0099] In an optional implementation, the first device analyzes the log information of each hardware in the hardware set in parallel according to the sorting result from front to back.

[0100] Based on the above implementation, the hardware in each hardware set can be analyzed in parallel to predict the probability of hardware failure in each hardware set, so that the resources in the first device can be used to analyze the logs of the hardware in different hardware sets respectively.

[0101] In this application, when analyzing the log information of the hardware to predict whether the hardware will fail, a distributed parallel analysis method is proposed, which can improve resource utilization and make the resources fully used for the analysis of hardware failures.

[0102] Optionally, in this application, there is a corresponding relationship between the hardware set and the resource pool, see Figure 4 ,exist Figure 4 In the example, hardware set 1 corresponds to resource pool 1, that is, the log information of the hardware in hardware set 1 is analyzed by resource pool 1; hardware set 2 corresponds to resource pool 2, that is, the log information of the hardware in hardware set 2 is analyzed by resource pool 2; hardware set 3 corresponds to resource pool 3, that is, the log information of the hardware in hardware set 3 is analyzed by resource pool 3.

[0103] In the above method 200, the first device preferentially analyzes the probability of failure of high-risk hardware, increases the priority of failure analysis of high-risk hardware, thereby improving the timeliness of failure prediction of high-risk hardware, increasing the response speed of hardware failure prediction, reducing the probability of hardware failure, and improving the stability and reliability of the hardware.

[0104] The above method 200 is described below with reference to a specific example: In one example, taking the method 200 as an example of performing parallel reasoning on log information, see Figure 5 In this example, the first device includes the following modules: 1. Data collection and processing platform: The data collection and processing platform is used to collect and process the hardware log information generated in the physical server, and send the collected data to the algorithm platform after processing. The algorithm platform includes a sorting module and a distributed parallel reasoning module.

[0105] 2. Sorting module: divide the hardware into multiple hardware sets, and divide the corresponding logs into corresponding sets in turn. Sort the log information in each hardware set, and send the division and sorting results of the hardware set to the distributed parallel reasoning module for distributed reasoning; 3. Distributed parallel reasoning module: performs distributed parallel reasoning on the received hardware log information; 4. Prediction and alarm platform: Report and manage alarms based on feedback from the algorithm platform; 5. Fault recovery / repair work order: Based on the prediction results of the algorithm platform, the corresponding subsequent disposal strategy is carried out according to the fault level.

[0106] See also Figure 6 , Figure 6 A flow chart of an example provided in this application, Figure 6 The specific process includes: S601: The first device obtains log information of the first hardware of the first server; Optionally, the first hardware includes: a hard disk, a disk, a memory, an optical module, a CPU, a GPU, a TPU or an NPU.

[0107] S602: The first device obtains a historical probability of each hardware failure in the first hardware; It is understandable that the so-called historical probability refers to the historical probability of each hardware failure obtained before the execution of the current round of S602, for example, it can be the historical probability of each hardware failure obtained in the previous round of analysis.

[0108] S603: The first device divides the first hardware into multiple hardware sets; For example, the first hardware is 100 memory bars, and the first hardware may include 4 hardware sets, each of which includes 25 memory bars.

[0109] Optionally, the first device may divide the first hardware into multiple hardware sets according to the number of resource pools.

[0110] S604: The first device sorts the hardware in each hardware set according to the size of the historical probability to obtain a sorting result; For example, the first hardware includes hardware 1 and hardware 2. The historical probability of hardware 1 failing is 0.3, and the historical probability of hardware 2 failing is 0.4. Then, hardware 2 is ranked before hardware 1.

[0111] S605: The first device analyzes the log information according to the sorting result; Optionally, the first hardware may perform distributed parallel reasoning on each hardware set.

[0112] Optionally, the first hardware may analyze the log information through a neural network model.

[0113] After S605 is executed, the probability obtained by the analysis in S605 may be returned to step S604 to be used as the historical probability for the next round.

[0114] S606: The first device determines whether alarm reporting and management are required based on the analysis result.

[0115] For example, when the analysis result indicates that the predicted probability of one or more hardware failures in the first hardware is greater than 60%, an alarm is issued and the failure information of the hardware is reported to the management personnel.

[0116] It can be seen that the present application proposes a hardware fault alarm system that effectively utilizes sorting to improve timeliness, which can be applied to fault prediction systems with huge sample sizes and high timeliness requirements. Priority is given to hardware with fault logs, and predictions are made based on priority, thereby improving the prediction priority of high-risk hardware and improving system timeliness. The present application further proposes a solution for sorting hardware reliability. Specifically, the hardware can be sorted according to the historical probability of hardware failure. The present application proposes a feedback mechanism; the existing prediction system results are used for sorting without the need for new modules, which has little impact on the overall speed of the system.

[0117] Accordingly, the present application also provides a related device for implementing the above solution. Figure 7 , Figure 7 A schematic diagram of the structure of a communication device provided in an embodiment of the present application. Figure 7 The communication device 300 in the embodiment may be a chip, a chip system, or a processor for supporting the communication device to implement the method; or the communication device may also be a logic configuration item, a logic module, or software for implementing all or part of the functions of the communication device. Figure 7 As shown, the communication device 300 includes: an acquisition module 301 , a sorting module 302 and an analysis module 303 .

[0118] For example, when the communication device 300 is the first device in method 200, the acquisition module 301 is used to obtain the log information of the first hardware, which includes multiple hardware; obtain the historical probability of failure of each hardware in the first hardware; the sorting module 302 is used to sort the first hardware according to the size of the historical probability to obtain a sorting result, when the historical probability is larger, the corresponding log information is ranked higher in the sorting result; the analysis module 303 is used to analyze the log information according to the order of the sorting result from front to back to predict the probability of failure of each hardware in the first hardware.

[0119] In an optional implementation, the first hardware includes multiple hardware sets, and the sorting module 302 is specifically used to: for each of the hardware sets, sort the first hardware according to the size of the historical probability of each hardware in the hardware set.

[0120] In an optional implementation, the analysis module 303 is specifically used to: for each of the hardware sets, analyze the log information according to the order from front to back in the ordering result.

[0121] In an optional implementation, the analysis module 303 is specifically configured to analyze the log information of each hardware in the hardware set in parallel according to the order of the sorting result from front to back.

[0122] In an optional implementation, the historical probability is the probability obtained by analyzing the log information in the first i rounds in order from front to back according to the sorting result, where i is a positive integer.

[0123] In an optional implementation, the first hardware is a memory.

[0124] It should be noted that the information interaction, execution process, etc. between the modules / units in the communication device are the same as those in this application. Figure 2 The corresponding method embodiments are based on the same concept. For specific contents, please refer to the description in the method embodiments shown above in this application, which will not be repeated here.

[0125] See also Figure 8 , Figure 8 A schematic diagram of a logical structure of a communication device 40 provided in an embodiment of the present application. Figure 8 The communication device 40 in the embodiment may be deployed with Figure 2 The communication device described in the corresponding embodiment is used to implement Figure 2 The communication device 40 includes a memory 401, a processor 402, a communication interface 403 and a bus 404. The memory 401, the processor 402 and the communication interface 403 are connected to each other through the bus 404.

[0126] The memory 401 may be a read only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 401 may store a program. When the program stored in the memory 401 is executed by the processor 402, the processor 402 and the communication interface 403 are used to execute S201-S204 of the above data processing method embodiment.

[0127] The processor 402 may be a central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components or any combination thereof, for executing related programs to implement one or more steps of S201-S204 of the data processing method embodiment in the present application, or to implement one or more steps of S201-S204 of the data processing method embodiment in the present application. The steps of the data processing method disclosed in the embodiment of the present application may be executed by a compiler and an executor, wherein the compiler and the executor may be executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 401, and the processor 402 reads the information in the memory 401, and executes one or more steps S201-S204 of the data processing method embodiment of the present application in combination with its hardware.

[0128] The communication interface 403 uses a transceiver device such as but not limited to a transceiver to implement communication between the communication device 40 and other devices or communication networks.

[0129] The bus 404 can realize a path for transmitting information between the components of the communication device 40 (for example, the memory 401, the processor 402, and the communication interface 403). The bus 404 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0130] It should be noted that the information interaction and execution process between the modules / units in the controller are the same as those in this application. Figure 2The corresponding method embodiments are based on the same concept. For specific contents, please refer to the description in the method embodiments shown above in this application, which will not be repeated here.

[0131] The present application also provides a computer program product including instructions. The computer program product may be a software or program product including instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the above-mentioned Figure 2 The illustrated embodiments describe the method.

[0132] The present application also provides a computer-readable storage medium. The computer-readable storage medium may be any available medium that can be stored by a computing device or a data storage device such as a data center that contains one or more available media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to execute the above application to execute the above application. Figure 2 The illustrated embodiments describe the method.

[0133] The communication device provided in the embodiment of the present application may be a chip, which includes: a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin or a circuit. The processing unit may execute the computer execution instructions stored in the storage unit to enable the chip to execute the above Figure 2 Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc. The storage unit may also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0134] It should be further noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the device embodiment drawings provided in the embodiments of the present application, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

[0135] Through the description of the above implementation methods, the technicians in the relevant field can clearly understand that the embodiments of the present application can be implemented by means of software plus necessary general hardware, and of course, can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the embodiments of the present application, software program implementation is a better implementation method in more cases. Based on such an understanding, the technical solution of the embodiments of the present application can be essentially or partly contributed to the prior art in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, U disk, mobile hard disk, ROM, RAM, disk or optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, training equipment, or network equipment, etc.) to execute the methods described in each embodiment of the present application.

[0136] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0137] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, training equipment, or data center to another website, computer, training equipment, or data center by wired (e.g., coaxial cable, optical fiber) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device, data center, etc. that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0138] In the various embodiments of the present application, unless otherwise specified or logically conflicting, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

Claims

1. A data processing method, characterized in that: include: Obtaining log information of a first hardware, where the first hardware includes a plurality of hardware; Obtaining a historical probability of failure of each hardware in the first hardware; Sorting the first hardware according to the magnitude of the historical probability to obtain a sorting result, wherein the larger the historical probability is, the higher the ranking of the corresponding first hardware in the sorting result; The log information is analyzed according to the order of the sorting results from front to back to predict the probability of failure of each hardware in the first hardware.

2. The method according to claim 1, characterized in that The first hardware includes a plurality of hardware sets, and the sorting of the first hardware according to the magnitude of the historical probability includes: For each of the hardware sets, the first hardware are sorted according to the historical probability of each hardware in the hardware set.

3. The method according to claim 2, characterized in that The analyzing the log information according to the sorting result in a front-to-back order includes: For each of the hardware sets, the log information is analyzed according to the order from front to back in the ordering result.

4. The method according to claim 2, characterized in that: The analyzing the log information according to the sorting result in a front-to-back order includes: The log information of each hardware in the hardware set is analyzed in parallel according to the order of the sorting results from front to back.

5. The method according to any one of claims 1 to 4, characterized in that: The historical probability is the probability obtained by analyzing the log information in the first i rounds in order from front to back according to the sorting result, and i is a positive integer.

6. The method according to any one of claims 1 to 4, characterized in that The first hardware is a memory.

7. A data processing device, characterized in that: The device comprises: An acquisition module is used to acquire log information of a first hardware, wherein the first hardware includes a plurality of hardware; and acquire a historical probability of failure of each hardware in the first hardware; A sorting module, used for sorting the first hardware according to the size of the historical probability to obtain a sorting result, when the historical probability is larger, the corresponding log information is ranked higher in the sorting result; An analysis module is used to analyze the log information according to the order of the sorting results from front to back to predict the probability of failure of each hardware in the first hardware.

8. The device according to claim 7, characterized in that The first hardware includes a plurality of hardware sets, and the sorting module is specifically used for: For each of the hardware sets, the first hardware are sorted according to the historical probability of each hardware in the hardware set.

9. The device according to claim 8, characterized in that The analysis module is specifically used for: For each of the hardware sets, the log information is analyzed according to the order from front to back in the ordering result.

10. The device according to claim 8, characterized in that The analysis module is specifically used for: The log information of each hardware in the hardware set is analyzed in parallel according to the order of the sorting results from front to back.

11. The device according to any one of claims 7 to 10, characterized in that The historical probability is the probability obtained by analyzing the log information in the first i rounds in order from front to back according to the sorting result, and i is a positive integer.

12. The device according to any one of claims 7 to 10, characterized in that The first hardware is a memory.

13. A communication device, characterized in that: include: Communication interfaces and processors; The communication interface and the processor perform the method according to any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that: The medium stores instructions, and when the instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

15. A computer program product, characterized in that The method comprises instructions, and when the instructions are executed on a processor, the method according to any one of claims 1 to 6 is executed.

16. A chip, characterized in that: The method comprises at least one processing unit and an interface circuit, wherein the interface circuit is used to provide program instructions or data to the at least one processing unit, and the at least one processing unit is used to execute the program instructions to implement the method according to any one of claims 1 to 6.

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