Address writing method and device, storage medium and chip

Abstract

The embodiment of the invention provides an address writing method and device, a storage medium and a chip. The method comprises the steps of determining data information of a to-be-written receiving frame and index information of the receiving frame; the data information and the index information are written into an available cache region address pointed by target identification information of an available cache region, and the available cache region address is used for storing the data information; target index information data corresponding to the index information in a linked list bitmap is determined, the linked list bitmap comprises multiple pieces of sorted index information data, and each piece of index information data in the multiple pieces of index information data comprises an effective identifier and an identifier information pointer; and setting an effective identifier in the target index information data as an effective identifier value, and writing the first piece of identifier information in the target identifier information into an identifier information pointer in the target index information data.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular, to an address writing method, device, storage medium and chip. Background Art

[0002] In the reordering scenario during the design of the Application-Specific Integrated Circuit (ASIC) chip, a linked list structure is generally used for reordering resource management. Since the sequence number (Num) of the received frame is a random value within a certain range, and the frame length of each frame is not fixed. When inserting the newly arrived received frame between two cached frames, the insertion operation of the intermediate node of the linked list is required. When the general linked list structure implements the function of inserting the intermediate node of the linked list, it is necessary to read the data of each node one by one from the head of the linked list to find two consecutive nodes, where the Num of the previous node is less than the Num of the received frame, and the Num of the next node is greater than the Num of the received frame. Then the pointer (next_pointer) pointing to the next node in the previous node points to the address assigned to the node, and the next_pointer of the node points to the address of the next node. The disadvantage of this method is that the efficiency of the linked list insertion operation is low, and it is not suitable for high-performance reordering scenarios. For the reordering of n received frames, its time complexity is O(n 2 ).

[0003] Regarding the related technology, the existing linked list structure reordering scheme has a low efficiency in linked list insertion operation, and is therefore not suitable for high-performance reordering scenarios. No effective solution has been proposed yet.

[0004] Therefore, it is necessary to improve the related technology to overcome the above-mentioned defects in the related technology. Summary of the invention

[0005] The embodiments of the present application provide an address writing method, device, storage medium and chip to at least solve the problem that the linked list insertion operation of the existing linked list structure reordering scheme is inefficient and thus not suitable for high-performance reordering scenarios.

[0006] According to one aspect of an embodiment of the present application, an address writing method is provided, comprising: determining data information of a received frame to be written and index information of the received frame; writing the data information and the index information into an available cache address pointed to by target identification information of an available cache, wherein the available cache address is used to store the data information; determining target index information data corresponding to the index information in a linked list bitmap, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each of the plurality of index information data includes: a valid identifier and an identifier information pointer; setting the valid identifier in the target index information data to a valid identifier value, and writing the first identifier in the target identifier information into the identifier information pointer in the target index information data.

[0007] In an exemplary embodiment, the data information and the index information are written to the available cache address pointed to by the target identification information of the available cache, including: determining the size relationship between the length value of the data information and a preset value; when the length value is less than the preset value, obtaining any identification information in the identification information queue as the target identification information, wherein the identification information queue records all the identification information of the available cache; writing the data information and the index information to the available cache address pointed to by any identification information; when the length value is greater than or equal to the preset value, slicing the data information according to the length value to obtain multiple data information slices; writing the multiple data information slices and the index information to the available cache address pointed to by the target identification information of the available cache.

[0008] In an exemplary embodiment, multiple data information fragments and the index information are written into the available cache area address pointed to by the target identification information of the available cache area, including: for each data information fragment among the multiple data information fragments: determining the fragment number corresponding to each data information fragment according to the fragment order of the multiple data information fragments; writing each data information fragment, the fragment number, and the index information into the available cache area address pointed to by the target identification information of the available cache area.

[0009] In an exemplary embodiment, after writing the data information and the index information into the available cache area address pointed to by any identification information, the method further includes: setting the shard field in the available cache area address to a first value, and setting the identification information field in the available cache area address to a null value, wherein the shard field is set to the first value to indicate that what is written to the available cache area address is not a data information shard, or that the data information shard written to the available cache area address is the last data information shard.

[0010] In an exemplary embodiment, each data information fragment, the fragment number, and the index number are written into the available cache area address pointed to by the target identification information of the available cache area, including: obtaining m identification information from the identification information queue, and determining the m identification information as the target identification information, wherein each data information fragment in the multiple data information fragments corresponds one-to-one to each identification information in the m identification information, and m is an integer greater than 1; for each data information fragment: writing each data information fragment, the fragment number, and the index information into the available cache area address pointed to by each identification information corresponding to each data information fragment.

[0011] In an exemplary embodiment, each data information fragment, the fragment number, and the index number are written into the available cache area address pointed to by the target identification information of the available cache area, including: obtaining n identification information from the identification information queue, wherein the n identification information is used to ensure that in the process of writing the kth data information fragment among the multiple data information fragments into the Kth available cache area address pointed to by the kth identification information among the n identification information, there is identification information corresponding to the nth data information fragment in the identification information field that can be written to the kth available cache area address in the n identification information, wherein the identification information field is used to indicate the identification information corresponding to the next data information fragment of the kth data information fragment, and n is an integer greater than 1, and n is less than m. , k=n-1; when the kth data information fragment has been written into the available cache area, determine whether the current length value is greater than or equal to the preset value, wherein the current length value is used to indicate the length value obtained by updating the length value after any data information fragment among the multiple data information fragments is written into the available cache area address pointed to by the target identification information; when the current length value is greater than or equal to the preset value, write the wth data information fragment, the fragment number corresponding to the wth data information fragment, and the index information into the available cache area address pointed to by any identification information, wherein the arbitrary identification information is any identification information in the identification information queue that has not been acquired, and the multiple data information fragments include the wth data information fragment, w=n+1.

[0012] In an exemplary embodiment, after writing each data information fragment, the fragment number, and the index number into the available cache address pointed to by the target identification information of the available cache, the method further includes: determining whether each data information fragment is the last data information fragment; if each data information fragment is the last data information fragment, determining the target available cache address to which each data information fragment is written; setting the fragment field in the target available cache address to a first value, and setting the identification information field in the target available cache address to a null value, wherein the fragment field is set to the first value to indicate that the target available cache address is written. The data information fragment written into the target available cache area address is not a data information fragment, or the data information fragment written into the target available cache area address is the last data information fragment; in the case that each data information fragment is not the last data information fragment, the target available cache area address to which each data information fragment is written is determined; the fragment field in the target available cache area address is set to a second value, and the identification information field in the target available cache area address is written as the identification information of the available cache area to which the next data information fragment corresponding to each data information fragment is expected to be written, wherein the fragment field is set to the second value to indicate that the data information fragment written into the target available cache area address is not the last data information fragment.

[0013] In an exemplary embodiment, the first identification information in the target identification information is written into the identification information pointer in the target index information data, including: when the length value is less than a preset value, any identification information is determined as the first identification information and written into the identification information pointer in the target index information data; when the length value is greater than or equal to the preset value, the first identification information obtained in the target identification information is used as the first identification information and written into the identification information pointer in the target index information data.

[0014] According to another aspect of the embodiment of the present application, an address writing device is also provided, including: a first determination module, used to determine the data information of the received frame to be written and the index information of the received frame; a first writing module, used to write the data information and the index information into the available cache address pointed to by the target identification information of the available cache, wherein the available cache address is used to store the data information; a second determination module, used to determine the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identifier and an identifier information pointer; a second writing module, used to set the valid identifier in the target index information data to a valid identifier value, and write the first identifier in the target identifier information into the identifier information pointer in the target index information data.

[0015] According to another aspect of the embodiments of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the above-mentioned address writing method when running.

[0016] According to another aspect of the embodiments of the present application, a chip is provided, comprising the above-mentioned address writing device.

[0017] Through the present application, the data information of the received frame to be written and the index information of the received frame are determined; the data information and the index information are written into the available cache address pointed to by the target identification information of the available cache, wherein the available cache address is used to store the data information; the target index information data corresponding to the index information in the linked list bitmap is determined, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identification and an identification information pointer; the valid identification in the target index information data is set to a valid identification value, and the first identification information in the target identification information is written into the identification information pointer in the target index information data. That is to say, in the case of a received frame to be written, the data information of the received frame is written into the available cache address, and the first identification information in the target identification information of the available cache address is written into the index information data corresponding to the received frame in the plurality of index information data that have been sorted included in the linked list bitmap, which solves the technical problem that the linked list insertion operation of the existing linked list structure reordering scheme is low in efficiency and thus not suitable for high-performance reordering scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The exemplary embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 It is a hardware structure block diagram of a chip of the address writing method of an embodiment of the present application;

[0020] Figure 2 is a flowchart of an address writing method according to an embodiment of the present application;

[0021] Figure 3 It is a schematic diagram of the internal structure of an embodiment of the present application;

[0022] Figure 4 is a flow chart of an embodiment of an address writing method according to an embodiment of the present application;

[0023] Figure 5 1 is a schematic diagram of a specific embodiment of the address writing method according to an embodiment of the present application (I);

[0024] Figure 6 2 is a schematic diagram of a specific embodiment of the address writing method according to an embodiment of the present application;

[0025] Figure 7 3 is a schematic diagram of a specific embodiment of the address writing method according to an embodiment of the present application;

[0026] Figure 8 It is a structural block diagram of an address writing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] The method embodiments provided in the embodiments of the present application can be executed in a chip or a similar computing device to implement the reordering process of the receiving side hardware for the received frames during chip operation. The chips may include but are not limited to: Wireless Fidelity (WIFI) chips, Ethernet switching chips, routing chips, etc.; the devices that can run on the above chips include but are not limited to: WIFI devices, Ethernet switches, routers, general serial communication devices, etc. The above chips are suitable for the field of network communications. Taking running on a chip as an example, Figure 1 is a hardware structure block diagram of a chip of the address writing method of the embodiment of the present application. Figure 1 As shown, the chip may include one or more ( Figure 1 Only one is shown in the figure) processor 102 (processor 102 may include but is not limited to a microprocessor (Microprocessor Unit, referred to as MPU) or a programmable logic device (Programmable logic device, referred to as PLD)) and a memory 104 for storing data. In an exemplary embodiment, the above chip may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above chip. Figure 1 More or fewer components as shown, or with Figure 1 Equivalent functions or comparisons shown Figure 1 A different configuration with more features is shown.

[0030] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the chip corresponding to the address writing method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the chip via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0031] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by the communication provider of the chip. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet wirelessly.

[0032] Figure 2 is a flow chart of an address writing method according to an embodiment of the present application, such as Figure 2 As shown, the steps of the method are applied to the above chip, including:

[0033] Step S202, determining data information of a received frame to be written and index information of the received frame;

[0034] Step S204, writing the data information and the index information into the available cache address pointed to by the target identification information of the available cache, wherein the available cache address is used to store the data information;

[0035] Step S206, determining the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each of the plurality of index information data includes: a valid identifier and an identifier information pointer;

[0036] Step S208, setting the valid identification in the target index information data to a valid identification value, and writing the first identification information in the target identification information into the identification information pointer in the target index information data.

[0037] The embodiment of the present application determines the data information of the received frame to be written and the index information of the received frame through the above steps; writes the data information and the index information into the available cache address pointed to by the target identification information of the available cache, wherein the available cache address is used to store the data information; determines the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identification and an identification information pointer; sets the valid identification in the target index information data to a valid identification value, and writes the first identification information in the target identification information into the identification information pointer in the target index information data. That is to say, in the case of a received frame to be written, the data information of the received frame is written into the available cache address, and the first identification information in the target identification information of the available cache address is written into the index information data corresponding to the received frame in the plurality of index information data that have been sorted included in the linked list bitmap, which solves the technical problem that the linked list insertion operation of the existing linked list structure reordering scheme is low in efficiency and thus not suitable for high-performance reordering scenarios.

[0038] In an exemplary embodiment, the technical solution for writing the data information and the index information into the available cache area address pointed to by the target identification information of the available cache area in step S204 specifically includes the following steps: determining the size relationship between the length value of the data information and a preset value; when the length value is less than the preset value, obtaining any identification information in the identification information queue as the target identification information, wherein the identification information queue records all the identification information of the available cache area; writing the data information and the index information into the available cache area address pointed to by any identification information; when the length value is greater than or equal to the preset value, fragmenting the data information according to the length value to obtain multiple data information fragments; writing the multiple data information fragments and the index information into the available cache area address pointed to by the target identification information of the available cache area.

[0039] Optionally, the preset value can be selected as 2. In this case, when the length of the data information of the receiving frame to be written is less than 2, the data information can be written only to an available cache address, and then any identification information is selected from the identification information queue as the target identification information, and the data information and the index information of the receiving frame to be written are written to the available cache address pointed to by any identification information. Among them, the identification information queue records all the identification information of the available cache area, which means that the identification information queue records the identification information corresponding to the available cache area, and the available cache area corresponding to the available cache address to which the data information and other data have been written can be understood as no longer available (in the case of no other operations: such as data information clearing operations, etc.), and the identification information queue does not include the identification information corresponding to the available cache area to which the data information has been written.

[0040] When the length of the data information is greater than or equal to 2, the data information is segmented according to the actual length of the data information (i.e., the length value). For example, if the length value of the data information is 5, the data information is segmented into 5 data information segments, and if the length of the data information is 8, the data information is segmented into 8 data information segments. The multiple data information segments and index information obtained according to the length value are written to the available buffer address pointed to by the target identification information obtained from the identification information queue.

[0041] It should be noted that in the embodiment of the present application, the preset value of 2 is preferred, but it is not used to limit the present application, that is, the preset value can be 3, 5, 6, etc. The setting of the preset value can be determined according to the memory and processing power of the device used to execute the address writing method in the embodiment of the present application. The preset value selection of 2 is only used to ensure that when the data information is written to the available cache address in fragments, the first written data information fragment has at least one identification information that can be pointed to and corresponds to the available cache address to which the next data information fragment may be written. It can be further clarified that if the preset value is selected as 3, it can be made that in the process of writing the second written data information fragment to the available cache address, there is identification information that can be pointed to and corresponds to the available cache address to which the third written data information fragment will be written.

[0042] In an exemplary embodiment, multiple data information fragments and the index information are written into the available cache area address pointed to by the target identification information of the available cache area, including: for each data information fragment among the multiple data information fragments: determining the fragment number corresponding to each data information fragment according to the fragment order of the multiple data information fragments; writing each data information fragment, the fragment number, and the index information into the available cache area address pointed to by the target identification information of the available cache area.

[0043] It is understandable that in the process of slicing data information, each of the multiple data information slicing has a corresponding slicing number, and the slicing number of each data information slicing is related to the order in which each data information slicing is sliced. For example, the slicing number corresponding to the first data information slicing obtained in the slicing process is 1, and the slicing number of the second data information slicing obtained is 2, and so on. It should be noted that the slicing of data information is slicing in order from beginning to end. The numbering of data information needs to be characters in a certain order, which can be Arabic numerals: such as 1, 2, 3,..., or English letters: such as A, B, C, D..., or a combination of numbers and letters, etc., which is not limited in this embodiment of the present application. Furthermore, in the process of actually writing each data information slicing to the available cache address, the information that needs to be written includes: data information slicing, slicing number, index information.

[0044] In an exemplary embodiment, after writing the data information and the index information into the available cache area address pointed to by any identification information, the method further includes: setting the shard field in the available cache area address to a first value, and setting the identification information field in the available cache area address to a null value, wherein the shard field is set to the first value to indicate that what is written to the available cache area address is not a data information shard, or that the data information shard written to the available cache area address is the last data information shard.

[0045] It should be noted that the fragment field in the available cache address is used to indicate whether the data information fragment written to the current available cache address is a data information fragment according to the current value of the field; the identification information pointer is used to indicate: when the data information fragment written to the current available cache address is the target data information fragment, but the target data information fragment is not the last data information fragment among all data information fragments, the pointer of the identification information corresponding to the available cache address to which the next target data information fragment of the target data information fragment should be written. In other words, it is essentially a chain pointer for chaining all data information fragments (equivalent to multiple data information fragments).

[0046] It can be understood that when the preset value is 2, one available buffer area can meet the writing demand of data information. Therefore, any identification information is selected from the identification information of the available buffer area in the identification information queue, and the data information fragment is written to the available buffer area address pointed to by any identification information. After writing, the fragment field of the available buffer area address is set to a first value, and the first value is preferably 0, which is used to indicate that what is written to the available buffer area address is not a data information fragment, but a complete data information in the embodiment of the present application. The identification information field in the available buffer area address to which the complete data information is written does not need to point to the identification information where the next data information fragment is located, and is therefore set to a null value. For example, the null value can be replaced by 0.

[0047] Exemplarily, the write row format of data information and the like written to the available cache address is, for example: {0, 0, info[x]}, wherein the first "0" is used to indicate that what is written to the available cache address is not a data information fragment but complete data information, and the second "0" is used to indicate that there is no identification information corresponding to the available cache area to which the next data information fragment of the current data information fragment is written that needs to be pointed to, "info" represents data information, and "x" represents index information.

[0048] Regarding the writing of data information fragments, in a preferred embodiment, each data information fragment, the fragment number, and the index number are written into the available cache area address pointed to by the target identification information of the available cache area, including: obtaining m identification information from the identification information queue, and determining the m identification information as the target identification information, wherein each data information fragment in the multiple data information fragments corresponds one-to-one to each identification information in the m identification information, and m is an integer greater than 1; for each data information fragment: writing each data information fragment, the fragment number, and the index information into the available cache area address pointed to by each identification information corresponding to each data information fragment.

[0049] When the data information is segmented according to the length value and the length value is m, m data information segments will be generated. Accordingly, it is necessary to obtain m identification information from the identification information queue to store the m data information segments in the available buffer addresses pointed to by the m identification information, and then the m identification information can be used together as the target identification information. Generally speaking, data information needs to be segmented only when the length value is greater than 1, so m is an integer greater than 1. After clarifying the composition of the target identification information, each data information segment, the segment number of the data information segment corresponding to each data information, and the index information should be written to the available buffer address pointed to by each identification information corresponding to each data information segment.

[0050] Regarding the writing of data information fragments, in another preferred embodiment, each data information fragment, the fragment number, and the index number are written into the available cache area address pointed to by the target identification information of the available cache area, and it also includes: obtaining n identification information from the identification information queue, wherein the n identification information is used to ensure that in the process of writing the kth data information fragment among the multiple data information fragments to the Kth available cache area address pointed to by the kth identification information among the n identification information, there is identification information corresponding to the nth data information fragment in the identification information field that can be written to the kth available cache area address in the n identification information, wherein the identification information field is used to indicate the identification information corresponding to the next data information fragment of the kth data information fragment, and n is greater than 1. integer, and n is less than m, k=n-1; when the kth data information fragment has been written into the available cache area, determine whether the current length value is greater than or equal to the preset value, wherein the current length value is used to indicate the length value obtained by updating the length value after any data information fragment among the multiple data information fragments is written into the available cache area address pointed to by the target identification information; when the current length value is greater than or equal to the preset value, write the wth data information fragment, the fragment number corresponding to the wth data information fragment, and the index information into the available cache area address pointed to by any identification information, wherein the arbitrary identification information is any identification information in the identification information queue that has not been obtained, and the multiple data information fragments include the wth data information fragment, w=n+1.

[0051] In the case where there are m data information fragments, n identification information can also be obtained from the identification information queue in priority, so that at least when the kth data information fragment among the m data information is written to the kth available cache address, there is the (k+1)th identification information corresponding to the (k+1)th data information fragment in the identification information field that can be written to the kth available cache address, so that in the subsequent reading process of the data information, under the guidance of the identification information field (equivalent to the identification information pointer), the data information fragments with the same fragment order can be read in sequence. For example, if there are 10 data information fragments, two identification information can be obtained first, and then in the process of writing the first data information fragment to the available cache address pointed to by the first identification information, the identification information corresponding to the second data information fragment is written to the identification information field of the first available cache address.

[0052] It should be noted that, each time a data information segment is written into an available buffer address, the length value of the data information segment will be reduced by 1 accordingly. Furthermore, when there are 10 data information fragments and 2 identification information are obtained first, after the first data information fragment is written into the available cache area, the current length value = 10-1 = 9. If the preset value is 2, the length value is still greater than the preset value, and it is necessary to continue to select any identification information from the remaining identification information in the identification information queue, wherein the remaining identification information is the identification information remaining in the identification information queue after n identification information are taken away (which can be essentially understood as the current identification information queue); the arbitrary identification information is used as the (n+1)th identification information to point to the (n+1)th available cache area address that should be written into the (n+1)th data information fragment, and is also used to be written into the identification information field of the nth available cache area address, so that in the subsequent reading process of the data information fragments, the (n+1)th available cache area address carrying the (n+1)th data information fragment can be found based on the nth available cache area address.

[0053] In an exemplary embodiment, after writing each data information fragment, the fragment number, and the index number into the available cache address pointed to by the target identification information of the available cache, the method further includes: determining whether each data information fragment is the last data information fragment; if each data information fragment is the last data information fragment, determining the target available cache address to which each data information fragment is written; setting the fragment field in the target available cache address to a first value, and setting the identification information field in the target available cache address to a null value, wherein the fragment field is set to the first value to indicate that the target available cache address is written. The data information fragment written into the target available cache area address is not a data information fragment, or the data information fragment written into the target available cache area address is the last data information fragment; in the case that each data information fragment is not the last data information fragment, the target available cache area address to which each data information fragment is written is determined; the fragment field in the target available cache area address is set to a second value, and the identification information field in the target available cache area address is written as the identification information of the available cache area to which the next data information fragment corresponding to each data information fragment is expected to be written, wherein the fragment field is set to the second value to indicate that the data information fragment written into the target available cache area address is not the last data information fragment.

[0054] It is understandable that in the process of writing data information fragments to the available cache area address, there are two situations: the data information fragment currently being written is not the last data information fragment, and the data information fragment currently being written is the last data information fragment.

[0055] For the case where it is the last data information fragment: the fragment field in the target available cache address being written should be set to the second value, indicating that the target available cache address is the last data information fragment written, and the identification information field of the target available cache should be set to a null value, because the last data information does not exist to point to the next data information fragment. For example: the field representation in the available cache address can be: {0, 0, info[x, y], 0 is used to represent the first value, that is, the current data information fragment is the last data information fragment, 0 indicates that when the target available cache address is the last data information fragment written, there is no identification information corresponding to the available cache address to which the next data information fragment that needs to be pointed does not exist, info represents the data information, x represents the index information, y represents the fragment number corresponding to the last data information fragment;

[0056] In the case where it is not the last data information fragment, the fragment field of the target available cache address is written as the first value, which is used to indicate that the data information fragment written in the target available cache address is not the last data information fragment, and the identification information field in the target available cache address should be written as the identification information of the available cache area to which the next data information fragment corresponding to the data information fragment written in the target available cache is expected to be written. For example: the field representation format in the available cache address can be: {1, ID[n+1], info[x, y]}, 1 is used to represent the second value, that is, the current data information fragment is not the last data information fragment, ID[n+1] represents the identification information corresponding to the (n+1)th data information fragment when the nth data information fragment is written in the target available cache address, info represents data information, x represents index information, and y represents the fragment number corresponding to the nth data information fragment.

[0057] In an exemplary embodiment, the first identification information in the target identification information is written into the identification information pointer in the target index information data, including: when the length value is less than a preset value, any identification information is determined as the first identification information and written into the identification information pointer in the target index information data; when the length value is greater than or equal to the preset value, the first identification information obtained in the target identification information is used as the first identification information and written into the identification information pointer in the target index information data.

[0058] It can be understood that if the data information does not need to be fragmented and is directly written into the address of the available cache area, then the identification information pointer in the index information data corresponding to the data information in the linked list bitmap only needs to point to the available cache area where the data information is written, and then the identification information pointer is written with any of the aforementioned identification information.

[0059] If the data information needs to be fragmented, the identification information pointer needs to point to the available buffer area where the first data information fragment is written. Since the identification information of the available buffer area may be obtained out of order, the identification information pointer needs to write the first obtained identification information.

[0060] Next, the address writing method is further described in conjunction with the following optional embodiments.

[0061] The optional embodiment of the present application is designed for the front-end development of an ASIC chip, and is used to implement the function of reordering received frames by the receiving side hardware in the operation of a wireless local area network (Wireless Fidelity, referred to as WIFI) chip.

[0062] The internal structure of the optional embodiment of the present application is as follows Figure 3 As shown, it is composed of three storage units: a linked list bitmap (bitmap), an available buffer area (info_buffer) and an available buffer area identification queue (ID Fifo).

[0063] The valid flag (valid) of each data storage linked list corresponding node of the bitmap and the linked list node (info_ptr) allocated to the descriptor (equivalent to the identification information pointer in the above embodiment), valid is 1, indicating that the data information (info) corresponding to the index information (Num) has been received, and the info_ptr is valid at this time.

[0064] Info_buffer stores info resource blocks, and also stores the chain information in info when the info lengths are not equal and multiple resource blocks are required to store them. Each buffer storage content consists of three parts: {next_vld, next_ID, info}, where next_vld is used to indicate whether it is the last data information fragment, or whether it is a data information fragment; next_ID is used to indicate the identification information corresponding to the next data information fragment of the currently stored data information fragment. Info can be the frame body of the received frame itself (equivalent to the data information or data information fragment in the above embodiment), or indicate the relevant information stored in the received frame.

[0065] The ID FIFO maintains the number and serial number of resource blocks that can be allocated in the info buffer (equivalent to the available buffer addresses in the above embodiment). Figure 3 The identifier information queue 0, 3, 6, 8 corresponds to the available buffer area address (addr) 0, 3, 6, 8 in the available buffer area.

[0066] Optionally, next_vld, next_ID and info of info_buffer in an optional embodiment of the present application can be divided into three storage units.

[0067] The optional embodiment of the present application adopts Figure 4 The process shown adopts a serial processing method, which specifically includes the following steps:

[0068] Step S401, initializing the identification information queue.

[0069] The ID Fifo is initialized and written with 0, 1, 2, etc. in sequence until it is full.

[0070] Step S402: Data information and index information are input. The input info and corresponding Num are received.

[0071] Step S403: whether the length value of the data information is greater than 2. If it is greater than 2, execute step S404; if it is less than 2, execute step S405.

[0072] Step S404, apply for 2 available identification information (ID[n], ID[n+1]) from the identification information queue.

[0073] If the info length (info_length) is greater than 2 info_buffer resource blocks, two available buffer IDs are requested from the ID FIFO, which are recorded as ID[n] and ID[n+1]. Go to step S406.

[0074] Step S405: Apply for one available identification information from the identification information queue. Directly proceed to S408.

[0075] If the length of info is 1 info_buffer resource block, only 1 buffer ID is applied. The first applied ID is ID_head.

[0076] Step S406, {1, ID[n+1], info[x, y]} is written into the available buffer address, and the length value of the data information is reduced by 1, n=n+1, y=y+1.

[0077] Take the first resource block of info and record it as info[x,y], where x represents the Num of info and y represents the fragment number in info. Write the field {1, ID[n+1], info[x,y]} to the ID[n] address of info_buffer, where 1 represents the info storage fragment. At this time, ID[n+1] is valid, indicating the address of the next fragment (info[x,y+1]). After writing, info_length is reduced by 1; y and n are increased by 1, indicating that the next info fragment is ready.

[0078] Step S407, continue to determine whether the length of the data information is greater than 2. If it is determined to be greater than 2, proceed to step S409; if it is determined to be less than 2, proceed to step S408.

[0079] If info_length is greater than 2, apply for 1 buffer ID (ID[n+1]) from the ID FIFO and then repeat step S406; otherwise, proceed to step S408.

[0080] Step S408, the available buffer address of the available buffer is written into {0,0,info[x,y]}, and the process proceeds to step S410.

[0081] Write {0, 0, info[x, y]} to the ID[n] address of info_buffer. The first 0 indicates the last info fragment.

[0082] Step S409: Apply for the next available identification information from the identification information queue.

[0083] Step S410, {1, the first ID} is written into the index information data in the linked list bitmap.

[0084] It should be noted that, in the above steps S401 to S410, if it is not explicitly stated that a step needs to be skipped, it needs to be executed in sequence.

[0085] The bitmap's Num address is written as {1, ID_head}, where 1 indicates that the Num has received info, and ID_head is the first address of info in info_buffer.

[0086] A specific embodiment is given below to explain the above embodiment. In the specific embodiment, the linked list structure receives info of Num=0, Num=4, and Num=2 in sequence, wherein the info of Num=2 requires two buffers to store.

[0087] 1. Receive info[0] with Num=0, apply for a buffer ID(0) from ID FIFO, write info[0] to info_buffer address 0, and write data {0,0,info[0]}. Write {1,0} to bitmap[0], such as Figure 5 shown.

[0088] 2. After receiving info[4] with Num=4, request a buffer ID(3) from the ID FIFO, write info[4] to info_buffer address 3, and write data {0,0,info[4]}. Write bitmap[4] to {1,3}, such as Figure 6 shown.

[0089] 3. Receive info[2] with Num=2, apply for 2 buffer IDs (6, 8) from ID FIFO, write info[2.0] to info_buffer address 6, and write data {1, 8, info[2.0]}, where 1 indicates the next info fragment, and 8 indicates the address of the next fragment is 8; write info[2.1] to info_buffer address 8, and write data {0, 0, info[2.1]}. Bitmap[2] is written to {1, 6}, such as Figure 7 shown.

[0090] Furthermore, based on the address writing method given in the above optional embodiment, the corresponding output process is: when the output condition is met, the bitmap is shifted. If the removed field contains a valid indication, the info output is read from the infobuffer according to the corresponding ID. If the next_vld of the obtained info is 0, the bitmap continues to be shifted; if the next_vld of the obtained info is 1, the next info fragment is obtained according to the next ID until the fragment has a tail info indication (next_vld is 0).

[0091] Furthermore, the implementation method and device of the fast insertion and hanging chain of the linked list structure provided in the optional embodiment of the present application meet the requirements of the reordering service for fast insertion and hanging chain in the ASIC front-end design. Specifically, the embodiment of the present application adopts a linked list structure facing the scene of variable frame length, and completes the reordering of received frames by inserting a linked list in the middle of the linked list instead of inserting a node in a linked list, thereby improving the reordering performance. The delay of each insertion and hanging chain is a fixed value, and the time complexity for reordering n received frames is O(n).

[0092] Therefore, compared with the prior art, the insertion delay of each received frame in the optional embodiment of the present application is a fixed value, which meets the requirements of the WIFI receiving side chip for the flow and delay stability of the received frame reordering.

[0093] In the present embodiment, an address writing device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the equipment described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0094] Figure 8 is a structural block diagram of an address writing device according to an embodiment of the present application. Figure 8 As shown, the address writing device includes:

[0095] A first determining module 82, used to determine data information of a received frame to be written and index information of the received frame;

[0096] A first writing module 84, used for writing the data information and the index information into an available cache address pointed to by the target identification information of the available cache, wherein the available cache address is used for storing the data information;

[0097] A second determination module 86 is used to determine the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each of the plurality of index information data includes: a valid identifier and an identifier information pointer;

[0098] The second writing module 88 is used to set the valid identification in the target index information data to a valid identification value, and write the first identification information in the target identification information into the identification information pointer in the target index information data.

[0099] The present application determines the data information of the received frame to be written and the index information of the received frame through the above module; writes the data information and the index information into the available cache address pointed to by the target identification information of the available cache, wherein the available cache address is used to store the data information; determines the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each index information data in the plurality of index information data includes: a valid identification and an identification information pointer; sets the valid identification in the target index information data to a valid identification value, and writes the first identification information in the target identification information into the identification information pointer in the target index information data. That is to say, in the case of a received frame to be written, the data information of the received frame is written into the available cache address, and the first identification information in the target identification information of the available cache address is written into the index information data corresponding to the received frame in the plurality of index information data that have been sorted included in the linked list bitmap, which solves the technical problem that the linked list insertion operation of the existing linked list structure reordering scheme is low in efficiency and thus not suitable for high-performance reordering scenarios.

[0100] In an exemplary embodiment, the first writing module 84 is also used to determine the size relationship between the length value of the data information and a preset value; when the length value is less than the preset value, obtain any identification information in the identification information queue as the target identification information, wherein the identification information queue records all identification information of the available cache area; write the data information and the index information into the available cache area address pointed to by any identification information; when the length value is greater than or equal to the preset value, slice the data information according to the length value to obtain multiple data information slices; write the multiple data information slices and the index information into the available cache area address pointed to by the target identification information of the available cache area.

[0101] In an exemplary embodiment, the first writing module 84 is also used to: for each data information fragment among the multiple data information fragments: determine the fragment number corresponding to each data information fragment according to the fragment order of the multiple data information fragments; write each data information fragment, the fragment number, and the index information into the available cache area address pointed to by the target identification information of the available cache area.

[0102] In an exemplary embodiment, the above-mentioned device also includes a setting module, which is used to set the fragment field in the available cache area address to a first value, and set the identification information field in the available cache area address to a null value, wherein the fragment field is set to the first value to indicate that the data information fragment written to the available cache area address is not a data information fragment, or that the data information fragment written to the available cache area address is the last data information fragment.

[0103] In an exemplary embodiment, the first writing module 84 is also used to obtain m identification information from the identification information queue and determine the m identification information as the target identification information, wherein each data information slice in the multiple data information slices corresponds one-to-one to each identification information in the m identification information, and m is an integer greater than 1; for each data information slice: write each data information slice, the slice number, and the index information into the available cache area address pointed to by each identification information corresponding to each data information slice.

[0104] In an exemplary embodiment, the first writing module 84 is further used to obtain n identification information from the identification information queue, wherein the n identification information is used to ensure that in the process of writing the kth data information fragment among the multiple data information fragments to the Kth available cache area address pointed to by the kth identification information among the n identification information, there is identification information corresponding to the nth data information fragment in the identification information field that can be written to the kth available cache area address among the n identification information, wherein the identification information field is used to indicate the identification information corresponding to the next data information fragment of the kth data information fragment, n is an integer greater than 1, and n is less than m, k=n-1; when the kth data information fragment has been written In the case where the w-th data information fragment is written to the available cache area address pointed to by the target identification information, determine whether the current length value is greater than or equal to the preset value, wherein the current length value is used to indicate the length value obtained by updating the length value after any data information fragment among the multiple data information fragments is written to the available cache area address pointed to by the target identification information; in the case where the current length value is greater than or equal to the preset value, write the w-th data information fragment, the fragment number corresponding to the w-th data information fragment, and the index information into the available cache area address pointed to by any identification information, wherein the arbitrary identification information is any identification information in the identification information queue that has not been obtained, and the multiple data information fragments include the w-th data information fragment, and w=n+1.

[0105] In an exemplary embodiment, the setting module is also used to determine whether each of the data information fragments is the last data information fragment; if each of the data information fragments is the last data information fragment, determine the target available cache address to which each of the data information fragments is written; set the fragment field in the target available cache address to a first value, and set the identification information field in the target available cache address to a null value, wherein the fragment field is set to the first value to indicate that the target available cache address does not write a data information fragment, or the data information fragment written by the target available cache address is the last data information fragment; if each of the data information fragments is not the last data information fragment, determine the target available cache address to which each of the data information fragments is written; set the fragment field in the target available cache address to a second value, and write the identification information field in the target available cache address as the identification information of the available cache area to which the next data information fragment corresponding to each of the data information fragments is expected to be written, wherein the fragment field is set to the second value to indicate that the data information fragment written by the target available cache address is not the last data information fragment.

[0106] In an exemplary embodiment, the second writing module 88 is also used to, when the length value is less than a preset value, determine any one of the identification information as the first identification information and write it into the identification information pointer in the target index information data; when the length value is greater than or equal to the preset value, determine the first identification information obtained in the target identification information as the first identification information and write it into the identification information pointer in the target index information data.

[0107] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a readable storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of each embodiment of the present application.

[0108] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0109] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0110] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0111] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0112] S1, determining data information of a received frame to be written and index information of the received frame;

[0113] S2, writing the data information and the index information into an available cache address pointed to by the target identification information of the available cache, wherein the available cache address is used to store the data information;

[0114] S3, determining the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each of the plurality of index information data includes: a valid identifier and an identifier information pointer;

[0115] S4, setting the valid identification in the target index information data to a valid identification value, and writing the first identification information in the target identification information into the identification information pointer in the target index information data.

[0116] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0117] Optionally, in this embodiment, the electronic device may also be configured to execute steps S1, S2, S3, and S4 via a computer program.

[0118] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0119] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0120] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for writing an address, characterized in that: include: Determining data information of a received frame to be written and index information of the received frame; Writing the data information and the index information into an available cache address pointed to by the target identification information of the available cache, wherein the available cache address is used to store the data information; Determine the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each of the plurality of index information data includes: a valid identifier and an identifier information pointer; The valid identification in the target index information data is set to a valid identification value, and the first identification information in the target identification information is written into the identification information pointer in the target index information data.

2. The address writing method according to claim 1, characterized in that: Writing the data information and the index information into an available cache area address pointed to by the target identification information of the available cache area includes: Determine the size relationship between the length value of the data information and a preset value; When the length value is less than a preset value, obtaining any identification information in the identification information queue as the target identification information, wherein the identification information queue records all identification information of the available buffer area; writing the data information and the index information into the address of the available buffer area pointed to by any identification information; When the length value is greater than or equal to the preset value, the data information is segmented according to the length value to obtain multiple data information segments; the multiple data information segments and the index information are written into the available cache area address pointed to by the target identification information of the available cache area.

3. The address writing method according to claim 2, characterized in that: Writing the plurality of data information fragments and the index information into the available cache area address pointed to by the target identification information of the available cache area comprises: For each data information fragment in the plurality of data information fragments: Determine a fragment number corresponding to each data information fragment according to a fragmentation order of the multiple data information fragments; Each data information fragment, the fragment number, and the index information are written into the available cache area address pointed to by the target identification information of the available cache area.

4. The address writing method according to claim 2, characterized in that: After writing the data information and the index information into the available cache address pointed to by any identification information, the method further includes: The fragment field in the available cache area address is set to a first value, and the identification information field in the available cache area address is set to a null value, wherein the fragment field is set to the first value to indicate that the data information fragment written to the available cache area address is not a data information fragment, or that the data information fragment written to the available cache area address is the last data information fragment.

5. The address writing method according to claim 3, characterized in that: Writing each data information fragment, the fragment number, and the index number into the available cache area address pointed to by the target identification information of the available cache area includes: Obtain m pieces of identification information from the identification information queue, and determine the m pieces of identification information as the target identification information, wherein each of the multiple data information fragments corresponds to each of the m pieces of identification information one by one, and m is an integer greater than 1; For each data information slice: write each data information slice, the slice number, and the index information into the available cache area address pointed to by each identification information corresponding to each data information slice.

6. The address writing method according to claim 3, characterized in that: Writing each data information fragment, the fragment number, and the index number into the available cache area address pointed to by the target identification information of the available cache area includes: Obtaining n identification information from the identification information queue, wherein the n identification information is used to ensure that in a process in which the kth data information fragment among the multiple data information fragments is written to the Kth available cache area address pointed to by the kth identification information among the n identification information, the n identification information contains identification information corresponding to the nth data information fragment in the identification information field that can be written to the kth available cache area address, wherein the identification information field is used to indicate the identification information corresponding to the next data information fragment of the kth data information fragment, n is an integer greater than 1, and n is less than m, and k=n-1; In the case where the kth data information fragment has been written into the available buffer area, determining whether the current length value is greater than or equal to the preset value, wherein the current length value is used to indicate a length value obtained by updating the length value after any data information fragment among the multiple data information fragments is written into the available buffer area address pointed to by the target identification information; When the current length value is greater than or equal to the preset value, the w-th data information fragment, the fragment number corresponding to the w-th data information fragment, and the index information are written into the available cache area address pointed to by any identification information, wherein the arbitrary identification information is any identification information that has not been acquired in the identification information queue, and the w-th data information fragment is included in multiple data information fragments, and w=n+1.

7. The address writing method according to claim 3, characterized in that: After writing each data information fragment, the fragment number, and the index number into the available cache area address pointed to by the target identification information of the available cache area, the method further includes: Determining whether each of the data information fragments is the last data information fragment; In the case where each data information fragment is the last data information fragment, determining a target available cache address to which each data information fragment is written; setting a fragment field in the target available cache address to a first value, and setting an identification information field in the target available cache address to a null value, wherein the fragment field is set to the first value to indicate that the target available cache address does not write a data information fragment, or that the data information fragment written by the target available cache address is the last data information fragment; In the case that each data information fragment is not the last data information fragment, determine the target available cache area address to which each data information fragment is written; set the fragment field in the target available cache area address to a second value, and write the identification information field in the target available cache area address as the identification information of the available cache area to which the next data information fragment corresponding to each data information fragment is expected to be written, wherein the fragment field is set to the second value to indicate that the data information fragment written by the target available cache area address is not the last data information fragment.

8. The address writing method according to claim 2, characterized in that: Writing the first identification information in the target identification information into the identification information pointer in the target index information data includes: In the case where the length value is less than a preset value, determining any one of the identification information as the first identification information and writing it into the identification information pointer in the target index information data; When the length value is greater than or equal to the preset value, the first identification information obtained in the target identification information is used as the first identification information and written into the identification information pointer in the target index information data.

9. An address writing device, characterized in that: include: A first determining module, used to determine data information of a received frame to be written and index information of the received frame; A first writing module, used for writing the data information and the index information into an available cache area address pointed to by the target identification information of the available cache area, wherein the available cache area address is used for storing the data information; A second determination module is used to determine the target index information data corresponding to the index information in the linked list bitmap, wherein the linked list bitmap includes: a plurality of index information data that have been sorted, wherein each of the plurality of index information data includes: a valid identifier and an identifier information pointer; The second writing module is used to set the valid identification in the target index information data to a valid identification value, and write the first identification information in the target identification information into the identification information pointer in the target index information data.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 8 when executed.

11. A chip, characterized in that: Includes the address writing device as described in claim 9.

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