Design of domestic 1553B communication board card based on PCIE (Peripheral Component Interface Express)

Abstract

The invention discloses a domestic 1553B communication board card design based on PCIE (Peripheral Component Interface Express). The domestic 1553B communication board card design comprises an interface conversion module (3), a signal conversion module (5) and a 1553B communication module (8), on the basis of PCIEx1 design, the design requirements are met, meanwhile, the specifications and dimensions are considered, and the application range is wide. The interface chip can be provided with a configuration chip, and identification information can be modified according to needs. According to the invention, an LHB155304 chip design is adopted, and autonomous and controllable design and application are realized.

Description

Technical Field

[0001] The invention relates to the field of 1553B communication, and in particular to a design of a domestic 1553B communication board based on PCIE. Background Art

[0002] PCIE, the full name of which is Peripheral Component Interconnect Express, is a computer bus interface standard used for data transmission between expansion cards and computer motherboards. It is an upgraded version of the traditional PCI (Peripheral Component Interconnect) standard, with the aim of providing higher data transmission rates and performance, and providing faster and more stable connections for various types of external devices. PCIE is widely used in various hardware devices such as graphics cards, sound cards, network cards, storage devices, etc.

[0003] The MIL-STD-1553B bus is a standard bus for networking electronic subsystems of the U.S. Air Force. It is a centralized serial bus. According to the functions in the bus system, the 1553B bus communication protocol divides the terminal units on the bus into three types: bus controller, remote terminal and bus monitor. The three types of terminal units share the main line of the bus in parallel. The bus uses command response to achieve system communication, and uses redundant channels, odd parity and corresponding error handling to improve the reliability of system communication. Because the 1553B bus has extremely high reliability, it is widely used in electronic networking systems in the fields of aviation, aerospace, and military.

[0004] The 1553B bus has been increasingly valued and applied in modern weapon systems due to its extremely high reliability and real-time performance. Previously, China has always used foreign chips or modules, which are not self-controllable. Summary of the invention

[0005] The purpose of the present invention is to provide a domestic 1553B communication board design based on PCIE, including an interface conversion module, a signal conversion module, and a 1553B communication module;

[0006] The interface conversion module provides a PCIE interface and a parallel port connected to an external device;

[0007] The interface conversion module receives a PCIE signal from an external device through a PCIE interface and converts the PCIE signal into a parallel port signal;

[0008] The interface conversion module is connected to the signal conversion module via a parallel port;

[0009] The signal conversion module is connected to the 1553B communication module via a bus;

[0010] The signal conversion module transmits the parallel port signal output by the interface conversion module to the 1553B communication module;

[0011] The signal conversion module initializes the 1553B communication module, reads and writes data based on the parallel port signal, and responds to the reception and transmission message interruptions of the 1553B communication module.

[0012] The output bus of the 1553B communication module is interconnected with the external bus controller BC, the bus monitor MT, and the remote terminal RT after coupling.

[0013] Furthermore, the domestic 1553B communication board is connected to an external device through an interface conversion module; the external device includes a computer.

[0014] Furthermore, the interface conversion module adopts a PCIE interface.

[0015] Furthermore, the communication interface function of the 1553B communication module is developed based on a PCIE interface chip.

[0016] Furthermore, the interface conversion module has a PCIE bus specification of PCIEx1.

[0017] Furthermore, the interface conversion module receives the PCIE signal of the external device through the PCIE bus, decodes it, and converts it into a parallel port signal;

[0018] The parallel port signal includes an internal data bus D31-D0, an internal address bus A31-A0, a read I / O port signal, a write I / O port signal, a read memory signal, and a write memory signal.

[0019] Further, it also includes configuring the chip;

[0020] The interface conversion module checks the data in the configuration chip after power-on or PCIE bus reset;

[0021] If the interface conversion module is connected to the configuration chip and the data is valid, the interface conversion module automatically loads the data of the configuration chip and replaces the default PCIE identification information.

[0022] Further, the signal conversion module includes an FPGA state machine;

[0023] The FPGA state machine performs instruction queue reading and writing, interrupt signal processing and message reception.

[0024] Furthermore, the dual redundant bus output by the 1553B communication module supports a rate of 4 Mbps, and the output is transformer coupled.

[0025] Furthermore, the 1553B communication module adopts the LHB155304 chip.

[0026] The technical effect of the present invention is unquestionable. The present invention meets the design requirements based on PCIEx1 design while taking into account the specifications and dimensions, and has a wide range of adaptability. The interface chip of the present invention can be equipped with a configuration chip, and the identification information can be modified as needed. The present invention adopts the LHB155304 chip design to achieve autonomous and controllable design and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the hardware framework of the board.

[0028] Figure 2 This is a schematic diagram of the FPGA principle.

[0029] Figure 3 This is the structural block diagram of LHB155304.

[0030] Figure 4 The software flow chart of the board is shown in Figure 2.

[0031] In the figure, board 1, PCIE interface 2, interface conversion module 3, parallel port 4, signal conversion module 5, address bus 6, control signal 7, 1553B communication module 8, isolation transformer 9, channel A 10, channel B 11, 1553B bus 12, PCIE bus 13, configuration chip 14, hardware address configuration 15. DETAILED DESCRIPTION

[0032] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0033] Embodiment 1:

[0034] See also Figures 1 to 4 , a domestic 1553B communication board design based on PCIE (such as Figure 1 As shown in reference numeral 1), it includes an interface conversion module 3, a signal conversion module 5, and a 1553B communication module 8;

[0035] The interface conversion module 3 provides a PCIE interface 2 and a parallel port 4 connected to an external device;

[0036] The interface conversion module 3 receives the PCIE signal from the external device through the PCIE interface 2, and converts the PCIE signal into a parallel port signal;

[0037] The interface conversion module 3 is connected to the signal conversion module 5 via a parallel port;

[0038] The signal conversion module 5 is connected to the 1553B communication module 8 via a bus;

[0039] The signal conversion module 5 transmits the parallel port signal output by the interface conversion module 3 to the 1553B communication module 8;

[0040] The signal conversion module 5 initializes and reads and writes data to the 1553B communication module 8 based on the parallel port signal, and responds to the reception and transmission message interruptions of the 1553B communication module 8.

[0041] The output bus of the 1553B communication module 8 is interconnected with the external bus controller BC, the bus monitor MT, and the remote terminal RT after coupling.

[0042] The domestic 1553B communication board is connected to an external device via an interface conversion module 3; the external device includes a computer.

[0043] The interface conversion module 3 adopts a PCIE interface.

[0044] The communication interface function of the 1553B communication module 8 is developed based on the PCIE interface chip.

[0045] The interface conversion module 3 has a PCIE bus specification of PCIEx1.

[0046] The interface conversion module 3 receives the PCIE signal of the external device through the PCIE bus, decodes it, and converts it into a parallel port signal;

[0047] The parallel port signal includes an internal data bus D31-D0, an internal address bus A31-A0, a read I / O port signal, a write I / O port signal, a read memory signal, and a write memory signal.

[0048] Also includes a configuration chip 14;

[0049] The interface conversion module 3 checks the data in the 24CXX configuration chip after power-on or PCIE bus reset;

[0050] If the interface conversion module 3 is connected to the configuration chip and the data is valid, the interface conversion module 3 automatically loads the data of the configuration chip and replaces the default PCIE identification information.

[0051] The signal conversion module 5 includes an FPGA state machine;

[0052] The FPGA state machine performs instruction queue reading and writing, interrupt signal processing and message reception.

[0053] The dual redundant bus output by the 1553B communication module 8 supports a rate of 4 Mbps, and the output adopts a transformer coupling method.

[0054] The 1553B communication module 8 adopts the LHB155304 chip.

[0055] Embodiment 2:

[0056] A domestic 1553B communication board design based on PCIE, including an interface conversion module 3, a signal conversion module 5, and a 1553B communication module 8;

[0057] The interface conversion module 3 provides a PCIE interface 2 and a parallel port 4 connected to an external device;

[0058] The interface conversion module 3 receives the PCIE signal from the external device through the PCIE interface 2, and converts the PCIE signal into a parallel port signal;

[0059] The PCIE interface 2 of the interface conversion module 3 is connected to the PCIE bus 13 of the external device;

[0060] The interface conversion module 3 is connected to the signal conversion module 5 via a parallel port;

[0061] The signal conversion module 5 is connected to the 1553B communication module 8 via a bus;

[0062] The signal conversion module 5 transmits the parallel port signal output by the interface conversion module 3 to the 1553B communication module 8;

[0063] The signal conversion module 5 initializes and reads and writes data to the 1553B communication module 8 based on the parallel port signal, and responds to the reception and transmission message interruptions of the 1553B communication module 8.

[0064] The output bus of the 1553B communication module 8 is interconnected with external devices after coupling, and the external devices include an external bus controller BC, a bus monitor MT, and a remote terminal RT.

[0065] Embodiment 3:

[0066] A design of a domestic 1553B communication board based on PCIE, the technical content is the same as that of Example 2, further, the domestic 1553B communication board is connected to an external device through an interface conversion module 3; the external device includes a computer.

[0067] Embodiment 4:

[0068] A domestic 1553B communication board design based on PCIE, the technical content is the same as any one of Examples 2-3, and further, the interface conversion module 3 adopts a PCIE interface.

[0069] Embodiment 5:

[0070] A domestic 1553B communication board design based on PCIE, the technical content is the same as any one of Examples 2-4, further, the communication interface function of the 1553B communication module 8 is developed based on the PCIE interface chip.

[0071] Embodiment 6:

[0072] A domestic 1553B communication board design based on PCIE, the technical content is the same as any one of embodiments 2-5, further, the interface conversion module 3 has a PCIE bus specification of PCIEx1.

[0073] Embodiment 7:

[0074] A domestic 1553B communication board design based on PCIE, the technical content is the same as any one of embodiments 2-6, further, the interface conversion module 3 receives the PCIE signal of the external device through the PCIE bus, and decodes and converts it into a parallel port signal;

[0075] The parallel port signal includes an internal data bus D31-D0, an internal address bus A31-A0, a read I / O port signal, a write I / O port signal, a read memory signal, and a write memory signal.

[0076] Embodiment 8:

[0077] A domestic 1553B communication board design based on PCIE, the technical content is the same as any one of embodiments 2-7, and further includes a configuration chip 14;

[0078] The interface conversion module 3 checks the data in the 24CXX configuration chip after power-on or PCIE bus reset;

[0079] If the interface conversion module 3 is connected to the configuration chip and the data is valid, the interface conversion module 3 automatically loads the data of the configuration chip and replaces the default PCIE identification information.

[0080] Embodiment 9:

[0081] A domestic 1553B communication board design based on PCIE, the technical content is the same as any one of embodiments 2-8, further, the signal conversion module 5 includes an FPGA state machine;

[0082] The FPGA state machine performs instruction queue reading and writing, interrupt signal processing and message reception.

[0083] Embodiment 10:

[0084] A domestic 1553B communication board design based on PCIE, the technical content is the same as any one of Examples 2-9, further, the dual redundant bus output by the 1553B communication module 8 supports a 4Mbps rate, and the output adopts transformer coupling.

[0085] Embodiment 11:

[0086] A domestically produced 1553B communication board design based on PCIE, the technical content of which is the same as any one of Embodiments 2-3, and further, the 1553B communication module 8 adopts the LHB155304 chip.

[0087] Embodiment 12:

[0088] A design of a domestic 1553B communication board based on PCIE. The hardware of the board involves a framework diagram as shown below: Figure 1 As shown, the board includes an interface conversion 3, a signal conversion 5, a 1553B communication and software part. The interface conversion part 3 chip has a built-in PCIE interface 2 and a parallel port 4. The board 1 can be connected to a computer and other devices through the interface conversion part PCIE interface 13. The output bus of the 1553B communication part 8 is interconnected with external 1553B devices such as BC, MT and RT after coupling. The interface conversion part 3 is connected to the signal conversion part 5 through the parallel port 4. The signal conversion part 5 is connected to the 1553B communication part 8 through the data, address bus 6 and control signal. The 1553B communication interface function of the supporting software is developed based on the PCIE interface chip. The PCIE signal initializes and writes data to the 1553B chip through FPGA and responds to the receiving and sending interrupts.

[0089] The interface conversion part 3 chip has a PCIE bus specification of PCIEx1.

[0090] After the interface conversion part 3 chip decodes various signals of the PCIE bus 2, it generates internal data bus D31~D0, internal address bus A31~A0, read I / O port signal, write I / O port signal, read memory signal, write memory signal, etc.

[0091] The interface conversion part 3 chip will check the data in the external 24CXX configuration chip 14 after each startup or PCIE bus reset. If the configuration chip 14 is connected and the data is valid, it will be automatically loaded into the chip to replace the default PCIE identification information.

[0092] The signal conversion part 5FPGA state machine performs instruction queue reading and writing, interrupt signal processing and message receiving FIFO.

[0093] Specifically, the dual redundant bus output by the 1553B communication part 8 supports a rate of 4 Mbps.

[0094] Specifically, the output of the 1553B communication part 8 adopts a dual isolation transformer 9 coupling mode.

[0095] Specifically, the core 1553B chip of the 1553B communication part 8 adopts LHB155304 produced by the 771st Institute of the 9th Academy of China Aerospace Science and Technology Corporation.

[0096] This embodiment integrates the hardware address configuration 15 on the 1553B communication part 8, which can switch and change the RT address of each group of 1553B bus outputs (channel A10, channel B11). At the same time, the hardware address configuration 15 can be selected to be on-board or lead out using a connector according to different application scenarios, which has greater versatility and flexibility.

[0097] refer to Figure 2 FPGA mainly completes the read and write operations of the LHB155304 chip, and responds to the receive and send message interrupts of LHB155304. The FPGA design block diagram includes "PCIE bus interface", "interrupt signal processing", "read and write LHB155304 instruction queue", "receive message FIFO", "state machine execution", and "LHB155304 bus interface". "PCIE bus interface" and "LHB155304 bus interface" adapt to the parallel bus of the corresponding interface; "interrupt signal processing" manages various interrupt signals and generates interrupt signals adapted to the system; "read and write LHB155304 instruction queue" stores the read and write operations of the bus interface on LHB155304 as an instruction queue; "receive message FIFO" stores the message data received by LHB155304; "state machine execution" executes the read and write operations of the LHB155304 chip and processes the receive and send messages of LHB155304.

[0098] refer to Figure 3 The control circuit of 1553B bus 12 adopts LHB155304 with a rate of 4Mbps. The chip integrates two independent 3.3V powered transceivers, which are used in combination with an external step-up isolation transformer. No more power supply is required, which simplifies the design and has higher terminal input impedance. The chip integrates BC / RT / MT multi-protocol processing unit, and the BC, RT and MT working modes can be configured through internal software. The chip integrates a 16-bit interface mode, which can work with the host in a shared memory mode, making the host access waiting time shorter.

[0099] The board needs to be used with the corresponding driver. The driver mainly completes the initialization of the device, the reading and writing operations of the port, and other functions. The interface chip connected to the PCIE bus provides the driver for the computer operating system. Based on this driver, secondary development is carried out to design the 1553B interface function and dynamic link library suitable for upper-level applications.

[0100] The application software can be developed and programmed using VisualC and VisualC++ to complete the read and write operations on PCIE, thereby controlling the data transmission of the 1553B bus. This design implements the RT working mode of the 1553B bus. In the RT mode, first complete the configuration of the corresponding registers of the RT mode and a series of initialization tasks, and then complete the related processing after receiving the BC instruction. The basic process Figure 4 .

[0101] RT mode initialization is the key and basis for RT mode application. The basic steps are as follows:

[0102] (1) Reset RT, that is, write 0001H to the start / reset register.

[0103] (2) If you want to use the enhanced mode of RT (for example, use of sub-address double buffering mode), write 8000H to configuration register #3.

[0104] (3) Initialize the interrupt mask register. In most applications, the RT message end interrupt should be enabled; the RT subaddress control word interrupt, RT circular buffer wrap interrupt, RT mode instruction interrupt, and format error interrupt should also be enabled.

[0105] (4) Write the address of the instruction stack into the stack pointer RAM unit of the current active area.

[0106] (5) Initialize the RT query table of the active area. The RT query table specifies the data word addresses of various messages for each sub-address. Before initializing the data unit, the user must fill in the planned message data unit address into the RT query table.

[0107] (6) If the user does not use the enhanced instruction processing mode (controlled by configuration register #3.0), the data pointers of receiving subaddresses 0 and 31 (for synchronous instructions with words) are generally initialized to the same value, and the data pointers of sending subaddresses 0 and 31 (for sending vector word instructions) are generally initialized to the same value. If the enhanced instruction processing mode is used, the synchronous data word received by the synchronous instruction will be stored in the 0111H unit, and the message word of the sending vector word instruction will be obtained from the 0120H unit.

[0108] (7) Initialize configuration register #2. Configure enhanced RT storage management, separation of broadcast data, time stamp resolution, automatic clearing of interrupt status, etc.

[0109] (8) Initialize configuration register #3. This register mainly includes enhancement mode enable, instruction stack size configuration, illegal table prohibition, and enhancement mode instruction processing.

[0110] (9) Write the sent data into the corresponding data block and clear the received data area.

[0111] (10) The last step of configuration is to initialize configuration register #1. Select RT mode and select the current active region. According to the selection of the two status modes, initialize the control bits of the RT status word.

[0112] After initialization, the receiving or sending of data is determined by querying whether the T / R bit of the BC instruction is 1. If the T / R bit is 1, it means that the RT end needs to send data. According to the sub-address, the data of the corresponding stack is sent to BC, and then the RT status word is sent. If the T / R bit is 0, it means that the RT end needs to receive data. 1553B receives the data and sends the RT status word. The board receives the data from BC and temporarily stores it in the buffer area, then requests an interrupt from the computer CPU. The CPU responds to the interrupt to receive the data. At this point, the computer completes the process of receiving data from the 1553B bus.

Claims

1. A design of a domestic 1553B communication board based on PCIE, characterized by: It comprises an interface conversion module (3), a signal conversion module (5), and a 1553B communication module (8); The interface conversion module (3) provides a PCIE interface (2) and a parallel port (4) for connecting to external devices. The interface conversion module (3) receives a PCIE signal from an external device through a PCIE interface (2), and converts the PCIE signal into a parallel port signal. The interface conversion module (3) is connected to the signal conversion module (5) via a parallel port; The signal conversion module (5) is connected to the 1553B communication module (8) via a bus; The signal conversion module (5) transmits the parallel port signal output by the interface conversion module (3) to the 1553B communication module (8); The signal conversion module (5) performs initialization and data reading and writing operations on the 1553B communication module (8) based on the parallel port signal, and responds to the reception and transmission message interruptions of the 1553B communication module (8). The output bus of the 1553B communication module (8) is interconnected with the external bus controller BC, the bus monitor MT, and the remote terminal RT after coupling.

2. According to the design of a domestic 1553B communication board based on PCIE according to claim 1, it is characterized in that: The domestic 1553B communication board is connected to an external device via an interface conversion module (3); the external device includes a computer.

3. According to the design of a domestic 1553B communication board based on PCIE according to claim 1, it is characterized in that: The interface conversion module (3) adopts a PCIE interface.

4. According to the design of a domestic 1553B communication board based on PCIE according to claim 1, it is characterized in that: The communication interface function of the 1553B communication module (8) is developed based on a PCIE interface chip.

5. According to the design of a localized 1553B communication board based on PCIE according to claim 1, it is characterized in that: The interface conversion module (3) has a PCIE bus specification of PCIEx1.

6. According to the design of a localized 1553B communication board based on PCIE according to claim 1, it is characterized in that: The interface conversion module (3) receives the PCIE signal of the external device through the PCIE bus, decodes it, and converts it into a parallel port signal; The parallel port signal includes an internal data bus D31-D0, an internal address bus A31-A0, a read I / O port signal, a write I / O port signal, a read memory signal, and a write memory signal.

7. According to the design of a localized 1553B communication board based on PCIE according to claim 1, it is characterized in that: Also includes a configuration chip (14); The interface conversion module (3) checks the data in the configuration chip after powering on or resetting the PCIE bus; If the interface conversion module (3) is connected to the configuration chip and the data is valid, the interface conversion module (3) automatically loads the data of the configuration chip and replaces the default PCIE identification information.

8. According to the design of a localized 1553B communication board based on PCIE according to claim 1, it is characterized in that: The signal conversion module (5) comprises an FPGA state machine; The FPGA state machine performs instruction queue reading and writing, interrupt signal processing and message reception.

9. According to the design of a localized 1553B communication board based on PCIE according to claim 1, it is characterized in that: The dual redundant bus output by the 1553B communication module (8) supports a rate of 4 Mbps, and the output adopts a transformer coupling mode.

10. The design of a domestic 1553B communication board based on PCIE according to claim 1, characterized in that: The 1553B communication module (8) adopts the LHB155304 chip.

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