A global layout method driven by chip network weight timing

Abstract

The present invention discloses a global layout method driven by chip network weight timing, which belongs to the field of computer-aided design technology, including: performing initial layout according to a global layout algorithm to obtain an initial layout chip network; optimizing the initial layout chip network; using the Nadam gradient optimization algorithm to update the timing and layout parameters of the chip network after layout optimization; judging whether the updated parameters converge, if not, continuing iterative optimization, and if converged, entering the legalization stage. The present invention dynamically updates the weights of the chip network after layout optimization through static timing analysis, improves the convergence of the layout objective function using the first-order and second-order momentum gradients of the Nadam method, and adds historical gradients in the gradient descent to reduce oscillation. The present invention effectively improves the efficiency and performance of circuit design, reduces timing violations, and ensures timing convergence.

Description

Technical Field

[0001] The present invention relates to the technical field of computer-aided design, and more specifically to a global layout method driven by chip network weight timing. Background Art

[0002] During the design phase of very large scale integrated circuits (VLSI), static timing analysis (STA) is a key step to ensure that the design meets timing requirements. STA ensures that the signal reaches the destination correctly within the clock cycle by evaluating the delay of each signal path in the circuit. Static timing analysis does not rely on the specific waveform of the input signal, but evaluates the timing by analyzing all possible paths of the circuit. It can identify timing violations, including setup time and hold time violations, which directly affect the function and reliability of the circuit. The advantage of STA is that it can quickly and comprehensively evaluate the timing characteristics of the entire design without simulation.

[0003] However, as the design scale increases and the operating frequency increases, the complexity of timing analysis also increases. Therefore, in the STA process, factors such as design rule compliance, signal integrity, and power integrity become particularly important, and timing convergence becomes more difficult in larger and more complex integrated circuits. Traditional timing analysis mainly relies on static timing analysis tools, which ensure that signals can be successfully transmitted within the predetermined clock cycle by analyzing all possible paths in the circuit. However, as the scale of the circuit increases, the computational complexity of STA increases significantly, resulting in longer analysis time and increased resource consumption. In addition, traditional STA is usually performed after layout is completed, which means that any changes in layout or routing require re-timing analysis, causing delays in the design cycle.

[0004] At the same time, traditional STA also faces challenges of multiple timing violations, including setup time and hold time violations. Due to the complex clock tree and dynamic power management technology frequently used in modern designs, how to effectively identify and repair these violations has become an important task for the design team.

[0005] Global layout is a key stage in the VLSI design process, and is mainly used to determine the preliminary location of circuit components on the chip. The goal of global layout is to optimize the chip area, reduce the length of the connection, and improve the manufacturability and testability of the layout. Global layout usually involves a series of complex optimization problems, including area optimization, timing optimization, and power optimization.

[0006] In the global layout stage, the design tool will use heuristic algorithms (such as simulated annealing and genetic algorithms) to perform preliminary layout of components based on design constraints (such as power networks, clock trees, and signal paths) and design rules. These algorithms seek the optimal layout solution through random search and local optimization to reduce the length of connections and crossing paths between components, thereby improving circuit performance.

[0007] For traditional methods, although these methods can provide feasible layout solutions within a reasonable time, it is often difficult to ensure the optimality and consistency of the layout. The goals of layout optimization are mainly focused on area and wire length, while timing and signal integrity are relatively less considered. This limitation may lead to large timing violations in subsequent detailed layout and routing, increasing the workload of design repair.

[0008] Therefore, how to provide a chip network weight timing-driven global layout method that can effectively reduce timing violations and ensure timing convergence is an issue that technical personnel in this field urgently need to solve. Summary of the invention

[0009] In view of this, the present invention provides a global layout method driven by chip network weight timing, which dynamically adjusts the chip network weight according to the chip network characteristics, reduces the influence of parasitic capacitance, and reduces the net delay; and proposes a Nadam-based gradient descent method to accurately calculate the gradient and dynamically adjust the chip network weight, improve timing convergence, and enhance circuit performance.

[0010] In order to achieve the above object, the present invention adopts the following technical solution:

[0011] A global layout method driven by chip network weight timing includes the following steps:

[0012] Performing initial layout of the chip network according to a global layout algorithm to obtain an initial layout chip network;

[0013] Performing layout optimization on the initially laid out chip network;

[0014] Use the Nadam gradient optimization algorithm to perform gradient optimization and update the timing and layout parameters of the chip network after layout optimization;

[0015] Determine whether the updated timing and layout parameters have converged. If not, substitute the updated parameters into the next iteration and re-enter the layout optimization stage to continue gradient solution. If the whole process converges, enter the legalization stage.

[0016] Preferably, the Nadam gradient optimization algorithm is used to perform gradient optimization, and the timing and layout parameters of the chip network after layout optimization are updated, including:

[0017] Performing static timing analysis on the initial layout chip network to obtain timing information, and optimizing the timing information based on a hybrid heuristic method;

[0018] Optimize the gradient of timing constraints through first-order momentum and second-order momentum;

[0019] The timing and layout parameters are dynamically updated in real time according to the gradient of the optimized timing and timing constraints.

[0020] Preferably, static timing analysis is performed on the initial layout chip network to obtain timing information, and the timing of the chip network is optimized based on a hybrid heuristic algorithm, including:

[0021] Performing static timing analysis on the initial layout chip network to extract timing information of the initial layout chip network;

[0022] Adjusting the weights of chip networks after layout optimization of different layers according to the timing information;

[0023] The objective function of the nonlinear layouter is to reduce the timing violation value, optimize the circuit timing, and reduce the line length. Through the gradient descent process of the objective function, the position of the standard cell is dynamically adjusted to reduce the line length of the chip network and optimize the timing.

[0024] In each iteration, static timing analysis is re-performed to update timing information;

[0025] Adjust chip network weights and objective functions based on new timing information;

[0026] Repeat the above steps until the timing converges or the preset number of iterations is reached.

[0027] Preferably, performing static timing analysis on the initial layout chip network to extract timing information of the initial layout chip network includes:

[0028] Calculate the relaxed criticality of the chip network:

[0029] ;

[0030] in, represents the criticality of chip network e, s wns represents the worst negative relaxation value, s e is the net slack value of chip network e;

[0031] Calculate the fan-out sensitivity parameter:

[0032] ;

[0033] Among them, Pins represents the number of network pins, represents the sensitivity parameter of the chip network e fan-out, τ is the normalization adjustment hyperparameter, Represents the output pin within the chip network e; Represents all output pins driven by output pin in chip net e.

[0034] Preferably, the network criticality value after iteration is:

[0035] ;

[0036] in, It is a dynamic parameter used to balance the critical value of relaxation and fan-out.

[0037] Preferably, the Nadam gradient optimization algorithm is used to perform gradient optimization, and the timing and layout parameters of the chip network after layout optimization are updated, including:

[0038] In each timing iteration, calculate the critical value after each timing iteration , and merge the critical value increment into the current momentum The momentum is updated in the figure; the calculation formula of the momentum of the chip network after the update is:

[0039] ;

[0040] Where T is the total number of first-order iterations, is the first-order kinetic energy criticality, represents the momentum at the tth timing iteration, β1 is the first-order momentum attenuation coefficient;

[0041] In the non-timed iteration, the net weight is adjusted by the second-order momentum. The calculation formula of the second-order momentum of the updated chip network is:

[0042] ;

[0043] Where I is the total number of second-order iterations, β 2 is the second-order momentum decay coefficient, is the second-order momentum of the i-th iteration, is the first-order kinetic energy criticality.

[0044] Preferably, the first-order kinetic energy and second-order momentum are corrected based on the current decay rate to reduce the bias introduced by the momentum estimation:

[0045] ;

[0046] ;

[0047] in, is the first-order current momentum of the t-th iteration; is the second-order current momentum of the i-th iteration, is the first-order momentum decay coefficient of the t-th iteration; is the second-order momentum decay coefficient of the i-th iteration.

[0048] Preferably, the momentum attenuation coefficient β is calculated by the overflow value 1 , β 2 To make dynamic adjustments:

[0049] ;

[0050] ;

[0051] Among them, overflow represents the overall overlap in the global layout stage.

[0052] It can be known from the above technical solutions that, compared with the prior art, the present invention discloses a global layout method driven by chip network weight timing, which significantly improves the timing convergence and circuit performance of ultra-large-scale integrated circuit design by introducing static timing analysis and dynamic chip network weight adjustment in the global layout stage. Utilizing the first-order and second-order momentum based on the Nadam algorithm, the present invention can dynamically adjust the chip network weights in time-driven layout optimization, reduce timing violations, and optimize chip area and connection length. In addition, the present invention also improves the efficiency and stability of the optimization algorithm, reduces resource consumption and design cycle, and is of great significance to improving circuit design efficiency and performance through the introduction of adaptive parameter allocation and historical gradients. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0054] Figure 1 It is the overall flow chart of the present invention;

[0055] Figure 2 Comparison graph for hybrid heuristic fan-out optimization;

[0056] Figure 3 Schematic diagram of first-order gradient, second-order gradient and historical gradient. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] The present invention discloses a global layout method driven by chip network weight timing, which mainly includes three stages: (1) optimizing timing by hybrid heuristic method; (2) optimizing the gradient of timing constraints from static timing analysis by adjusting first-order momentum and second-order momentum; and (3) dynamically updating relevant timing and layout parameters in real time.

[0059] The embodiment of the present invention discloses a global layout method driven by chip network weight timing, such as Figure 1 As shown, the following steps are included:

[0060] Performing initial layout of the chip network according to a global layout algorithm to obtain an initial layout chip network;

[0061] Performing layout optimization on the initially laid out chip network;

[0062] Use the Nadam gradient optimization algorithm to perform gradient optimization and update the timing and layout parameters of the chip network after layout optimization;

[0063] Determine whether the updated timing and layout parameters have converged. If not, substitute the updated parameters into the next iteration and re-enter the layout optimization stage to continue gradient solution. If the whole process converges, enter the legalization stage.

[0064] Furthermore, the Nadam gradient optimization algorithm is used to perform gradient optimization and update the timing and layout parameters of the chip network after layout optimization, including:

[0065] Performing static timing analysis on the initial layout chip network to obtain timing information, and optimizing the timing information based on a hybrid heuristic method;

[0066] Optimize the gradient of timing constraints through first-order momentum and second-order momentum;

[0067] The timing and layout parameters are dynamically updated in real time according to the gradient of the optimized timing and timing constraints.

[0068] Furthermore, in modern global layouters, most of them use nonlinear layout algorithms. Experiments have shown that nonlinear global layout algorithms not only have excellent results in solution quality, but also have great advantages in scalability and convergence. In global layout, nonlinear layout abstracts the layout problem into a constrained target equation and solves it through gradient descent. Since the goal of global layout is to minimize the line length to ensure that the subsequent wiring can proceed smoothly, most standard cells are concentrated together in the early stage of layout to achieve the minimum line length. As the weight of the density constraint continues to increase, the standard cells gradually disperse, and the gradient descent is performed through the Nesterov gradient descent method, and finally the optimal solution of the target equation is obtained while satisfying the density constraint. In the layout, there will be not only small-sized standard cells, but also larger macro cells, but macro cells are generally immovable.

[0069] As the integration scale of modern chips increases, the logic structure of chip units becomes very complex, and the convergence of timing faces greater challenges. In modern static timing analysis, the layer analysis method is usually used to divide the logic unit into N layers, and analyze the timing of each unit layer by layer. What is difficult to solve for timing is how to calculate the parasitic circuits that couple complex circuits to each other. Because the excessive line length will increase the resistance of the overall circuit, it will bring higher delay. At the same time, the fan-out of each timing path will still affect the delay of its path. Based on this, the present invention proposes that in the chip network with timing violations, the line length of the relevant chip network will be based on different layers, different fan-outs, and different violation values ​​(relaxed negative values ​​to adjust). The more layers of standard cells have a lower impact on the timing of subsequent paths, and the larger fan-out units have a greater impact on subsequent paths. A larger fan-out usually means a larger line length. For high fan-out and violation chip networks, dynamically adjust the larger chip network weights to obtain a larger step size during the gradient descent of the objective function of the line length.

[0070] Specifically, static timing analysis is performed on the initial layout chip network to obtain timing information, and the timing of the chip network after layout optimization is optimized based on a hybrid heuristic algorithm, including:

[0071] Performing static timing analysis on the initial layout chip network to extract timing information of the initial layout chip network;

[0072] Adjust the weights of chip networks after layout optimization at different levels according to the timing information, and dynamically adjust a larger chip network weight for high fan-out and violation chip networks;

[0073] The objective function of the nonlinear layouter is to reduce the timing violation value, optimize the circuit timing, and reduce the line length. Through the gradient descent process of the objective function, the position of the standard cell is dynamically adjusted to reduce the line length of the chip network and optimize the timing.

[0074] In each iteration, static timing analysis is re-performed to update timing information;

[0075] Adjust chip network weights and objective functions based on new timing information;

[0076] Repeat the above steps until the timing converges or the preset number of iterations is reached.

[0077] Furthermore, static timing analysis is performed on the initial layout chip network to extract the timing information of the initial layout chip network, including:

[0078] like Figure 2 As shown, the timing results of static timing analysis indicate that shrinking a larger fan-out violating chip network can effectively reduce the timing violation value, or even eliminate the timing violation of the chip network. And in a chip network with a larger fan-out, the impact on subsequent chip networks will be greater. The present invention reduces the line length by adjusting the position of the standard cell in the global layout stage, and ultimately achieves the effect of reducing the timing violation value, or even eliminating the timing violation of the chip network. Where WNS represents the worst negative slack, and TNS represents the total negative slack. Therefore, the slack criticality of the chip network is calculated:

[0079] ;

[0080] in, represents the criticality of chip network e, s wns represents the worst negative relaxation value, s e is the net slack value of chip network e;

[0081] A flip-flop with too large a fan-out will negatively impact timing by increasing load capacitance, leading to longer wavelengths and more complex circuits. However, since the fan-out of the flip-flop is determined during the logic synthesis stage, we can reduce these negative effects by increasing the sensitivity to the fan-out during the placement stage. The net weight of the sensitivity parameter relative to the fan-out is given by the following formula:

[0082] ;

[0083] Among them, Pins represents the number of network pins, represents the sensitivity parameter of the chip network e fan-out, τ is the normalization adjustment hyperparameter, Represents the output pin within the chip network e; Represents all output pins driven by output pins in chip network e. The above formula can be used to obtain the key value of fan-out output, and adjust the position of pins during placement to reduce the timing impact caused by high fan-out output.

[0084] Furthermore, the criticality value of the current iteration is obtained by multiplying and To define, and then normalize the result, so the network criticality value after iteration is:

[0085] ;

[0086] in, It is a dynamic parameter used to balance the critical value of relaxation and fan-out;

[0087] During the initial stages of placement, the location of cells can change significantly, making slack values ​​unreliable, so in the early stages, more emphasis is placed on fan-out. As Update to an adaptive parameter of network criticality, calculated as follows:

[0088] ;

[0089] Among them, overflow represents the overall overlap in the global layout stage.

[0090] In traditional nonlinear global layout algorithms, only the line length is added to the target. The present invention adjusts the weight of the chip network after layout optimization of different layers through the different layers of standard cells of static timing analysis, and then adjusts the position of the standard cells through the line length objective function of the global layout to reduce the line length of the chip network.

[0091] In the global layout stage, the nonlinear layouter is currently the most advanced and widely used global layouter. The present invention adds static timing analysis in the global layout stage to extract the timing information in the iteration of the layout stage, and optimizes the timing in the layout according to different timing information through a hybrid heuristic method. Standard cells with different numbers of layers, chip networks with different fan-outs, and chip networks with high latency are adjusted through the objective function of the nonlinear layouter to achieve the effect of optimizing and reducing timing violations and ensuring timing convergence.

[0092] like Figure 3As shown, in the global layout, the net is the smallest unit for calculating the wire length. In each timing iteration, we calculate the wire length gradient through the chip network. According to the relaxation of each net, the first-order momentum and second-order momentum moment of its gradient are updated to dynamically adjust the weight of the net. The updated net weight is then applied to the Nesterov accelerated gradient descent method. The present invention introduces a chip network weight scheme based on Nadam, which uses first-order and second-order momentum to dynamically adjust the weight of a single net in a time-driven layout optimization process. Specifically, the Nadam gradient optimization algorithm is used for gradient optimization to update the timing and layout parameters of the chip network after layout optimization, including:

[0093] In each timing iteration, calculate the critical value after each timing iteration , and merge the critical value increment into the current momentum To update the momentum:

[0094] ;

[0095] Since a new momentum is obtained at each timing iteration, the increment is the gradient determined by the timing metric. Our goal is to use To emphasize momentum . The chip network criticality is the intermediate variable for momentum mobilization of the final chip network weight.

[0096] The term can be considered as velocity. Usually momentum is inconsistent with the gradient of the objective function, so the historical gradient is recorded at each timing iteration to guide the actual gradient increment. The calculation of each momentum provides guidance for the historical momentum and gradually increases as the placement progresses. The calculation formula for the momentum of the updated chip network is:

[0097] ;

[0098] Where T is the total number of first-order iterations, is the first-order kinetic energy criticality, represents the momentum at the tth timing iteration, β1 is the first-order momentum attenuation coefficient; , The calculation formula is as follows:

[0099] ;

[0100] ;

[0101] in, and k are two hyperparameters in the range [0,1] that are dynamically adjusted according to the overflow in position. Their values ​​are inversely proportional to the overflow value.

[0102] In timing-driven global placement, the cost of timing iterations is very high, which leads to considerable resource and runtime overhead. Therefore, the number of timing iterations constitutes only a small fraction of the total iterations in the entire timing-driven global placement process. The first-order momentum is only updated during the timing iterations. In the untimed iterations, the accuracy of the first-order momentum direction decreases as the number of untimed iterations increases. To address this issue, we introduce the second-order momentum method.

[0103] In the non-timed iteration, the net weight is adjusted by the second-order momentum. The calculation formula of the second-order momentum of the updated chip network is:

[0104] ;

[0105] Among them, the second-order momentum v i Track the variance of the gradient and perform adaptive parameter assignment for each parameter. Parameters with larger gradients are updated with smaller steps, and parameters with smaller gradients are updated with larger steps. This balances different parameters and improves the efficiency of the optimization algorithm. I is the total number of second-order iterations, β 2 is the second-order momentum decay coefficient, is the second-order momentum of the i-th iteration, is the first-order kinetic energy criticality.

[0106] Preferably, the first-order kinetic energy and second-order momentum are corrected based on the current decay rate to reduce the bias introduced by the momentum estimation:

[0107] ;

[0108] ;

[0109] in, is the first-order current momentum of the t-th iteration; is the second-order current momentum of the i-th iteration, is the first-order momentum decay coefficient of the t-th iteration; is the second-order momentum decay coefficient of the i-th iteration.

[0110] Preferably, the momentum decay coefficients β1 and β2 are dynamic parameters, and it is expected that the reduction of momentum in the early stage of layout will have an impact on the later stage of layout. 1 , β 2 To make dynamic adjustments:

[0111] ;

[0112] .

[0113] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0114] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A global layout method driven by chip network weight timing, characterized in that: The following steps are involved: Performing initial layout of the chip network according to a global layout algorithm to obtain an initial layout chip network; Performing layout optimization on the initially laid out chip network; Use the Nadam gradient optimization algorithm to perform gradient optimization and update the timing and layout parameters of the chip network after layout optimization; Determine whether the updated timing and layout parameters have converged. If not, substitute the updated parameters into the next iteration and re-enter the layout optimization phase to continue gradient solving. If the whole converges, it enters the legalization stage; Use the Nadam gradient optimization algorithm to perform gradient optimization and update the timing and layout parameters of the chip network after layout optimization, including: Performing static timing analysis on the initial layout chip network to obtain timing information, and optimizing the timing information based on a hybrid heuristic method; Optimize the gradient of timing constraints through first-order momentum and second-order momentum; Dynamically update timing and layout parameters in real time based on the gradient of optimized timing and timing constraints; Performing static timing analysis on the initial layout chip network to obtain timing information, and optimizing the timing of the layout-optimized chip network based on a hybrid heuristic algorithm, including: Performing static timing analysis on the initial layout chip network to extract timing information of the initial layout chip network; Adjusting the weights of chip networks after layout optimization of different layers according to the timing information; The objective function of the nonlinear layouter is to reduce the timing violation value, optimize the circuit timing, and reduce the line length. Through the gradient descent process of the objective function, the position of the standard cell is dynamically adjusted to reduce the line length of the chip network and optimize the timing. In each iteration, static timing analysis is re-performed to update timing information; Adjust chip network weights and objective functions based on new timing information; Repeat the above steps until the timing converges or the preset number of iterations is reached.

2. A chip network weight timing driven global layout method according to claim 1, characterized in that: Performing static timing analysis on the initial layout chip network to extract timing information of the initial layout chip network includes: Calculate the relaxed criticality of the chip network: in, represents the criticality of chip network e, s wns represents the worst negative relaxation value, s e is the net slack value of chip network e; Calculate the fan-out sensitivity parameter: Among them, Pins represents the number of network pins, represents the sensitivity parameter of the fan-out of chip network e, τ is the normalization adjustment hyperparameter, output pin∈e represents the output pin in chip network e; output pin∈input represents all output pins driven by the output pin in chip network e.

3. A chip network weight timing driven global layout method according to claim 2, characterized in that: The network criticality value after iteration is: Here, μ is a dynamic parameter used to balance the critical value of relaxation and fan-out.

4. The global layout method driven by chip network weight timing according to claim 1, characterized in that: Use the Nadam gradient optimization algorithm to perform gradient optimization and update the timing and layout parameters of the chip network after layout optimization, including: In each timing iteration, calculate the critical value after each timing iteration And merge the critical value increment into the current momentum The momentum is updated in the figure; the calculation formula of the momentum of the chip network after the update is: Where T is the total number of first-order iterations, is the first-order kinetic energy criticality, represents the momentum at the tth timing iteration, β1 is the first-order momentum attenuation coefficient; In the non-timed iteration, the net weight is adjusted by the second-order momentum. The calculation formula of the second-order momentum of the updated chip network is: Where I is the total number of second-order iterations, β2 is the second-order momentum decay coefficient, is the second-order momentum of the i-th iteration, is the first-order kinetic energy criticality.

5. A chip network weight timing driven global layout method according to claim 4, characterized in that: Corrections to the first-order kinetic energy and second-order momentum based on the current decay rate to reduce the bias introduced by the momentum estimate: Among them, m t is the first-order current momentum of the t-th iteration; v i is the second-order current momentum of the i-th iteration, is the first-order momentum decay coefficient of the t-th iteration; is the second-order momentum decay coefficient of the i-th iteration.

6. A chip network weight timing driven global layout method according to claim 5, characterized in that: The momentum attenuation coefficients β1 and β2 are dynamically adjusted through the overflow value: Among them, overflow represents the overall overlap in the global layout stage.

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