A low-latency beam direction finding technology based on FPGA

Abstract

The present invention provides a low-latency beam direction finding technology based on FPGA, including the following steps: establishing a beam direction finding simulation mathematical model according to a beam direction finding algorithm combined with specific hardware parameters and indicators and characteristic information of a flight target to be tested; converting the established beam direction finding simulation mathematical model into an FPGA program; building a hardware test platform, and burning the FPGA program into an FPGA baseband board; operating according to a direction test process to complete the direction test. Compared with the prior art, the present invention greatly reduces the delay caused by direction finding by relying on the powerful parallel processing capability and high-speed clock of the FPGA chip, and at the same time improves the resolution of direction determination. Through the application of FPGA and precise mathematical modeling, it has significant advantages in direction finding accuracy, real-time performance, system scalability, and anti-interference capability, and can effectively cope with complex flight target direction finding tasks. This makes the technology have broad application prospects in the fields of aerospace, military reconnaissance, and unmanned aerial vehicles.

Description

Technical Field

[0001] The present invention relates to the field of communication confrontation using ultra-short waves to detect the trajectory of a flying target, and in particular to using an array processing technology to quickly and accurately detect, find the direction and track ultra-short wave signals within a long range. Background Art

[0002] Beam direction finding is a key technology for locating and tracking signal sources, and is widely used in radar, communications, sonar and other fields. The implementation method of beam direction finding mainly relies on array antenna systems, which perform signal processing after receiving the signal to determine the direction of the signal source. With the advancement of technology, beam direction finding technology is developing towards higher integration, real-time and intelligent directions. For example, more and more systems tend to integrate signal processing, storage and interface functions into a single chip to improve efficiency and reduce costs. The introduction of new algorithms (such as machine learning algorithms) to improve the accuracy and robustness of beam direction finding.

[0003] The current implementation method of beam direction finding technology is to first sample the array antenna, cache it, and then transfer it to DSP for processing. The advantage of using DSP is that the program design is simple and the hardware cost is lower than FPGA, which can meet the direction finding of most low-speed flights.

[0004] The disadvantages are: the array antenna data sampled by ADC requires the system to provide a buffer area to store the baseband data, which not only causes delays but also increases the risk of desynchronization between different arrays. Secondly, DSP cannot perform parallel processing like FPGA, and switching between processes requires interruption. Frequent switching will increase the uncertainty of the system and also increase delays. Thirdly, DSP cannot provide a rich external interface like FPGA, which limits the system's expansion and external interaction capabilities. Summary of the invention

[0005] The purpose of the present invention is to provide a low-latency beam direction finding technology based on FPGA, thereby improving parallel processing capabilities, being able to process multiple signal streams simultaneously, and reducing latency and uncertainty. To ensure flexibility and programmability, FPGA allows users to configure and program hardware according to specific needs, giving it greater flexibility in complex application scenarios. To improve expansion capabilities, FPGA can support multiple interface standards, facilitate connection and communication with other devices, and expand system functions.

[0006] To achieve the above object, the present invention proposes the following technical solution: a low-latency beam direction finding technology based on FPGA, comprising:

[0007] S1, obtaining the hardware parameters of the test system and the expected technical indicators and characteristic information of the flight target to be tested, and determining the simulation mathematical model based on the above;

[0008] S2. passing the hardware parameters and technical indicators to the siglepulse_Author simulation mathematical model to obtain the array beam weight vector and the sum and difference beam amplitude ratio vector, wherein the siglepulse_Author simulation mathematical model includes: an array beam weight vector calculation equation, and a sum beam and a difference beam calculation equation;

[0009] S3. Convert the established siglepulse_Author simulation mathematical model and the obtained beam weight vector into an FPGA program. The FPGA program obtains the direction angle of the flying target in real time according to the response signal of the flying target, and transmits the azimuth parameters to the host computer in real time for strategy and interaction.

[0010] S4, burning the FPGA program into the baseband board of the direction finding system, and operating according to the direction test process to complete the direction angle test;

[0011] Further, in the present invention, step S2 includes:

[0012] Constructing a beam introduction signal vector according to actual array antenna parameters;

[0013] The steering vector equation for constructing a uniform linear array is expressed as:

[0014]

[0015] Where θ is the signal incident azimuth, d is the spacing between uniform linear arrays, M is the number of antenna elements, and λ is the wavelength;

[0016] Solve the equations based on the actual array antenna parameters and beam weight output;

[0017]

[0018] Where x(t) is the input signal of each array element

[0019] When the plane wave reaches the M-1 array element first and the 0th array element last, the time delay between the two adjacent array elements is dsin(θ). Therefore, if the signals arriving earlier from each array element are delayed in sequence, that is, the signals x(t) of each array element pass through the θ direction. After phase compensation, they will be added in phase, and the signal strength will increase by M times. Unwanted signals or interference from other directions may only be superimposed at random phases, and the signal strength will be much smaller. In the sense of spatial filtering, the signal in the θ direction is selected. Similarly, other signals can also be designed with other appropriate weight coefficients according to needs through similar methods to suppress interference and output the desired signal. If the weight vectors are different, there will be different responses to signals from different wave directions, thus forming different spatial beams;

[0020] Solve the difference beam weight output equation according to the actual array antenna parameters;

[0021] The difference beam requires a null at the beam pointing point. First, the beam is pointed at θ 0 Centered on θ 0 Take two angles θ respectively r and θ l The selection of these two angles is related to the 3dB cutoff angle of the beam main lobe. Assume that the 3dB main lobe width is θ abs , then θ r and θ l The equation is:

[0022]

[0023] Combining the above formula, we can get the difference beam output equation:

[0024] Δ(θ)=|α H (θ l )α(θ)|-|α H (θ r )α(θ)|;

[0025] Similarly, the sum beam also needs to be processed into amplitude values, that is,

[0026]

[0027] in Pointing to θ 0 The beam weight vector in the direction can also be expressed as α(θ 0 ) represents the specific equation as follows:

[0028]

[0029] Solve the sum and difference beam amplitude ratio output equation according to the sum and difference beam weight vector;

[0030] Combined with θ l The equation, difference beam output equation, and amplitude value formula are used to obtain the sum and difference beam amplitude ratio output equation:

[0031]

[0032] Amplitude comparison direction finding uses the amplitude ratio of the difference beam and the sum beam as the single pulse ratio, making use of the symmetry of the left and right beams, and is not limited to the particularity of the geometric structure of the array itself;

[0033] Substitute the sum and difference beam amplitude ratio output values ​​into the pre-fitted linear function to find the corresponding angle value.

[0034] Further, in the present invention, step S3 includes:

[0035] Input the array antenna type, number of array elements, array element distance and wavelength parameters to the siglepulse_Author simulation mathematical model, and call the guidance calculation formula to construct a directional input beam signal;

[0036] Constructing the beam filter bank output sum and difference beams according to the beam weights and difference beam weights and calculating the sum and difference ratio;

[0037] Substitute the ratio into the fitted linear function to output the direction angle value.

[0038] Further, in the present invention, step S4 includes the following process:

[0039] Build a hardware test platform, which consists of FPGA baseband board, array antenna assembly, host computer, and RGS-2000NG test instrument;

[0040] The RGS-2000NG test instrument transmits a wireless response signal to the test platform at a specific direction and distance. The test platform receives the signal through the array antenna and sends it to the FPGA baseband chip through AD sampling.

[0041] The FPGA baseband board performs orthogonal digital down-conversion, decimation, and low-pass filtering on the input signal, and then sends it to the beam weight digital filter group for filtering. It calls the Complex Multiplier and CORDIC FPGA IP cores to implement complex multiplication and square root operations to obtain two sets of vectors: the sum beam and the difference beam.

[0042] Call the Divider Generator IP core to realize the ratio of the sum signal and the difference signal, compare the ratio with the ideal fitting value pre-stored in ROM, output the direction angle value of the current flight target and pass it to the host computer;

[0043] The host computer obtains the direction angle value of the current flying target in real time and combines it with parameters such as distance to draw the flight trajectory of the target and make corresponding strategies;

[0044] The RGS-2000NG test instrument tests and records according to the above process at different directions and distances, realizing a closed loop of the directional test process.

[0045] Beneficial effects: The technical solution of this application has the following technical effects:

[0046] 1. The present invention has a low-latency characteristic. By using FPGA to process array antenna signals, the technology can achieve low-latency beam direction finding. This is because FPGA can perform parallel processing, avoiding the delay caused by interrupt switching of DSP during the processing process, thereby meeting the requirements for rapid response, especially in the direction finding application of high-speed flying targets. With high parallel processing capabilities, FPGA has a high degree of parallel processing capabilities and can process multiple signal streams at the same time. This is in contrast to the sequential processing method of DSP, which increases the uncertainty and delay of the system when switching between multiple processes. The parallel processing of FPGA enables the system to respond quickly and obtain the direction angle of the flying target in real time. The present invention can enhance the system scalability. FPGA can provide a rich external interface, which enhances the system's expansion and external interaction capabilities. This makes the system more flexible and adaptable in subsequent upgrades and functional expansions, and can be adjusted and improved according to different application scenarios. .

[0047] 2. The present invention has accurate direction-finding capability. By using the siglepulse_Author simulation mathematical model, it can perform accurate beam weight calculation and output according to the actual array antenna parameters. This accuracy improves the direction-finding accuracy and makes the direction-finding of the flying target more reliable. It has good anti-interference ability. The present invention takes into account the influence of AD index and noise interference in the design, and adopts appropriate signal processing algorithms and filters, which can effectively reduce the influence of interference on the direction-finding results and improve the anti-interference ability of the system. This is particularly important in direction-finding applications in complex environments. It can process data in real time. The application of FPGA enables the technology to obtain and process the response signal of the flying target in real time, quickly calculate the direction angle of the target, and transmit it to the host computer in real time for subsequent strategy analysis. This real-time performance is crucial in dynamically changing application environments.

[0048] 3. The present invention can reduce the risk of desynchronization. Due to the DSP's cache requirements for sampled data, there may be a risk of desynchronization between different arrays. Through direct processing of FPGA, intermediate caching is avoided, the possibility of such desynchronization is reduced, and the accuracy of direction finding is ensured. In addition, by modeling antenna array parameters and other environmental factors, the system can better adapt to complex working environments and perform effective direction finding, thereby improving the system's adaptability in different scenarios. Through interaction with the host computer, the system can not only obtain the direction angle of the target, but also draw the flight trajectory in combination with parameters such as distance, thereby continuously optimizing the direction finding strategy and parameters to form a closed-loop control.

[0049] 4. The design of the present invention takes into account the adjustment principles of multiple control parameters, so that the system can be flexibly adjusted according to different application requirements and target characteristics, thereby improving the versatility of the system. Through the application of FPGA and precise mathematical modeling, the low-latency beam direction finding technology has significant advantages in direction finding accuracy, real-time performance, system scalability and anti-interference capability, and can effectively cope with complex flight target direction finding tasks. This makes the technology have broad application prospects in aerospace, military reconnaissance, and drones.

[0050] It should be appreciated that all combinations of the foregoing concepts, as well as additional concepts described in greater detail below, may be considered to be part of the inventive subject matter of the present disclosure, provided such concepts are not mutually inconsistent.

[0051] The foregoing and other aspects, embodiments and features of the present invention can be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as the features and / or beneficial effects of the exemplary embodiments, will be apparent from the following description or learned from the practice of the specific embodiments according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in various figures may be represented by the same reference numeral. For clarity, not every component is labeled in every figure. Embodiments of various aspects of the present invention will now be described by way of example and with reference to the accompanying drawings, in which:

[0053] Figure 1 This is the simulation process of the direction finding system signal processing algorithm in the embodiment of the present application.

[0054] Figure 2 This is a flowchart of FPGA development in an embodiment of this application.

[0055] Figure 3 This is a functional block diagram of the angle measurement module in an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to better understand the technical content of the present invention, specific embodiments are cited and described as follows in conjunction with the accompanying drawings. Various aspects of the present invention are described in this disclosure with reference to the accompanying drawings, in which many illustrative embodiments are shown. The embodiments of the present disclosure are not necessarily defined to include all aspects of the present invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed in the present invention are not limited to any implementation. In addition, some aspects disclosed in the present invention can be used alone, or in any appropriate combination with other aspects disclosed in the present invention.

[0057] See also Figure 1 , Figure 2 and Figure 3 As shown, a low-latency beam direction finding technology is characterized in that the method comprises the following steps:

[0058] S1, obtaining the hardware parameters of the test system and the expected technical indicators and characteristic information of the flight target to be tested, and determining the simulation mathematical model based on the above;

[0059] S2. Pass the parameters and indicators to the siglepulse_Author simulation mathematical model to obtain the array beam weight vector and the sum and difference beam amplitude vector, wherein the siglepulse_Author function includes: an array beam weight vector calculation equation, and a sum beam and difference beam calculation equation;

[0060] S3. Convert the established siglepulse_Author simulation mathematical model and the obtained beam weight vector into an FPGA program, which has the ability to obtain the direction angle of the flying target in real time according to the response signal of the flying target, and can transmit the azimuth parameter to the host computer in real time for strategy and interaction.

[0061] S4, burning the FPGA program into the baseband board of the direction finding system, and operating according to the direction test process to complete the direction angle test;

[0062] Furthermore, the design in step S2 is specifically as follows:

[0063] 1) Construct the beam introduction signal equation based on the actual array antenna parameters;

[0064] The steering vector equation for constructing a uniform linear array is expressed as:

[0065]

[0066] Where θ is the signal incident azimuth, d is the spacing between uniform linear arrays, M is the number of antenna elements, and λ is the wavelength.

[0067] 2) Solve the equations based on the actual array antenna parameters and beam weight output;

[0068]

[0069] Where x(t) is the input signal of each array element

[0070] When the plane wave reaches the M-1 array element first and the 0th array element last, the time delay between the two adjacent array elements is dsin(θ). Therefore, if the signals arriving earlier from each array element are delayed in sequence, that is, the signals x(t) of each array element pass through the θ direction. After phase compensation, they will be added in phase, and the signal strength will increase by M times. Unwanted signals or interference from other directions may only be superimposed at random phases, and the signal strength will be much smaller. In the sense of spatial filtering, the signal in the θ direction is selected. Similarly, other signals can also be designed with other appropriate weight coefficients according to needs through similar methods to suppress interference and output the desired signal.

[0071] If the weight vectors are different, there will be different responses to signals from different incoming directions, thus forming different spatial beams.

[0072] 3) Solve the difference beam weight output equation based on the actual array antenna parameters;

[0073] The difference beam requires a null at the beam pointing location. The method used here is: first point the beam to θ 0 Centered on θ 0 Take two angles θ respectively r and θ l , the selection of these two angles is related to the 3dB cutoff angle of the beam main lobe. Assume that the 3dB main lobe width is θ abs , then θ r and θ l The equation is:

[0074]

[0075] Combining formula (3), we can get the difference beam output equation:

[0076] Δ(θ)=|α H (θ l )α(θ)|-|α H (θ r )α(θ)|(4)

[0077] Similarly, the sum beam also needs to be processed into amplitude values, that is,

[0078]

[0079] in Pointing to θ 0 The beam weight vector in the direction can also be expressed as α(θ 0 ) is expressed as follows:

[0080]

[0081] 4) solving the sum and difference beam amplitude ratio output equation according to the sum and difference beam weight vector;

[0082] Combining equations (3), (4) and (5), we get the sum and difference beam amplitude ratio output equation:

[0083]

[0084] As the name suggests, amplitude comparison direction finding uses the amplitude ratio of the difference beam and the sum beam as the single pulse ratio. In fact, it utilizes the symmetry of the left and right beams and is not limited to the particularity of the geometric structure of the array itself.

[0085] 5) Substitute the sum and difference beam amplitude ratio output values ​​into the pre-fitted linear function to find the corresponding angle value;

[0086] There is no explicit sub-expression for the single pulse ratio MRC of the amplitude comparison method, so it can only be obtained by curve fitting and then used for direction finding in the single pulse direction finding system.

[0087] Curve fitting can be obtained through the siglepulse_Author function, the function content is as follows:

[0088] First, you need to import parameters, including the number of antenna elements, the spacing between antenna elements, the beam frequency, and the angle measurement range. The specific process is as follows:

[0089] N = 8;

[0090] theta = (-90:0.1:90);

[0091] theta0=0;

[0092] thetaL=-7+theta0;

[0093] thetaR=7+theta0;

[0094] theta0 = theta0*pi / 180;

[0095] theta = theta * pi / 180;

[0096] thetaL = thetaL*pi / 180;

[0097] thetaR = thetaR*pi / 180;

[0098] d_lembda=0.1125 / (3e8 / 1030e6);

[0099] a=exp(j*2*pi*d_lembda*(0:N1)'*sin(theta+theta0));

[0100] wSigma=exp(j*2*pi*d_lembda*(0:N1)'*sin(theta0));

[0101] wDeltaL=exp(j*2*pi*d_lembda*(0:N-1)'*sin(thetaL));

[0102] wDeltaR=exp(j*2*pi*d_lembda*(0:N1)'*sin(thetaR));

[0103] ySigma = abs(wSigma'*a);

[0104] yDelta=abs(wDeltaL'*a)-abs(wDeltaR'*a);

[0105] figure;

[0106] plot(theta*180 / pi, 20*log10(ySigma / max(ySigma)), 'linewidth', 1);

[0107] hold on;

[0108] plot(theta*180 / pi, 20*log10(yDelta / max(yDelta)), 'linewidth', 1);

[0109] legend('sum beam', 'difference beam');

[0110] xlabel('azimuth / °'); ylabel('normalized power pattern / dB');

[0111] axis tight;

[0112] First, we simulated a large number of points. Different angles correspond to different ratios. The more points we get, the higher the angle resolution and the larger the table we get. When actually measuring the angle, we get the amplitude of the signal under the sum and difference beams, and then calculate the ratio of the two. After getting this ratio, we look it up in the table. The actual ratio calculated must be a floating point number. We round it off to a certain number of digits and find the same value in the table. If we use curve fitting, we can get a linear function similar to y=kx+b. Substitute the sum and difference ratio into it to get the angle.

[0113] grid on;

[0114] ylim([-50,0]);

[0115] title(sprintf('Number of elements: %d, beam direction: %.0f°', N, theta0))

[0116] m1=(-7+theta0-(-90)) / 0.1+1;

[0117] m2=(7+theta0-(-90)) / 0.1+1;

[0118] MRC=yDelta(m1:m2). / ySigma(m1:m2);

[0119] figure;

[0120] plot((-7:0.1:7),MRC,'linewidth',1);

[0121] set(gca,'XTick',[-7:1:7]);

[0122] xlabel('Angle (°)'); ylabel('Ratio of sum and difference');

[0123] axis tight;

[0124] grid on;

[0125] title('Sum and difference beam diagram');

[0126] Furthermore, the design in step S3 is specifically as follows:

[0127] 1) Circuit function design. Before designing the circuit system, certain preparations must be made, including demonstration scheme, design system, and selection of FPGA chips. System designers weigh system indicators, system operating speed, and chip resources according to the requirements of the design task to select qualified design schemes and appropriate device types. Usually, the design adopts a top-down design method, and the entire system is designed layer by layer.

[0128] 2) Input design: The process of representing the circuit or system to be designed in a form that meets the requirements in the FPGA development software and inputting it into the EDA tool is called design input.

[0129] 3) Functional simulation: After the circuit design file is completed, it is generally necessary to simulate and verify the function of the project engineering file to confirm whether the file can obtain the expected output under the given input.

[0130] 4) Synthesis: Synthesis can convert the design of conceptual hardware description language into logical or physical representation for the target device, and generate corresponding logical connections according to the target and optimization requirements. In order to successfully synthesize a standard gate-level structure netlist, the hardware description language written by the designer must conform to the programming language style required by the corresponding FPGA synthesizer. Currently, commonly used synthesis tools include Xilinx's XST and other development software, which can support gate-level and RTL-level program synthesis.

[0131] 5) Post-synthesis simulation: The standard delay file generated after synthesis is annotated into the simulation model to estimate the impact of gate delay in the design on the system. The purpose is to check whether the synthesized circuit meets the requirements of the original design. If it is found after layout and routing that the implemented circuit structure does not meet the functional design requirements of the system, it is necessary to return to the post-synthesis simulation to confirm the problems in the system design.

[0132] 6) Implementation and layout and routing. Layout is to reasonably configure the underlying units and hardware primitives in the logic netlist to the inherent hardware inside the FPGA chip. It is the basic requirement for FPGA circuit layout. It usually has two optimization methods: area optimization and speed optimization. Routing is to use various connection resources inside the FPGA chip to correctly and reasonably connect various related underlying components according to the designed topology.

[0133] 7) Timing simulation and verification. After generating the netlist file and completing the layout and routing, the system can usually complete the given function. However, there will be a certain delay when the signal passes through the physical logic device and the connection between the devices. Therefore, the simulation after layout and routing is also called timing simulation or post-simulation. The delay information it contains is the most accurate. Its purpose is to verify whether the system can complete the given function in the case of signal delay and eliminate competition and risk.

[0134] 8) Board-level simulation and verification. Board-level simulation is generally performed and verified using third-party tools. It is mainly used in high-speed circuit design to analyze characteristics such as electromagnetic interference and signal integrity of high-speed systems.

[0135] 9) Chip programming and debugging. Chip programming means that the EDA development tool generates the corresponding data files according to the previous steps, and then downloads the corresponding bit files to the specific FPGA chip. At present, mainstream programmable device suppliers have provided embedded online logic analyzers to solve this problem, such as ChipScope in Xilinx ISE development software. They only need to occupy very few logic resources to complete the online debugging of the system, which has very high practical value.

[0136] Furthermore, the design in step S4 is specifically as follows:

[0137] The input interface of the angle measurement module is the intermediate frequency signal of the sum channel, the intermediate frequency signal of the azimuth difference channel, the intermediate frequency signal of the elevation difference channel, the azimuth and elevation angles of the beam pointing, and the Doppler frequency deviation parameter; the output interface is the target azimuth information and the elevation angle information; its functional block diagram is shown in Figure 3. Figure 3 It can be seen that the front end of the angle measurement module completes the digital sampling of the intermediate frequency communication signal through the A / D conversion chip, converts the analog signal into a digital signal, and completes the quantization and encoding of the digital signal; after completing the A / D conversion, the quantized and encoded digital signal is sent to the FPGA for digital down-conversion (DDC) processing, converts the intermediate frequency signal into a baseband signal, and demodulates the signal into orthogonal I and Q channels; since the communication signal is a Doppler sensitive signal, it is necessary to use a series of Doppler compensation algorithms to improve the effect of matched filtering. The three-channel signal undergoes Doppler compensation and matched filtering signal processing at the same time, and then the modulus value of the sum channel signal after matched filtering is calculated, and the three-channel signal value corresponding to the sum channel peak point is selected. The FPGA transmits the selected three-channel signal data to the DSP through the link port. The DSP uses the sum and difference angle measurement formula to perform floating-point operations on the received data to obtain the angle information of the target.

[0138] After the design is completed, step S4 includes the following process: building a hardware test platform, which consists of an FPGA baseband board, an array antenna assembly, a host computer, and an RGS-2000NG test instrument.

[0139] The RGS-2000NG test instrument transmits a wireless response signal to the test platform at a specific direction and distance. The test platform receives the signal through the array antenna and sends it to the FPGA baseband chip through AD sampling.

[0140] The FPGA baseband board performs orthogonal digital down-conversion, decimation, and low-pass filtering on the input signal, and then sends it to the beam weight digital filter group for filtering. It calls the Complex Multiplier and CORDIC FPGA IP cores to implement complex multiplication and square root operations to obtain two sets of vectors: the sum beam and the difference beam.

[0141] Call the Divider Generator IP core to realize the ratio of the sum signal and the difference signal, compare the ratio with the ideal fitting value pre-stored in ROM, output the direction angle value of the current flight target and pass it to the host computer;

[0142] The host computer obtains the direction angle value of the current flying target in real time and combines it with parameters such as distance to draw the flight trajectory of the target and make corresponding strategies;

[0143] The RGS-2000NG test instrument tests and records according to the above process at different directions and distances, realizing a closed loop of the directional test process.

[0144] In some embodiments, designing each control parameter according to the control system design principle and performance index includes: designing the control parameters of the entire control system of the cruise missile according to the following principles: Principle 1: The main lobe width of the beam is constrained by the actual antenna array parameters by the antenna array parameter constraint principle; Principle 2: The higher the matching procedure of the guidance signal and the weight vector, the higher the linearity of the sum difference ratio and the direction angle, and the higher the direction finding accuracy, and vice versa; Principle 3: Limited by the AD index and the influence of noise interference and antenna parameters, the resolution of direction finding cannot reach the ideal state; Principle 4: Due to the beam sidelobe limitation, the direction finding of two flying targets at different angles and the same distance results in a certain degree of directional ambiguity. Principle 5: Due to the blind spot theory, the test instrument simulating the flying target cannot be placed within 50 wavelengths from the test system.

[0145] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A low-latency beam direction finding method based on FPGA, characterized in that: include: S1. Obtain the hardware parameters of the test system, the expected technical indicators and the characteristic information of the flight target to be tested, and determine the siglepulse_Author simulation mathematical model; S2. passing the hardware parameters and technical indicators to the siglepulse_Author simulation mathematical model to obtain the array beam weight vector and the sum and difference beam amplitude ratio vector, wherein the siglepulse_Author simulation mathematical model includes: an array beam weight vector calculation equation, and a sum beam and a difference beam calculation equation; S3, convert the established siglepulse_Author simulation mathematical model and the obtained beam weight vector into an FPGA program. The FPGA program obtains the direction angle of the flying target in real time according to the response signal of the flying target, and transmits the azimuth parameters to the host computer in real time for strategy and interaction; S4, burning the FPGA program into the baseband board of the direction finding system, and operating according to the direction test process to complete the direction angle test; Step S2 includes: Constructing a beam introduction signal vector according to actual array antenna parameters; The steering vector equation for constructing a uniform linear array is expressed as: ； in is the signal incident azimuth, d is the spacing between uniform linear arrays, M is the number of antenna elements, is the wavelength; Solve the equations based on the actual array antenna parameters and beam weight output; ； in x i ( t ) is the input signal of each array element; When the plane wave reaches the M-1 array element first and reaches the 0th array element last, the time delay between two adjacent array elements is Therefore, if the signals arriving earlier from each array element are delayed in sequence, that is, the signals x(t) of each array element are Direction Passing After phase compensation, they will be added in phase, and the signal strength will increase M times. Unwanted signals or interference from other directions may only be superimposed at random phases, and the signal strength will be smaller. The signal in the direction is selected. Similarly, other signals are also designed with other appropriate weight coefficients according to the requirements through the above method to suppress interference and output the desired signal. If the weight vectors are different, there will be different responses to signals from different wave directions, thus forming different spatial beams. Solve the difference beam weight output equation according to the actual array antenna parameters; The difference beam requires a null at the beam pointing location. First, the beam is pointed Centered on Take two angles respectively and , the selection of these two angles is related to the 3dB cutoff angle of the beam main lobe. Assume that the 3dB main lobe width is ,but and The equation is: ； Combining the above formula, we can get the difference beam output equation: ； Similarly, the sum beam also needs to be processed into amplitude values, that is, ； in To point to The beam weight vector of the direction can also be used The specific equation is as follows: ； Solve the sum and difference beam amplitude ratio output equation according to the sum and difference beam weight vector; Combination The equation, difference beam output equation, and amplitude value formula are used to obtain the sum and difference beam amplitude ratio output equation: ； Amplitude comparison direction finding uses the amplitude ratio of the difference beam and the sum beam as the single pulse ratio, making use of the symmetry of the left and right beams, and is not limited to the particularity of the geometric structure of the array itself; Substitute the sum and difference beam amplitude ratio output values ​​into the pre-fitted linear function to find the corresponding angle value.

2. The low-latency beam direction finding method based on FPGA according to claim 1, characterized in that: Step S3 includes: Input the array antenna type, number of array elements, array element distance and wavelength parameters to the siglepulse_Author simulation mathematical model, and call the guidance calculation formula to construct a directional input beam signal; Constructing the beam filter bank output sum and difference beams according to the beam weights and difference beam weights and calculating the sum and difference ratio; Substitute the ratio into the fitted linear function to output the direction angle value.

3. The low-latency beam direction finding method based on FPGA according to claim 1 or 2, characterized in that: Step S4 includes the following process: Build a hardware test platform, which consists of FPGA baseband board, array antenna assembly, host computer, and RGS-2000NG test instrument; The RGS-2000NG test instrument transmits a wireless response signal to the test platform at a specific direction and distance. The test platform receives the signal through the array antenna and sends it to the FPGA baseband chip through AD sampling. The FPGA baseband board performs orthogonal digital down-conversion, decimation, and low-pass filtering on the input signal, and then sends it to the beam weight digital filter group for filtering. It calls the Complex Multiplier and CORDIC FPGA IP cores to implement complex multiplication and square root operations to obtain two sets of vectors: the sum beam and the difference beam. Call the Divider Generator IP core to realize the ratio of the sum signal and the difference signal, compare the ratio with the ideal fitting value pre-stored in ROM, output the direction angle value of the current flight target and pass it to the host computer; The host computer obtains the direction angle value of the current flying target in real time and combines it with the distance parameter to draw the flight trajectory of the target and make corresponding strategies; The RGS-2000NG test instrument tests and records according to the above process at different directions and distances, realizing a closed loop of the directional test process.

Images