Method and device for processing layout

Abstract

The embodiment of the invention provides a method and a device for processing a layout. The method comprises the following steps: receiving a plurality of OASIS file blocks respectively corresponding to a plurality of layout blocks of the layout; and merging the plurality of OASIS file blocks to generate an OASIS file corresponding to the layout. In this way, deserialization processing on the layout data on the main node and OASIS format conversion processing on all the layouts can be avoided, and therefore use of computing resources of the main node is reduced. In addition, merging processing on the original layout blocks on the main node can be avoided, and use of memory resources is reduced. In addition, layout data transmission can be carried out between the working node and the main node in an OASIS format, and the data volume of network transmission is reduced.

Description

Technical Field

[0001] The present disclosure generally relates to the field of chip design tools, and more particularly to a method, an apparatus, an electronic device, a computer-readable storage medium, a computer program product, and a chip for processing a layout. Background Art

[0002] Electronic design automation (EDA) software is widely used in chip design. With the help of various EDA software, engineers can easily carry out chip design, such as architecture design and register transfer level (RTL) code design, synthesis, design for test (DFT), physical development and signoff.

[0003] Layout processing is an important step in chip design. With the development of technology, the resolution of chip design processes is becoming more and more refined, and the complexity of chip design is becoming higher and higher. This also leads to a large amount of layout data that needs to be processed. Usually, the layout can be processed in a distributed manner to increase the processing speed. For example, the layout can be divided into multiple layout blocks, the layout blocks are processed by working nodes, and then the processed layout blocks are transmitted to the master node for merging. However, transmitting the processed layout blocks to the master node requires serialization and deserialization of the layout data. The processing overhead of the master node is therefore large, because the computing resources of the master node need to be occupied for deserialization processing, and then the memory resources of the master node need to be occupied for merging processing of the layout data. In this case, the master node usually takes a long time to perform deserialization and merging. Summary of the invention

[0004] In view of the above problems, an embodiment of the present disclosure aims to provide a solution for processing a layout, which can use a working node to convert multiple layout blocks of a layout into multiple open artwork system interchange standard (OASIS) file blocks, and the master node only needs to merge multiple OASIS file blocks to obtain the OASIS file corresponding to the entire layout. In this way, it is possible to avoid deserializing the layout data on the master node and converting all layouts into OASIS format, thereby reducing the use of computing resources of the master node. In addition, it is possible to avoid merging the original layout blocks on the master node, reducing the use of memory resources. In addition, the layout data is transmitted between the working node and the master node in OASIS format, which can reduce the amount of data transmitted over the network.

[0005] In a first aspect of the present disclosure, a method for processing a layout is provided, comprising: receiving a plurality of OASIS file blocks corresponding to a plurality of layout blocks of the layout; and merging the plurality of OASIS file blocks to generate an OASIS file corresponding to the layout.

[0006] In this way, the master node can directly merge multiple OASIS file blocks to obtain the OASIS file corresponding to the entire layout, avoiding the deserialization of layout data and the OASIS format conversion of all layouts on the master node, thereby reducing the use of computing resources of the master node. In addition, it is possible to avoid merging the original layout blocks on the master node, reducing the use of memory resources. In addition, layout data can be transmitted between the working node and the master node in OASIS format, reducing the amount of data transmitted over the network.

[0007] In some embodiments of the first aspect, merging the multiple OASIS file blocks includes: generating a first header byte and a first tail byte of the OASIS file; removing corresponding header bytes and corresponding tail bytes of the multiple OASIS file blocks to obtain corresponding multiple intermediate byte sets of the multiple OASIS file blocks; and merging the first header byte and the first tail byte of the OASIS file with the corresponding multiple intermediate byte sets of the multiple OASIS file blocks.

[0008] In this way, a solution for merging multiple OASIS file blocks is provided, which can realize the merging of multiple OASIS file blocks.

[0009] In some embodiments of the first aspect, the header bytes include a header byte and a start record, the tail bytes include an end record, and the intermediate byte set includes a unit record, a unit name record, and an attribute record.

[0010] In some embodiments of the first aspect, before receiving the multiple OASIS file blocks, the method also includes: dividing the layout into the multiple layout blocks; serializing the multiple layout blocks; and sending the serialized multiple layout blocks to at least one first processing device.

[0011] In this way, the master node can divide the layout into multiple layout blocks and transmit them to the working nodes, so that the working nodes can perform distributed processing on the layout data.

[0012] In some embodiments of the first aspect, a format of the plurality of OASIS file chunks complies with one or more OASIS constraints for avoiding OASIS file chunk conflicts.

[0013] In this way, it is possible to avoid byte conflicts in multiple OASIS file blocks when merging multiple OASIS file blocks, thereby ensuring that the correct OASIS file corresponding to the entire layout is obtained.

[0014] In some embodiments of the first aspect, the conflict comprises at least one of: a reference number conflict, a table conflict, a start record conflict, an end record conflict, and a CBLOCK conflict.

[0015] In a second aspect of the present disclosure, a method for processing a layout is provided. The method comprises: obtaining a plurality of initial layout blocks of a layout; performing layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks; and converting the plurality of target layout blocks into a plurality of open source system exchange standard OASIS file blocks.

[0016] In this way, OASIS format conversion processing can be performed at the working node, serialization processing can be avoided at the working node, and deserialization processing and OASIS format conversion processing of layout data can be avoided on the main node, thereby reducing the use of computing resources.

[0017] In some embodiments of the second aspect, the multiple initial layout blocks are unserialized initial layout blocks, and obtaining the multiple initial layout blocks of the layout includes: obtaining the multiple serialized initial layout blocks; and deserializing the multiple serialized initial layout blocks to generate the multiple initial layout blocks.

[0018] In this way, the worker nodes can perform distributed processing on the layout blocks.

[0019] In some embodiments of the second aspect, a format of the plurality of OASIS file chunks complies with one or more OASIS constraints for avoiding OASIS file chunk conflicts.

[0020] In this way, it is possible to avoid byte conflicts in multiple OASIS file blocks when merging multiple OASIS file blocks, thereby ensuring that the correct OASIS file corresponding to the entire layout is obtained.

[0021] In some embodiments of the second aspect, the conflict comprises at least one of: a reference number conflict, a table conflict, a start record conflict, an end record conflict, and a CBLOCK conflict.

[0022] According to a third aspect of the present disclosure, a method for processing a layout is provided. The method comprises: obtaining a plurality of initial layout blocks of a layout from a second processing device by at least one first processing device; performing layout optimization processing on the plurality of initial layout blocks by the at least one first processing device to generate a plurality of target layout blocks; converting the plurality of target layout blocks into a plurality of open source image system exchange standard OASIS file blocks by the at least one first processing device; receiving the plurality of OASIS file blocks from the at least one first processing device by the second processing device; and merging the plurality of OASIS file blocks by the second processing device to generate an OASIS file corresponding to the layout.

[0023] According to a fourth aspect of the present disclosure, a device for processing a layout is provided. The device comprises: a receiving unit configured to receive a plurality of Open Source System Interchange Standard OASIS file blocks corresponding to a plurality of layout blocks of the layout; and a merging unit configured to merge the plurality of OASIS file blocks to generate an OASIS file corresponding to the layout.

[0024] In some embodiments of the fourth aspect, the merging unit is further configured to: generate a first header byte and a first tail byte of the OASIS file; remove corresponding header bytes and corresponding tail bytes of the multiple OASIS file blocks to obtain corresponding multiple intermediate byte sets of the multiple OASIS file blocks; and merge the first header byte and the first tail byte of the OASIS file with the corresponding multiple intermediate byte sets of the multiple OASIS file blocks.

[0025] In some embodiments of the fourth aspect, the header bytes include a header byte and a start record, the tail bytes include an end record, and the intermediate byte set includes a unit record, a unit name record, and an attribute record.

[0026] In some embodiments of the fourth aspect, the device also includes: a segmentation unit configured to segment the layout into the multiple layout blocks; a serialization unit configured to serialize the multiple layout blocks; and a sending unit configured to send the serialized multiple layout blocks to at least one first processing device.

[0027] In some embodiments of the fourth aspect, a format of the plurality of OASIS file chunks complies with one or more OASIS constraints for avoiding OASIS file chunk conflicts.

[0028] In some embodiments of the fourth aspect, the conflict comprises at least one of: a reference number conflict, a table conflict, a start record conflict, an end record conflict, and a CBLOCK conflict.

[0029] According to a fifth aspect of the present disclosure, a device for processing a layout is provided. The device comprises: an acquisition unit configured to acquire a plurality of initial layout blocks of the layout; a generation unit configured to perform layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks; and a conversion unit configured to convert the plurality of target layout blocks into a plurality of open source system exchange standard OASIS file blocks.

[0030] In some embodiments of the fifth aspect, the multiple initial layout blocks are unserialized initial layout blocks, and the acquisition unit is further configured to: acquire the multiple serialized initial layout blocks; and deserialize the multiple serialized initial layout blocks to generate the multiple initial layout blocks.

[0031] In some embodiments of the fifth aspect, a format of the plurality of OASIS file chunks complies with one or more OASIS constraints for avoiding OASIS file chunk conflicts.

[0032] In some embodiments of the fifth aspect, the conflict comprises at least one of: a reference number conflict, a table conflict, a start record conflict, an end record conflict, and a CBLOCK conflict.

[0033] According to a sixth aspect of the present disclosure, a system for processing a layout is provided. The system comprises: a first processing device, the first processing device comprising: an acquisition unit, configured to acquire a plurality of initial layout blocks of a layout from a second processing device; a generation unit, configured to perform layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks; and a conversion unit, configured to convert the plurality of target layout blocks into a plurality of open source system exchange standard OASIS file blocks; and a second processing device, the second processing device comprising: a receiving unit, configured to receive the plurality of OASIS file blocks from the at least one first processing device; and a merging unit, configured to merge the plurality of OASIS file blocks to generate an OASIS file corresponding to the layout.

[0034] In the seventh aspect of the present disclosure, there is provided an electronic device comprising at least one processor and at least one memory, wherein the at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, wherein the instructions, when executed by the at least one processor, enable the electronic device to implement: receiving a plurality of OASIS file blocks corresponding to a plurality of layout blocks of a layout, respectively; and merging the plurality of OASIS file blocks to generate an OASIS file corresponding to the layout.

[0035] In an eighth aspect of the present disclosure, there is provided an electronic device comprising at least one processor and at least one memory, wherein the at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, wherein the instructions, when executed by the at least one processor, enable the electronic device to implement: acquiring a plurality of initial layout blocks of a layout; performing layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks; and converting the plurality of target layout blocks into a plurality of Open Artifact System Interchange Standard OASIS file blocks.

[0036] In the ninth aspect of the present disclosure, there is provided an electronic device, comprising at least one processor and at least one memory, wherein the at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, wherein the instructions, when executed by the at least one processor, enable the electronic device to implement: acquiring, by at least one first processing device, a plurality of initial layout blocks of a layout from a second processing device; performing layout optimization processing on the plurality of initial layout blocks by the at least one first processing device to generate a plurality of target layout blocks; converting the plurality of target layout blocks into a plurality of Open Artifact System Interchange Standard OASIS file blocks by the at least one first processing device; receiving the plurality of OASIS file blocks from the at least one first processing device by the second processing device; and merging the plurality of OASIS file blocks by the second processing device to generate an OASIS file corresponding to the layout.

[0037] In the tenth aspect of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the operations of the method according to the first aspect or any one of its embodiments are implemented.

[0038] In an eleventh aspect of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the operations of the method according to the second aspect or any one of its embodiments are implemented.

[0039] In the twelfth aspect of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the operations of the method according to the third aspect or any one of its embodiments are implemented.

[0040] In a thirteenth aspect of the present disclosure, a computer program or a computer program product is provided. The computer program or computer program product is tangibly stored on a computer-readable medium and includes computer executable instructions, which, when executed, implement the operation of the method according to the first aspect or any of its embodiments.

[0041] In a fourteenth aspect of the present disclosure, a computer program or a computer program product is provided. The computer program or computer program product is tangibly stored on a computer-readable medium and includes computer executable instructions, which, when executed, implement the operation of the method according to the second aspect or any of its embodiments.

[0042] In a fifteenth aspect of the present disclosure, a computer program or a computer program product is provided. The computer program or computer program product is tangibly stored on a computer-readable medium and includes computer executable instructions, which, when executed, implement the operation of the method according to the third aspect or any of its embodiments.

[0043] In a sixteenth aspect of the present disclosure, a chip or a chip system is provided, which includes a processing circuit configured to perform operations according to the method in the first aspect or any of its embodiments.

[0044] In a seventeenth aspect of the present disclosure, a chip or a chip system is provided, which includes a processing circuit configured to perform the operations of the method according to the second aspect or any of its embodiments.

[0045] In an eighteenth aspect of the present disclosure, a chip or a chip system is provided, which includes a processing circuit configured to perform operations according to the method in the third aspect or any one of its embodiments.

[0046] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner.

[0048] Figure 1A An example flow chart showing the chip design and manufacturing process;

[0049] Figure 1B An example block diagram of a related distributed processing system is shown;

[0050] Figure 2 An example flow chart showing the distributed processing of the relevant layout is shown;

[0051] Figure 3 An example flow chart of layout distributed processing according to some embodiments of the present disclosure is shown;

[0052] Figure 4 An example flow chart of a method for processing a layout according to some embodiments of the present disclosure is shown;

[0053] Figure 5 An example flow chart of a method for processing a layout according to some embodiments of the present disclosure is shown;

[0054] Figure 6 An example flow chart of a method for merging multiple OASIS file blocks according to other embodiments of the present disclosure is shown;

[0055] Figure 7 An example flow chart of a method for processing a layout according to still other embodiments of the present disclosure is shown;

[0056] Figure 8 A schematic block diagram of an apparatus for processing a layout according to some embodiments of the present disclosure is shown;

[0057] Fig. 9 A schematic block diagram of an apparatus for processing a layout according to some other embodiments of the present disclosure is shown;

[0058] Fig.10 A schematic block diagram showing an apparatus for processing a layout according to some further embodiments of the present disclosure; and

[0059] Fig.11 A schematic block diagram of an example device that can be used to implement embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0060] The principles and spirit of the present disclosure will be described below with reference to several exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these specific embodiments is only to enable those skilled in the art to better understand and implement the present disclosure, and does not limit the scope of the present disclosure in any way. In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the meanings commonly understood by those of ordinary skill in the art.

[0061] The term "including" and its variations used in this document represent open inclusion, that is, "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one other embodiment". Terms such as "upper", "lower", "front", and "rear" indicating placement or positional relationships are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the principles of the present disclosure, and do not indicate or imply that the referred elements must have a specific orientation, be constructed or operate in a specific orientation, and therefore should not be understood as limitations on the present disclosure.

[0062] Figure 1A An example flow chart of a chip design and manufacturing process 100A is shown. The design and manufacturing process 100A starts with specification formulation 110. At the stage of specification formulation 110, the requirements for the functions and performances that the integrated circuit needs to achieve are determined. At the stage of chip design 120, circuit design is performed with the aid of EDA software to obtain, for example, a layout file for chip manufacturing. Based on the difference in circuits (e.g., digital circuits or analog circuits), the design 120 may include different design links. At the stage of manufacturing 140, integrated circuits are formed on wafers through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. At the stage of packaging 150, the wafer is cut to obtain a bare die, and the bare die is packaged to obtain a chip through processes such as pasting, welding, and mold sealing. The obtained chip is tested at the stage of testing 160 to ensure that the performance of the finished chip meets the requirements determined in the specification formulation 110. The chip 170 that passes the test can be delivered to the customer. It can be understood that the above process is only illustrative and does not limit the scope of the present disclosure. In some cases, the design and manufacturing process of the chip may be different. For example, tape-out may be performed before manufacturing 140. A small number of chips obtained from the tape-out may be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates that the tape-out has failed and the chip design may need to be adjusted or redesigned.

[0063] In some embodiments, the design 120 of the digital circuit may exemplarily include an architecture design 121, an RTL design 123, a functional simulation 125, a synthesis 127, a timing analysis 129, a DFT 131, a verification check 133, a layout 135, a design rule check (DRC) 137, and a layout 139. The architecture design 121 includes, for example, designing the architecture of the chip. For example, EDA software may be used to determine the categories and quantities of components or subcircuits included in the chip system, as well as the functions, connections, and interactions of each component or subcircuit. In the stage of RTL design 123, a hardware programming language such as Verilog or VHDL may be used to describe the determined chip architecture in code at the RTL level. Functional simulation 125 is also referred to as RTL-level behavioral simulation or front-end simulation. The purpose of functional simulation is to analyze the correctness of the logical relationship of the design circuit. Synthesis 127 may convert RTL into a gate-level netlist. Synthesis 127 may include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis may first convert the RTL code into a general Boolean equation and compile it. The netlist may be optimized according to the constraints imposed by the designer, such as delay and area, and then the RTL netlist may be mapped to the process library to generate a gate-level netlist.

[0064] Timing analysis 129 includes static timing analysis, which mainly involves timing calculation and prediction of digital circuits. Timing analysis is performed on the paths in the digital circuit to determine whether timing convergence is achieved, thereby ensuring whether the timing of various circuits meets various timing requirements. The verification of such digital circuits is usually completed statically and does not require simulation of digital logic. At the stage of DFT 131, various hardware logics for improving chip testability (including controllability and observability) can be embedded in the design. By using this part of logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits. DFT can, for example, include a test method based on a scan chain or a built-in self-test circuit (BIST). At the stage of verification check 133, the circuit can be formally verified and / or equivalence checked. Formal verification can use mathematical methods to prove its correctness or incorrectness based on one or more formal specifications or attributes. Formal verification can, for example, include abstract interpretation, formal model checking (also known as characteristic checking) and theorem proving. Equivalence checking can be used to verify whether the register transfer level design is consistent with the gate-level netlist, and between the gate-level netlist and the gate-level netlist.

[0065] In the stage of layout and routing 135, the chip circuit can be laid out (placement) and routed (routing). The layout can reasonably arrange the gate-level netlist generated by logic synthesis 127 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing generally expects the total routing to be short, the routing delay to meet the timing requirements, and to comply with the routing rules in the process (such as routing density). Although layout and routing are described separately here, this is only illustrative and does not limit the scope of the present disclosure. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.

[0066] At the DRC 137 stage, the layout can be checked for potential open circuits, short circuits or adverse effects caused by violations of design rules. After passing the DRC, a file representing the layout, such as a GDSII file, an OASIS file, etc., can be generated 139 by the EDA software. It can be understood that the above links are only exemplary and not intended to limit the scope of the present disclosure. In the actual design process, the above links can be added, deleted or modified according to design needs. In addition, some of the above links can be implemented by different EDA software or integrated in one or more EDA software. The present disclosure does not limit this.

[0067] As mentioned above, as the amount of layout data that needs to be processed becomes increasingly large, the layout can usually be processed in a distributed manner to increase processing speed. Figure 1B An example block diagram of a related distributed processing system 100B is shown. Figure 1B As shown, in a distributed processing system, computing nodes can be classified into master nodes 102 (master node) and worker nodes 104 (worker node) according to processing logic. System 100B may include master node 102 and worker nodes 104-1 to 104-3. Master node 102 is the central node in the distributed system, responsible for the scheduling of the overall business, distribution and aggregation of data. Worker nodes 104-1 to 104-3 are processing nodes in the distributed system, responsible for processing the distributed data and returning the processed data. In some embodiments, at least one of the master node and the worker node may be, for example, a computer or a server. It should be understood that Figure 1B The number of master nodes and working nodes does not constitute a limitation of the present disclosure, and system 100B may include any number of master nodes and working nodes.

[0068] Figure 2 An example flow chart of the related layout distributed processing 200 is shown. First, in 220, the master node can divide the layout file 210 into multiple layout blocks (for example, layout blocks 1, 2, and 3), serialize the multiple layout blocks after segmentation, and then send the multiple layout blocks to at least one working node (for example, three working nodes). At least one working node performs distributed processing on the layout blocks respectively. In 230 (including 230-1 to 230-3), the working node deserializes and optimizes the received serialized multiple layout blocks, and then serializes the processed layout blocks and sends them to the master node. In 240, the master node deserializes the received processed and serialized multiple layout blocks, merges the layout blocks in memory, and obtains the processed entire layout. The master node then converts the entire layout into a layout file in OASIS format. In 250, the master node exports the generated OASIS file.

[0069] However, in the above 230-1 to 230-3 and 240, the master node needs to serialize and deserialize the processed multiple layout blocks, which has a large processing overhead. This requires the master node's computing resources to perform deserialization processing, and the master node's memory resources to perform layout data merging processing.

[0070] In order to solve or alleviate the above-mentioned problems and other potential problems, a scheme for processing a layout is proposed in each embodiment of the present disclosure, aiming to realize the use of working nodes to convert multiple layout blocks of the layout at each working node into multiple OASIS file blocks respectively. The master node merges multiple OASIS file blocks to obtain the OASIS file corresponding to the entire layout. This can avoid deserialization of layout data and OASIS format conversion of all layouts on the master node, thereby reducing the use of computing resources of the master node. In addition, it can avoid merging the original layout blocks on the master node, reducing the use of memory resources. In addition, layout data can be transmitted between the working node and the master node in OASIS format, reducing the amount of data transmitted over the network, and solving some other potential problems.

[0071] Figure 3 FIG. 3 shows an example flow chart of layout distributed processing 300 according to some embodiments of the present disclosure. Figures 4 to 7 right Figure 3 The method 300 may be executed by an electronic device such as a computer. It should be understood that Figure 3 The method may include other additional steps not shown, or some steps shown may be omitted. The scope of the present disclosure is not limited thereto.

[0072] In 320, the master node may divide the layout file 310 into a plurality of layout blocks, and perform serialization processing on the plurality of layout blocks after division. The master node then sends the plurality of layout blocks to at least one working node, and the working node then performs distributed processing on the layout blocks. For example, the master node may divide the layout block 310 into three layout blocks, including layout blocks 1, 2, and 3. The master node performs serialization processing on the three layout blocks after division, and then sends the three layout blocks to the three working nodes. In some embodiments, the serialization processing includes converting the data into a format such as Protobuf, MessagePack, etc., to be suitable for network transmission.

[0073] In some embodiments, the layout file may store graphic data in a two-dimensional spatial coordinate system, and the master node may perform spatial segmentation processing on the layout according to a fixed size. As an example, the size of the layout file is 1000 microns * 1000 microns. The master node is segmented according to a fixed size of 100 microns * 100 microns to obtain 10 * 10 small layouts. Each small layout is 100 microns * 100 microns in size. These small layouts can be called layout blocks or tiles. In some embodiments, a layout block can be the smallest data unit in a distributed scene.

[0074] In some embodiments, during the layout segmentation process, when cropping some layout graphics that span multiple regions, the original graphics can be cropped according to the boundaries of the regions. In some embodiments, after obtaining the layout block data, the master node serializes the layout block data to obtain binary data, and then transmits the binary data of the layout block to the working node through the network protocol.

[0075] In 330, the working node performs deserialization and layout optimization on the received serialized multiple layout blocks. Then the working node converts the processed layout blocks into one or more OASIS files. OASIS is a layout file format with good compression efficiency. For example, in 330-1, the first working node performs deserialization and layout optimization on the received serialized first layout block, and converts it into a first OASIS file block. Similarly, in 330-2 and 330-3, the second working node and the third working node respectively perform deserialization and layout optimization on the received serialized second layout block and the third layout block, and convert them into a second OASIS file block and a third OASIS file block.

[0076] Specifically, 330 can be combined with Figure 4 Give a description. Figure 4 An example flow chart of a method 400 for processing a layout according to some embodiments of the present disclosure is shown. In 410, a working node obtains multiple initial layout blocks of a layout. The initial layout blocks are initial layout blocks that are not serialized, that is, original layout blocks. In some embodiments, the working node obtains multiple serialized initial layout blocks from the master node, and deserializes the multiple serialized initial layout blocks to restore the multiple initial layout blocks.

[0077] In 420, the working node performs layout optimization processing on the multiple initial layout blocks to generate multiple target layout blocks. In some embodiments, depending on the specific business, the working node can perform one or more rounds of layout optimization processing on the multiple initial layout blocks, such as optical proximity correction (OPC) processing. It can be understood that the layout optimization processing is not limited to OPC, and can also include other optimization processing for layout design, such as source mask optimization (SMO). In some embodiments, during the layout optimization processing, the working node may communicate with other working nodes to synchronize layout data.

[0078] In 430, the working node converts the multiple target layout blocks into multiple OASIS file blocks. The OASIS file block is composed of continuous binary data, which is conducive to network transmission. In some embodiments, after the layout optimization process, the hierarchical structure between the layout blocks has been eliminated. All layout graphics can be placed in the same OASIS unit, and the structure of each OASIS file block is shown in Table 1.

[0079] Table 1

[0080]

[0081] In Table 1, MAGICBYTES represents the header byte of the OASIS file block, also known as the magic byte, which is used to identify the current file as an OASIS file. START record represents the start record, which is used to indicate the beginning of the OASIS file. CELL record represents the OASIS cell record, which is used to indicate the information of the CELL in the OASIS file. CELL is a named object in the layout, which contains the graphic information, annotation information of the current CELL, and the location information of other CELLs. CELLNAMErecord represents the OASIS cell name record, which is used to describe the name of the CELL in the OASIS file. PROPERTY record represents the property record, which is used to describe the property value of the OASIS file. END record represents the end record, which is used to indicate the end of the OASIS file. Among them, the header byte and the start record can be called the header byte, and the end record can be called the tail byte.

[0082] Continue to refer Figure 3 At 340, each of the multiple working nodes sends the OASIS file generated by it to the master node, and then the master node merges the multiple OASIS file blocks to obtain the OASIS file corresponding to the entire layout.

[0083] Specifically, 340 can be combined with Figure 5 Give a description. Figure 5 An example flow chart of a method 500 for processing a layout according to some embodiments of the present disclosure is shown. In 510, a master node receives a plurality of OASIS file blocks corresponding to a plurality of layout blocks of a layout from a plurality of worker nodes. In 520, the master node merges the plurality of OASIS file blocks to generate an OASIS file corresponding to the entire layout.

[0084] In some embodiments, the master node generates a first header byte and a first tail byte of the OASIS file corresponding to the entire layout, removes corresponding header bytes and corresponding tail bytes of multiple OASIS file blocks to obtain corresponding multiple intermediate byte sets of multiple OASIS file blocks, and merges the first header byte and the first tail byte of the OASIS file corresponding to the entire layout with the corresponding multiple intermediate byte sets of multiple OASIS file blocks.

[0085] In some embodiments, the header bytes include header bytes (MAGICBYTES) and a start record (STARTrecord), the tail bytes include an end record (END record), and the intermediate byte set includes a cell record (CELL record), a cell name record (CELLNAMErecord), and a property record (PROPERTY record).

[0086] Furthermore, 520 can be combined with Figure 6 Give a description. Figure 6 An example flow chart of a method 600 for merging multiple OASIS file chunks according to still other embodiments of the present disclosure is shown.

[0087] In 610, the master node generates and exports a MAGICBYTES and a START record. The constructed MAGICBYTES and START record will be used as the header bytes and start records of the OASIS file corresponding to the entire layout. The two can be collectively referred to as header bytes. In 620, the master node receives the OASIS file block data of the layout block that has been processed by the layout optimization from the working node. In 630, each time the data of an OASIS file block is received, the master node removes the corresponding header bytes and the corresponding tail bytes of the OASIS file block, copies the CELL record part of the OASIS file block and exports it. In 640, the master node stores the name of the OASIS cell (e.g., cellname-string='cell1') and the offset in the exported file (e.g., propname-string="S_CELL_OFFSET").

[0088] In 650, the master node determines whether all OASIS file blocks corresponding to the layout have been processed. If it is determined that all OASIS file blocks have not been processed, the method returns to 620 and repeats the process of 620 to 650 until all OASIS file blocks are processed. If it is determined that all OASIS file blocks have been processed, the method 600 proceeds to 660.

[0089] In 660, the master node generates a new unit as the parent unit of all previous OASIS units and writes out its CELL record. In 670, the master node constructs and exports the CELLNAMErecord and PROPERTY record of all OASIS units, where all OASIS units include the units of the OASIS file block corresponding to the layout block and the newly generated parent unit. In 680, the master node constructs and exports the END record. As an example, the structure of the exported OASIS file is shown in Table 2.

[0090] Table 2

[0091]

[0092] In some embodiments, during the merging process of OASIS file blocks, conflicts may occur between multiple OASIS file blocks, resulting in inability to merge correctly. Therefore, one or more OASIS constraints can be set so that the formats of multiple OASIS file blocks follow one or more OASIS constraints for avoiding OASIS file block conflicts. In some embodiments, the OASIS file block conflict includes at least one of the following conflicts: reference number conflict, table conflict, start record conflict, end record conflict, CBLOCK conflict. Accordingly, the one or more OASIS constraints include at least one of the following constraints: reference number constraint, table constraint, start record constraint, end record constraint, CBLOCK constraint.

[0093] For each OASIS file, the cellname and propname it contains support reference-numbers expressed in digital form. When merging, reference-numbers in different OASIS files may be expressed with the same number, but the corresponding strings they represent are different, so reference-number conflicts may occur during merging. To resolve reference-number conflicts, you can set the following OASIS constraints: OASIS files do not use reference-numbers, but directly use strings to express them.

[0094] For example, referring to Table 3, before the reference-number constraint is applied, the OASIS file block uses reference-number (ie, ref-num). After the reference-number constraint is applied, the OASIS file block does not use reference-number and directly uses the string layout to represent it.

[0095] Table 3

[0096]

[0097] For each OASIS file, it contains cellname table, textstring table, propnametable, propstring table, layername table and xname table. The multiple tables of each OASIS file are independent of each other, so table conflicts may occur when merging. Cellname table is a collection of CELLNAMErecords in the OASIS file. Textstring table is a collection of TEXTSTRING records in the OASIS file. TEXTSTRING records are used to describe text strings in OASIS files. Propname table is a collection of PROPNAMErecords in the OASIS file. PROPNAMErecords are used to describe property names in OASIS files. Propstring table is a collection of PROPSTRING records in the OASIS file. PROPSTRING records are used to describe property strings in OASIS files. Layername table is a collection of LAYERNAMErecords in the OASIS file. LAYERNAMErecords are used to describe the name strings of the layers in the OASIS file. Xname table is a collection of XNAMErecords in the OASIS file. XNAME records are used to describe custom element name strings in OASIS files.

[0098] To resolve table conflicts, you can set the following OASIS constraints: the cellname table must be at the end, the cellnames of different OASIS files must not be repeated, only the S_CELL_OFFSET attribute is supported, the S_CELL_OFFSET value needs to be recalculated when merging, and only the strict mode is supported; the layername table must be at the end, the layernames of different OASIS files need to be deduplicated when merging, and only the strict mode is supported; no other tables are used.

[0099] Table constraints can be used together with reference-number constraints. For example, Table 4 shows the OASIS file format before and after the constraints are applied. It can be seen that before the constraints are applied, ref-num is used in the OASIS file block. After the constraints are applied, ref-num is not used in the OASIS file block, and the string S_CELL_OFFSET is used directly to represent it, and the requirements of the table constraint are also met.

[0100] Table 4

[0101]

[0102] Each OASIS file contains a START record. When merging the START records of each OASIS file, a conflict may occur. To resolve the conflict, you can set the following OASIS constraints: the offset-flag of the START record must be 1 (indicating that table-offsets is at the end), discard the original START record when merging, and generate a new START record when exporting.

[0103] Each OASIS file contains an END record. When merging, the END records of each OASIS file may conflict with each other. To resolve the conflict, you can set the following OASIS constraints: table-offsets is at the end; validation-scheme must be 0 (indicating that no validation is required); discard the original END record when merging, and generate a new END record when exporting. For example, referring to Table 5, after applying the END record constraint, cellname-offset and propname-offset are both at the end.

[0104] Table 4

[0105]

[0106] In addition, if the CBLOCK in the OASIS file block contains a table, it will make the merge more complicated. To simplify the merge operation, you can set the following OASIS constraint: CBLOCK does not contain a table.

[0107] Figure 7 FIG. 7 is an example flow chart of a method 700 for processing a layout according to some other embodiments of the present disclosure. The method 700 may be executed by EDA software. It should be understood that Figure 7 The method may include other additional steps not shown, or some steps shown may be omitted. The scope of the present disclosure is not limited thereto.

[0108] In 710, at least one first processing device obtains a plurality of initial layout blocks of a layout from a second processing device. In some embodiments, the first processing device may be a working node, and the second processing device may be a master node. The initial layout blocks may be original layout blocks that are not serialized. In 720, at least one first processing device performs layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks. In 730, at least one first processing device converts the plurality of target layout blocks into a plurality of OASIS file blocks.

[0109] In 740, a second processing device receives a plurality of OASIS file blocks from at least one first processing device. In 750, a second processing device merges the plurality of OASIS file blocks to generate an OASIS file corresponding to the layout.

[0110] According to the above scheme of the present disclosure, a plurality of layout blocks of a layout are converted into a plurality of OASIS file blocks by using a working node, so that the master node merges the plurality of OASIS file blocks to obtain the OASIS file corresponding to the entire layout. This can avoid deserialization processing of the layout data and OASIS format conversion processing of all layouts on the master node, thereby reducing the use of computing resources of the master node. In addition, it can avoid merging the original layout blocks on the master node, reducing the use of memory resources. In addition, the layout data can be transmitted between the working node and the master node in the OASIS format, reducing the amount of data transmitted over the network. Furthermore, the present disclosure also provides OASIS constraints, which can avoid conflicts when merging OASIS file blocks.

[0111] It should be noted that the above combination Figures 3 to 7 The examples are merely illustrative and should not be construed as limiting the embodiments of the present disclosure.

[0112] It should be understood that in the embodiments of the present disclosure, the expressions "first", "second", "third", etc. are only intended to indicate that multiple objects may be different, but do not exclude that two objects are the same. The expressions "first", "second", "third", etc. should not be interpreted as any limitation on the embodiments of the present disclosure.

[0113] It should also be understood that the above content is only to help those skilled in the art better understand the embodiments of the present disclosure, rather than to limit the scope of the embodiments of the present disclosure. Those skilled in the art may make various modifications, changes or combinations based on the above content. Such modifications, changes or combinations are also within the scope of the embodiments of the present disclosure.

[0114] Figure 8 A schematic block diagram of an apparatus 800 for processing a layout according to some embodiments of the present disclosure is shown. The apparatus 800 may be implemented by software, hardware, or a combination of both. Specifically, the apparatus 800 may be an EDA apparatus.

[0115] like Figure 8 As shown, the apparatus 800 includes a receiving unit 810 and a merging unit 820. The receiving unit 810 is configured to receive a plurality of open source image system exchange standard OASIS file blocks corresponding to a plurality of layout blocks of a layout. The merging unit 820 is configured to merge the plurality of OASIS file blocks to generate an OASIS file corresponding to the layout.

[0116] In some embodiments, the merging unit 820 may be further configured to generate a first header byte and a first tail byte of the OASIS file. The merging unit 820 may be further configured to remove corresponding header bytes and corresponding tail bytes of multiple OASIS file blocks to obtain corresponding multiple intermediate byte sets of multiple OASIS file blocks. The merging unit 820 may be further configured to merge the first header byte and the first tail byte of the OASIS file with corresponding multiple intermediate byte sets of multiple OASIS file blocks.

[0117] In some embodiments, the header bytes include a header byte and a start record, the tail bytes include an end record, and the intermediate byte set includes a unit record, a unit name record, and an attribute record.

[0118] In some embodiments, the apparatus 800 may further include a segmentation unit configured to segment the layout into a plurality of layout blocks. In some embodiments, the apparatus 800 may further include a serialization unit configured to serialize the plurality of layout blocks. In some embodiments, the apparatus 800 may further include a sending unit configured to send the plurality of serialized layout blocks to at least one first processing device.

[0119] In some embodiments, the format of the plurality of OASIS file chunks complies with one or more OASIS constraints for avoiding OASIS file chunk conflicts.

[0120] In some embodiments, the conflict includes at least one of: a reference number conflict, a table conflict, a start record conflict, an end record conflict, a CBLOCK conflict.

[0121] Fig. 9 A schematic block diagram of an apparatus 900 for processing a layout according to some other embodiments of the present disclosure is shown. The apparatus 900 may be implemented by software, hardware, or a combination of both. Specifically, the apparatus 900 may be an EDA apparatus.

[0122] like Fig. 9 As shown, the apparatus 900 includes an acquisition unit 910, a generation unit 920, and a conversion unit 930. The acquisition unit 910 is configured to acquire a plurality of initial layout blocks of a layout. The generation unit 920 is configured to perform layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks. The conversion unit 930 is configured to convert the plurality of target layout blocks into a plurality of open source system exchange standard OASIS file blocks.

[0123] In some embodiments, the multiple initial layout blocks are unserialized initial layout blocks. In some embodiments, the acquisition unit 910 may be further configured to: acquire multiple serialized initial layout blocks. The acquisition unit 910 may also be further configured to: deserialize the multiple serialized initial layout blocks to generate multiple initial layout blocks.

[0124] In some embodiments, the format of the plurality of OASIS file chunks complies with one or more OASIS constraints for avoiding OASIS file chunk conflicts.

[0125] In some embodiments, the conflict includes at least one of: a reference number conflict, a table conflict, a start record conflict, an end record conflict, a CBLOCK conflict.

[0126] Fig.10 A schematic block diagram of an apparatus 1000 for processing a layout according to some further embodiments of the present disclosure is shown. The apparatus 1000 may be implemented by software, hardware, or a combination of both. Specifically, the apparatus 1000 may be an EDA apparatus.

[0127] like Fig.10As shown, the apparatus 1000 includes a first processing device 1010 and a second processing device 1020. The first processing device 1010 includes an acquisition unit 1012, a generation unit 1014 and a conversion unit 1015. The acquisition unit 1012 is configured to acquire a plurality of initial layout blocks of a layout from the second processing device. The generation unit 1014 is configured to perform layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks. The conversion unit 1016 is configured to convert the plurality of target layout blocks into a plurality of open source system exchange standard OASIS file blocks.

[0128] The second processing device 1020 includes a receiving unit 1022 and a merging unit 1024. The receiving unit 1022 is configured to receive a plurality of OASIS file blocks from the at least one first processing device. The merging unit 1024 is configured to merge the plurality of OASIS file blocks to generate an OASIS file corresponding to the layout.

[0129] The division of modules or units in the embodiments of the present disclosure is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional unit in the disclosed embodiments may be integrated into one unit, or may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0130] Figures 8 to 10 The devices 800, 900, 1000 in the embodiment can be used to realize the above combination Figures 3 to 7 The various methods and processes described, such as process 300, methods 400, 500, 600, and 700, are not described in detail here for the sake of brevity.

[0131] Fig.11 A schematic block diagram of an example device 1100 that may be used to implement embodiments of the present disclosure is shown.

[0132] As shown in the figure, the device 1100 includes a central processing unit (CPU) 1101, a read-only memory (ROM) 1102, and a random access memory (RAM) 1103. The CPU 1101 can perform various appropriate actions and processes according to computer program instructions stored in the RAM 1102 and / or the RAM 1103 or computer program instructions loaded from the storage unit 1108 into the ROM 1102 and / or the RAM 1103. In the ROM 1102 and / or the RAM 1103, various programs and data required for the operation of the device 1100 can also be stored. The CPU 1101 and the ROM 1102 and / or the RAM 1103 are connected to each other via a bus 1104. An input / output (I / O) interface 1105 is also connected to the bus 1104.

[0133] A number of components in the device 1100 are connected to the I / O interface 1105, including: an input unit 1106, such as a keyboard, a mouse, etc.; an output unit 1107, such as various types of displays, speakers, etc.; a storage unit 1108, such as a disk, an optical disk, etc.; and a communication unit 1109, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1109 allows the device 1100 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0134] CPU 1101 can be various general and / or special processing components with processing and computing capabilities. Some examples that can be implemented include, but are not limited to, graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc., which can be referred to as computing units accordingly. CPU 1101 performs the various methods and processes described above, such as processing 300, methods 400, 500, 600, and 700. For example, in some embodiments, the various processes described above can be implemented as computer software programs, specifically EDA programs, which are tangibly contained in computer-readable media, such as storage unit 1108. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1100 via ROM 1102 and / or RAM 1103 and / or communication unit 1109. When the computer program is loaded into ROM 1102 and / or RAM 1103 and executed by CPU 1101, one or more steps of the process described above may be performed. Alternatively, in other embodiments, CPU 1101 may be configured to perform the various processes described above in any other appropriate manner (e.g., by means of firmware).

[0135] For example, Fig.11 The device 1100 in the embodiment may be implemented as a computing device, or may be implemented as a chip or a chip system in a computing device, which is not limited in the embodiments of the present disclosure.

[0136] The embodiment of the present disclosure further provides a chip, which may include an input interface, an output interface and a processing circuit. In the embodiment of the present disclosure, the input interface and the output interface may complete the interaction of signaling or data, and the processing circuit may complete the generation and processing of signaling or data information.

[0137] The embodiments of the present disclosure also provide a chip system, including a processor, for supporting a computing device to implement the functions involved in any of the above embodiments. In one possible design, the chip system may also include a memory for storing necessary program instructions and data, and when the processor runs the program instructions, the device on which the chip system is installed implements the method involved in any of the above embodiments. Exemplarily, the chip system may be composed of one or more chips, and may also include chips and other discrete devices.

[0138] An embodiment of the present disclosure further provides a processor for coupling with a memory, wherein the memory stores instructions. When the processor executes the instructions, the processor executes the methods and functions involved in any of the above embodiments.

[0139] The embodiments of the present disclosure also provide a computer program product including instructions, which, when executed on a computer, enables the computer to execute the methods and functions involved in any of the above embodiments.

[0140] An embodiment of the present disclosure further provides a computer-readable storage medium on which computer instructions are stored. When a processor executes the instructions, the processor executes the methods and functions involved in any of the above embodiments.

[0141] In general, various embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be performed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flow charts, or using some other graphical representation, it should be understood that the blocks, devices, systems, techniques, or methods described herein may be implemented as, by way of non-limiting example, hardware, software, firmware, dedicated circuits or logic, general purpose hardware or controllers or other computing devices, or some combination thereof.

[0142] The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer-readable storage medium. The computer program product includes computer executable instructions, such as instructions included in a program module, which are executed in a device on a real or virtual processor of the target to perform the process / method as described above with reference to the accompanying drawings. Typically, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform specific tasks or implement specific abstract data types. In various embodiments, the functions of program modules can be combined or divided between program modules as needed. Machine executable instructions for program modules can be executed in local or distributed devices. In distributed devices, program modules can be located in local and remote storage media.

[0143] The computer program code for realizing the method of the present disclosure can be written in one or more programming languages. These computer program codes can be provided to the processor of general-purpose computer, special-purpose computer or other programmable data processing device, so that the program code, when being executed by computer or other programmable data processing device, causes the function / operation specified in flow chart and / or block diagram to be implemented. The program code can be executed completely on computer, partly on computer, as independent software package, partly on computer and partly on remote computer or completely on remote computer or server.

[0144] In the context of the present disclosure, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like. Examples of signals may include electrical, optical, radio, acoustic or other forms of propagation signals, such as carrier waves, infrared signals, and the like.

[0145] A computer readable medium may be any tangible medium that contains or stores a program for or related to an instruction execution system, device, or apparatus. A computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of computer readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0146] In addition, although each operation is described in a specific order, this should be understood as not being limited to requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

[0147] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. A method for processing a layout, characterized in that: include: receiving a plurality of open source image system exchange standard OASIS file blocks corresponding to a plurality of layout blocks of the layout; as well as The multiple OASIS file blocks are merged to generate an OASIS file corresponding to the layout.

2. The method according to claim 1, characterized in that Merging the multiple OASIS file blocks includes: Generate a first header byte and a first tail byte of the OASIS file; removing corresponding header bytes and corresponding tail bytes of the plurality of OASIS file chunks to obtain corresponding plurality of intermediate byte sets of the plurality of OASIS file chunks; and The first header byte and the first trailer byte of the OASIS file are merged with the corresponding plurality of intermediate byte sets of the plurality of OASIS file chunks.

3. The method according to claim 2, characterized in that The header bytes include a header byte and a start record, the tail bytes include an end record, and the middle byte set includes a unit record, a unit name record, and an attribute record.

4. The method according to any one of claims 1 to 3, characterized in that Prior to receiving the plurality of OASIS file chunks, the method further comprises: Dividing the layout into the plurality of layout blocks; Serializing the plurality of layout blocks; and The serialized plurality of layout blocks are sent to at least one first processing device.

5. The method according to any one of claims 1 to 4, characterized in that The formats of the plurality of OASIS file chunks comply with one or more OASIS constraints for avoiding conflicts in the OASIS file chunks.

6. The method according to claim 5, characterized in that The conflict includes at least one of the following: reference number conflict, table conflict, start record conflict, end record conflict, CBLOCK conflict.

7. A method for processing a layout, characterized in that: include: Get multiple initial layout blocks of the layout; Performing layout optimization processing on the multiple initial layout blocks to generate multiple target layout blocks; as well as The multiple target layout blocks are converted into multiple open source image system exchange standard OASIS file blocks.

8. The method according to claim 7, characterized in that The multiple initial layout blocks are non-serialized initial layout blocks, and obtaining the multiple initial layout blocks of the layout includes: Obtaining the plurality of serialized initial layout blocks; and The serialized plurality of initial layout blocks are deserialized to generate the plurality of initial layout blocks.

9. The method according to claim 7 or 8, characterized in that: The formats of the plurality of OASIS file chunks comply with one or more OASIS constraints for avoiding conflicts in the OASIS file chunks.

10. The method according to claim 9, characterized in that The conflict includes at least one of: a reference number conflict, a table conflict, a start record conflict, an end record conflict, and a CBLOCK conflict.

11. A method for processing a layout, characterized in that: include: Acquiring, by at least one first processing device, a plurality of initial layout blocks of a layout from a second processing device; The at least one first processing device performs layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks; The at least one first processing device converts the plurality of target layout blocks into a plurality of Open Artifact System Interchange Standard OASIS file blocks; receiving, by the second processing device, the plurality of OASIS file chunks from the at least one first processing device; as well as The second processing device merges the multiple OASIS file blocks to generate an OASIS file corresponding to the layout.

12. A device for processing a layout, characterized in that: include: A receiving unit is configured to receive a plurality of open source image system exchange standard OASIS file blocks corresponding to a plurality of layout blocks of the layout; as well as A merging unit is configured to merge the multiple OASIS file blocks to generate an OASIS file corresponding to the layout.

13. The device according to claim 12, characterized in that The merging unit is further configured as: Generate a first header byte and a first tail byte of the OASIS file; removing corresponding header bytes and corresponding tail bytes of the plurality of OASIS file chunks to obtain corresponding plurality of intermediate byte sets of the plurality of OASIS file chunks; and The first header byte and the first trailer byte of the OASIS file are merged with the corresponding plurality of intermediate byte sets of the plurality of OASIS file chunks.

14. The device according to claim 13, characterized in that The header bytes include a header byte and a start record, the tail bytes include an end record, and the middle byte set includes a unit record, a unit name record, and an attribute record.

15. The device according to any one of claims 12 to 14, characterized in that The device also includes: A segmentation unit, configured to segment the layout into the plurality of layout blocks; A serialization unit configured to serialize the plurality of layout blocks; and The sending unit is configured to send the plurality of serialized layout blocks to at least one first processing device.

16. The device according to any one of claims 12 to 15, characterized in that The formats of the plurality of OASIS file chunks comply with one or more OASIS constraints for avoiding conflicts in the OASIS file chunks.

17. The method according to claim 16, characterized in that The conflict includes at least one of the following: reference number conflict, table conflict, start record conflict, end record conflict, CBLOCK conflict.

18. A device for processing a layout, characterized in that: include: An acquisition unit is configured to acquire a plurality of initial layout blocks of the layout; A generating unit, configured to perform layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks; as well as The conversion unit is configured to convert the plurality of target layout blocks into a plurality of open source image system exchange standard OASIS file blocks.

19. The method according to claim 18, characterized in that The multiple initial layout blocks are non-serialized initial layout blocks, and the acquisition unit is further configured to: Obtaining the plurality of serialized initial layout blocks; and The serialized plurality of initial layout blocks are deserialized to generate the plurality of initial layout blocks.

20. The method according to claim 18 or 19, characterized in that The formats of the plurality of OASIS file chunks comply with one or more OASIS constraints for avoiding conflicts in the OASIS file chunks.

21. The method according to claim 20, characterized in that The conflict includes at least one of: a reference number conflict, a table conflict, a start record conflict, an end record conflict, and a CBLOCK conflict.

22. A system for processing a layout, characterized in that: include: A first processing device, the first processing device comprising: An acquisition unit, configured to acquire a plurality of initial layout blocks of the layout from the second processing device; a generating unit configured to perform layout optimization processing on the plurality of initial layout blocks to generate a plurality of target layout blocks; and A conversion unit is configured to convert the plurality of target layout blocks into a plurality of Open Artifact System Interchange Standard OASIS file blocks; and A second processing device, the second processing device comprising: a receiving unit configured to receive the plurality of OASIS file blocks from the at least one first processing device; and A merging unit is configured to merge the multiple OASIS file blocks to generate an OASIS file corresponding to the layout.

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