Display device

Abstract

A display device is provided. The display device includes: a pixel array including a plurality of pixels connected to a plurality of source lines; a voltage generator configured to generate a reference voltage; and a source driver configured to output a first source signal corresponding to a first source line among the plurality of source lines, receive a first return signal corresponding to the first source signal through a second source line disposed adjacent to the first source line, and generate a first count value based on a first comparison of the first return signal and a reference voltage.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0111499 filed in the Korean Intellectual Property Office on August 24, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device and a driving method thereof. Background Art

[0003] With the development of information and communication technology, electronic devices including display devices for delivering image information to users, such as electronic systems, smart phones, and artificial reality systems, are rapidly developing. As the amount of data processed to provide image information increases, high-performance display devices are required.

[0004] A display device may generate and emit light using various elements. To improve the quality of an image displayed by such a display device, a display driver integrated circuit (DDI) for displaying an image on a display panel may perform various operations. Summary of the invention

[0005] The present disclosure relates to a display device and a driving method thereof. In particular, the present disclosure covers a display device for measuring the output of a source line.

[0006] Generally, in some aspects, the subject matter of the present disclosure relates to a display device, comprising: a pixel array, including a plurality of pixels connected to a plurality of source lines; a voltage generator, configured to generate a reference voltage; and a source driver, configured to output a first source signal corresponding to a first source line among the plurality of source lines, receive a first return signal corresponding to the first source signal through a second source line arranged adjacent to the first source line, and generate a first count value based on a first comparison result of the first return signal and the reference voltage.

[0007] Generally, in some aspects, the subject matter of the present disclosure relates to a display device, comprising: a pixel array, including a plurality of pixels connected to a plurality of source lines; a voltage generator, configured to generate a reference voltage; and a source driver, configured to output a first source signal corresponding to a first source line among the plurality of source lines, receive a first return signal corresponding to the first source signal through a first return line among a plurality of return lines connected to each of the plurality of source lines, and generate a first count value based on a first comparison result of the first return signal and the reference voltage.

[0008] Generally, in some aspects, the subject matter of the present disclosure relates to a display device, comprising: a pixel array, including a plurality of pixels connected to a plurality of source lines; a voltage generator, configured to generate a reference voltage; and a source driver, configured to output a first source signal corresponding to a first source line among the plurality of source lines, receive a first return signal corresponding to the first source signal through a first return line among a plurality of return lines connected to each of the plurality of source lines, and generate a first count value based on a first comparison result of the first return signal with the reference voltage, the source driver being connected to the plurality of source lines and the plurality of return lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example of a display system.

[0010] Figure 2 is a block diagram illustrating an example of a display device.

[0011] Figure 3 is a diagram illustrating an example of a display device.

[0012] Figure 4 It shows that Figure 3 A flow chart of an example of a method of operating a display device in a direct current (DC) level measurement mode.

[0013] Figure 5 is shown when the display device operates in the DC level measurement mode Figure 3 A timing diagram of an example of the operation of a display device.

[0014] Figure 6 is shown when the display device operates in the DC level measurement mode Figure 3 A timing diagram of an example of the operation of a display device.

[0015] Figure 7 It shows that Figure 3 A flow chart of an example of a method for operating a display device in a slew rate measurement mode.

[0016] Figure 8 is shown when the display device is operated in the slew rate measurement mode Figure 3 A timing diagram of an example of the operation of a display device.

[0017] Fig. 9 is a diagram illustrating an example of a display device.

[0018] Fig.10 is a diagram illustrating an example of a display device.

[0019] Fig.11 is a diagram illustrating an example of a display device.

[0020] Fig.12 is a diagram illustrating an example of a display device.

[0021] Fig.13 is a diagram showing an example of a display system. DETAILED DESCRIPTION

[0022] Hereinafter, the present disclosure will be described in detail below with reference to the accompanying drawings, in which examples of the present disclosure are shown. As will be appreciated by those skilled in the art, the described examples may be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0023] Therefore, the drawings and description are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals designate the same elements. In the flowcharts described with reference to the drawings in this specification, the order of operations may be changed, several operations may be combined, specific operations may be divided, and specific operations may not be performed.

[0024] In the description, unless an explicit expression such as "one" or "single" is used, an expression described in the singular in this specification may be interpreted as the singular or the plural. Although the terms "first", "second", etc. are used to explain various constituent elements, the constituent elements are not limited to such terms. These terms are only used to distinguish one constituent element from another constituent element.

[0025] Figure 1 is a block diagram illustrating an example of a display system.

[0026] For example, the display system 10 includes an artificial reality system (such as a virtual reality (VR) system, an augmented reality (AR) system, a mixed reality (MR) system, a hybrid reality system, or some combination thereof and / or a derivative AR system). The artificial reality system may be implemented on various platforms including a head-mounted display (HMD), a mobile device, a computing system, or other hardware platforms capable of providing artificial reality content to one or more viewers. In some embodiments, the display system 10 may be installed on an electronic device having an image display function. For example, the electronic device may include a smart phone, a tablet personal computer, a portable multimedia player (PMP), a camera, a wearable device, a television, a digital video disc (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, a drone, various medical devices, a navigation device, a global positioning system (GPS) receiver, a vehicle device, furniture, and various measuring devices.

[0027] Reference Figure 1 The display system 10 includes a host processor 100 and a display device 200. The display device 200 includes a display driving circuit 220 and a display panel 270.

[0028] The host processor 100 may generate an input image signal IS to be displayed on the display panel 270, and send the input image signal IS and a control command CTRL to the display driving circuit 220. The input image signal IS may include frame data corresponding to each frame. The control command CTRL may include setting information about the brightness, gamma, frame rate, and operation mode of the display driving circuit 220. For example, the operation mode may include a driving mode and a test mode, and the test mode includes a direct current (DC) level measurement mode and a conversion rate measurement mode. Here, the conversion rate may be a parameter indicating the operating speed of an operational amplifier (OP Amp), and may indicate the degree to which the output voltage can be changed per unit time.

[0029] The host processor 100 may be a graphics processor. However, the present disclosure is not limited thereto, and the host processor 100 may be implemented using various types of processors such as a central processing unit (CPU), a microprocessor, a multimedia processor, and an application processor. In some embodiments, the host processor 100 may be implemented as an integrated circuit (IC) or a system on chip (SoC).

[0030] The display device 200 may receive an input image signal IS from the host processor 100 and display the input image signal IS. The display device 200 may display a two-dimensional or three-dimensional image to a user. In some embodiments, the display device 200 may be a device in which the display driver circuit 220 and the display panel 270 are implemented as a single module. For example, the display driver circuit 220 may be mounted on a substrate of the display panel 270, or the display driver circuit 220 and the display panel 270 may be electrically connected via a connecting member such as a flexible printed circuit board (FPCB).

[0031] The display device 200 may include a display panel 270 and a display driving circuit 220 .

[0032] The display panel 270 may display an image to a user according to an input image signal received from the host processor 100. The display panel 270 may be a display device (such as a thin film transistor liquid crystal display (TFT-LCD), an organic light emitting diode (OLED) display, a field emission display, a plasma display panel (PDP)) that receives an electrically transmitted image signal and displays a two-dimensional image.

[0033] In some embodiments, there may be one or more display panels 270. For example, two display panels 270 may provide an image for each eye of the user.

[0034] The display driving circuit 220 may generate a plurality of analog signals for driving the display panel 270 based on the input image signal IS received from the host processor 100. For example, the plurality of analog signals may include gate signals and data signals for driving a plurality of pixels included in the display panel 270. The display driving circuit 220 may provide the gate signal and the data signal to the plurality of pixels. The display panel 270 may emit image light corresponding to the input image signal IS through the signal provided by the display driving circuit 220.

[0035] The display driving circuit 220 may include a driving controller 250 and a voltage generator 260 .

[0036] The driving controller 250 may control the voltage generator 260 to generate a plurality of grayscale voltages and a plurality of reference voltages. In some embodiments, the driving controller 250 may generate image data corresponding to the image signal IS. In some embodiments, the driving controller 250 may measure the DC level of the source signal based on a comparison value between the reference voltage provided to the display panel 270 in response to the image data and the source signal. Additionally, the driving controller 250 may measure the slew rate level of the source signal based on a comparison value between the reference voltage provided to the display panel 270 in response to the image data and the source signal.

[0037] The driving controller 250 may correct the image data based on the DC level of the source signal and the slew rate level of the source signal. In some embodiments, the driving controller 250 may send the DC level of the source signal and the slew rate level of the source signal to the host processor 100. The host processor 100 may correct the image signal IS based on the DC level of the source signal and the slew rate level of the source signal.

[0038] The voltage generator 260 may generate a plurality of grayscale voltages to be provided to the display panel 270 under the control of the driving controller 250. In addition, the voltage generator 260 may generate a reference voltage necessary for measuring a DC level of a source signal and a slew rate level of a source signal. In some embodiments, the reference voltage may be a sawtooth wave voltage or a DC voltage.

[0039] Figure 2 is a block diagram illustrating an example of a display device.

[0040] Reference Figure 2 , the display device 200 includes a pixel array 210 including a plurality of pixels PX and a display driving circuit 220 .

[0041] The pixel array 210 includes a plurality of gate lines GL (e.g., GL0 to GLh-1), a plurality of source lines SL (e.g., SL0 to SLk-1); the plurality of source lines SL are arranged in a direction intersecting with the plurality of gate lines GL0 to GLh-1; and a plurality of pixels PX are arranged in an area where the plurality of gate lines GL and the plurality of source lines SL intersect.

[0042] For example, if the display device 200 is a thin film transistor (TFT) liquid crystal display, each pixel PX may include a TFT having a gate electrode and a source electrode connected to a gate line and a data line, respectively, a liquid crystal capacitor connected to a drain electrode of the TFT, and a storage capacitor. When a specific gate line is selected among a plurality of gate lines GL, the TFT of the pixel PX connected to the selected gate line is turned on, and then a data voltage may be applied to each of a plurality of source lines SL through a source driver 240. The data voltage is applied to the liquid crystal capacitor and the storage capacitor through the TFT of the corresponding pixel PX, and the liquid crystal capacitor and the storage capacitor may be driven to display an image.

[0043] exist Figure 2 , the pixel PX is shown as being connected to one source line SL and one gate line GL, but the connection structure of the signal lines of the pixel PX of the display device is not limited thereto. For example, various signal lines may be additionally connected according to the circuit structure of the pixel PX.

[0044] The display driving circuit 220 may convert an externally received input image signal IS into a plurality of analog signals (such as a plurality of data voltages) for driving the pixel array 210 , and provide the converted plurality of analog signals to the pixel array 210 .

[0045] The display driving circuit 220 may include a gate driver 230, a source driver 240, a driving controller 250, and a voltage generator 260. The configuration including the driving controller 250 and the voltage generator 260 may be referred to as a main logic 201. The main logic 201 may also include a memory storing arbitrary data for controlling the configuration within the display device 200. However, the present disclosure is not limited thereto, and the memory may be located outside the display device 200.

[0046] The gate driver 230 is connected to a plurality of gate lines GL of the pixel array 210 and can sequentially drive the plurality of gate lines GL of the pixel array 210. The gate driver 230 can provide a plurality of gate signals G0, G1, G2, ..., Gh-1 to the pixel array 210. The plurality of gate signals G0, G1, G2, ..., Gh-1 can be pulse signals having an enable level and a disable level. The plurality of gate signals G0, G1, G2, ..., Gh-1 can be applied to the plurality of gate lines GL. In some embodiments, the gate driver 230 can receive a control voltage V_CTRL from a voltage generator 260.

[0047] The gate driver 230 may apply a plurality of gate signals G0, G1, G2, . . . , Gh-1 to the plurality of gate lines GL in different ways based on the control signal CONT1 of the driving controller 250. For example, when an enable level gate signal is applied to a pixel PX connected to one of the plurality of gate lines GL, a source signal applied to a source line connected to the corresponding pixel PX among the plurality of source lines SL may be transmitted to the pixel PX.

[0048] The source driver 240 is connected to the k source lines SL0 to SLk-1 and may output source signals for driving the pixel array 210 through the k source lines. The source driver 240 may implement one frame by outputting source signals for each of the k source lines SL0 to SLk-1.

[0049] The source driver 240 may receive data DATA in the form of a digital signal from the driving controller 250. In addition, the source driver 240 may receive a plurality of voltages VOL and a reference voltage V_REF from the voltage generator 260. The plurality of voltages VOL may include a plurality of grayscale voltages. The source driver 240 may convert the image data DATA received from the driving controller 250 into source signals S0, S1, S2, ..., Sk-1 in the form of analog signals based on a plurality of grayscale voltages (or, referred to as gamma voltages) within the plurality of voltages VOL.

[0050] The source driver 240 may receive the image data DATA in units of data corresponding to a plurality of pixels PX included in one horizontal line of the pixel array 210. The image data DATA may include grayscale information corresponding to each pixel PX for displaying the input image signal IS on the pixel array 210. The source driver 240 may output a plurality of source signals S0, S1, S2, ..., Sk-1 to the pixel array 210 in units of horizontal lines through a plurality of source lines SL0 to SLk-1. Specifically, the source driver 240 may transmit the plurality of source signals S0, S1, S2, ..., Sk-1 to the pixel array 210 according to the source driver control signal CONT2 provided from the driving controller 250. The source driver 240 may also be referred to as a data driver.

[0051] Since the source driver 240 includes a plurality of amplifiers and decoders as will be described later, even if a plurality of source signals S0, S1, S2, ..., Sk-1 are generated corresponding to the image data DATA, there may be differences between the generated plurality of source signals S0, S1, S2, ..., Sk-1 and the source signals actually output.

[0052] In some embodiments, the source driver 240 is connected to m return lines RL0 to RLm-1, and can receive return signals R0, R1, ..., Rm-1 output from the pixel array 210 in response to the source signal through the m return lines. For example, the return signals R0, R1, ..., Rm-1 may be signals actually output by the source driver 240 in response to the image data DATA. Figure 2 , the return line RL is not shown, but each of the multiple return lines RL0 to RLm-1 may be connected to each of the multiple source lines SL, and the present disclosure is not limited thereto. For example, the source driver 240 may output multiple source signals S0, S1, S2, ..., Sk-1 in the form of analog signals through any source line, and receive multiple return signals R0, R1, ..., Rm-1 through source lines adjacent to the corresponding source lines. Optionally, the source driver 240 may output source signals in the form of analog signals through any source line, and receive return signals through the same source line. In some embodiments, the source driver 240 may output source signals through some of the multiple source lines, and some source lines may not output source signals.

[0053] The source driver 240 may obtain a count value COUNT_NUM based on the plurality of source signals S0, S1, S2, . . . , Sk-1 and return signals R0, R1, . . . , Rm-1 corresponding to each of the plurality of source signals S0, S1, S2, . . . , Sk-1.

[0054] Here, the count value COUNT_NUM may represent the difference between the source signal and the return signal. Specifically, the source driver 240 may compare a plurality of reference voltages with the return signal R0, R1, ..., Rm-1 to obtain a count value COUNT_NUM representing the DC level of the return signal R0, R1, ..., Rm-1 and a count value COUNT_NUM representing the conversion rate of the return signal R0, R1, ..., Rm-1.

[0055] Thereafter, the source driver 240 may transmit the obtained count value COUNT_NUM to the driving controller 250 .

[0056] The driving controller 250 may control the overall operation of the display driving circuit 220. For example, the driving controller 250 may control the overall operation of the display driving circuit 220 based on the image signal IS (eg, received from an external source) and the image signal IS received from a host device (eg, Figure 1 The display driving circuit 220 is controlled by a driving control signal CTRL of the host processor 100 , so that the image signal IS can be displayed on the pixel array 210 .

[0057] For example, the driving control signal CTRL may include a horizontal synchronization signal, a vertical synchronization signal, a main clock signal, and a data enable signal. Specifically, the driving controller 250 may generate the image data DATA by dividing the input image signal IS into a frame unit based on the vertical synchronization signal and dividing the input image signal IS into a plurality of gate line GL units based on the horizontal synchronization signal.

[0058] In some embodiments, the driving controller 250 may generate the output image data DATA by converting a format based on the received input image signal IS to match an interface specification of the source driver 240 , and output the image data DATA to the source driver 240 .

[0059] The drive controller 250 may generate a control command independently from the drive controller 250 and communicate with a host device (eg, Figure 1 The source driver 240, the gate driver 230, and the voltage generator 260 are controlled by a control command generated separately from a driving control signal CTRL received by a host processor 100 in the control module 100, or a control command generated in addition to the driving control signal CTRL.

[0060] In some embodiments, the driving controller 250 may control the operation timing of the display driving circuit 220. The driving controller 250 may control the operation timing of the source driver 240, the gate driver 230, and the voltage generator 260 so that the input image signal IS is displayed on the pixel array 210. Specifically, the driving controller 250 may generate various control signals CONT1, CONT2, and CONT3 to control the timing of the gate driver 230, the source driver 240, and the voltage generator 260. The driving controller 250 may output a first control signal CONT1 to the gate driver 230, a second control signal CONT2 to the source driver 240, and a third control signal CONT3 to the voltage generator 260. The first control signal CONT1 may include a control signal for controlling the gate level of a plurality of pixels PX. In addition, the second control signal CONT2 may include a switch control signal, an amplifier control signal, and other components within the source driver 240. The third control signal CONT3 may be a signal for causing the voltage generator 260 to generate a reference voltage.

[0061] The driving controller 250 may receive a count value COUNT_NUM from the source driver 240. The driving controller 250 may modify the image data DATA based on the received count value COUNT_NUM. For example, when the count value COUNT_NUM is greater than a predetermined value, the driving controller 250 may correct the image data DATA based on the count value COUNT_NUM and provide the corrected image data as the image data DATA to the source driver 240. For example, the driving controller 250 may correct the image data DATA corresponding to the input image signal IS using a lookup table corresponding to the count value COUNT_NUM. For example, the driving controller 250 may receive a first count value from the source driver 240 and select a lookup table corresponding to the first count value. The driving controller 250 may apply a data value corresponding to the first count value to the image data DATA and output the image data to which the data value is applied as new image data DATA to the source driver 240. For example, applying the count value may mean adding or subtracting a specific value from the image data DATA.

[0062] However, the present disclosure is not limited thereto, and the source driver 240 may generate a source signal corrected based on the image data DATA received from the driving controller 250 based on the count value COUNT_NUM. Specifically, the source driver 240 may generate a source signal based on the image data DATA received from the driving controller 250, generate a corrected source signal by using a lookup table corresponding to the count value COUNT_NUM, and transmit the corrected source signal to the pixel array 210 via the plurality of source lines SL0 to SLk-1.

[0063] The voltage generator 260 may generate various voltages necessary for driving the display device 200. The voltage generator 260 may receive a power supply voltage from the outside and generate a plurality of voltages VOL based on the power supply voltage. Additionally, the voltage generator 260 may generate a plurality of reference voltages V_REF. The reference voltage V_REF may be a voltage used by the driving controller 250 to measure a DC level and a conversion rate of a source signal.

[0064] In some embodiments, the configuration of the display driving circuit 220 of the present disclosure may include additional configurations. For example, the configuration of the display driving circuit 220 may be implemented to include a memory that stores the input image signal IS frame by frame, or a memory that stores a lookup table storing correction data corresponding to the count value COUNT_NUM to correct the image data DATA.

[0065] The memory may be referred to as, for example, a graphics random access memory (RAM) or a frame buffer. The memory may include a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM) or a non-volatile memory such as a read-only memory (ROM) or flash memory, a resistive random access memory (ReRAM), and a magnetic random access memory (MRAM). In some embodiments, the display driver circuit 220 may also include other common components (e.g., a clock generator, etc.).

[0066] exist Figure 2 , the gate driver 230, the source driver 240, the drive controller 250 and the voltage generator 260 are shown as different functional blocks. In some embodiments, each component can be implemented using a different semiconductor chip. In some embodiments, at least two components of the gate driver 230, the source driver 240, the drive controller 250 and the voltage generator 260 can be implemented as one semiconductor chip. For example, the gate driver 230, the source driver 240 and the voltage generator 260 can be integrated into one semiconductor chip. Additionally, some components can be integrated on the pixel array 210. For example, the gate driver 230 can be integrated on the pixel array 210.

[0067] Figure 3 is a diagram illustrating an example of a display device.

[0068] like Figure 3As shown in FIG. 1 , the display device 1000 includes a pixel array 1010 and a display driving circuit 1020. The display driving circuit 1020 includes a gate driver 1030, a source driver 1040, a driving controller 1050, and a voltage generator 1060. The configuration including the driving controller 1050 and the voltage generator 1060 may be referred to as a main logic 1001. The main logic 1001 may also include a memory storing arbitrary data for controlling the configuration within the display device 1000. However, the present disclosure is not limited thereto, and the memory may be located outside the display device 1000.

[0069] The pixel array 1010 may include a plurality of pixels PX. The pixel array 1010 may include a plurality of gate lines GL0, ..., GLh-1 and a plurality of source lines SL0, ..., SLk-1 connected to the plurality of pixels PX.

[0070] The gate driver 1030 may transmit gate signals G0 , . . . , Gh- 1 to the plurality of gate lines GL0 , . . . , GLh- 1 based on the first control signal CONT1 received from the driving controller 1050 .

[0071] The driving controller 1050 may drive the display device 1000 in a plurality of modes.

[0072] For example, when the display device 1000 operates in the driving mode, the driving controller 1050 may generate a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 corresponding to the driving mode. When operating in the driving mode, the display device 1000 may display an image corresponding to the image signal IS. In this case, the second control signal CONT2 may be a signal for controlling a plurality of switches SW11 to SW16 within the source driver 1040.

[0073] For another example, when the display device 1000 operates in the test mode, the driving controller 1050 may generate a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 corresponding to the test mode. When operating in the test mode, the display device 1000 may be in a mode for measuring a DC level and a slew rate of a source signal Si output by the source driver 1040.

[0074] In some embodiments, the driving controller 1050 may measure the DC level and conversion rate of the source signal Si output by the channel amplifier 1021 connected to the source line SLi through the second channel amplifier 1031 connected to the adjacent source line SLi+1 of the source line SLi. Specifically, the plurality of source lines SL within the pixel array 1010 may include a first test mode and a second test mode, in which the source line set at 2n-1 (where n is a natural number greater than 1) is operated in the driving mode and the source line set at 2n is operated in the comparator mode, and in which the source line set at 2n is operated in the driving mode and the source line set at 2n-1 (where n is a natural number greater than 1) is operated in the comparator mode.

[0075] Specifically, Figure 3 1 is a diagram illustrating an example in which the display device 1000 operates in the first test mode. For example, the first source line 1110 may operate in the operation mode, and the second source line 1210 may operate in the test mode.

[0076] When the display device 1000 operates in the first test mode, the driving controller 1050 may generate a first control signal CONT1 corresponding to the first test mode, a second control signal CONT2 corresponding to the first test mode, and a third control signal CONT3 corresponding to the first test mode.

[0077] When the display device 1000 operates in the second test mode, the driving controller 1050 may generate a first control signal CONT1 corresponding to the second test mode, a second control signal CONT2 corresponding to the second test mode, and a third control signal CONT3 corresponding to the second test mode.

[0078] The voltage generator 1060 may generate various voltages required to drive the display device 1000 under the control of the driving controller 1050. For example, the voltage generator 1060 may include a plurality of voltages VOL including a plurality of grayscale voltages and a reference voltage V_REF.

[0079] The source driver 1040 may include logic units 1025 and 1035 , decoders 1023 and 1033 , channel amplifiers 1021 and 1031 , and a selector 1011 .

[0080] An output terminal of the channel amplifier 1021 may be connected to the selector 1011, a first input terminal of the channel amplifier 1021 may be connected to the selector 1011, and a second input terminal may be connected to the decoder 1023. The selector 1011 may be connected to the output terminal of the channel amplifier 1021, the first input terminal of the channel amplifier 1021, the output terminal of the channel amplifier 1031, the first input terminal of the channel amplifier 1031, the source line SLi, the source line SLi+1, the logic unit 1025, and the logic unit 1035.

[0081] The source driver 1040 may convert the image data DATA received from the driving controller 1050 into a source signal Si, and output the source signal Si through a first source line (SLi, i is an integer greater than 0 and less than or equal to k-2). In addition, the source driver 1040 may convert the image data DATA received from the driving controller 1050 into a source signal Si+1, and output the source signal Si+1 through a second source line (SLi+1, i is an integer greater than 0 and less than or equal to k-2).

[0082] In some embodiments, the source driver 1040 may measure a DC level difference between a source signal Si output by the channel amplifier 1021 and a decoder signal S_DEC1 output to the channel amplifier 1021 by the decoder 1023. Additionally, the source driver 1040 may measure a slew rate of the source signal Si. The source driver 1040 may generate a count value COUNT_NUM based on the measured DC level and slew rate.

[0083] The logic units 1025 and 1035 may receive the image data DATA from the driving controller 1050 and transmit the count value COUNT_NUM to the driving controller 1050. The present disclosure is not limited thereto, and the logic units 1025 and 1035 may transmit the count value COUNT_NUM to the host processor ( Figure 1 100 in ) or a separate test device.

[0084] The first logic unit 1025 may include a latch 1027 and a counter 1029. The second logic unit 1035 may include a latch 1037 and a counter 1039.

[0085] The latches 1027 and 1037 may receive image data DATA from the driving controller 1050. The latches 1027 and 1037 may sample and store the image data under the control of the driving controller 1050. The latches 1027 and 1037 may transmit the sampled image data to the decoders 1023 and 1033. In some embodiments, the latches 1027 and 1037 may include a sampling circuit that samples the data and a holding latch that stores the data sampled by the sampling circuit.

[0086] The counter 1029 generates a first count value COUNT_NUM11 based on a counter input signal CNT_S1 received from the selector 1011. The counter 1039 generates a second count value COUNT_NUM12 based on a counter input signal CNT_S2 received from the selector 1011. Here, the counter input signal CNT_S1 may be a signal indicating the source signal Si, or a signal indicating a comparison result of comparing the source signal Si+1 with the reference voltage V_REF, and the counter input signal CNT_S2 may be a signal indicating the source signal Si+1, or a signal indicating a comparison result of comparing the source signal Si with the reference voltage V_REF.

[0087] Each of the counters 1029 and 1039 may transmit the generated first count value COUNT_NUM11 and the second count value COUNT_NUM12 to the driving controller 1050. Alternatively, the counter 1029 may transmit the generated first count value COUNT_NUM11 to the latch 1027, and the counter 1039 may transmit the generated second count value COUNT_NUM12 to the latch 1037.

[0088] exist Figure 3 , the latch 1027 and the counter 1029 are shown as being included in the logic unit 1025, and the latch 1037 and the counter 1039 are shown as being included in the logic unit 1035. However, the present disclosure is not limited thereto, and the latch and the counter may be configured separately from the source driver 1040.

[0089] The decoders 1023 and 1033 may receive sampled image data from the corresponding latches 1027 and 1037. The decoder 1023 may receive a plurality of voltages VOL from the voltage generator 1060. The plurality of voltages VOL may include gamma voltages corresponding to various levels of brightness of the display device 1000. The number of gamma voltages may be determined based on the number of colors to be displayed by the pixel array 1010 or the number of bits of digital data provided from outside the display device 1000. In some embodiments, the decoder 1023 may select one of the plurality of voltages VOL in response to the sampled image data. The decoder 1023 may output the selected gamma voltage to the channel amplifier 1021. The decoder 1033 may receive a reference voltage V_REF from the voltage generator 1060. For example, the reference voltage V_REF may be a DC voltage or a sawtooth voltage. In some embodiments, the decoders 1023 and 1033 may be implemented as digital-to-analog converters.

[0090] The channel amplifier 1021 may receive the gamma voltage selected from the decoder 1023, amplify the gamma voltage selected by the decoder 1023 in response to the second control signal CONT2 received from the driving controller 1050, and send the selected gamma voltage as the source signal Si to the selector 1011. The channel amplifier 1021 may be implemented as an operational amplifier. For example, the channel amplifier 1021 may output the source signal Si through the first source line SLi. Since the channel amplifier 1021 is connected to the corresponding source line SLi, the channel amplifier 1021 and the decoder 1023 may control the driving of the source line SLi.

[0091] In some embodiments, the channel amplifier 1021 may include a first input terminal, a second input terminal, and an output terminal, and the gamma voltage is input from the decoder 1023 through the second input terminal, and the output voltage is output through the output terminal. The channel amplifier 1031 may include a first input terminal, a second input terminal, and an output terminal, and the reference voltage is input from the voltage generator 1060 through the second input terminal. The first input terminal of each of the channel amplifiers 1021 and 1031 may be connected to the output terminal of each of the channel amplifiers 1021 and 1031. In some embodiments, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

[0092] For example, the output voltages of the channel amplifiers 1021 and 1031 may be input as input voltages to inverting input terminals of the channel amplifiers 1021 and 1031. The channel amplifiers 1021 and 1031 may be implemented as unit buffers.

[0093] The selector 1011 may be connected to the first channel amplifier 1021 and the second channel amplifier 1031, and to two adjacent source lines SLi, SLi+1. The selector 1011 may include first to sixth switches SW11, SW12, SW13, SW14, SW15, and SW16. The selector 1011 may control the connection relationship between the plurality of switches SW11 to SW16 within the selector 1011 based on the second control signal CONT2 received from the drive controller 1050. Specifically, the first switch SW11 may be connected between the first source line SLi and the output terminal of the first channel amplifier 1021, and the second switch SW12 may be connected between the second source line SLi+1 and the output terminal of the second channel amplifier 1031. The third switch SW13 may be connected between one end of the first switch SW11 (e.g., the output terminal of the first channel amplifier 1021) and the first input terminal of the second channel amplifier 1031. The fourth switch SW14 may be connected between one end of the second switch SW12 (e.g., the output terminal of the second channel amplifier 1031) and the first input terminal of the first channel amplifier 1021. The fifth switch SW15 may connect one end of the first switch SW11 (e.g., the output terminal of the first channel amplifier 1021) and the logic unit 1025, or connect one end of the first switch SW11 and the first input terminal of the first channel amplifier 1021, according to the second control signal CONT2. The sixth switch SW16 may connect one end of the second switch SW12 (e.g., the output terminal of the second channel amplifier 1031) and the logic unit 1035, or connect one end of the second switch SW12 and the first input terminal of the second channel amplifier 1031, according to the second control signal CONT2. Figure 3 , the fifth switch SW15 and the sixth switch SW16 are each illustrated as a single-pole double-throw (SPDT) switch, but the present disclosure is not limited thereto. Each of the fifth switch SW15 and the sixth switch SW16 may be implemented as two switches.

[0094] As described above, in some embodiments, when the display device 1000 operates in the driving mode, the driving controller 1050 may generate a second control signal CONT2 corresponding to the driving mode and transmit the second control signal CONT2 to the selector 1011. For example, the second control signal CONT2 may be a signal that controls the plurality of switches SW11 to SW16 so that the channel amplifier 1021 is connected to the corresponding source line SLi and the channel amplifier 1031 is connected to the corresponding source line SLi+1.

[0095] Based on the second control signal CONT2, the first switch SW11 and the second switch SW12 may be turned on, the third switch SW13 and the fourth switch SW14 may be turned off, the fifth switch SW15 may connect one end of the first switch SW11 to the first input terminal of the first channel amplifier 1021, and the sixth switch SW16 may connect one end of the second switch SW12 to the first input terminal of the second channel amplifier 1031. Therefore, the selector 1011 may receive the first source signal Si from the first channel amplifier 1021 and transmit the first source signal Si to the source line SLi, and may receive the second source signal Si+1 from the second channel amplifier 1031 and transmit the second source signal Si+1 to the source line SLi+1. The third control signal CONT3 may be a signal that controls the voltage generator 1060 to generate a voltage provided to the display driving circuit 1020. For example, the third control signal CONT3 may be a signal that controls the plurality of grayscale voltages to be transmitted as the plurality of voltages VOL to the decoders 1023 and 1033. Alternatively, the third control signal CONT3 may be a signal that controls the voltage generator 1060 to generate a plurality of reference voltages and transmits the plurality of reference voltages to the channel amplifier 1021 or the channel amplifier 1031 through the decoders 1023 and 1033 .

[0096] As described above, in some embodiments, when the display device 1000 operates in the test mode, the driving controller 1050 may generate a second control signal CONT2 corresponding to the test mode and transmit the second control signal CONT2 to the selector 1011. The second control signal CONT2 may be a signal that controls the plurality of switches SW11 to SW16 so that the output of the channel amplifier 1021 or the channel amplifier 1031 is connected to the first input terminal of the adjacent channel amplifier.

[0097] For example, in the case of the first test mode, based on the second control signal CONT2 corresponding to the first test mode, the first switch SW11, the second switch SW12, and the third switch SW13 may be turned on, the fourth switch SW14 may be turned off, the fifth switch SW15 may connect one end of the first switch SW11 with the first input terminal of the first channel amplifier 1021, and the sixth switch SW16 may connect the output of the second channel amplifier 1031 with the logic unit 1035. Therefore, the selector 1011 may receive the first source signal Si from the first channel amplifier 1021 and transmit the first source signal Si to the source line SLi, and transmit the first source signal Si to the first input terminal of the second channel amplifier 1031 through the third switch SW13. The second channel amplifier 1031 may compare the first source signal Si input to the first input terminal with the reference voltage received from the second decoder 1033, and transmit the comparison result to the logic unit 1035 through the sixth switch SW16. The third control signal CONT3 may be a signal controlling the voltage generator 1060 to transmit a plurality of grayscale voltages as a plurality of voltages VOL to the decoder 1023 and to transmit the reference voltage V_REF to the decoder 1033. In this case, the reference voltage V_REF may be input to the second channel amplifier 1031 through the decoder 1033.

[0098] For another example, in the case of the second test mode, based on the second control signal CONT2 corresponding to the second test mode, the first switch SW11, the second switch SW12, and the fourth switch SW14 may be turned on, the third switch SW13 may be turned off, the fifth switch SW15 may connect one end of the first switch SW11 with the logic unit 1025, and the sixth switch SW16 may connect one end of the second switch SW12 with the first input terminal of the second channel amplifier 1031. Therefore, the selector 1011 may receive the second source signal Si+1 from the second channel amplifier 1031, and transmit the second source signal Si+1 to the source line SLi+1, and transmit the second source signal Si+1 to the first input terminal of the first channel amplifier 1021 through the fourth switch SW14. The first channel amplifier 1021 may compare the second source signal Si+1 input to the first input terminal with the reference voltage received from the first decoder 1023, and transmit the comparison result to the logic unit 1025 through the fifth switch SW15. The third control signal CONT3 may be a signal controlling the voltage generator 1060 to transmit a plurality of grayscale voltages as a plurality of voltages VOL to the decoder 1023 and to transmit the reference voltage V_REF to the decoder 1033. In this case, the reference voltage V_REF may be input to the first channel amplifier 1021 through the decoder 1023.

[0099] Generally, the charging time of one row of pixels of a panel continues to decrease to drive high frequency and high resolution displays.

[0100] Additionally, a greater number of source lines may be required in a display driving circuit to support high resolution. The increase in the number of source lines may increase the load when transmitting the gamma voltage, thereby slowing down the stabilization time of the gamma voltage. The slowing down of the stabilization time may deteriorate the stabilization time of the source line and cause problems when driving the display device at high speed.

[0101] Figure 4 It shows that Figure 3 A flow chart of an example of a method for operating a display device in a DC level measurement mode. Figure 5 is shown when the display device operates in the DC level measurement mode Figure 3 A timing diagram of an example of the operation of a display device. Specifically, Figure 5 and Figure 6 The reference voltage V_REF output from the voltage generator 1060 and the source signal Si and the outputs of the logic units 1025 and 1035 are shown when the display device 1000 operates in the DC level measurement mode.

[0102] The display device 1000 compares a first reference voltage with a target voltage to generate a first comparison result (S401). In some embodiments, the display device 1000 may generate a plurality of first reference voltages and compare each of the plurality of first reference voltages with the target voltage to generate a plurality of first comparison results. Figure 5 In the embodiment, a case where the display apparatus 1000 generates two first comparison results is described as an example, but the present disclosure is not limited thereto, and the display apparatus 1000 may generate an appropriate number of first comparison results.

[0103] Hereinafter, a signal as a target of comparison is referred to as a target voltage, and a signal as a reference for comparison is referred to as a reference voltage.

[0104] The voltage generator 1060 may generate a first sawtooth waveform 5011 having an arbitrary DC level. The first sawtooth waveform 5011 may be input to a second input terminal of the first channel amplifier 1021 through the first decoder 1023. Thereafter, the output from the first channel amplifier 1021 may be input to a first input terminal of the second channel amplifier 1031. In some embodiments, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

[0105] The voltage generator 1060 may generate a first reference voltage 5001 having a DC level of a first value as a reference voltage V_REF, and the first reference voltage 5001 may be output as a second decoder signal S_DEC2 through the second decoder 1033 .

[0106] exist Figure 5 , the first value is shown as VDD / 2, but the present disclosure is not limited thereto, and the reference voltage V_REF may be a DC voltage having any level. In some embodiments, VDD represents a power supply voltage, and VSS represents a ground voltage.

[0107] The second channel amplifier 1031 may compare the first reference voltage 5001 with the first sawtooth waveform 5011, and output the comparison result as the counter signal CNT_S2 to the logic unit 1035. When the first sawtooth waveform 5011 has the first DC level, the first sawtooth waveform 5011 has a higher value than the first reference voltage 5001 during t102 to t105, and thus the counter signal CNT_S2_REF1 may have a high level.

[0108] The counter 1039 can generate a count value COUNT_NUM12 by counting the time that the counter signal CNT_S2_REF1 maintains a specific level. Thereafter, the logic unit 1035 can send the generated count value COUNT_NUM12 as a reference count value to the driving controller 1050. The driving controller 1050 can obtain the count value according to the DC level of the first sawtooth waveform 5011 relative to the first reference voltage 5001.

[0109] In some embodiments, the voltage generator 1060 may generate a first reference voltage 5001 having a first value as the reference voltage V_REF, and the first reference voltage 5001 may be output as a second decoder signal S_DEC2 through the second decoder 1033. The second channel amplifier 1031 may compare the first reference voltage 5001 with the first sawtooth waveform 5011, and output the comparison result to the logic unit 1035 as the counter signal CNT_S2.

[0110] The counter 1039 in the logic unit 1035 may generate a count value COUNT_NUM12 by counting the time that the counter signal CNT_S2 (ie, the counter signal CNT_S2_REF1) maintains a specific level. Thereafter, the logic unit 1035 may send the generated count value COUNT_NUM12 to the driving controller 1050 as a reference count value.

[0111] Therefore, the driving controller 1050 can obtain a count value representing a DC level of the first sawtooth waveform 5011 relative to a reference voltage V_REF. The driving controller 1050 can compare the target voltage as a plurality of sawtooth waveforms with the first reference voltage as a DC voltage to measure a change in the count value as the DC level of the target voltage changes, and the result of the comparison can be referred to as a first comparison result.

[0112] In some implementations, the driving controller 1050 may store the plurality of first comparison results in the form of a lookup table.

[0113] The display device 1000 compares the source signal (or data signal) with the second reference voltage to generate a second comparison result ( S403 ).

[0114] The voltage generator 1060 may generate a plurality of grayscale voltages as a plurality of voltages VOL and input the plurality of grayscale voltages to the first decoder 1023. The first decoder 1023 may select a grayscale voltage corresponding to the image data DATA from among the plurality of voltages VOL and output the grayscale voltage as a decoder signal S_DEC1 to the first channel amplifier 1021. The first channel amplifier 1021 may output a source signal Si as a target voltage. The source signal Si outputted through the first channel amplifier 1021 may be inputted to the first input terminal of the second channel amplifier 1031 through the third switch SW13.

[0115] The voltage generator 1060 may generate a first sawtooth waveform 5015 having an arbitrary DC level as a reference voltage. In this case, the first sawtooth waveform 5015 may be a target voltage in step S401 of generating a first comparison result. The first sawtooth waveform 5015 may be input to a second input terminal of the second channel amplifier 1031 through the second decoder 1033. Thereafter, an output from the first channel amplifier 1021 may be input to a first input terminal of the second channel amplifier 1031. The second channel amplifier 1031 may compare the source signal Si with the first sawtooth waveform 5015, and output the comparison result to the logic unit 1035 as a counter signal CNT_S2. The counter signal CNT_S2 (i.e., the counter signal CNT_S2_REF1) may have a high level during t104 to t105.

[0116] The counter 1039 can generate a count value COUNT_NUM12 by counting the time that the counter signal CNT_S2_REF1 maintains a specific level. The driving controller 1050 can obtain a count value according to the DC level of the source signal 5003 relative to the second reference voltage, which is the first sawtooth waveform 5015 .

[0117] The driving controller 1050 may generate a value obtained by subtracting the count value of the second comparison result from the count value of the first comparison result as a final count value. Figure 5 , the count value of the DC level of the first sawtooth waveform 5011 relative to the first reference voltage 5001 is a first value (corresponding to t102 to t105), and the count value of the DC level of the source signal 5003 relative to the first reference voltage may be a second value (corresponding to t104 to t105), and the first reference voltage is the first sawtooth waveform 5015. The driving controller 1050 may determine a value obtained by subtracting the second value from the first value (i.e., a value calculated by counting the time (t102 to t104) during which the final counter signal COUNT_NUM_REF1 maintains a specific level) as the final count value.

[0118] In some embodiments, the voltage generator 1060 may generate a second sawtooth waveform 5013 having a different DC level from the first sawtooth waveform 5011. The second sawtooth waveform 5013 may be input to the second input terminal of the first channel amplifier 1021 through the first decoder 1023. Thereafter, the output from the first channel amplifier 1021 may be input to the input terminal of the second channel amplifier 1031.

[0119] In some embodiments, the voltage generator 1060 may generate a first reference voltage 5001 having a first value as the reference voltage V_REF, and the first reference voltage 5001 may be output as the second decoder signal S_DEC2 through the second decoder 1033. The second channel amplifier 1031 may compare the first reference voltage 5001 with the second sawtooth waveform 5013, and output the comparison result as the counter signal CNT_S2 to the logic unit 1035. When the second sawtooth waveform 5013 has the second DC level, the second sawtooth waveform 5013 has a higher value than the first reference voltage 5001 during t101 to t105, and thus the counter signal CNT_S2_REF2 may have a high level.

[0120] The driving controller 1050 may obtain a count value according to a DC level of the second sawtooth waveform 5013 relative to the first reference voltage 5001 .

[0121] Similarly, the display device 1000 may generate a second sawtooth waveform 5017 having an arbitrary DC level as a reference voltage. In this case, the second sawtooth waveform 5017 may be a target voltage in step S401 of generating the first comparison result. The second sawtooth waveform 5017 may be input to the second input terminal of the second channel amplifier 1031 through the second decoder 1033. Thereafter, the output from the first channel amplifier 1021 may be input to the first input terminal of the second channel amplifier 1031. The second channel amplifier 1031 may compare the source signal Si with the second sawtooth waveform 5017, and output the comparison result as the counter signal CNT_S2 to the logic unit 1035. The counter signal CNT_S2 (i.e., the counter signal CNT_S2_REF2) may have a high level during t103 to t105.

[0122] The counter 1039 may generate a count value COUNT_NUM12 by counting the time that the counter signal CNT_S2_REF2 maintains a specific level. The driving controller 1050 may obtain a count value based on a DC level of the source signal 5003 relative to a reference voltage (ie, the second sawtooth waveform 5017 ).

[0123] The display apparatus 1000 generates a final count value based on the first comparison result and the second comparison result ( S405 ).

[0124] The count value of the second sawtooth waveform 5013 with respect to the DC level of the first reference voltage 5001 may be a third value (corresponding to t101 to t105), and the count value of the source signal 5003 with respect to the DC level of the second sawtooth waveform 5017 may be a fourth value (t103 to t105). The driving controller 1050 may determine a value obtained by subtracting the fourth value from the third value (i.e., a value calculated by counting the time (t101 to t103) during which the final counter signal COUNT_NUM_REF2 maintains a specific level) as the final count value.

[0125] The driving controller 1050 may obtain a count value CNT_S2_REF1 indicating a value of the first sawtooth waveform 5011 relative to the first reference voltage 5001 and a count value CNT_S2_REF1 indicating a value of the source signal 5003 relative to the first sawtooth waveform 5011 .

[0126] Additionally, the driving controller 1050 may obtain a count value CNT_S2_REF2 indicating the value of the first sawtooth waveform 5011 relative to the second reference voltage (e.g., the first sawtooth waveform 5015), and a count value CNT_S2_REF2 indicating the value of the source signal 5003 relative to the second sawtooth waveform 5013. The driving controller 1050 may obtain a count value indicating the source signal regardless of the type of the reference voltage. That is, the driving controller 1050 may obtain a count value indicating the source signal regardless of the offset level of the reference voltage, and thus may accurately measure the source voltage.

[0127] The display device 1000 measures a DC level of a source signal (or a data signal) based on the final count value ( S407 ).

[0128] In some embodiments, the driving controller 1050 may have a DC level difference corresponding to a count value pre-set based on a plurality of first comparison results. The driving controller 1050 may measure the DC level of the source signal 5003 based on the final count value. In some embodiments, the higher the DC level of the source signal 5003, the smaller the final count value may be.

[0129] The driving controller 1050 may change the image data DATA based on the measured DC level of the source signal. For example, when the source signal 5003 has a high DC level, the driving controller 1050 may generate modified image data by adding an arbitrary value to the image data DATA and transmit the modified image data to the source driver 1040.

[0130] As mentioned above, Figure 5 Reference voltages (e.g., first reference voltage 5001, first and second sawtooth waveforms 5015 and 5017, source signal 5003, and count value CNT_S2) are shown when display device 1000 operates in a first test mode (e.g., when source line SLi operates in a driving mode and source line SLi+1 operates in a test mode).

[0131] However, the present disclosure is not limited thereto, and the display device 1000 may operate in the second test mode.

[0132] In short, Figure 5, the voltage generator 1060 generates a sawtooth waveform and a DC voltage, sets the sawtooth waveform as a target voltage and sets the DC voltage as a reference voltage, and compares the target voltage with the reference voltage to generate a first comparison result. Thereafter, the following case is shown: the voltage generator 1060 generates a source signal and a sawtooth waveform, sets the source signal to a target voltage and sets the sawtooth waveform to a reference voltage to compare the target voltage with the reference voltage to generate a second comparison result, and measures the DC level of the source signal based on the first comparison result and the second comparison result. However, the present disclosure is not limited thereto, and the voltage generator 1060 may measure the DC level of the source signal by using a waveform other than the sawtooth waveform as a target voltage or a reference voltage.

[0133] The operation of the display device 1000 from t101 to t105 may be similar to the operation of the display device 1000 from t106 to t110 .

[0134] Figure 6 is shown when the display device operates in the DC level measurement mode Figure 3 A timing diagram of an example of the operation of a display device.

[0135] In some embodiments, the voltage generator 1060 may measure the DC level of the source signal using a voltage having a ramp waveform form. Depending on the type of voltage used by the display device 1000 to measure the DC level of the source signal, the absolute count value according to the comparison result may vary. However, since the display device 1000 measures the DC level of the source signal based on the difference between the referenced first comparison result and the measured second comparison result, the DC level may not be affected by the type of voltage used.

[0136] Specifically, Figure 6 1 shows a timing diagram when the voltage generator 1060 measures the DC level of the source signal using a voltage having a ramp waveform. Unless otherwise specified, when operating in the DC level measurement mode, the above reference Figure 4 and Figure 5 The description of the operation of the display device 1000 described above can also be applied to Figure 6 .

[0137] The voltage generator 1060 may generate a ramp waveform 6011 having an arbitrary DC level. The ramp waveform 6011 may be input to the second input terminal of the first channel amplifier 1021 through the first decoder 1023. Thereafter, the output from the first channel amplifier 1021 may be input to the first input terminal of the second channel amplifier 1031. In some embodiments, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

[0138] The voltage generator 1060 may generate a DC voltage 6001 having a first value as a reference voltage V_REF, and the DC voltage 6001 may be output as a second decoder signal S_DEC2 through the second decoder 1033. Figure 6 , the first value is shown as AVDD / 2, but the present disclosure is not limited thereto, and the reference voltage V_REF may be a DC voltage having any level. In some implementations, AVDD represents a power supply voltage, and AVSS represents a ground voltage.

[0139] The second channel amplifier 1031 may compare the DC voltage 6001 with the ramp waveform 6011 and output the comparison result as the counter signal CNT_S2 to the logic unit 1035. When the ramp waveform 6011 has the first DC level, the ramp waveform 6011 has a higher value than the first reference voltage (e.g., DC waveform 6001) during t201 to t203, and thus the counter signal CNT_S2_REF1 may have a high level.

[0140] The counter 1039 may generate a count value COUNT_NUM12 by counting the time that the counter signal CNT_S2_REF1 maintains a specific level. Thereafter, the logic unit 1035 may send the generated count value COUNT_NUM12 as a reference count value to the driving controller 1050. The driving controller 1050 may obtain the count value according to the DC level of the ramp waveform 6011 relative to the first reference voltage (e.g., the DC waveform 6001).

[0141] The voltage generator 1060 may generate a plurality of grayscale voltages as a plurality of voltages VOL and input the plurality of grayscale voltages to the first decoder 1023. The first decoder 1023 may select a grayscale voltage corresponding to the image data DATA from among the plurality of voltages VOL and output the grayscale voltage as a decoder signal S_DEC1 to the first channel amplifier 1021. The first channel amplifier 1021 may output a source signal Si as a target voltage. The source signal Si outputted through the first channel amplifier 1021 may be inputted to the first input terminal of the second channel amplifier 1031 through the third switch SW13.

[0142] The display device 1000 may generate a second ramp waveform 6013 having an arbitrary DC level as a reference voltage. At this time, the second ramp waveform 6013 may have the same voltage as the ramp waveform 6011. The second channel amplifier 1031 may compare the source signal Si with the second ramp waveform 6013, and output the comparison result as a counter signal CNT_S2 to the logic unit 1035. The counter signal CNT_S2_REF2 may have a specific level during t202 to t203.

[0143] The counter 1039 may generate a count value COUNT_NUM12 by counting the time that the counter signal CNT_S2_REF2 maintains a specific level. The driving controller 1050 may obtain a count value according to the DC level of the second target voltage 6003 of the second ramp waveform 6013 (ie, the source signal Si relative to the reference voltage).

[0144] Next, the driving controller 1050 may generate a value obtained by subtracting the count value of the second comparison result from the count value of the first comparison result as a final count value. Figure 6 , the count value of the DC level of the first target value (e.g., ramp waveform 6011) of the reference voltage (e.g., DC voltage 6001) may be a first value (corresponding to t201 to t203), and the count value of the DC level of the second target voltage 6003 of the reference voltage (e.g., second ramp waveform 6013) may be a second value (corresponding to t202 to t203). The drive controller 1050 may determine a value obtained by subtracting the second value from the first value (i.e., a value calculated by counting the time (t201 to t202) that the final counter signal COUNT_NUM_REF maintains a specific level) as the final count value. Figure 6 , the count value of the DC level of the first target value (e.g., ramp waveform 6011) of the reference voltage (e.g., DC voltage 6001) may be a first value (corresponding to t201 to t203), and the count value of the DC level of the second target voltage 6003 of the reference voltage (e.g., second ramp waveform 6013) may be a second value (corresponding to t201 to t202). The driving controller 1050 may determine a value obtained by subtracting the first value from the second value (i.e., a value calculated by counting the time (t201 to t202) that the final counter signal COUNT_NUM_REF maintains a specific level) as the final count value.

[0145] The driving controller 1050 may measure the DC level of the source signal 6003 based on the final count value. In some implementations, the higher the DC level of the source signal 6003, the smaller the final count value may be.

[0146] The driving controller 1050 may change the image data DATA based on the measured DC level of the source signal.

[0147] The driving controller 1050 may set an appropriate reference voltage according to the shape of the waveform of the source signal. For example, if there is a large amount of data indicating white in the image data DATA, there is a high probability that the waveform of the source signal will have a low value. In this case, the driving controller 1050 may use the ramp signal as a reference voltage to measure the DC level of the waveform of the source signal.

[0148] The operation of the display device 1000 from t201 to t203 may be similar to the operation of the display device 1000 from t204 to t206 .

[0149] Figure 7 It shows that Figure 3 A flow chart of an example of a method for operating a display device in a slew rate measurement mode. Figure 8 is shown when the display device is operated in the slew rate measurement mode Figure 3 A timing diagram of an example of the operation of a display device. Specifically, Figure 7 and Figure 8 The reference voltage V_REF output from the voltage generator 1060 and the source signal Si and the outputs of the logic units 1025 and 1035 are shown when the display device 1000 operates in the DC level measurement mode.

[0150] The display device 1000 compares a first reference voltage with a source signal (or a data signal) to generate a first comparison result ( S701 ).

[0151] The voltage generator 1060 may generate a plurality of grayscale voltages as a plurality of voltages VOL, and input the plurality of grayscale voltages to the first decoder 1023. The first decoder 1023 may select a grayscale voltage corresponding to the image data DATA from among the plurality of voltages VOL, and output the grayscale voltage as a decoder signal S_DEC1 to the first channel amplifier 1021. The first channel amplifier 1021 may output a source signal Si as a target voltage. The source signal Si output by the first channel amplifier 1021 may be input to a first input terminal of the second channel amplifier 1031 through a third switch SW13. In some embodiments, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

[0152] The voltage generator 1060 may generate a DC voltage 8001 having a first value as a reference voltage V_REF, and the DC voltage 8001 may be output as a second decoder signal S_DEC2 through the second decoder 1033. Figure 8 , the first value is shown to have a VTOP value, and the VTOP value may be, for example, a value that is 90% of the power supply voltage VDD.

[0153] The second channel amplifier 1031 may compare the DC voltage 8011 with the source signal 8003 and output the comparison result as the counter signal CNT_S2 to the logic unit 1035. Since the source signal 8003 has a greater value than the DC voltage 8011 during t302 to t303, the counter signal CNT_S21 may have a high level during t302 to t303.

[0154] The counter 1039 may generate a count value COUNT_NUM12 by counting the time that the counter signal CNT_S21 maintains a specific level. Thereafter, the logic unit 1035 may transmit the generated count value COUNT_NUM12 to the driving controller 1050 as a reference count value.

[0155] The display device 1000 compares the second reference voltage with the source signal (or the data signal) to generate a second comparison result ( S703 ).

[0156] The voltage generator 1060 may generate a DC voltage 8013 having a second value as a reference voltage V_REF, and the DC voltage 8013 may be output as a second decoder signal S_DEC2 through the second decoder 1033. Figure 8 , the second value is shown to have a VBOTTOM value, and the VBOTTOM value may be, for example, a value of 10% of the power supply voltage VDD.

[0157] The second channel amplifier 1031 may compare the DC voltage 8013 with the source signal 8003 and output the comparison result as the counter signal CNT_S2 to the logic unit 1035. Since the source signal 8003 has a greater value than the DC voltage 8013 during t301 to t304, the counter signal CNT_S22 may have a high level during t301 to t304.

[0158] The counter 1039 may generate a count value COUNT_NUM12 by counting the time that the counter signal CNT_S22 maintains a specific level. Thereafter, the logic unit 1035 may transmit the generated count value COUNT_NUM12 to the driving controller 1050 as a reference count value.

[0159] In some embodiments, the display device 1000 may count the counter signals CNT_S21 and CNT_S22 based on an internal clock.

[0160] The display apparatus 1000 generates a final count value based on the first comparison result and the second comparison result ( S705 ).

[0161] The driving controller 1050 may determine the final count value by performing an OR operation based on the counter signals CNT_S21 and CNT_S22. Figure 8 As shown in , the final count value is shown as the result signal COUNT_NUM_REF, which may be a signal obtained by subtracting the counter signal CNT_S21 from the counter signal CNT_S22. That is, the final result value may indicate a case where the source signal 8003 has a value between the VTOP voltage value and the VBOTTOM voltage value.

[0162] Therefore, the driving controller 1050 can obtain a count value according to the conversion rate of the source signal 8003 for the DC voltage 8011 and the DC voltage 8013 .

[0163] The display device 1000 measures a conversion rate of the source signal 8003 (or data signal) based on the final count value ( S707 ).

[0164] The display device 1000 may obtain the final count value and measure the conversion rate of the source signal based on the final count value. For example, if the final count value is small, the voltage level of the source signal 8003 increases rapidly, so the source signal 8003 may have a high conversion rate. For another example, when the final count value is large, the voltage level of the source signal 8003 gradually increases, so the source signal 8003 may have a low conversion rate.

[0165] The driving controller 1050 may determine whether there is a difference between a predetermined slew rate and a slew rate measured for the source signal. If the predetermined slew rate is greater than the slew rate measured for the source signal, the driving controller 1050 may control the voltage generator 1060 to reduce the voltage provided to the channel amplifiers 1021 and 1031. If the predetermined slew rate is less than the slew rate measured for the source signal, the driving controller 1050 may control the voltage generator 1060 to increase the voltage provided to the channel amplifiers 1021 and 1031.

[0166] The display device may use a channel amplifier located on a source line to measure the DC level and slew rate of a source signal adjacent to the source line. Typically, the source line operates in a driving mode while the measurement is being made, which may make it difficult to measure the DC level and slew rate of the source signal. In other words, when the display device 1000 is driven, it may not be possible to perform a test on the source signal in real time.

[0167] The operation of the display device 1000 from t301 to t304 may be similar to the operation of the display device 1000 from t305 to t308 .

[0168] Fig. 9is a diagram illustrating an example of a display device.

[0169] like Fig. 9 As shown in FIG. 1 , the display device 2000 includes a pixel array 2010 and a display driving circuit 2020. The display driving circuit 2020 includes a gate driver 2030, a source driver 2040, a driving controller 2050, and a voltage generator 2060. The configuration including the driving controller 2050 and the voltage generator 2060 may be referred to as a main logic 2001. The main logic 2001 may also include a memory storing arbitrary data for controlling the configuration within the display device 2000. However, the present disclosure is not limited thereto, and the memory may be located outside the display device 2000.

[0170] The pixel array 2010 may include a plurality of pixels PX. The pixel array 2010 may include a plurality of gate lines GL0, ..., GLh-1 connected to the plurality of pixels PX, a plurality of source lines SL0, ..., SLk-1, and a plurality of return lines RL0, ..., RLk-1 respectively connected to corresponding source lines among the plurality of source lines SL0, ..., SLk-1.

[0171] The gate driver 2030 may transmit gate signals G0 , . . . , Gh- 1 to the plurality of gate lines GL0 , . . . , GLh- 1 based on the first control signal CONT1 received from the driving controller 2050 .

[0172] The driving controller 2050 may drive the display device 2000 in a plurality of modes. For example, when the display device 2000 operates in the driving mode, the driving controller 2050 may generate a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 corresponding to the driving mode. In this case, the second control signal CONT2 may be a signal for controlling a plurality of switches SW21 to SW26 within the selector 2011.

[0173] For another example, when the display device 2000 operates in the test mode, the driving controller 2050 may generate a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 corresponding to the test mode. In some embodiments, the driving controller 2050 may measure the DC level and the slew rate of the source signal Si output through the source line SLi through the return line RLi connected to the target source line SLi. Each of the plurality of return lines RL may be connected to a corresponding source line among the plurality of source lines SL through a switch.

[0174] Specifically, the multiple source lines SL within the pixel array 2010 may include a first test mode and a second test mode. In the first test mode, the source line set at the 2n-1th (where n is a natural number greater than 1) operates in a driving mode, and the source line set at the 2nth operates in a comparator mode. In the second test mode, the source line set at the 2nth operates in a driving mode, and the source line set at the 2n-1th (where n is a natural number greater than 1) operates in a comparator mode.

[0175] When the display device 2000 operates in the first test mode, the driving controller 2050 may generate a first control signal CONT1 corresponding to the first test mode, a second control signal CONT2 corresponding to the first test mode, and a third control signal CONT3 corresponding to the first test mode.

[0176] When the display device 2000 operates in the second test mode, the driving controller 2050 may generate a first control signal CONT1 corresponding to the second test mode, a second control signal CONT2 corresponding to the second test mode, and a third control signal CONT3 corresponding to the second test mode.

[0177] The voltage generator 2060 may generate various voltages required to drive the display device 2000 under the control of the driving controller 2050. For example, the voltage generator 2060 may include a plurality of voltages VOL including a plurality of grayscale voltages and a reference voltage V_REF.

[0178] The source driver 2040 may include logic units 2025 and 2035, decoders 2023 and 2033, channel amplifiers 2021 and 2031, and a selector 2011. In some embodiments, the logic unit 2025 may include a latch 2027 and a counter 2029, and the logic unit 2035 may include a latch 2037 and a counter 2039. Each of the counters 2029 and 2039 may transmit the generated first count value COUNT_NUM21 and the second count value COUNT_NUM22 to the driving controller 2050.

[0179] Unless otherwise stated, refer to Figure 3 The description of the described logic units 1025 and 1035 , decoders 1023 and 1033 , and channel amplifiers 1021 and 1031 may be applied to the logic units 2025 and 2035 , decoders 2023 and 2033 , and channel amplifiers 2021 and 2031 .

[0180] The selector 2011 may be connected to the first channel amplifier 2021 and the second channel amplifier 2031, and may be connected to return lines RLi and RLi+1 which are respectively connected to two adjacent source lines SLi and SLi+1.

[0181] The selector 2011 may include first to sixth switches SW21, SW22, SW23, SW24, SW25, and SW26. The selector 2011 may control the connection relationship between the plurality of switches SW21 to SW26 within the selector 2011 based on the second control signal CONT2 received from the driving controller 2050. Specifically, the first switch SW21 may connect the output terminal of the first channel amplifier 2021 with the first source line SLi or the first return line RLi. The second switch SW22 may connect the output terminal of the second channel amplifier 2031 with the second source line SLi+1 or the second return line RLi+1. The third switch SW23 may be connected between one end of the first switch SW21 (e.g., the output terminal of the first channel amplifier 2021) and the first input terminal of the second channel amplifier 2031. The fourth switch SW24 may be connected between one end of the second switch SW22 (e.g., the output terminal of the second channel amplifier 2031) and the first input terminal of the first channel amplifier 2021. The fifth switch SW25 may connect one end of the first switch SW21 (e.g., the output terminal of the first channel amplifier 2021) to the logic unit 2025, or connect one end of the first switch SW21 to the first input terminal of the first channel amplifier 2021, according to the second control signal CONT2. The sixth switch SW26 may connect one end of the second switch SW22 (e.g., the output terminal of the second channel amplifier 2031) to the logic unit 2035, or connect one end of the second switch SW22 to the first input terminal of the second channel amplifier 2031, according to the second control signal CONT2. Figure 3 , the first switch SW21, the second switch SW22, the fifth switch SW25, and the sixth switch SW26 are each shown as one SPDT switch, but the present disclosure is not limited thereto. In some embodiments, each of the first switch SW21, the second switch SW22, the fifth switch SW25, and the sixth switch SW26 may be implemented as two switches.

[0182] As described above, when the display device 2000 operates in the driving mode, the driving controller 2050 may generate a second control signal CONT2 corresponding to the driving mode and transmit the second control signal CONT2 to the selector 2011. Based on the second control signal CONT2 corresponding to the driving mode, the first switch SW21 may connect the output terminal of the first channel amplifier 2021 with the first source line SLi, and the second switch SW22 may connect the output terminal of the second channel amplifier 2031 with the second source line SLi+1. The third switch SW23, the fourth switch SW24, the fifth switch SW25, and the sixth switch SW26 may be disconnected. Therefore, the selector 2011 may receive the first source signal Si from the first channel amplifier 2021 and transmit the first source signal Si to the source line SLi, and may receive the second source signal Si+1 from the second channel amplifier 2031 and transmit the second source signal Si+1 to the source line SLi+1.

[0183] As described above, when the display device 2000 operates in the test mode, the driving controller 2050 may generate the second control signal CONT2 corresponding to the test mode and transmit the second control signal CONT2 to the selector 2011 .

[0184] For example, when the display device 2000 operates in the first test mode, the second control signal CONT2 may be a signal that controls the selector 2011 to output the source signal Si to the corresponding source line SLi, and controls the selector 2011 to send the source signal Si to the first input terminal of the channel amplifier 2031 connected to the source line SLi+1.

[0185] In the case of the first test mode, based on the second control signal CONT2 corresponding to the first test mode, the first switch SW21 may connect the output terminal of the first channel amplifier 2021 to the first return line RLi, the second switch SW22 may connect the output terminal of the second channel amplifier 2031 to the second source line SLi+1, the third switch SW23 may be turned on, the fourth switch SW24 may be turned off, the fifth switch SW25 may connect one end of the first switch SW21 to the first input terminal of the first channel amplifier 2021, and the sixth switch SW26 may connect the output terminal of the second channel amplifier 2031 to the logic unit 2035. Therefore, the selector 2011 may receive the first return signal Ri from the first return line RLi and transmit the first return signal Ri to the first input terminal of the second channel amplifier 2031 through the third switch SW23. The second channel amplifier 2031 may compare the first return signal Ri input to the first input terminal with the reference voltage received from the second decoder 2033, and transmit the comparison result to the logic unit 2035 through the sixth switch SW26.

[0186] In some embodiments, the return signal Ri input to the first input terminal of the second channel amplifier 2031 through the return line RLi can be a signal from the corresponding source line SLi, which has been sent to a pixel far away from the source driver 2040 through multiple gate lines GL and then returned.

[0187] In this case, the switch connecting the return line RLi and the source line SLi may be turned on. Since the return signal Ri is a signal sent through a plurality of gate lines GL and returned again, the return signal Ri may be different from the source signal Si output from the output terminal of the first channel amplifier 2021. In some embodiments, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

[0188] The third control signal CONT3 may be a signal that controls the voltage generator 2060 to transmit a plurality of grayscale voltages as a plurality of voltages VOL to the decoder 2023 and transmits the reference voltage V_REF to the decoder 2033. In this case, the reference voltage V_REF may be input to the second channel amplifier 2031 through the decoder 2033.

[0189] For another example, in the case of the second test mode, based on the second control signal CONT2 corresponding to the second test mode, the first switch SW21 may connect the output terminal of the first channel amplifier 2021 to the first source line SLi, the second switch SW22 may connect the output terminal of the second channel amplifier 2031 to the second return line RLi+1, the third switch SW23 may be turned off, the fourth switch SW24 may be turned on, the fifth switch SW25 may connect the output terminal of the first channel amplifier 2021 with the logic unit 2025, and the sixth switch SW26 may connect the output terminal of the second channel amplifier 2031 with the first input terminal of the second channel amplifier 2031. Therefore, the selector 2011 may receive the second return signal Ri+1 from the return line RLi+1, and transmit the second return signal Ri+1 to the first input terminal of the first channel amplifier 2021 through the fourth switch SW24. The first channel amplifier 2021 may compare the second return signal Ri+1 input to the first input terminal with the reference voltage received from the first decoder 2023, and transmit the comparison result to the logic unit 2025 through the fifth switch SW25.

[0190] The second control signal CONT2 may be a signal that controls the selector 2011 to output the source signal Si+1 to the source line SLi+1, and controls the selector 2011 to transmit the source signal Si+1 as the return signal RLi+1 to the first input terminal of the channel amplifier 2021 through the return line RLi+1 connected to the source line SLi+1. The third control signal CONT3 may be a signal that controls the voltage generator 2060 to transmit a plurality of grayscale voltages as a plurality of voltages VOL to the second decoder 2033 and to transmit the reference voltage V_REF to the first decoder 2023. In this case, the reference voltage V_REF may be input to the first channel amplifier 2021 through the first decoder 2023.

[0191] Fig.10 is a diagram illustrating an example of a display device.

[0192] like Fig.10 As shown in FIG. 3 , the display device 3000 includes a pixel array 3010 and a display driving circuit 3020. The display driving circuit 3020 includes a gate driver 3030, a source driver 3040, a driving controller 3050, and a voltage generator 3060. The configuration including the driving controller 3050 and the voltage generator 3060 may be referred to as a main logic 3001. The main logic 3001 may also include a memory storing arbitrary data for controlling the configuration within the display device 3000. However, the present disclosure is not limited thereto, and the memory may be located outside the display device 3000.

[0193] The pixel array 3010 may include a plurality of pixels PX. The pixel array 3010 may include a plurality of gate lines GL0, ..., GLh-1 connected to the plurality of pixels PX, a plurality of source lines SL0, ..., SLk-1, and a plurality of return lines RL0, ..., RLk-1 respectively connected to corresponding source lines among the plurality of source lines SL0, ..., SLk-1.

[0194] The gate driver 3030 may transmit gate signals G0 , . . . , Gh- 1 to the plurality of gate lines GL0 , . . . , GLh- 1 based on the first control signal CONT1 received from the driving controller 3050 .

[0195] The driving controller 3050 may drive the display device 3000 in a plurality of modes. For example, when the display device 3000 operates in the driving mode, the driving controller 3050 may generate a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 corresponding to the driving mode. In this case, the second control signal CONT2 may be a signal for controlling a plurality of switches SW31 to SW34 within the selector 3011. The third control signal CONT3 may be a signal for controlling the voltage generator 3060 to generate a voltage provided to the source driver 3040. In some embodiments, the driving controller 3050 may receive a first count value COUNT_NUM31 and a second count value COUNT_NUM32 provided from the source driver 3040.

[0196] For another example, when the display device 3000 operates in the test mode, the driving controller 3050 may generate a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 corresponding to the test mode. In some embodiments, the driving controller 3050 may measure the DC level and the slew rate of the source signal Si output through the source line SLi through the return line RLi connected to the target source line SLi.

[0197] When the display device 3000 operates in the test mode, the driving controller 3050 may generate a first control signal CONT1 corresponding to the test mode, a second control signal CONT2 corresponding to the test mode, and a third control signal CONT3 corresponding to the test mode. For example, when the display device 3000 operates in the test mode, the second control signal CONT2 may be a signal that controls the selector 3011 to output the source signal Si to the corresponding source line SLi, and controls the selector 3011 to send the return signal Ri corresponding to the source signal Si to the comparator 3101.

[0198] The third control signal CONT3 may be a signal that controls the voltage generator 3060 to generate a plurality of grayscale voltages as a plurality of voltages VOL and transmit the plurality of grayscale voltages to the decoder 3103 , and to generate and transmit reference voltages V_REF1 and V_REF2 to the comparator 3101 .

[0199] The voltage generator 3060 may generate various voltages required to drive the display device 3000 under the control of the driving controller 3050. For example, the voltage generator 3060 may generate a plurality of voltages VOL including a plurality of grayscale voltages and a plurality of reference voltages V_REF1 and V_REF2.

[0200] The source driver 3040 may include a logic unit 3105 , a decoder 3103 , a channel amplifier 3102 , a comparator 3101 , and a selector 3011 .

[0201] The source driver 1040 may convert the image data DATA received from the driving controller 3050 into a source signal Si and output the source signal Si through a second source line (SLi, i is an integer greater than 0 and less than or equal to k-2). The source driver 3040 may generate a count value COUNT_NUM31 based on a DC level and a conversion rate measured based on a return signal Ri corresponding to the source signal Si and a reference voltage.

[0202] The logic unit 3105 may receive the image data DATA from the driving controller 3050 and transmit the count value COUNT_NUM31 to the driving controller 3050 .

[0203] The logic unit 3105 may include a latch 3107 and a counter 3109 .

[0204] The latch 3107 may receive image data DATA from the driving controller 3050. The latch 3107 may sample and store the image data DATA under the control of the driving controller 3050. The latch 3107 may transmit the sampled image data to the decoder 3103. In some embodiments, the latch 3107 may include a sampling circuit that samples the data and a holding latch that stores the data sampled by the sampling circuit.

[0205] The counter 3109 generates a first count value COUNT_NUM31 based on the counter input signal CNT_S received from the comparator 3101. Here, the counter input signal CNT_S may be a signal indicating a comparison result of comparing the source signal Si with the reference voltage or a comparison result of comparing the return signal Ri corresponding to the source signal Si with the reference voltage. The counter 3109 may send the generated count value COUNT_NUM31 to the driving controller 3050.

[0206] exist Fig.10 , the latch 3107 and the counter 3109 are shown to be included in the logic unit 3105. However, the present disclosure is not limited thereto, and the latch 3107 and the counter 3109 may be configured in separate configurations.

[0207] The decoder 3103 may receive the sampled image data from the latch 3107 and receive a plurality of voltages VOL from the voltage generator 3060. The plurality of voltages VOL may include gamma voltages corresponding to respective levels of brightness of the display device 3000. In some embodiments, the decoder 3103 may select one of the plurality of voltages VOL in response to the sampled image data. The decoder 3103 may output the selected gamma voltage to the channel amplifier 3102. For example, the decoder 3103 may be implemented as a digital-to-analog converter.

[0208] The channel amplifier 3102 may receive the gamma voltage selected from the decoder 3103 , amplify the gamma voltage selected by the decoder 3103 in response to the second control signal CONT2 received from the driving controller 3050 , and transmit the selected gamma voltage to the selector 3011 as a source signal Si.

[0209] The selector 3011 may be connected to the channel amplifier 3102, the comparator 3101, the source line SLi, the return line RLi, and the voltage generator 3060. The selector 3011 may include first to fourth switches SW31, SW32, SW33, and SW34. The selector 3011 may control the connection relationship between the plurality of switches SW31 to SW34 in the selector 3011 based on the second control signal CONT2 received from the drive controller 3050. Specifically, the first switch SW31 may be connected between the voltage line providing the first reference voltage V_REF1 and the first input terminal of the comparator 3101. The second switch SW32 may connect the second input terminal of the comparator 3101 with the return line RLi, or connect the second input terminal of the comparator 3101 with the source line SLi. The third switch SW33 may be connected between the second input terminal of the comparator 3101 and the voltage line providing the second reference voltage V_REF2. The fourth switch SW34 may be connected between the output terminal of the channel amplifier 3102 and the source line SLi. exist Fig.10 , the second switch SW32 is shown as one SPDT switch, but the present disclosure is not limited thereto. For example, the second switch SW32 may be implemented as two switches.

[0210] As described above, when the display device 3000 operates in the driving mode, the driving controller 3050 may generate the second control signal CONT2 corresponding to the driving mode and transmit the second control signal CONT2 to the selector 3011 .

[0211] Based on the second control signal CONT2 corresponding to the driving mode, the first switch SW31 and the fourth switch SW34 may be turned on, the second switch SW32 may connect the comparator 3101 with the return line RLi or the source line SLi, and the third switch SW33 may be turned off. Therefore, the selector 3011 may receive the source signal Si from the channel amplifier 3102 and transmit the source signal Si to the source line SLi through the fourth switch SW34.

[0212] The display device 3000 may operate in a test mode while operating in a driving mode. For example, when the display device 3000 operates in a DC level measurement mode, the first switch SW31 and the fourth switch SW34 may be turned on, the second switch SW32 may connect the comparator 3101 with the return line RLi or the source line SLi, and the third switch SW33 may be turned off. In some embodiments, the first reference voltage V_REF1 may be a sawtooth waveform voltage for measuring the DC level of the source signal Si. When the display device 3000 operates in the DC level measurement mode, the drive controller 3050 may compare the return signal Ri or the source signal Si with the first reference voltage V_REF1.

[0213] When comparing the first reference voltage V_REF1 with the second reference voltage V_REF2 to measure the DC level of the source signal Si, the first switch SW31 may connect the comparator 3101 with the voltage line providing the first reference voltage V_REF1, and the third switch SW33 may be turned on. Therefore, the comparator 3101 may compare the first reference voltage V_REF1 with the second reference voltage V_REF2.

[0214] For another example, when the display device 3000 operates in the slew rate measurement mode, the first switch SW31 and the fourth switch SW34 may be turned on, the second switch SW32 may connect the comparator 3101 with the return line RLi or the source line SLi, and the third switch SW33 may be turned off. In some embodiments, the second reference voltage V_REF2 may be a DC voltage for measuring the slew rate of the source signal Si. When the display device 3000 operates in the slew rate measurement mode, the drive controller 3050 may compare the return signal Ri with the second reference voltage V_REF2. When the display device 3000 operates in the slew rate measurement mode, the second switch SW32 may be configured to connect the comparator 3101 and the return line RLi to accurately measure the change in the source signal Si.

[0215] The source driver 3040 includes a plurality of comparators, and each of the plurality of comparators is connected to a corresponding source line among the plurality of source lines and a corresponding return line among the plurality of return lines corresponding to the plurality of source lines. Therefore, even when operating in the driving mode, the display device 3000 can measure the DC level or conversion rate of the source signal Si.

[0216] Therefore, the display device 3000 can correct the image data in real time based on the DC level or conversion rate of the source signal Si measured while the display device 3000 operates in the driving mode. In some embodiments, the display device 3000 can also correct the image signal ( Figure 1 IS in the ).

[0217] Fig.11 is a diagram illustrating an example of a display device.

[0218] like Fig.11 As shown in , the display device 4000 includes a pixel array 4010 and a display driving circuit 4020. The display driving circuit 4020 may include a gate driver 4030, a source driver 4040, a driving controller 4050, and a voltage generator 4060. The configuration including the driving controller 4050 and the voltage generator 4060 may be referred to as the main logic 201. The main logic 4001 may also include a memory storing arbitrary data for controlling the configuration within the display device 4000. However, the present disclosure is not limited thereto, and the memory may be located outside the display device 4000.

[0219] Unless otherwise specified, the display device 4000 may be used in conjunction with the reference Fig.10 The display device 3000 described is similar.

[0220] like Fig.11 As shown in , the source driver 4040 may have a comparator connected only to the source line SL0 and the source line SLk-1 at both ends of the plurality of source lines SL0, ..., SLk-1 within the pixel array 4010. In some embodiments, the driving controller 4050 may receive the first count value COUNT_NUM41 and the second count value COUNT_NUM42 provided from the source driver 4040.

[0221] In some embodiments, the source driver 4040 may include a comparator 4101, a channel amplifier 4102, a decoder 4103, a logic unit 4105, a latch 4107, a counter 4109, and a selector 4011. The selector 4011 may include a first switch SW41, a second switch SW42, a third switch SW43, and a fourth switch SW44. Specifically, the first switch SW41 may be connected between a voltage line providing a first reference voltage V_REF1 and a first input terminal of the comparator 4101. The second switch SW42 may connect a second input terminal of the comparator 4101 to a return line RLi, or connect a second input terminal of the comparator 4101 to a source line SLi. The third switch SW43 may be connected between a second input terminal of the comparator 4101 and a voltage line providing a second reference voltage V_REF2. The fourth switch SW44 may be connected between an output terminal of the channel amplifier 4102 and a source line SLi.

[0222] As the number of source lines increases, the load applied to the display panel may further increase. Therefore, in order to reduce the load on the source line SL connected to the pixel array 4010, representative characteristics of the source signals Si, Sk-1 provided to both ends of the pixel array 4010 may be measured. However, the present disclosure is not limited thereto, and the configuration of the source driver including a comparator for measuring the characteristics of the source signal Si may be provided on any source line SL.

[0223] Fig.12 is a diagram showing a display device except as otherwise described.

[0224] like Fig.12 As shown in FIG. 5 , the display device 5000 includes a pixel array 5010 and a display driving circuit 5020. The display driving circuit 5020 includes a gate driver 5030, a source driver 5040, a driving controller 5050, and a voltage generator 5060. The configuration including the driving controller 5050 and the voltage generator 5060 may be referred to as a main logic 201. The main logic 201 may also include a memory storing arbitrary data for controlling the configuration within the display device 5000. However, the present disclosure is not limited thereto, and the memory may be located outside the display device 5000.

[0225] The pixel array 5010 may include a plurality of pixels PX. The pixel array 5010 may include a plurality of gate lines GL0, ..., GLh-1 connected to the plurality of pixels PX, a plurality of source lines SL0, ..., SLk-1, and a plurality of return lines RL0, ..., RLk-1 respectively connected to corresponding source lines among the plurality of source lines SL0, ..., SLk-1.

[0226] The gate driver 5030 may transmit gate signals G0 , . . . , Gh- 1 to the plurality of gate lines GL0 , . . . , GLh- 1 based on the first control signal CONT1 received from the driving controller 5050 .

[0227] The driving controller 5050 may drive the display device 5000 in a plurality of modes. For example, when the display device 5000 operates in the driving mode, the driving controller 5050 may generate a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 corresponding to the driving mode. In this case, the second control signal CONT2 may be a signal for controlling a plurality of switches SW51 to SW53 within the selector 5111. The third control signal CONT3 may be a signal for controlling the voltage generator 5060 to generate a voltage provided to the source driver 5040.

[0228] For example, when the display device 5000 operates in the test mode, the driving controller 5050 may generate a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 corresponding to the test mode. In some embodiments, the driving controller 5050 may measure a DC level and a slew rate of a source signal Si output through a source line SLi through a return line RLi connected to a target source line SLi.

[0229] When the display device 5000 operates in the test mode, the driving controller 5050 may generate a first control signal CONT1 corresponding to the test mode, a second control signal CONT2 corresponding to the test mode, and a third control signal CONT3 corresponding to the test mode. For example, when the display device 5000 operates in the test mode, the second control signal CONT2 may be a signal that controls the selector 5111 to output the source signal Si to the corresponding source line SLi and controls the selector 5111 to send the return signal Ri corresponding to the source signal Si to the channel amplifier 5101.

[0230] The third control signal CONT3 may be a signal that controls the voltage generator 5060 to generate a plurality of grayscale voltages as a plurality of voltages VOL and transmit the plurality of grayscale voltages to the decoder 5103 , and to generate reference voltages V_REF1 and V_REF2 and transmit the reference voltages V_REF1 and V_REF2 to the comparator 5102 .

[0231] The voltage generator 5060 may generate various voltages required to drive the display device 5000 under the control of the driving controller 5050. For example, the voltage generator 5060 may generate a plurality of voltages VOL including a plurality of grayscale voltages and a plurality of reference voltages V_REF1 and V_REF2.

[0232] The source driver 5040 may include a channel amplifier 5101 , a comparator 5102 , a decoder 5103 , a logic unit 5105 , a counter 5109 , and a selector 5111 .

[0233] The source driver 5040 may convert the image data DATA received from the driving controller 5050 into a source signal Si and output the source signal Si through a second source line (SLi, i is an integer greater than 0 and less than or equal to k-2). The source driver 5040 may generate a count value COUNT_NUM51 based on a DC level and a conversion rate measured based on a return signal Ri corresponding to the source signal Si and a reference voltage.

[0234] The logic unit 5105 may receive image data DATA from the driving controller 5050. The logic unit 5105 may include a latch 5107. The latch 5107 may receive the image data DATA from the driving controller 5050. The latch 5107 may sample and store the image data DATA under the control of the driving controller 5050. The latch 5107 may send the sampled image data to the decoder 5103. In some embodiments, the latch 5107 may include a sampling circuit that samples data and a holding latch that stores the data sampled by the sampling circuit.

[0235] The counter 5109 generates a count value COUNT_OUT based on a counter input signal CNT_S received from the comparator 5102. Here, the counter input signal CNT_S may be a signal indicating a comparison result of comparing the source signal Si with a reference voltage or a comparison result of comparing a return signal Ri corresponding to the source signal Si with a reference voltage. The counter 5109 may send the generated count value COUNT_OUT to the drive controller 5050. For example, the counter 5109 may send the count value COUNT_OUT to the logic unit 5105, and the logic unit 5105 may send the count value COUNT_OUT received from the counter 5109 to the drive controller 5050.

[0236] The decoder 5103 may receive the sampled image data from the latch 5107, and may receive a plurality of voltages VOL from the voltage generator 5060. The plurality of voltages VOL may include gamma voltages corresponding to various levels of brightness of the display device 5000. In some embodiments, the decoder 5103 may select one of the plurality of voltages VOL in response to the sampled image data. The decoder 5103 may output the selected gamma voltage to the channel amplifier 5101. For example, the decoder 5103 may be implemented as a digital-to-analog converter.

[0237] The channel amplifier 5101 may receive the gamma voltage selected from the decoder 5103 , amplify the gamma voltage selected by the decoder 5103 in response to the second control signal CONT2 received from the driving controller 5050 , and transmit the selected gamma voltage to the selector 5111 as a source signal Si.

[0238] The selector 5111 may be connected to the channel amplifier 5101, the comparator 5102, the source line SLi, the return line RLi and the voltage generator 5060. The selector 5111 may include first to third switches SW51, SW52 and SW53. The selector 5111 may control the connection relationship between the multiple switches SW51 to SW53 within the selector 5111 based on the second control signal CONT2 received from the drive controller 5050. Specifically, the first switch SW51 may connect the first input terminal of the comparator 5102 with the return line RLi, or connect the first input terminal of the comparator 5102 with the source line SLi. The second switch SW52 may be connected between the second input terminal of the comparator 5102 and the voltage line providing the second reference voltage V_REF2. The third switch SW53 may be connected between the output terminal of the channel amplifier 5101 and the source line SLi. Fig.12 , the first switch SW51 is shown as one SPDT switch, but the present disclosure is not limited thereto. In some embodiments, the first switch SW51 may be implemented as two switches.

[0239] As described above, when the display device 5000 operates in the driving mode, the driving controller 5050 may generate the second control signal CONT2 corresponding to the driving mode and transmit the second control signal CONT2 to the selector 5111 .

[0240] Based on the second control signal CONT2 corresponding to the driving mode, the first switch SW51 can connect the comparator 5102 with the return line RLi or the source line SLi, the second switch SW52 can be turned off, and the third switch SW53 can be turned on. Therefore, the selector 5111 can receive the source signal Si from the channel amplifier 5101 and send the source signal Si to the source line SLi through the third switch SW53.

[0241] The display device 5000 may operate in a test mode while operating in a driving mode. For example, when the display device 5000 operates in a DC level measurement mode, the first switch SW51 may connect the comparator 5102 with the return line RLi or the source line SLi, the second switch SW52 may be disconnected, and the third switch SW53 may be turned on. In some embodiments, the first reference voltage V_REF1 may be a sawtooth waveform voltage for measuring the DC level of the source signal Si. When the display device 5000 operates in a DC level measurement mode, the drive controller 5050 may compare the return signal Ri or the source signal Si with the first reference voltage V_REF1.

[0242] When comparing the first reference voltage V_REF1 with the second reference voltage V_REF2 to measure the DC level of the source signal Si, the first switch SW51 may be turned off, the second switch SW52 may be connected to a voltage line providing the second reference voltage V_REF2, and the third switch SW53 may be turned on or off. Therefore, the comparator 5102 may compare the first reference voltage V_REF1 with the second reference voltage V_REF2.

[0243] For example, when the display device 5000 operates in the slew rate measurement mode, the first switch SW51 may connect the comparator 5102 with the return line RLi or the source line SLi, the second switch SW52 may be disconnected, and the third switch SW53 may be turned on. In some embodiments, the second reference voltage V_REF2 may be a DC voltage for measuring the slew rate of the source signal Si. When the display device 5000 operates in the slew rate measurement mode, the first switch SW51 may be configured to connect the comparator 5102 and the return line RLi to accurately measure the change in the source signal Si.

[0244] The source driver 5040 includes a comparator connected to the plurality of source lines SL, and may measure a DC level or a slew rate of a source signal Si of all the source lines SL through the comparator 5102 by controlling the source signal Si input into the comparator 5102 .

[0245] Fig.13 is a diagram showing an example of a display system.

[0246] Reference Fig.13 , the display system 1300 includes a processor 1310 , a memory 1320 , a display device 1330 , and a peripheral device 1340 , which are electrically connected to a system bus 1350 .

[0247] The processor 1310 controls input and output of data from the memory 1320 , the display device 1330 , and the peripheral device 1340 , and may perform image processing of image data transmitted between corresponding devices.

[0248] The memory 1320 may include a volatile memory such as a dynamic random access memory (DRAM) and / or a non-volatile memory such as a flash memory. The memory 1320 may include a DRAM, a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a NOR flash memory, a NAND flash memory, and a fusion flash memory (e.g., a memory combined with a static random access memory (SRAM) buffer, a NAND flash memory, and a NOR interface logic).

[0249] The memory 1320 may store image data obtained from the peripheral device 1340 or an image signal processed by the processor 1310 .

[0250] The display device 1330 includes a display panel 1331, and may display image data transmitted through the system bus 1350 on the display panel 1331. The display panel 1331 may be a display area. The display panel 1331 may include a driving circuit (DC) 1332. The driving circuit 1332 may measure a DC level of a source signal provided from the driving circuit 1332 to the display panel 1331 and a slew rate of the source signal. Thereafter, the driving circuit 1332 may modify the image data based on the measured DC level and slew rate.

[0251] The peripheral device 1340 may be a device that converts a moving image or a still image into an electrical signal, such as a camera, a scanner, or a webcam. Image data obtained through the peripheral device 1340 may be stored in the memory 1320 or displayed on the display panel 1331 in real time.

[0252] The display system 1300 may be provided in a mobile electronic product such as a smart phone, but is not limited thereto, and may be provided in various types of electronic products that display an image.

[0253] Although examples of the present disclosure have been described in detail, it should be understood that the present disclosure is not limited to the disclosed examples, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0254] In some embodiments, reference Figures 1 to 13 Each constituent element described or a combination of two or more constituent elements may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), or the like.

[0255] Although the present disclosure contains many specific implementation details, these implementation details should not be interpreted as limiting the scope of possible protection. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in a specific combination or even initially claimed as such, one or more features from the combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variant of the sub-combination.

[0256] While the embodiments of the present disclosure have been described in detail, it should be understood that the present disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising: a pixel array including a plurality of pixels connected to a plurality of source lines; a voltage generator configured to generate a reference voltage; as well as A source driver is configured to output a first source signal corresponding to a first source line among the plurality of source lines, receive a first return signal corresponding to the first source signal through a second source line arranged adjacent to the first source line, and generate a first count value based on a first comparison result of the first return signal and a reference voltage.

2. The display device according to claim 1, wherein: The source driver includes: a first channel amplifier connected to the first source line and configured to output a first source signal; a second channel amplifier configured to receive a reference voltage and a first return signal and output a first comparison result; a selector connected to the first source line and configured to send the first return signal to the second channel amplifier; and The first counter is configured to generate a first count value based on the first comparison result.

3. The display device according to claim 2, wherein: The second channel amplifier is configured to output a second source signal corresponding to a second source line, The first channel amplifier is configured to receive a second return signal corresponding to the second source signal, The first channel amplifier is configured to output a second comparison result between the reference voltage and the second source signal. The selector is also connected to the second source line and sends a second return signal to the first channel amplifier, The source driver further includes a second counter configured to generate a second count value based on the second comparison result.

4. The display device according to claim 3, wherein: The selectors are: a first switch configured to connect an output terminal of the first channel amplifier to a first input terminal of the first channel amplifier or a first counter; a second switch configured to connect an output terminal of the first channel amplifier to a first input terminal of the second channel amplifier; a third switch configured to connect the output terminal of the second channel amplifier to the first input terminal of the second channel amplifier or the second counter; and The fourth switch is configured to connect the output terminal of the second channel amplifier and the first input terminal of the first channel amplifier.

5. The display device according to claim 4, wherein: When the second switch is turned on, the fourth switch is turned off, the first switch connects the output terminal of the first channel amplifier to the first input terminal of the first channel amplifier, the third switch connects the output terminal of the second channel amplifier to the second counter, and the second channel amplifier outputs the first comparison result, When the fourth switch is turned on, the second switch is turned off, the first switch connects the output terminal of the first channel amplifier to the first counter, the third switch connects the output terminal of the second channel amplifier to the first input terminal of the second channel amplifier, and the first channel amplifier outputs a second comparison result.

6. The display device according to claim 3, further comprising: The drive controller is configured as: receiving an image signal from an external source; generating image data corresponding to the received image signal; correcting the image data of the first source signal based on the first count value and the second count value; as well as The corrected image data is provided to the source driver.

7. The display device according to claim 6, wherein: The reference voltage is a sawtooth waveform, and The driving controller is configured to measure a DC level value of the first source signal based on the first count value, and to measure a DC level value of the second source signal based on the second count value.

8. The display device according to claim 6, wherein: The reference voltage is a DC voltage, and The driving controller is configured to measure a conversion rate of the first source signal based on the first count value, and to measure a conversion rate of the second source signal based on the second count value.

9. The display device according to claim 3, wherein: The source driver is configured to correct the first source signal based on the first count value and the second count value.

10. The display device according to claim 1, further comprising: a plurality of return lines, respectively connected to corresponding source lines among the plurality of source lines, The source driver is configured to receive the first source signal through a first return line connected to the first source line among the plurality of return lines.

11. A display device, comprising: a pixel array including a plurality of pixels connected to a plurality of source lines; a voltage generator configured to generate a reference voltage; as well as A source driver is configured to output a first source signal corresponding to a first source line among the multiple source lines, receive a first return signal corresponding to the first source signal through a first return line among a plurality of return lines respectively connected to corresponding source lines among the multiple source lines, and generate a first count value based on a first comparison result of the first return signal and a reference voltage.

12. The display device according to claim 11, wherein: The source driver includes: a first channel amplifier configured to be connected to a first source line and output a first source signal; a first comparator configured to receive a reference voltage and a first return signal, and output a first comparison result; a selector configured to be connected to the first source line and to send a first return signal to the first comparator; and The first counter is configured to generate a first count value based on the first comparison result.

13. The display device according to claim 12, wherein: The selectors are: a first switch configured to be connected to a first return line or to be connected between a first voltage line and a first input terminal of a first comparator, the first voltage line being configured to provide a reference voltage; a second switch configured to connect the second input terminal of the first comparator with the first return line, or to connect the second input terminal of the first comparator with the first source line; and The third switch is configured to connect the second voltage line and the second input terminal, and the second voltage line is configured to provide a reference voltage.

14. The display device according to claim 11, further comprising: The drive controller is configured as: receiving an image signal from an external source, generating image data corresponding to the received image signal, correcting image data of the first source signal based on the first count value, and The corrected image data is provided to the source driver.

15. The display device according to claim 13, wherein: When the first switch is turned on, the second switch is configured to connect the second input terminal of the first comparator to the first return line, and When the third switch is turned off, the first channel amplifier is configured to output a first comparison result.

16. The display device according to claim 11, wherein: The first source line is located at two ends of the pixel array.

17. A display device, comprising: a pixel array including a plurality of pixels connected to a plurality of source lines; a voltage generator configured to generate a reference voltage; as well as a source driver configured to output a first source signal corresponding to a first source line among the plurality of source lines, receive a first return signal corresponding to the first source signal through a first return line among a plurality of return lines connected to a corresponding source line among the plurality of source lines, and generate a first count value based on a first comparison result of the first return signal and a reference voltage, Wherein, the source driver is connected to the plurality of source lines and the plurality of return lines.

18. The display device according to claim 17, wherein: The source driver includes: a first channel amplifier connected to the first source line and configured to output a first source signal; a first comparator connected to the plurality of source lines and the plurality of return lines, wherein the first comparator is configured to receive a reference voltage and a first return signal and output a first comparison result; a selector connected to the first source line and the first return line, wherein the selector is configured to send a first return signal to the first comparator; and The first counter is configured to generate a first count value based on the first comparison result.

19. The display device according to claim 18, wherein: The selectors are: a first switch configured to connect a first input terminal of the first comparator to a first return line or a first source line; a second switch configured to connect the first input terminal of the first comparator to a voltage line configured to provide a reference voltage; and The third switch is configured to connect the output terminal of the first channel amplifier and the first source line.

20. The display device according to claim 19, wherein: When the first switch connects the first input terminal of the first comparator to the first return line, The second switch is open, and When the third switch is turned on, The first channel amplifier is configured to output a first comparison result.

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