Display panel, display device and display method

Abstract

The invention provides a display panel, a display device and a display method, and relates to the technical field of display. The display panel comprises a pixel array which comprises a plurality of sub-pixel units, and each sub-pixel unit is electrically connected with a scanning line and a data line; a control circuit electrically connected to the plurality of control lines, the plurality of transmission lines, and the plurality of data lines, the control circuit being configured to conduct the plurality of transmission lines with the plurality of data lines, respectively, based on a control signal applied to the plurality of control lines; and a transmission circuit electrically connected to the plurality of transmission lines, the transmission circuit configured to apply a plurality of data signals to a plurality of sub-pixel units for displaying one color via the plurality of transmission lines and the plurality of data lines based on scanning signals applied to the scanning lines.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a display panel, a display device and a display method. Background Art

[0002] Display panels based on organic electroluminescence display (OLED) are widely used in mobile phones, household appliances and other fields.

[0003] In an OLED display panel, the driver chip can charge multiple columns of pixels in the display panel through a transmission line in the same row scanning period through a multiplexer, thereby reducing the number of transmission lines required to be laid out in the driver circuit. This can reduce the cost of the driver circuit while reducing the area of ​​the non-display area on the display panel and increasing the display area of ​​the display panel. Summary of the invention

[0004] The present disclosure provides a display panel, a display device and a display method.

[0005] According to one aspect of the present disclosure, a display panel is provided, including a display area and a peripheral area located on one side of the display area, the display panel including: a pixel array located in the display area, including a plurality of sub-pixel units, each sub-pixel unit being electrically connected to a scan line and a data line; a control circuit located in the peripheral area, electrically connected to a plurality of control lines, a plurality of transmission lines and a plurality of data lines, the control circuit being configured to respectively conduct the plurality of transmission lines with the plurality of data lines based on control signals applied to the plurality of control lines; a transmission circuit located in the peripheral area and located on a side away from the display area relative to the control circuit, electrically connected to the plurality of transmission lines, the transmission circuit being configured to apply a plurality of data signals to a plurality of sub-pixel units for displaying a color via the plurality of transmission lines and the plurality of data lines based on scan signals applied to the scan lines.

[0006] According to another aspect of the present disclosure, a display device is provided, including: the above-mentioned display panel.

[0007] According to another aspect of the present disclosure, the present disclosure provides a display method, including: based on a control signal applied to a plurality of control lines, controlling a transmission line to be connected to a plurality of data lines in sequence, so as to apply a plurality of data signals applied on the transmission line to the plurality of data lines respectively; and based on a scan signal applied to a scan line, applying the data signals applied respectively on the plurality of data lines to a plurality of sub-pixel units for displaying a color. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0009] Figure 1 A schematic diagram of the structure of an exemplary pixel circuit is shown schematically.

[0010] Figure 2A A schematic structural diagram of a display panel of a first example is shown schematically.

[0011] Figure 2B A signal timing diagram of a display panel of the first example is schematically shown.

[0012] Figure 3A A schematic structural diagram of a display panel of a second example is shown schematically.

[0013] Figure 3B A signal timing diagram of a display panel of the second example is schematically shown.

[0014] Figure 4 A schematic diagram of a display panel according to an embodiment of the present disclosure is schematically shown.

[0015] Figure 5A A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0016] Figure 5B A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0017] Figure 5C A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0018] Figure 5D A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0019] Figure 5E A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0020] Fig. 5F A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0021] Fig. 6A A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0022] Figure 6B A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0023] Figure 6CA signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0024] Fig.6D A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0025] Fig. 6E A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0026] Fig. 7A A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0027] Figure 7B A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0028] Figure 7C A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0029] Fig.7D A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0030] Fig. 7E A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0031] Figure 8 The structural diagram of a display device according to an embodiment of the present disclosure is schematically shown.

[0032] Fig. 9 A schematic flow chart of a display method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present disclosure. In the following description, some specific embodiments are only used for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or constructions will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0034] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by those skilled in the art. The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0035] In addition, in the description of the embodiments of the present disclosure, the term "connected to" or "connected" may refer to two components being directly connected, or may refer to two components being connected via one or more other components, and the connection method is electrical connection or electrical coupling. In addition, the two components may also be connected or coupled by wire or wirelessly.

[0036] The source and drain of the switch transistor used in the embodiment of the present disclosure are symmetrical, so the source and drain can be interchanged. In the embodiment of the present disclosure, according to its function, one of the source and drain is called the first electrode, and the other of the source and drain is called the second electrode.

[0037] It should be noted that in the description of the embodiments of the present disclosure, the symbols G1, ..., GP can represent both scan lines and scan signals provided by the scan lines. Similarly, the symbols DT1, ..., DTM can represent both data lines and data signals provided by the data lines. The following embodiments are the same and will not be described in detail.

[0038] Figure 1 A schematic diagram of the structure of an exemplary pixel circuit is shown schematically.

[0039] like Figure 1 As shown, the pixel circuit 100 in this example may be a 7T1C low temperature polysilicon (LTPS) pixel circuit. The pixel circuit 100 may include transistors M1 to M7. Among them, transistor M1, transistor M2, transistor M4, transistor M5, transistor M6 and transistor M7 are switch transistors. Transistor M3 is a driving transistor. In this example, the switch transistor and the driving transistor are P-type transistors.

[0040] In the pixel circuit 100, in the first stage, the enable signal EM is at a high level, thereby controlling the transistors M5 and M6 to be turned off, and the low-level reset signal RST1 is applied to the gate of the transistor M1 to turn on the transistor M1, so that the initialization signal Vinit1 can be written to the node Q1, thereby resetting the capacitor Cst and the gate of the driving transistor M3. After the reset, the driving transistor M3 is turned on.

[0041] In the second stage, the reset signal RST1 is at a high level, so that the transistor M1 is turned off. The low-level scan signals Gate1 and Gate2 are applied to the gates of the transistors M2 and M4, respectively, so that the transistors M2 and M4 are turned on. As a result, the data signal Vdata can flow through the transistor M4, the driving transistor M3 and the transistor M2, and is written into the Q1 node, thereby charging the capacitor Cst and increasing the gate-source voltage Vgs of the driving transistor M3 at the same time. When the gate-source voltage Vgs of the driving transistor M3 = V(Q1)-V(Q2) = V(Q1)-Vdata = Vth, the driving transistor M3 is turned off. Among them, V(Q1) represents the voltage of the node Q1; V(Q2) represents the voltage of the node Q2; Vth represents the threshold voltage of the driving transistor M3. At this time, V(N1) = Vdata + Vth, thereby completing the change of the gate-source voltage Vgs of the driving transistor M3, thereby achieving the adjustment of the brightness of the light-emitting element EL. At the same time, a low-level reset signal RST2 is applied to the gate of the transistor M2 to turn on the transistor M2, so that the initialization signal Vinit2 can be written into the node Q4, thereby resetting the anode of the light emitting element EL.

[0042] After that, the scanning signal Gate1, the scanning signal Gate2 and the reset signal RST2 are at a high level, and the enable signal EM is at a low level, so that the transistors M5 and M6 are turned on, so that the power supply voltage VDD charges the light-emitting element EL, so as to make the light-emitting element EL emit light. Based on this, the working process of the pixel circuit 100 has been described. It should be understood that the pixel circuit 100 can be used to form the sub-pixel unit in each of the following display substrates.

[0043] Figure 2A A schematic structural diagram of a display panel of a first example is shown schematically. Figure 2B A signal timing diagram of a display panel of the first example is schematically shown.

[0044] exist Figure 2A In the example of , the display panel 200 includes a display area 2AA and a peripheral area 2BB located on one side of the display area 2AA. The display panel 200 includes a pixel array 210, a control circuit 220, and a transmission circuit 230. The pixel array 210 is located in the display area 2AA, the control circuit 220 and the transmission circuit 230 are located in the peripheral area 2BB, and the transmission circuit 230 is located on a side away from the display area 2AA relative to the control circuit 220.

[0045] In this example, the pixel array 210 includes 4 rows and 4 columns of sub-pixel units arranged in an array. The 1st to 4th column sub-pixel units are electrically connected to the data lines DT1 to DT4, respectively. The 1st to 4th row sub-pixel units are electrically connected to the scan lines G1 to G4, respectively. It should be noted that in the drawings of the present disclosure, white, black and gray refer to three different colors, respectively. The three different colors may refer to the three primary colors, such as white refers to red, black refers to blue, and gray refers to green. Further, refer to Figure 2A In each display panel shown in the drawings of the present disclosure, a box filled with white, black or gray represents a sub-pixel unit for emitting light in the display panel, and different grayscales filled in the box represent the color of the light emitted by the sub-pixel unit. For example, each sub-pixel unit (sub-pixel) includes a light-emitting element. The light-emitting element is an organic light-emitting semiconductor (Organic Electroluminescence Display, OLED).

[0046] The control circuit 220 includes a multiplexer (MUX1:2), which in this example includes transistors Ta1 to Ta4. Transistors Ta1 to Ta4 are P-type transistors. The gates of transistors Ta1 and Ta3 are electrically connected to a first control line C1. The gates of transistors Ta2 and Ta4 are electrically connected to a second control line C2. The first electrodes of transistors Ta1 to Ta4 are electrically connected to data lines DT1 to DT4, respectively. The second electrodes of transistors Ta1 and Ta2 are electrically connected to a transmission line FT1. The second electrodes of transistors Ta3 and Ta4 are electrically connected to a transmission line FT2.

[0047] Based on the above Figure 2A The connection relationship of each device in the display panel 200 is as follows: Figure 2B The signal timing diagram shown is for Figure 2A It should be further explained by the example in . It should be noted that in the signal timing diagram schematically shown in the present disclosure, a certain grayscale graphic represents a data signal provided to the sub-pixel unit represented by the grayscale. For example, a white graphic represents a data signal provided to the sub-pixel unit represented by white. The black graphic and the gray graphic are similar, and are not described in detail here.

[0048] refer to Figure 2BTaking the transmission line FT1 as an example, in the first row scanning period, the control signal C1 of the first control line C1 is first at a low level, and the control signal C2 of the second control line C2 is first at a high level, so that the transistor Ta1 conducts between the data line DT1 and the transmission line FT1, so that the transmission line FT1 applies the data signal from the transmission circuit 230 to the data line DT1 via the transistor Ta1. The sub-pixel unit is charged via the data line DT1 using the data signal from the transmission line FT1. At the same time, the transistor Ta2 is in the off state, so that the data signal on the transmission line FT1 will not be applied to the data line DT2.

[0049] Afterwards, the control signal C1 of the first control line C1 changes to a high level, the control signal C2 of the second control line C2 changes to a low level, the transistor Ta1 is turned off, and the transistor Ta2 conducts between the data line DT2 and the transmission line FT1, so that the transmission line FT1 applies the data signal from the transmission circuit 230 to the data line DT2. The sub-pixel unit is charged via the data line DT2 using the data signal from the transmission line FT1.

[0050] Afterwards, the scanning signal G1 on the scanning line G1 is at an effective level, so that the data signal of the data line DT1 is applied to the light-emitting element of the sub-pixel unit in the first row and the first column, thereby driving the light-emitting element of the sub-pixel unit in the first row and the first column to emit light. At the same time, the data signal of the data line DT2 is applied to the light-emitting element of the sub-pixel unit in the first row and the second column, thereby driving the light-emitting element of the sub-pixel unit in the first row and the second column to emit light. The principle of receiving data signals and scanning signals by other sub-pixel units of the pixel array 210 is similar to the above process, which will not be described in detail here. In addition, the operations performed in other row scanning periods are similar to the operations performed in the above-mentioned first row scanning period, which will not be described in detail here.

[0051] As another example, Figure 3A A schematic structural diagram of a display panel of a second example is shown schematically. Figure 3B A signal timing diagram of a display panel of the second example is schematically shown.

[0052] exist Figure 3A In the example of , the display panel 300 includes a display area 3AA and a peripheral area 3BB located on one side of the display area 3AA. The display panel 300 includes a pixel array 310, a control circuit 320, and a transmission circuit 330. The pixel array 310 is located in the display area 3AA, the control circuit 320 and the transmission circuit 330 are located in the peripheral area 3BB, and the transmission circuit 330 is located on a side away from the display area 3AA relative to the control circuit 320.

[0053] In this example, the pixel array 310 includes 4 rows and 4 columns of sub-pixel units arranged in an array. The 1st to 4th columns of sub-pixel units are electrically connected to data lines DT1 to DT4, respectively. The 1st to 4th rows of sub-pixel units are electrically connected to scan lines G1 to G4, respectively.

[0054] The control circuit 320 includes a multiplexer (MUX1:2), and the multiplexer includes transistors Ta5 to Ta8. Transistors Ta5 to Ta8 are P-type transistors. The gates of transistors Ta5 and Ta6 are electrically connected to the first control line C1. The gates of transistors Ta7 and Ta8 are electrically connected to the second control line C2. The first electrodes of transistors Ta5 to Ta6 are electrically connected to the sub-pixel units in the first to fourth columns, respectively. The second electrodes of transistors Ta5 and Ta7 are electrically connected to the transmission line FT1. The second electrodes of transistors Ta6 and Ta8 are electrically connected to the transmission line FT2.

[0055] Based on the above Figure 3A The connection relationship of each device in the display panel 300 is as follows: Figure 3B The signal timing diagram shown is for Figure 3A The examples in this section further illustrate this.

[0056] refer to Figure 3B Taking the transmission lines FT1 and FT2 as an example, in the first row scanning period, the control signal C1 of the first control line C1 is first at a low level, and the control signal C2 of the second control line C2 is first at a high level, so that the transistors Ta7 and Ta8 are in the cut-off state, and the transistor Ta5 conducts between the data line DT1 and the transmission line FT1, so that the transmission line FT1 applies the data signal from the transmission circuit 330 to the data line DT1 via the transistor Ta5. The sub-pixel unit is charged via the data line DT1 using the data signal from the transmission line FT1. The transistor Ta6 conducts between the data line DT2 and the transmission line FT2, so that the transmission line FT2 applies the data signal from the transmission circuit 330 to the data line DT2 via the transistor Ta6. The sub-pixel unit is charged via the data line DT2 using the data signal from the transmission line FT2.

[0057] Afterwards, the control signal C1 of the first control line C1 is changed to a high level, and the control signal C2 of the second control line C2 is changed to a low level, whereby the transistors Ta5 and Ta6 are turned off, and the transistor Ta7 conducts between the data line DT3 and the transmission line FT1, so that the transmission line FT1 applies the data signal from the transmission circuit 330 to the data line DT3. The sub-pixel unit is charged via the data line DT3 using the data signal from the transmission line FT1. Furthermore, the transistor Ta8 conducts between the data line DT4 and the transmission line FT2, so that the transmission line FT2 applies the data signal from the transmission circuit 330 to the data line DT4. The sub-pixel unit is charged via the data line DT4 using the data signal from the transmission line FT2.

[0058] After that, the scanning signal G1 on the scanning line G1 is at an effective level, so that the data signals of the data lines DT1 to DT4 are applied to the light-emitting elements of the sub-pixel units of the 1st row, the 1st column to the 4th column, so as to drive the light-emitting elements of the sub-pixel units of the 1st row, the 1st column to the 4th column to emit light. The principle of receiving data signals and scanning signals by other sub-pixel units of the pixel array 310 is similar to the above process, and will not be described in detail here. In addition, the operations performed in other row scanning periods are the same as the operations performed in the above first row scanning period, and will not be described in detail here.

[0059] For the above example, taking the transmission line FT1 as an example, in one row scanning period, the transmission line FT1 is successively connected to the data line DT1 and the data line DT3. Since the sub-pixel unit connected to the data line DT1 is used to display a different color from the sub-pixel unit connected to the data line DT2, even if the two sub-pixel units are required to emit light of the same gray scale, there may be a large difference between the potentials of the two data signals used to drive the two sub-pixel units to emit light. That is, in one row scanning period, the potential difference between the potential of the data signal applied to the data line DT1 via the transmission line FT1 and the potential of the data signal applied to the data line DT3 via the transmission line FT1 may be large, and the transmission circuit 330 needs to perform a potential switching with a large potential difference, thereby increasing the time and power consumption consumed by the potential switching operation, which will cause the transmission circuit 330 to reduce the charging time of the sub-pixel unit connected to the data line DT3, which may cause the sub-pixel unit to be insufficiently charged, resulting in poor low grayscale image quality and high power consumption of the display panel 300.

[0060] In view of this, an embodiment of the present disclosure provides a display panel, comprising: a pixel array, comprising a plurality of sub-pixel units, each sub-pixel unit being electrically connected to a scan line and a data line; a control circuit, electrically connected to the plurality of control lines, the plurality of transmission lines and the plurality of data lines, the control circuit being configured to respectively connect the plurality of transmission lines to the plurality of data lines based on control signals applied to the plurality of control lines; a driving circuit, electrically connected to the plurality of transmission lines, the driving circuit being configured to apply a plurality of data signals to the plurality of sub-pixel units for displaying a color via the plurality of transmission lines and the plurality of data lines based on scan signals applied to the scan lines.

[0061] Figure 4 A schematic diagram of a display panel according to an embodiment of the present disclosure is schematically shown.

[0062] exist Figure 4 In the embodiment of the present disclosure, the display panel 400 may be an active matrix organic light emitting diode (AMOLED) panel. The display panel 400 includes a display area 4AA and a peripheral area 4BB located on one side of the display area 4AA. In the embodiment of the present disclosure, the display panel 400 includes a pixel array 410, a control circuit 420, and a transmission circuit 430. For example, the pixel array 410 is located in the display area 4AA, the control circuit 420 and the transmission circuit 430 are located in the peripheral area 4BB, and the transmission circuit 430 is located on a side away from the display area 4AA relative to the control circuit 420.

[0063] In the disclosed embodiment, the pixel array 410 includes a plurality of sub-pixel units. Each sub-pixel unit is electrically connected to a scan line and a data line. Thus, based on a scan signal and a data signal applied to the sub-pixel unit through the scan line and the data line, the light-emitting element in the sub-pixel unit can be driven to emit light.

[0064] In the embodiment of the present disclosure, the control circuit 420 is electrically connected to a plurality of control lines C1, ..., CR, a plurality of transmission lines FT1, ..., FTd, ..., FTD, and a plurality of data lines DT1, ..., DTm, ..., DTM, where P is a positive integer greater than 1, p is a positive integer less than P, M is a positive integer greater than 1, m is a positive integer less than M, D is a positive integer greater than 1, and d is a positive integer less than D. The control circuit 420 is configured to connect the plurality of transmission lines FT1, ..., FTd, ..., FTD to the plurality of data lines DT1, ..., DTm, ..., DTM, respectively, based on control signals applied to the plurality of control lines C1, ..., CR, thereby applying data signals on the plurality of transmission lines FT1, ..., FTd, ..., FTD to the data lines DT1, ..., DTm, ..., DTM. For example, the control circuit 420 may include a multiplexer. When the control signal of the control line is applied to the multiplexer, the multiplexer can control the conduction status between the transmission line and the data line based on the control signal.

[0065] In the embodiment of the present disclosure, the transmission circuit 430 may be a display driver integrated circuit (DDIC). For example, the transmission circuit 430 may apply multiple data signals to multiple sub-pixel units for displaying one color via multiple transmission lines FT1, ..., FTd, ..., FTD and multiple data lines DT1, ..., DTm, ..., DTM based on the scan signal applied to the scan line. However, the embodiment of the present disclosure is not limited thereto, and the transmission circuit 430 may also be a touch and display driver integrated circuit (TDDIC), whereby the transmission circuit 430 may transmit data signals to the pixel array 410 based on the touch signal of the touch instruction.

[0066] In the disclosed embodiment, the control circuit can conduct multiple transmission lines and multiple data lines based on the control signal applied to the control line. Thus, when the scan signal on the scan line is at an effective level, the transmission circuit can apply the data signal to the light-emitting elements of multiple sub-pixel units in the pixel array for displaying a color through the transmission line and the data line, so as to drive the light-emitting elements in the sub-pixel units to emit light. In the process of applying the data signal through the transmission line, the transmission circuit does not need to switch the potential of the data signal for the sub-pixel units for displaying different colors on the same transmission line, thereby reducing the power consumption of the transmission circuit and reducing the time consumed by the transmission circuit switching the potential of the data signal, so that the charging time of the data line is increased, so that the sub-pixel unit can be more fully charged, and the low grayscale image quality can be improved.

[0067] In the disclosed embodiment, the pixel array includes a plurality of first sub-pixel unit columns and a plurality of second sub-pixel unit columns, the first sub-pixel unit columns and the second sub-pixel unit columns are arranged alternately, the sub-pixel units in the first sub-pixel unit columns are used to display a first color and a second color, and the sub-pixel units used to display the first color and the sub-pixel units used to display the second color are arranged alternately. The sub-pixel units in the second sub-pixel unit columns are used to display a third color. For example, the first color may be one of red and blue, the second color may be the other of red and blue, and the third color may be green. It should be noted that, in the disclosed embodiment, the sub-pixel units arranged along the first direction may be referred to as a column of sub-pixel units, and the sub-pixel units arranged along the second direction intersecting with the first direction may be referred to as a row of sub-pixel units. The first direction and the second direction may intersect with each other, for example, the angle difference between the first direction and the second direction may be 90°.

[0068] In an embodiment of the present disclosure, the control circuit may include a plurality of transistors, the gate of each transistor being electrically connected to a control line, the first electrode of the transistor being electrically connected to a data line, and the second electrode of the transistor being electrically connected to a transmission line. The control line may apply a control signal to the gates of the plurality of transistors, thereby controlling the conduction or cutoff of the plurality of transistors. When the control line controls the transistor to be turned on, the transistor may conduct between the data line connected to the first electrode of the transistor and the transmission line connected to the second electrode of the transistor; when the control line controls the transistor to be cut off, the data signal on the transmission line connected to the second electrode of the transistor may be prevented from being applied to the data line connected to the first electrode of the transistor.

[0069] In order to better understand the solution of the present disclosure, the following provides various connection embodiments, and combined with Figures 5A to 5F , Figures 6A to 6E , Figures 7A to 7E To elaborate.

[0070] As an optional implementation, the optional first connection mode may be to change the connection mode between the scan line and the sub-pixel unit, so as to realize that one transmission line only charges the sub-pixel unit for displaying the same color in each row scanning period.

[0071] According to an embodiment of the present disclosure, each data line is electrically connected to a plurality of sub-pixel units included in a sub-pixel unit column of a pixel array. Each scan line is electrically connected to two consecutive sub-pixel units among a plurality of sub-pixel units included in a plurality of sub-pixel unit rows of a pixel array. Each transmission line is electrically connected to an mth data line and an m+2jth data line through a control circuit, where m is a positive integer and j is a positive integer.

[0072] Optionally, the p-th scan line is electrically connected to the sub-pixel unit of the p-th row, 1+4k column, the sub-pixel unit of the p-th row, 2+4k column, the sub-pixel unit of the p+1-th row, 3+4k column, and the sub-pixel unit of the p+1-th row, 4+4k column in the pixel array, and the p+1-th scan line is electrically connected to the sub-pixel unit of the p+1-th row, 1+4k column, the sub-pixel unit of the p+1-th row, 2+4k column, the sub-pixel unit of the p-th row, 3+4k column, and the sub-pixel unit of the p-th row, 4+4k column in the pixel array, wherein p is a positive odd number, k=0,1,2,…. The plurality of control lines include a first control line and a second control line. The control circuit includes a first transistor and a second transistor. The first transistor is electrically connected to the transmission line, the m-th data line, and the first control line, and the second transistor is electrically connected to the transmission line, the m+2j-th data line, and the second control line. The following takes the case where p=1 or 3, k=0 or 1, m=1, 2, 5 or 6, and j=1 as an example. Figure 5A and Figure 5B The first connection method is described in detail.

[0073] Figure 5A A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown. Figure 5B A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0074] exist Figure 5A In the embodiment of the present disclosure, the display panel 5100 includes a display area 51AA and a peripheral area 51BB located on one side of the display area 51AA. In the embodiment of the present disclosure, the display panel 5100 includes a pixel array 5110, a control circuit 5120, and a transmission circuit 5130. For example, the pixel array 5100 is located in the display area 51AA, the control circuit 5120 and the transmission circuit 5130 are located in the peripheral area 51BB, and the transmission circuit 5130 is located on a side away from the display area 51AA relative to the control circuit 5120.

[0075] The pixel array 5110 includes 4 rows and 8 columns of sub-pixel units arranged in an array. The scan line G1 can be connected to the sub-pixel units of the 1st row, the 1st column and the 2nd column, the sub-pixel units of the 3rd row and the 4th column, the sub-pixel units of the 1st row, the 5th column and the 6th column, and the sub-pixel units of the 2nd row, the 7th column and the 8th column. The scan line G2 can be connected to the sub-pixel units of the 1st row and the 2nd column, the sub-pixel units of the 1st row, the 3rd column and the 4th column, the sub-pixel units of the 2nd row, the 5th column and the 6th column, and the sub-pixel units of the 1st row, the 7th column and the 8th column. The scan line G3 can be connected to the sub-pixel units of the 1st row and the 2nd column, the sub-pixel units of the 3rd row and the 4th column, the sub-pixel units of the 3rd row and the 4th column, the sub-pixel units of the 5th row and the 6th column, and the sub-pixel units of the 4th row, the 7th column and the 8th column. The scan line G4 can be connected to the sub-pixel units in the 1st and 2nd columns of the 4th row, the sub-pixel units in the 3rd and 4th columns of the 3rd row, the sub-pixel units in the 5th and 6th columns of the 4th row, and the sub-pixel units in the 7th and 8th columns of the 3rd row. Based on this connection mode, the scan line can connect two consecutive sub-pixel units in an odd row and two consecutive sub-pixel units in an even row adjacent to the odd row, so as to apply scan signals to the sub-pixel units in two rows at the same time.

[0076] The control circuit 5120 includes a plurality of first transistors T1 and a plurality of second transistors T2. For example, the gates of the plurality of first transistors T1 are electrically connected to the control line C1, the first electrodes of the plurality of first transistors T1 are electrically connected to the data lines DT1, DT2, DT5 and DT6, respectively, and the second stages of the plurality of first transistors are electrically connected to the transmission lines FT1, FT2, FT3 and FT4, respectively. The gates of the plurality of second transistors T2 are electrically connected to the control line C2, the first electrodes of the plurality of second transistors T2 are electrically connected to the data lines DT3, DT4, DT7 and DT8, respectively, and the second stages of the plurality of second transistors are electrically connected to the transmission lines FT1, FT2, FT3 and FT4, respectively. Exemplarily, the plurality of first transistors T1 and the plurality of second transistors T2 are P-type transistors, which is not limited in the present disclosure.

[0077] The following combination Figure 5B The signal timing diagram shown is for Figure 5A The examples in this section further illustrate this. Figure 5BIn the first row scanning period, the control signal C1 of the first control line C1 is first at a low level, and the control signal C2 of the second control line C2 is first at a high level, thereby the plurality of second transistors T2 are turned off, and the plurality of first transistors T1 conduct the data lines DT1, DT2, DT5 and DT6 with the transmission lines FT1, FT2, FT3 and FT4, respectively, so that the transmission lines FT1 to FT4 apply the data signals from the transmission circuit 5130 to the data lines DT1, DT2, DT6 and DT5, respectively. The data lines DT1, DT2, DT6 and DT5 charge the sub-pixel units respectively using the data signals from the transmission lines FT1 to FT4.

[0078] Afterwards, the control signal C1 of the first control line C1 is changed to a high level, and the control signal C2 of the second control line C2 is changed to a low level, thereby the plurality of first transistors T1 are turned off, and the plurality of second transistors T2 conduct the data lines DT3, DT4, DT7 and DT8 to the transmission lines FT1, FT2, FT3 and FT4, respectively. Thus, the transmission lines FT1 to FT4 apply the data signals from the transmission circuit 5130 to the data lines DT3, DT4, DT7 and DT8, respectively. The data lines DT3, DT4, DT7 and DT8 charge the sub-pixel units using the data signals from the transmission lines FT1 to FT4, respectively. It can be seen that before and after the control signal C1 of the first control line C1 and the control signal C2 of the second control line C2 are switched, the transmission lines FT1 to FT4 always apply the data signals to the data lines connected to the sub-pixel units of the same color.

[0079] Afterwards, the scanning signal G1 applied by the scanning line G1 to the sub-pixel units of the 1st row, 1st column and 2nd column, the sub-pixel units of the 2nd row, 3rd column and 4th column, the sub-pixel units of the 1st row, 5th column and 6th column, and the sub-pixel units of the 2nd row, 7th column and 8th column is at an effective level, so that the data signals of the data lines DT1 to DT8 are applied to the light-emitting elements of the above-mentioned sub-pixel units, so as to drive the above-mentioned sub-pixel units to emit light. The principle of receiving data signals and scanning signals by other sub-pixel units of the pixel array 5110 is similar to the above process, which will not be described in detail here. In addition, the operations performed in other row scanning periods are similar to the operations performed in the above-mentioned first row scanning period, which will not be described in detail here.

[0080] Continue to refer Figure 5BIn the embodiment of the present disclosure, the i-th scanning signal applied to the i-th scanning line is at an invalid level in the first sub-period S1 of the i-th row scanning period, and is at an effective level in the second sub-period S2 of the i-th row scanning period. The scanning signals applied to the plurality of scanning lines except the i-th scanning signal are all at an invalid level in the i-th row scanning period, where i is a positive integer. On this basis, in the embodiment of the present disclosure, the effective level of the scanning signal in each row scanning period can be adjusted so that the sub-pixel unit can be charged more fully.

[0081] Figure 5C A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0082] like Figure 5C As shown, the second sub-period S2 can be widened and the first sub-period S1 can be shortened, so that in one row scanning period, the width of the effective level is wider than the width of the invalid level. For example, in one row scanning period, all can be effective levels. By making the width of the effective level wider than the width of the invalid level in one row scanning period, the charging time of the light-emitting element of the sub-pixel unit can be increased, thereby improving the low grayscale image quality.

[0083] The first connection method disclosed in the present invention is not limited to the above connection method. The first connection method can also be, for example: the p-th scan line is electrically connected to the sub-pixel unit of the p-th row and 1+4k column, the sub-pixel unit of the p+1-th row and 2+4k column, the sub-pixel unit of the p+1-th row and 3+4k column, and the sub-pixel unit of the p-th row and 4+4k column in the pixel array, and the p+1-th scan line is electrically connected to the sub-pixel unit of the p+1-th row and 1+4k column, the sub-pixel unit of the p-th row and 2+4k column, the sub-pixel unit of the p-th row and 3+4k column, and the sub-pixel unit of the p+1-th row and 4+4k column in the pixel array, wherein p is a positive odd number, and k=0,1,2,…. The following takes the case where p=1 or 3, k=0 or 1, m=1, 2, 5 and 6, and j=1 as an example. Figure 5D The above connection method is shown as an example.

[0084] Figure 5D A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0085] exist Figure 5DIn the embodiment of the present disclosure, the display panel 5200 includes a display area 52AA and a peripheral area 52BB located on one side of the display area 52AA. In the embodiment of the present disclosure, the display panel 5200 includes a pixel array 5210, a control circuit 5220, and a transmission circuit 5230. For example, the pixel array 5210 is located in the display area 52AA, the control circuit 5220 and the transmission circuit 5230 are located in the peripheral area 52BB, and the transmission circuit 5230 is located on a side away from the display area 52AA relative to the control circuit 5220.

[0086] The pixel array 5210 includes 4 rows and 8 columns of sub-pixel units arranged in an array. The scan line G1 can be connected to the sub-pixel unit in the 1st row and the 1st column, the sub-pixel unit in the 2nd row and the 3rd column, the sub-pixel unit in the 1st row, the sub-pixel unit in the 4th column and the 5th column, the sub-pixel unit in the 2nd row, the 6th column and the 7th column, and the sub-pixel unit in the 1st row and the 8th column. The scan line G2 can be connected to the sub-pixel unit in the 2nd row and the 1st column, the sub-pixel unit in the 1st row, the sub-pixel unit in the 2nd column and the 3rd column, the sub-pixel unit in the 2nd row, the 4th column and the 5th column, the sub-pixel unit in the 1st row, the sub-pixel unit in the 6th column and the 7th column, and the sub-pixel unit in the 2nd row and the 8th column. The scan line G3 can be connected to the sub-pixel unit in the 3rd row and the 1st column, the sub-pixel unit in the 4th row and the 2nd and 3rd columns, the sub-pixel unit in the 3rd row and the 5th column, the sub-pixel unit in the 4th row and the 6th and 7th columns, and the sub-pixel unit in the 3rd row and the 8th column. The scan line G4 can be connected to the sub-pixel unit in the 4th row and the 1st column, the sub-pixel unit in the 3rd row and the 2nd and 3rd columns, the sub-pixel unit in the 4th row and the 4th and the 5th columns, the sub-pixel unit in the 3rd row and the 6th and 7th columns, and the sub-pixel unit in the 4th row and the 8th column. Through this connection mode, the scan line can also connect two consecutive sub-pixel units in an odd row and two consecutive sub-pixel units in an even row adjacent to the odd row, so as to apply scan signals to the sub-pixel units in multiple rows at the same time.

[0087] The first connection method disclosed in the present invention is not limited to the above connection method. The display panel of the embodiment of the present invention can also be connected as follows Figure 5E to connect.

[0088] Figure 5E A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0089] exist Figure 5EIn the embodiment of the present disclosure, the display panel 5300 includes a display area 53AA and a peripheral area 53BB located on one side of the display area 53AA. In the embodiment of the present disclosure, the display panel 5300 includes a pixel array 5310, a control circuit 5320, and a transmission circuit 5330. For example, the pixel array 5310 is located in the display area 53AA, the control circuit 5320 and the transmission circuit 5330 are located in the peripheral area 53BB, and the transmission circuit 5330 is located on a side away from the display area 53AA relative to the control circuit 5320.

[0090] The pixel array 5310 includes 4 rows and 8 columns of sub-pixel units arranged in an array. The scan line G1 can be connected to the sub-pixel units of the 1st row, the 1st column and the 2nd column, the sub-pixel units of the 2nd row, the 3rd column and the 4th column, the sub-pixel units of the 3rd row, the 5th column and the 6th column, and the sub-pixel units of the 4th row, the 7th column and the 8th column. The scan line G2 can be connected to the sub-pixel units of the 2nd row, the 1st column and the 2nd column, the sub-pixel units of the 3rd row, the 3rd column and the 4th column, the sub-pixel units of the 4th row, the 5th column and the 6th column, and the sub-pixel units of the 1st row, the 7th column and the 8th column. The scan line G3 can be connected to the sub-pixel units of the 3rd row, the 1st column and the 2nd column, the sub-pixel units of the 4th row, the 3rd column and the 4th column, the sub-pixel units of the 1st row, the 5th column and the 6th column, and the sub-pixel units of the 2nd row, the 7th column and the 8th column. Scan line G4 can be connected to the sub-pixel units of the 4th row, 1st column and 2nd column, the sub-pixel units of the 1st row, 3rd column and 4th column, the sub-pixel units of the 2nd row, 5th column and 6th column, and the sub-pixel units of the 3rd row, 7th column and 8th column.

[0091] pass Figure 5E In the connection mode, one scan line can connect the sub-pixel units for displaying the same color in four adjacent rows.

[0092] The first connection method disclosed in the present invention is not limited to the above connection method. The display panel of the embodiment of the present invention can also be connected as follows Fig. 5F to connect.

[0093] Fig. 5F A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0094] exist Fig. 5F In the embodiment of the present disclosure, the display panel 5400 includes a display area 54AA and a peripheral area 54BB located on one side of the display area 54AA. In the embodiment of the present disclosure, the display panel 5400 includes a pixel array 5410, a control circuit 5420, and a transmission circuit 5430. For example, the pixel array 5410 is located in the display area 54AA, the control circuit 5420 and the transmission circuit 5430 are located in the peripheral area 54BB, and the transmission circuit 5430 is located on a side away from the display area 54AA relative to the control circuit 5420.

[0095] The pixel array 5410 includes a plurality of sub-pixel units arranged in an array. In the display panel 5400, the first scan line G1 is electrically connected to the sub-pixel units in the first row and first column, the sub-pixel units in the first row and second column, the sub-pixel units in the second row and third column, the sub-pixel units in the second row and fourth column, the sub-pixel units in the third row and fifth column, the sub-pixel units in the third row and sixth column, the sub-pixel units in the fourth row and seventh column, and the sub-pixel units in the fourth row and eighth column in the pixel array, and the connection methods of other scan lines and sub-pixel units are similar and will not be described in detail here. Fig. 5F The embodiment in which the scan lines connect adjacent rows of sub-pixel units is also shown. Figure 5E The difference of the embodiment is that Fig. 5F In the embodiment of the present disclosure, the scan lines are sequentially connected downwardly to the sub-pixel units of multiple rows. However, the embodiments of the present disclosure are not limited thereto. In another embodiment of the present disclosure, the scan lines may be sequentially connected upwardly to the sub-pixel units of multiple rows, and the connection method is the same as Fig. 5F The embodiments are similar to those in the embodiment and will not be described in detail here.

[0096] As an optional implementation, the optional second connection mode may be to change the connection mode between the data line and the transmission line, so as to realize that one transmission line only charges the sub-pixel units for displaying the same color in each row scanning period.

[0097] According to an embodiment of the present disclosure, each data line is electrically connected to a plurality of sub-pixel units included in a sub-pixel unit column of a pixel array. Each scan line is electrically connected to a plurality of sub-pixel units included in a sub-pixel unit row of a pixel array. Each transmission line is electrically connected to the mth data line and the m+4jth data line through a control circuit, respectively, where m is a positive integer and j is a positive integer. For example, the plurality of control lines include a first control line and a second control line. The control circuit includes a third transistor and a fourth transistor. The third transistor is electrically connected to the transmission line, the mth data line and the first control line, and the fourth transistor is electrically connected to the transmission line, the m+4jth data line and the second control line. The following takes the case where m=1, 2, 3 or 4, j=1 as an example, combined with Fig. 6A and Figure 6B Provide specific instructions.

[0098] Fig. 6A A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown. Figure 6B A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0099] exist Fig. 6AIn the embodiment of the present disclosure, the display panel 6100 includes a display area 61AA and a peripheral area 61BB located on one side of the display area 61AA. In the embodiment of the present disclosure, the display panel 6100 includes a pixel array 6110, a control circuit 6120, and a transmission circuit 6130. For example, the pixel array 6110 is located in the display area 61AA, the control circuit 6120 and the transmission circuit 6130 are located in the peripheral area 61BB, and the transmission circuit 6130 is located on a side away from the display area 61AA relative to the control circuit 6120.

[0100] The pixel array 6110 includes 4 rows and 8 columns of sub-pixel units arranged in an array. Scan lines G1 to G4 are respectively connected to the sub-pixel units in rows 1 to 4. Data lines DT1 to DT8 are respectively connected to the sub-pixel units in columns 1 to 8.

[0101] The control circuit 6120 includes a plurality of third transistors T3 and a plurality of fourth transistors T4. Exemplarily, the plurality of third transistors T3 and the plurality of fourth transistors T4 are P-type transistors, which is not limited in the present disclosure. The control signal C1 of the first control line C1 can control the conduction between the data lines G1 to G4 and the transmission lines FT1 to FT4, and the control signal C2 of the second control line C2 can control the conduction between the data lines G5 to G8 and the transmission lines FT1 to FT4. Through this connection method, after the control circuit 6120 switches the data lines connected to the transmission lines FT1 to FT4, the sub-pixel units targeted by the data signals applied by the transmission lines FT1 to FT4 and the sub-pixel units targeted by the data signals applied before the switching of the transmission lines FT1 to FT4 are used to display the same color.

[0102] In the first row scanning period, the control signal C1 of the first control line C1 is first at a low level, and the control signal C2 of the second control line C2 is first at a high level, thereby the plurality of fourth transistors T4 are turned off, and the plurality of third transistors T3 conduct the data lines DT1, DT2, DT3 and DT4 to the transmission lines FT1, FT2, FT3 and FT4, respectively. Thus, the transmission lines FT1, FT2, FT3 and FT4 apply the data signals from the transmission circuit 6130 to the data lines DT1, DT2, DT3 and DT4, respectively. The sub-pixel unit is charged via the data line DT1 using the data signal from the transmission line FT1. The sub-pixel unit is charged via the data line DT2 using the data signal from the transmission line FT2. The sub-pixel unit is charged via the data line DT3 using the data signal from the transmission line FT3. The sub-pixel unit is charged via the data line DT4 using the data signal from the transmission line FT4.

[0103] Afterwards, the control signal C1 of the first control line C1 is changed to a high level, and the control signal C2 of the second control line C2 is changed to a low level, thereby the plurality of third transistors T3 are turned off, and the plurality of fourth transistors T4 conduct the data lines DT5, DT6, DT7 and DT8 with the transmission lines FT1, FT2, FT3 and FT4, respectively. Thus, the transmission lines FT1, FT2, FT3 and FT4 apply the data signals from the transmission circuit 6130 to the data lines DT5, DT6, DT7 and DT8, respectively. The sub-pixel unit is charged via the data line DT5 using the data signal from the transmission line FT1. The sub-pixel unit is charged via the data line DT6 using the data signal from the transmission line FT2. The sub-pixel unit is charged via the data line DT7 using the data signal from the transmission line FT3. The sub-pixel unit is charged via the data line DT8 using the data signal from the transmission line FT4.

[0104] After that, the scanning signal applied by the scanning line G1 to the sub-pixel units of the 1st row, the 1st column to the 8th column is at an effective level, so that the light-emitting elements in the sub-pixel units of the 1st row, the 1st column to the 8th column emit light. The principle of receiving data signals and scanning signals by other sub-pixel units of the pixel array 6110 is similar to the above process, and will not be described in detail here. In addition, the operations performed in other row scanning periods are similar to the operations performed in the above-mentioned first row scanning period, and will not be described in detail here.

[0105] Continue to refer Figure 6B In the embodiment of the present disclosure, the i-th scanning signal applied to the i-th scanning line is at an invalid level in the first sub-period S1 of the i-th row scanning period, and is at an effective level in the second sub-period S2 of the i-th row scanning period. The scanning signals applied to the plurality of scanning lines except the i-th scanning signal are all at an invalid level in the i-th row scanning period, where i is a positive integer. On this basis, in the embodiment of the present disclosure, the effective level of the scanning signal in each row scanning period can be adjusted so that the sub-pixel unit can be charged more fully.

[0106] Figure 6C A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0107] like Figure 6C As shown, the second sub-period S2 can be widened and the first sub-period S1 can be shortened, so that in a row scanning period, the width of the effective level is wider than the width of the invalid level. For example, in a row scanning period, all can be effective levels. By making the width of the effective level wider than the width of the invalid level in a row scanning period, the charging time of the sub-pixel unit can be increased, thereby improving the low grayscale image quality.

[0108] The second connection method disclosed in the present invention is not limited to the above connection method. The display panel of the embodiment of the present invention can also be connected as follows: Fig.6D to connect. Fig.6D A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0109] exist Fig.6D In the embodiment of the present disclosure, the display panel 6200 includes a display area 62AA and a peripheral area 62BB located on one side of the display area 62AA. In the embodiment of the present disclosure, the display panel 6200 includes a pixel array 6210, a control circuit 6220, and a transmission circuit 6230. For example, the pixel array 6210 is located in the display area 62AA, the control circuit 6220 and the transmission circuit 6230 are located in the peripheral area 62BB, and the transmission circuit 6230 is located on a side away from the display area 62AA relative to the control circuit 6220.

[0110] The pixel array 6210 includes 4 rows and 8 columns of sub-pixel units arranged in an array. Scan lines G1 to G4 are respectively connected to the sub-pixel units in rows 1 to 4. Data lines DT1 to DT8 are respectively connected to the sub-pixel units in columns 1 to 8.

[0111] The control circuit 6220 includes a plurality of third transistors T3 and a plurality of fourth transistors T4. The transmission line FT1 is electrically connected to the data line DT1 via the third transistor T3, and is electrically connected to the data line DT5 via the fourth transistor T4; the transmission line FT2 is electrically connected to the data line DT2 via the third transistor T3, and is electrically connected to the data line DT4 via the fourth transistor T4; the transmission line FT3 is electrically connected to the data line DT3 via the third transistor T3, and is electrically connected to the data line DT7 via the fourth transistor T4; the transmission line FT4 is electrically connected to the data line DT6 via the third transistor T3, and is electrically connected to the data line DT8 via the fourth transistor T4.

[0112] The second connection method disclosed in the present invention is not limited to the above connection method. The display panel of the embodiment of the present invention can also be connected as follows: Fig. 6E to connect.

[0113] Fig. 6E A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0114] exist Fig. 6EIn the embodiment of the present disclosure, the display panel 6300 includes a display area 63AA and a peripheral area 63BB located on one side of the display area 63AA. In the embodiment of the present disclosure, the display panel 6300 includes a pixel array 6310, a control circuit 6320, and a transmission circuit 6330. For example, the pixel array 6310 is located in the display area 63AA, the control circuit 6320 and the transmission circuit 6330 are located in the peripheral area 63BB, and the transmission circuit 6330 is located on a side away from the display area 63AA relative to the control circuit 6320.

[0115] The pixel array 6310 includes 4 rows and 8 columns of sub-pixel units arranged in an array. Scan lines G1 to G4 are respectively connected to the sub-pixel units in rows 1 to 4. Data lines DT1 to DT8 are respectively connected to the sub-pixel units in columns 1 to 8.

[0116] The control circuit 6320 includes a plurality of third transistors T3 and a plurality of fourth transistors T4. For example, the gates of the plurality of third transistors T3 are electrically connected to the first control line C1, the first electrodes of the plurality of third transistors T3 are electrically connected to the data lines DT1, DT2, DT3 and DT4, respectively, and the second stages of the plurality of third transistors T3 are electrically connected to the transmission lines FT1, FT2, FT3 and FT4, respectively. The gates of the plurality of fourth transistors T4 are electrically connected to the second control line C2, the first electrodes of the plurality of fourth transistors T4 are electrically connected to the data lines DT5, DT6, DT7 and DT8, respectively, and the second stages of the plurality of second transistors are electrically connected to the transmission lines FT1, FT2, FT3 and FT4, respectively.

[0117] based on Fig. 6E The connection relationship of the display panel 6300 is shown in FIG. Figure 6B or Figure 6C It can be seen from the signal timing that in the first row scanning period, the control signal C1 of the first control line C1 is first at a low level, thereby the plurality of fourth transistors T4 are turned off, the control signal C2 of the second control line C2 is first at a high level, and the plurality of third transistors T3 conduct the data lines DT1, DT2, DT3 and DT4 to the transmission lines FT1, FT2, FT3 and FT4, respectively. Thus, the transmission lines FT1, FT2, FT3 and FT4 can apply the data signals from the transmission circuit 6330 to the data lines DT1, DT2, DT3 and DT4, respectively. The sub-pixel unit is charged via the data line DT1 using the data signal from the transmission line FT1. The sub-pixel unit is charged via the data line DT2 using the data signal from the transmission line FT4. The sub-pixel unit is charged via the data line DT3 using the data signal from the transmission line FT2. The sub-pixel unit is charged via the data line DT4 using the data signal from the transmission line FT3.

[0118] Afterwards, the control signal C1 of the first control line C1 is changed to a high level, and the control signal C2 of the second control line C2 is changed to a low level, thereby the plurality of third transistors T3 are turned off, and the plurality of fourth transistors T4 conduct the data lines DT5, DT6, DT7 and DT8 to the transmission lines FT1, FT2, FT3 and FT4, respectively. Thus, the transmission lines FT1, FT2, FT3 and FT4 can apply the data signals from the transmission circuit 6330 to the data lines DT5, DT6, DT7 and DT8, respectively. The sub-pixel unit is charged via the data line DT5 using the data signal from the transmission line FT1. The sub-pixel unit is charged via the data line DT6 using the data signal from the transmission line FT3. The sub-pixel unit is charged via the data line DT7 using the data signal from the transmission line FT2. The sub-pixel unit is charged via the data line DT8 using the data signal from the transmission line FT4.

[0119] After that, the scanning signal G1 applied by the scanning line G1 to the sub-pixel units of the first row and the first to eighth columns is at an effective level, so that the sub-pixel units of the first row emit light. The principle of receiving data signals and scanning signals by other sub-pixel units of the pixel array 6310 is similar to the above process, which will not be described in detail here. In addition, the operations performed in other row scanning periods are similar to the operations performed in the above first row scanning period, which will not be described in detail here.

[0120] As an optional implementation, the optional third connection method may be to change the connection method between the data line and the transmission line so as to achieve that one transmission line only charges the sub-pixel units for displaying the same color during multiple row scanning periods.

[0121] According to an embodiment of the present disclosure, each data line is electrically connected to a plurality of sub-pixel units respectively included in at least one pixel unit column of a pixel array, and the plurality of sub-pixel units connected to each data line are used to display a color. Each scan line is electrically connected to a plurality of sub-pixel units included in a sub-pixel unit row of a pixel array. Each transmission line is electrically connected to two data lines respectively through a control circuit, and the plurality of sub-pixel units respectively connected to the two data lines are used to display a color. Optionally, the 4m-3th data line is respectively electrically connected to the sub-pixel unit in the 4m-3th column and the qth row and the sub-pixel unit in the 4m-1th column and the q+1th row in the pixel array, the 4m-2th data line is respectively electrically connected to the multiple sub-pixel units included in the 4m-2th sub-pixel unit column of the pixel array, the 4m-1th data line is respectively electrically connected to the sub-pixel unit in the 4m-1th column and the q+1th row and the 4m-3th column in the pixel array, and the 4mth data line is respectively electrically connected to the multiple sub-pixel units included in the 4mth sub-pixel unit column of the pixel array, wherein m is a positive integer, and q=1, 2, 3,… The dth transmission line is electrically connected to the tth data line and the t+4jth data line respectively through the control circuit, and the d+1th transmission line is electrically connected to the t+1th data line and the t+2j+1th data line respectively through the control circuit, wherein the multiple sub-pixel units connected to the t+1th data line and the t+2j+1th data line are all used to display a third color, wherein d is a positive integer, t is a positive integer, and j is a positive integer. The multiple control lines include a first control line and a second control line. The control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The fifth transistor is electrically connected to the dth transmission line, the tth data line, and the first control line, the sixth transistor is electrically connected to the dth transmission line, the t+4jth data line, and the second control line, the seventh transistor is electrically connected to the d+1th transmission line, the t+1th data line, and the first control line, and the eighth transistor is electrically connected to the d+1th transmission line, the t+2j+1th data line, and the second control line. The following takes m=1 or 2, q=1 or 3, d=1, 2, 3 or 4, t=1 or 3, j=1 as an example. 7A to 7E The third connection method mentioned above is described in detail.

[0122] Fig. 7A A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown. Figure 7B A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0123] exist Fig. 7AIn the embodiment of the present disclosure, the display panel 7100 includes a display area 71AA and a peripheral area 71BB located on one side of the display area 71AA. In the embodiment of the present disclosure, the display panel 7100 includes a pixel array 7110, a control circuit 7120, and a transmission circuit 7130. For example, the pixel array 7110 is located in the display area 71AA, the control circuit 7120 and the transmission circuit 7130 are located in the peripheral area 71BB, and the transmission circuit 7130 is located on a side away from the display area 71AA relative to the control circuit 7120.

[0124] The pixel array 7110 includes 4 rows and 8 columns of sub-pixel units arranged in an array. Scan lines G1 to G4 are connected to the 1st to 4th rows of sub-pixel units respectively. Data line DT1 is connected to the 1st sub-pixel unit in the 1st row, the 3rd sub-pixel unit in the 2nd row, the 1st sub-pixel unit in the 3rd row, and the 3rd sub-pixel unit in the 4th row. Data line DT2 is connected to the sub-pixel unit in the 2nd column. Data line DT3 is connected to the 3rd sub-pixel unit in the 1st row, the 1st sub-pixel unit in the 2nd row, the 3rd sub-pixel unit in the 3rd row, and the 1st sub-pixel unit in the 4th row. Data line DT4 is connected to the sub-pixel unit in the 4th column. Data line DT5 is connected to the 5th sub-pixel unit in the 1st row, the 7th sub-pixel unit in the 2nd row, the 5th sub-pixel unit in the 3rd row, and the 7th sub-pixel unit in the 4th row. Data line DT6 is connected to the sub-pixel unit in the 6th column. The data line DT7 connects the 7th sub-pixel unit in the 1st row, the 5th sub-pixel unit in the 2nd row, the 7th sub-pixel unit in the 3rd row, and the 5th sub-pixel unit in the 4th row. The data line DT8 connects the sub-pixel unit in the 8th column.

[0125] The control circuit 7120 includes a plurality of fifth transistors T5, a plurality of sixth transistors T6, a plurality of seventh transistors T7, and a plurality of eighth transistors T8. Exemplarily, the plurality of fifth transistors T5, the plurality of sixth transistors T6, the plurality of seventh transistors T7, and the plurality of eighth transistors T8 are P-type transistors. The gates of the plurality of fifth transistors T5 are electrically connected to the first control line C1, the first electrodes of the plurality of fifth transistors T3 are electrically connected to the data lines DT1 and DT3, respectively, and the second stages of the plurality of fifth transistors T3 are electrically connected to the transmission lines FT1 and FT3, respectively. The gates of the plurality of sixth transistors T6 are electrically connected to the second control line C2, the first electrodes of the plurality of sixth transistors T6 are electrically connected to the data lines DT5 and DT7, respectively, and the second stages of the plurality of sixth transistors T6 are electrically connected to the transmission lines FT1 and FT3, respectively. The gates of the plurality of seventh transistors T7 are electrically connected to the first control line C1, the first electrodes of the plurality of seventh transistors T7 are electrically connected to the data lines DT2 and DT4, respectively, and the second stages of the plurality of seventh transistors T7 are electrically connected to the transmission lines FT2 and FT4, respectively. The gate electrodes of the plurality of eighth transistors T8 are electrically connected to the second control line C2, the first electrodes of the plurality of eighth transistors T8 are electrically connected to the data lines DT6 and DT8, respectively, and the second electrodes of the plurality of eighth transistors T8 are electrically connected to the transmission lines FT2 and FT4, respectively. Taking the sub-pixel units of the first column and the third column as an example, through this connection mode, the sub-pixel units of the same color in the sub-pixel units of the first column and the sub-pixel units of the third column can be alternately connected from top to bottom, so that each path composed of the transmission line and the data line only applies the data signal for the sub-pixel unit for displaying one color in each row scanning period, thereby avoiding the problem of increased power consumption caused by the transmission circuit 7130 needing to switch the data signal for the sub-pixel units for displaying different colors between adjacent rows.

[0126] The following combination Figure 7B The signal timing diagram shown is for Fig. 7A The examples in this section further illustrate this. Figure 7B, in the first row scanning period, the control signal of the first control line C1 is first at a low level, and the control signal of the second control line C2 is first at a high level, thereby the plurality of sixth transistors T6 and the plurality of eighth transistors T8 are turned off, the plurality of fifth transistors T5 respectively conduct the data lines DT1 and DT3 with the transmission lines FT1 and FT3, and the plurality of seventh transistors T7 respectively conduct the data lines DT2 and DT4 with the transmission lines FT2 and FT4. Thus, the data signals on the transmission lines FT1, FT2, FT3 and FT4 are respectively applied to the data lines DT1, DT2, DT3 and DT4. The sub-pixel unit is charged via the data line DT1 using the data signal from the transmission line FT1. The sub-pixel unit is charged via the data line DT2 using the data signal from the transmission line FT2. The sub-pixel unit is charged via the data line DT3 using the data signal from the transmission line FT3. The sub-pixel unit is charged via the data line DT4 using the data signal from the transmission line FT4.

[0127] Afterwards, the control signal of the first control line C1 is changed to a high level, the control signal of the second control line C2 is changed to a low level, the multiple fifth transistors T5 and the multiple seventh transistors T7 are turned off, the multiple sixth transistors T6 connect the data lines DT5 and DT7 to the transmission lines FT1 and FT3 respectively, and the multiple eighth transistors T8 connect the data lines DT6 and DT8 to the transmission lines FT2 and FT4 respectively. Thus, the transmission lines FT1, FT2, FT3 and FT4 apply the data signals from the transmission circuit 7130 to the data lines DT5, DT6, DT7 and DT8 respectively. The sub-pixel unit is charged via the data line DT5 using the data signal from the transmission line FT1. The sub-pixel unit is charged via the data line DT6 using the data signal applied from the transmission line FT2. The sub-pixel unit is charged via the data line DT7 using the data signal from the transmission line FT3. The sub-pixel unit is charged via the data line DT8 using the data signal from the transmission line FT4. Thus, in Figure 5B In all the row scanning periods shown, the transmission circuit does not need to switch the data signals applied to the sub-pixel units of different colors, and only needs to apply the data signal for the sub-pixel unit for displaying one color to one transmission line at all times.

[0128] After that, the scan line G1 applies a scan signal to the sub-pixel unit of the first row, so that the light-emitting element in the sub-pixel unit of the first row emits light. The principle of receiving data signals and scan signals by other sub-pixel units of the pixel array 7110 is similar to the above process, which will not be described in detail here. In addition, the operations performed in other row scanning periods are similar to the operations performed in the above first row scanning period, which will not be described in detail here.

[0129] Continue to refer Figure 7BIn the embodiment of the present disclosure, the i-th scanning signal applied to the i-th scanning line is at an invalid level in the first sub-period S1 of the i-th row scanning period, and is at an effective level in the second sub-period S2 of the i-th row scanning period. The scanning signals applied to the plurality of scanning lines except the i-th scanning signal are all at an invalid level in the i-th row scanning period, where i is a positive integer. On this basis, in the embodiment of the present disclosure, the effective level of the scanning signal in each row scanning period can be adjusted so that the sub-pixel unit can be charged more fully.

[0130] Figure 7C A signal timing diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0131] like Figure 7C As shown, the second sub-period S2 can be widened and the first sub-period S1 can be shortened, so that in a row scanning period, the width of the effective level is wider than the width of the invalid level. For example, in a row scanning period, all can be effective levels. By making the width of the effective level wider than the width of the invalid level in a row scanning period, the charging time of the sub-pixel unit can be increased, thereby improving the low grayscale image quality.

[0132] The third connection method disclosed in the present invention is not limited to the above connection method. The display panel of the embodiment of the present invention can also be connected as follows: Fig.7D to connect.

[0133] Fig.7D A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0134] exist Fig.7D In the embodiment of the present disclosure, the display panel 7200 includes a display area 72AA and a peripheral area 72BB located on one side of the display area 72AA. In the embodiment of the present disclosure, the display panel 7200 includes a pixel array 7210, a control circuit 7220, and a transmission circuit 7230. For example, the pixel array 7210 is located in the display area 72AA, the control circuit 7220 and the transmission circuit 7230 are located in the peripheral area 72BB, and the transmission circuit 7230 is located on a side away from the display area 72AA relative to the control circuit 7220.

[0135] The pixel array 7210 includes 4 rows and 8 columns of sub-pixel units arranged in an array. Scan lines G1 to G4 are respectively connected to the 1st to 4th rows of sub-pixel units. For the connection mode between the data lines and the sub-pixel units, taking the connection mode of the data line DTm as an example, the data line DTm is connected to the sub-pixel unit of the 1st row and the mth column, the sub-pixel unit of the 2nd row and the Tm+2nd column, the sub-pixel unit of the 3rd row and the Tm+4th column, and the sub-pixel unit of the 4th row and the Tm+6th column. The connection modes of other data lines are similar and will not be described in detail here.

[0136] The control circuit 7220 includes a plurality of fifth transistors T5, a plurality of sixth transistors T6, a plurality of seventh transistors T7, and a plurality of eighth transistors T8. The gates of the plurality of fifth transistors T5 and the plurality of seventh transistors T7 are electrically connected to the first control line C1. The gates of the plurality of sixth transistors T6 and the plurality of eighth transistors T8 are electrically connected to the second control line C2. On this basis, the data line DTm is electrically connected to the first electrode of a sixth transistor T6, and the second electrode of the sixth transistor T6 is electrically connected to the transmission line FTy+3, so that the sixth transistor T6 can conduct the sub-pixel unit for displaying the first color or the second color with the transmission line FTy+3 based on the control signal of the control line, so that the sub-pixel unit for displaying the first color or the second color receives the data signal from the transmission circuit 7230. The connection method of other sixth transistors T6 and the plurality of fifth transistors T5 is similar to this, and will not be repeated here. The data line DTm+1 is electrically connected to a first end of a seventh transistor T7, and a second end of the seventh transistor T7 is electrically connected to the transmission line FTy, so that the seventh transistor T7 can conduct the sub-pixel unit for displaying the third color and the transmission line FTy based on the control signal of the control line, so that the sub-pixel unit for displaying the third color receives the data signal from the transmission circuit 7230. The connection method of other seventh transistors T7 and multiple eighth transistors T8 to the transmission line is similar to this, which will not be repeated here.

[0137] Through the above connection mode, the data line connected to each transmission line is only connected to the sub-pixel unit for displaying the same color, so that the transmission line only applies data signals for the sub-pixel unit for displaying one color in multiple row scanning periods.

[0138] The third connection method disclosed in the present invention is not limited to the above connection method. The display panel of the embodiment of the present invention can also be connected as follows: Fig. 7E to connect.

[0139] Fig. 7E A schematic diagram of a display panel according to another embodiment of the present disclosure is schematically shown.

[0140] exist Fig. 7E In the embodiment of the present disclosure, the display panel 7300 includes a display area 73AA and a peripheral area 73BB located on one side of the display area 73AA. In the embodiment of the present disclosure, the display panel 7300 includes a pixel array 7310, a control circuit 7320, and a transmission circuit 7330. For example, the pixel array 7310 is located in the display area 73AA, the control circuit 7320 and the transmission circuit 7330 are located in the peripheral area 73BB, and the transmission circuit 7330 is located on a side away from the display area 73AA relative to the control circuit 7320.

[0141] The pixel array 7310 includes 4 rows and 8 columns of sub-pixel units arranged in an array. Scan lines G1 to G4 are respectively connected to sub-pixel units in rows 1 to 4. Taking the connection method of data line DTm+6 as an example, data line DTm+6 is connected to sub-pixel units in row 1, column Tm+6, sub-pixel units in row 2, column Tm+4, sub-pixel units in row 3, column Tm+2, and sub-pixel units in row 4, column Tm. For other data line connection methods, refer to Fig. 7E And so on, I won’t go into details here.

[0142] The control circuit 7320 includes a plurality of fifth transistors T5, a plurality of sixth transistors T6, a plurality of seventh transistors T7 and a plurality of eighth transistors T8. The gates of the plurality of fifth transistors T5 and the plurality of seventh transistors T7 are electrically connected to the first control line C1. The gates of the plurality of sixth transistors T6 and the plurality of eighth transistors T8 are electrically connected to the second control line C2. On this basis, the data line DTm+6 is electrically connected to the first electrode of a fifth transistor T5, and the second electrode of the fifth transistor T5 is electrically connected to the transmission line FTy, so that the fifth transistor T5 can conduct the sub-pixel unit for displaying the first color or the second color with the transmission line FTy based on the control signal of the control line, so that the sub-pixel unit for displaying the first color or the second color receives the data signal from the transmission circuit 7330. The connection method of the other fifth transistors T5 and the plurality of sixth transistors T6 is similar to this, and will not be repeated here. The data line DTm+1 is electrically connected to a first end of a seventh transistor T7, and a second end of the seventh transistor T7 is electrically connected to the transmission line FTy+3, so that the seventh transistor T7 can conduct the sub-pixel unit for displaying the third color and the transmission line FTy+3 based on the control signal of the control line, so that the sub-pixel unit for displaying the third color receives the data signal from the transmission circuit 7330. The connection method of other seventh transistors T7 and multiple eighth transistors T8 to the transmission line is similar to this, which will not be repeated here.

[0143] Based on this, the embodiment of the present disclosure describes the connection mode and working condition of the display panel. In addition to the advantages described above, the display panel of the present disclosure also has the advantages of being easier to implement and having lower consumption of manufacturing resources.

[0144] Figure 8 The structural diagram of a display device according to an embodiment of the present disclosure is schematically shown.

[0145] like Figure 8As shown, the display device 800 includes a display panel 810. The display panel 810 may be any one of the display panels in the above-mentioned embodiments of the present disclosure, such as the display panel 400, the display panel 5100, the display panel 5200, the display panel 5300, the display panel 5400, the display panel 6100, the display panel 6200, the display panel 6300, the display panel 7100, the display panel 7200, the display panel 7300, and the like.

[0146] Fig. 9 A schematic flow chart of a display method according to an embodiment of the present disclosure is shown.

[0147] like Fig. 9 As shown, the display method includes steps S910 to S920.

[0148] In the embodiments of the present disclosure, the display method can be applied to the display panel 400, display panel 5100, display panel 5200, display panel 5300, display panel 5400, display panel 6100, display panel 6200, display panel 6300, display panel 7100, display panel 7200, and display panel 7300 described above.

[0149] In operation S910, based on control signals applied to a plurality of control lines, the transmission lines are controlled to be connected to the plurality of data lines in sequence, so that the plurality of data signals applied to the transmission lines are applied to the plurality of data lines respectively.

[0150] In operation S920, data signals respectively applied to the plurality of data lines are applied to a plurality of sub-pixel units for displaying one color based on scan signals applied to the scan lines.

[0151] In the embodiments of the present disclosure, operation S910 and operation S920 are similar to the operations performed by the display panel 400, display panel 5100, display panel 5200, display panel 5300, display panel 5400, display panel 6100, display panel 6200, display panel 6300, display panel 7100, display panel 7200, and display panel 7300 described above, and are not repeated here.

[0152] The block diagram in the accompanying drawings illustrates the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0153] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0154] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A display panel, comprising a display area and a peripheral area located on one side of the display area, the display panel comprising: A pixel array, located in the display area, includes a plurality of sub-pixel units, each sub-pixel unit is electrically connected to a scan line and a data line; A control circuit is located in the peripheral area and is electrically connected to the plurality of control lines, the plurality of transmission lines and the plurality of data lines. The control circuit is configured to respectively conduct the plurality of transmission lines with the plurality of data lines based on control signals applied to the plurality of control lines. The transmission circuit is located in the peripheral area and on a side away from the display area relative to the control circuit, and is electrically connected to the plurality of transmission lines. The transmission circuit is configured to apply a plurality of data signals to a plurality of sub-pixel units for displaying a color via the plurality of transmission lines and the plurality of data lines based on a scanning signal applied to the scanning line.

2. The display panel according to claim 1, wherein: The pixel array includes multiple first sub-pixel unit columns and multiple second sub-pixel unit columns, the first sub-pixel unit columns and the second sub-pixel unit columns are arranged alternately, the sub-pixel units in the first sub-pixel unit columns are used to display a first color and a second color, the sub-pixel units used to display the first color and the sub-pixel units used to display the second color are arranged alternately; the sub-pixel units in the second sub-pixel unit columns are used to display a third color.

3. The display panel according to claim 1, wherein: The i-th scanning signal applied to the i-th scanning line is at an invalid level in a first sub-period of the i-th row scanning period, and is at a valid level in a second sub-period of the i-th row scanning period; The scan signals applied to the plurality of scan lines except the i-th scan signal are all at the inactive level during the i-th row scan period, wherein i is a positive integer.

4. The display panel according to claim 1, wherein: The control circuit includes a plurality of transistors, wherein a gate of each transistor is electrically connected to the control line, a first electrode of the transistor is electrically connected to the data line, and a second electrode of the transistor is electrically connected to the transmission line.

5. The display panel according to any one of claims 1 to 4, wherein: Each data line is electrically connected to a plurality of sub-pixel units included in a sub-pixel unit column of the pixel array; Each scanning line is electrically connected to two consecutive sub-pixel units among a plurality of sub-pixel units respectively included in a plurality of sub-pixel unit rows of the pixel array; Each transmission line is electrically connected to the mth data line and the m+2jth data line respectively through the control circuit, wherein m is a positive integer and j is a positive integer.

6. The display panel according to claim 5, wherein: The pth scan line is electrically connected to the sub-pixel units in the pth row and 1+4k column, the sub-pixel units in the pth row and 2+4k column, the sub-pixel units in the pth row and 3+4k column, and the sub-pixel units in the p+1th row and 4+4k column in the pixel array, respectively, and the p+1th scan line is electrically connected to the sub-pixel units in the p+1th row and 1+4k column, the sub-pixel units in the p+1th row and 2+4k column, the sub-pixel units in the pth row and 3+4k column, and the sub-pixel units in the pth row and 4+4k column in the pixel array, respectively, wherein p is a positive odd number, and k=0, 1, 2,….

7. The display panel according to claim 5, wherein: The pth scan line is electrically connected to the sub-pixel units in the pth row and 1+4k column, the sub-pixel units in the p+1th row and 2+4k column, the sub-pixel units in the p+1th row and 3+4k column, and the sub-pixel units in the pth row and 4+4k column in the pixel array, respectively, and the p+1th scan line is electrically connected to the sub-pixel units in the p+1th row and 1+4k column, the sub-pixel units in the pth row and 2+4k column, the sub-pixel units in the pth row and 3+4k column, and the sub-pixel units in the p+1th row and 4+4k column in the pixel array, respectively, wherein p is a positive odd number, and k=0, 1, 2,….

8. The display panel according to claim 5, wherein: The plurality of control lines include a first control line and a second control line; Wherein, the control circuit comprises a first transistor and a second transistor; The first transistor is electrically connected to the transmission line, the mth data line, and the first control line, and the second transistor is electrically connected to the transmission line, the m+2jth data line, and the second control line.

9. The display panel according to any one of claims 1 to 4, wherein: Each data line is electrically connected to a plurality of sub-pixel units included in a sub-pixel unit column of the pixel array; Each scanning line is electrically connected to a plurality of sub-pixel units included in a sub-pixel unit row of the pixel array; Each transmission line is electrically connected to the mth data line and the m+4jth data line respectively through the control circuit, wherein m is a positive integer and j is a positive integer.

10. The display panel according to claim 9, wherein: The plurality of control lines include a first control line and a second control line; Wherein, the control circuit includes a third transistor and a fourth transistor; The third transistor is electrically connected to the transmission line, the mth data line, and the first control line, and the fourth transistor is electrically connected to the transmission line, the m+4jth data line, and the second control line.

11. The display panel according to any one of claims 1 to 5, wherein: Each data line is electrically connected to a plurality of sub-pixel units respectively included in at least one pixel unit column of the pixel array, and the plurality of sub-pixel units connected to each data line are used to display one color; Each scanning line is electrically connected to a plurality of sub-pixel units included in a sub-pixel unit row of the pixel array; Each transmission line is electrically connected to two data lines respectively through the control circuit, and the multiple sub-pixel units respectively connected to the two data lines are used to display one color.

12. The display panel according to claim 11, wherein: The 4m-3th data line is respectively electrically connected to the sub-pixel units in the 4m-3th column and the qth row and the sub-pixel units in the 4m-1th column and the q+1th row in the pixel array, the 4m-2th data line is respectively electrically connected to the multiple sub-pixel units included in the 4m-2th sub-pixel unit column of the pixel array, the 4m-1th data line is respectively electrically connected to the sub-pixel units in the 4m-1th column and the q+1th row and the 4m-3th column in the pixel array, and the 4mth data line is respectively electrically connected to the multiple sub-pixel units included in the 4mth sub-pixel unit column of the pixel array, wherein m is a positive integer, and q=1, 2, 3,….

13. The display panel according to claim 12, wherein: The dth transmission line is electrically connected to the tth data line and the t+4jth data line respectively through the control circuit, and the d+1th transmission line is electrically connected to the t+1th data line and the t+2j+1th data line respectively through the control circuit, wherein the multiple sub-pixel units respectively connected to the t+1th data line and the t+2j+1th data line are used to display a third color, wherein d is a positive integer, t is a positive integer, and j is a positive integer.

14. The display panel according to claim 13, wherein: The plurality of control lines include a first control line and a second control line; Wherein, the control circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The fifth transistor is electrically connected to the dth transmission line, the tth data line and the first control line, the sixth transistor is electrically connected to the dth transmission line, the t+4jth data line and the second control line, the seventh transistor is electrically connected to the d+1th transmission line, the t+1th data line and the first control line, and the eighth transistor is electrically connected to the d+1th transmission line, the t+2j+1th data line and the second control line.

15. A display device comprising the display panel according to any one of claims 1 to 14.

16. A display method, comprising: Based on the control signals applied to the plurality of control lines, controlling the transmission lines to be connected to the plurality of data lines in sequence, so as to apply the plurality of data signals applied to the transmission lines to the plurality of data lines respectively; as well as The data signals respectively applied to the plurality of data lines are applied to a plurality of sub-pixel units for displaying one color based on the scan signals applied to the scan lines.

Images