Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, and relates to the technical field of display. The non-display area includes a first non-display area and a second non-display area. The second non-display area is located on one side of the display area along a first direction, and the first non-display area is located on opposite sides of the display area along a second direction. The display panel includes: a plurality of drive control lines, the drive control lines extend along the first direction and are arranged along the second direction, and the first direction and the second direction intersect; a plurality of data lines, the data lines extend along the second direction and are arranged along the first direction; and a plurality of multiplexing units, located in the first non-display area, each multiplexing unit includes one input end and N output ends, the N output ends are connected with N data lines respectively, N≥2, the input end of the multiplexing unit is connected with a first input line, at least part of the first input line is located in the display area, and the first input line is configured to obtain a data signal from a binding pad. In this way, the narrow frame design of the display product can be realized.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablet computers, notebook computers and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable important tool for people today.

[0003] At present, how to reduce the frame width of the display product and improve the screen ratio has become one of the technical problems to be solved. SUMMARY

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device, aiming to realize the narrow frame design of the display panel and improve the screen ratio.

[0005] In a first aspect, the present disclosure provides a display panel, comprising a display area and a non-display area located at the periphery of the display area, the non-display area comprising a first non-display area and a second non-display area, the second non-display area being located at one side of the display area along a first direction, and the first non-display area being located at opposite sides of the display area along a second direction; the second non-display area comprises a binding area, and the binding area comprises a binding pad; the display panel comprises:

[0006] a plurality of driving control lines, the driving control lines extending along the first direction and arranging along the second direction, the first direction and the second direction intersecting;

[0007] a plurality of data lines, the data lines extending along the second direction and arranging along the first direction;

[0008] a plurality of multiplexing units located in the first non-display area, each multiplexing unit comprising one input end and N output ends, the N output ends being connected with N data lines respectively, N≥2, the input end of the multiplexing unit being connected with a first input line, at least part of the first input line being located in the display area, and the first input line being configured to obtain a data signal from the binding pad.

[0009] In a second aspect, based on the same inventive concept, the present disclosure provides a display device comprising the display panel provided in the first aspect of the present disclosure.

[0010] The technical scheme provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0011] The display panel provided by the embodiment of the present disclosure has the following advantages. The arrangement of the data lines, the driving control lines, the multiplexing units and the binding area in the display panel is adjusted. Specifically, when the driving control lines extend along a first direction and are arranged along a second direction, and the data lines extend along the second direction and are arranged along the first direction, the multiplexing units and the binding pads are arranged in the non-display areas on different sides of the display area respectively. The multiplexing units are arranged in the first non-display area in the extension direction of the data lines, and the binding pads are arranged in the non-display area in the extension direction of the driving control lines. That is, the multiplexing units are arranged in the first non-display area on one side of the display area along the second direction, and the binding pads are arranged in the second non-display area on one side of the display area along the first direction. In this way, the binding pads and the multiplexing units are arranged in different non-display areas respectively, so that the arrangement of the binding pads and the multiplexing units in the same non-display area is avoided, and thus the narrow-frame design of the display panel is facilitated. In addition, the multiplexing units and the binding pads are arranged in the manner of the embodiment of the present disclosure. Even if the number of data lines and multiplexing units is increased, the space of the non-display area where the second non-display area is located will not be affected, and the narrow-frame design of the display product is facilitated, and the screen-to-body ratio of the display product is improved. When the multiplexing units and the binding pads are arranged in the non-display areas on different sides of the display area, in order to realize the electrical connection between the multiplexing units and the binding pads, the first input lines are introduced in the present disclosure. At least part of the first input lines is located in the display area. That is, the first input lines are electrically connected with the multiplexing units in the first non-display area, extend to the display area, are routed in the display area, and then further extend to the binding area from the display area. In this way, most of the line segments in the first input lines will not occupy the width space of the first non-display area of the display panel, so as not to affect the frame width of the first non-display area, and the narrow-frame design of the area where the first non-display area is located is also facilitated. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure.

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained from these drawings without any creative effort.

[0014] Figure 1 Fig. 1 shows a plan view of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 2 Fig. 2 shows a detailed view of the display panel; Figure 1 Fig. 3 shows a detailed view of the display panel;

[0016] Figure 3 Fig. 9 shows a circuit schematic diagram of a pixel driving circuit suitable for embodiments of the present disclosure;

[0017] Figure 4 Fig. 10 shows a driving timing diagram corresponding to the pixel driving circuit in Fig. 9; Figure 3

[0018] Figure 5 Fig. 11 shows a film layer schematic diagram of a display panel provided by embodiments of the present disclosure;

[0019] Figure 6 Fig. 12 shows a planar schematic diagram of a display panel in the related art;

[0020] Figure 7 Fig. 13 shows a layout schematic diagram of a pixel driving circuit in embodiments of the present disclosure;

[0021] Figure 8 Fig. 14 shows a relative position relationship diagram of a pixel driving circuit, a driving control line, a data line, and a sub-pixel;

[0022] Figure 9 Fig. 15 shows another planar schematic diagram of a display panel provided by embodiments of the present disclosure;

[0023] Figure 10 Fig. 16 shows a relative position reference schematic diagram of part of a first auxiliary line and part of a first connection line in a display panel;

[0024] Figure 11 Fig. 17 shows another planar schematic diagram of a display panel provided by embodiments of the present disclosure;

[0025] Figure 12 Fig. 18 shows a relative position reference schematic diagram of part of a second auxiliary line and part of a second connection line in a display panel;

[0026] Figure 13 Fig. 19 shows a connection schematic diagram of a multiplexing unit and a data line;

[0027] Figure 14 Fig. 20 shows a working timing diagram of a multiplexing unit in Fig. 19; Figure 13

[0028] Fig. 21 shows a connection schematic diagram of a multiplexing unit and a data line; Figure 15

[0029] Fig. 22 shows a working timing diagram of a multiplexing unit in Fig. 21; Figure 16 Figure 15

[0030] Figure 17 Fig. 23 shows another planar schematic diagram of a display panel provided by embodiments of the present disclosure;​​​

[0031] Figure 18 Shown is a schematic diagram of an arrangement of the second input line and the third auxiliary line L3;

[0032] Figure 19 Shown is a schematic diagram of a layout of the first input line and the second input line in the display panel;

[0033] Figure 20 FIG2 is another schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0034] Figure 21 FIG2 is another schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0035] Figure 22 FIG2 is another schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0036] Figure 23 FIG2 is another schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0037] Figure 24 Shown is a schematic diagram of a layout of power signal lines and gate drive circuits in a display panel;

[0038] Figure 25 Shown is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0041] Figure 1 FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure, illustrating the relative positional relationship between the drive control line SL, the data line DL, and the multiplexing unit 90 included in the display panel. Figure 2 Shown Figure 1 A detailed diagram of the display panel, specifically Figure 1 The structure and connection of the multiplexing unit 90 are refined. Figure 3 FIG. 1 is a circuit diagram of a pixel driving circuit applicable to an embodiment of the present disclosure.Figure 4 A driving timing diagram corresponding to a pixel driving circuit in the display panel 100 is shown in FIG. 3. Figure 3 A driving timing diagram corresponding to a pixel driving circuit in the display panel 100 is shown in FIG. 3.

[0042] A driving timing diagram corresponding to a pixel driving circuit in the display panel 100 is shown in FIG. 3. Figure 1 A driving timing diagram corresponding to a pixel driving circuit in the display panel 100 is shown in FIG. 3. Figure 2 A display panel 100 is provided, which includes a display area A0 and a non-display area A1 located at the periphery of the display area A0. The non-display area A1 includes a first non-display area A11 and a second non-display area A12. The second non-display area A12 is located at one side of the display area A0 along a first direction D1, and the first non-display area A11 is located at opposite sides of the display area A0 along a second direction D2. The second non-display area A12 includes a binding area A13, and the binding area A13 includes a binding pad P0. Optionally, the display panel includes a plurality of pixel driving circuits as shown in FIG. 2. Please refer to FIGS. 3 and 4. Figure 3 A driving timing diagram corresponding to a pixel driving circuit in the display panel 100 is shown in FIG. 3. Figure 3 A driving timing diagram corresponding to a pixel driving circuit in the display panel 100 is shown in FIG. 3. Figure 4 The pixel driving circuit is used to be electrically connected with the light emitting element 30 to drive the light emitting element 30 to emit light. Optionally, the pixel driving circuit includes a driving transistor DT, a first reset module 41 (for example, including a transistor T1 is taken as an example for description) and a data writing module 42 (for example, including a transistor T5 is taken as an example for description). The gate of the driving transistor DT is connected with a first node N1, the first electrode is connected with a second node N2, and the second electrode is connected with a third node N3. The two ends of the first reset module 41 are respectively connected with a first reset signal line Vref1 and the first node N1, and the control end is connected with a first scan line S1. The two ends of the data writing module 42 are respectively connected with a data signal line DL and the second node N2, and the control end is connected with a second scan line S2. The third node N3 is used to be electrically connected with the light emitting element 30. The pixel driving circuit further includes a first light emitting control module 43 (for example, including a transistor T3 is taken as an example for description) and a second light emitting control module 44 (for example, including a transistor T4 is taken as an example for description). The first light emitting control module 43 is connected between a first power signal end PVDD and the second node N2, and the second light emitting control module 44 is connected between the third node N3 and the light emitting element 30. The control ends of the first light emitting control module 43 and the second light emitting control module 44 are connected with a light emitting control signal line EM. Optionally, the pixel driving circuit further includes a threshold compensation module 45 (for example, including a transistor T6 is taken as an example for description). The threshold compensation module 45 is connected between the first node N1 and the third node N3, and the control end of the threshold compensation module 45 is connected with the second scan line S2.

[0043] The working process of the pixel driving circuit includes:

[0044] The first reset stage: the first scan line S1 provides an effective level signal to the first reset module 41, the first reset module 41 is turned on, and the reset signal on the first reset signal line Vref1 is transmitted to the first node N1 to reset the first node N1.

[0045] Data writing and threshold compensation stage: the second scan line S2 provides a valid level signal to the data writing module 42 and the threshold compensation module 45, the data writing module 42 and the threshold compensation module 45 are turned on, the data signal on the data signal line DL is transmitted to the second node N2, and the threshold compensation module 45 performs threshold compensation on the driving transistor DT.

[0046] Light-emitting stage: the light-emitting control signal line EM sends an effective level signal to the first light-emitting control module 43 and the second light-emitting control module 44 to control the first light-emitting control module 43 and the second light-emitting control module 44 to be turned on, and the signal of the first power signal terminal PVDD is transmitted to the driving transistor DT to form a current that drives the light-emitting element 30 to emit light.

[0047] It should be noted that the above embodiment is described by taking the transistors in the pixel driving circuit as P-type transistors as an example, but the present disclosure is not limited to this. In some other embodiments of the present disclosure, Figure 3 At least one transistor in the pixel driving circuit is configured as an N-type transistor. In addition, the above embodiment is only described by taking the pixel driving circuit including 7 transistors as an example. In some other embodiments of the present disclosure, the pixel driving circuit may also include other numbers of transistors, such as 8 or even more transistors, which are all applicable to the design concept of the present disclosure.

[0048] Please continue to refer to Figure 1 to Figure 5 , the display panel 100 in the embodiment of the present disclosure further includes:

[0049] Multiple drive control lines SL extend along a first direction D1 and are arranged along a second direction D2, with the first direction D1 and the second direction D2 intersecting. The drive control lines SL are used to provide control signals to the pixel drive circuit in the display panel. The drive control lines SL may include, for example, at least one of the first scan lines S1, the second scan lines S2, and the emission control signal lines EM mentioned in the aforementioned embodiments. When the display panel has a rectangular structure or a rounded rectangular structure, in the present disclosure, the drive control lines SL extend in the same direction as the long sides of the display panel, and the binding area A13 is located in the second non-display area A12 in the direction in which the drive control lines SL extend.

[0050] Multiple data lines DL extend along the second direction D2 and are arranged along the first direction D1; the data lines DL are used to provide data signals to the pixel driving circuit in the display panel. When the display panel has a rectangular structure or a rounded rectangular structure, in the present disclosure, the extension direction of the data lines DL is the same as the extension direction of the short side of the display panel.

[0051] Multiple multiplexing units 90 are located in the first non-display area A11, that is, in the non-display area A1 in the extension direction of the data line DL. Each multiplexing unit 90 includes an input end and N output ends. The N output ends are respectively connected to N data lines DL, N ≥ 2. The input end of the multiplexing unit 90 is connected to the first input line 20. At least a portion of the first input line 20 is located in the display area A0. The first input line 20 is configured to obtain a data signal from the binding pad P0.

[0052] It should be noted that Figure 1 The following description only uses a rectangular display panel as an example, and does not limit the actual shape of the display panel. In some other embodiments of the present disclosure, the display panel can also be embodied in any other feasible shape, such as a rounded rectangle. When the display panel has a rectangular structure or a rounded rectangle structure, the first non-display area A11 of the display panel can be, for example, a non-display area adjacent to the long side edge of the display panel, and the second non-display area A12 of the display panel can be, for example, located in the non-display area adjacent to the short side edge of the display panel. The binding area is located in the second non-display area A12, and the binding area A13 is provided with a plurality of binding pads P0. The binding pads P0 are electrically connected to the signal lines in the display panel, such as the data lines SL and other signal lines. It should be noted that the electrical connection mentioned in the present disclosure can be a direct connection or a connection through an intermediate connector such as a switch, and the present disclosure does not specifically limit this. In the binding area A13, the binding pads P0 can be used to bind to the control chip or the flexible circuit board, thereby realizing the transmission of signals between the control chip or the flexible circuit board and the display panel.

[0053] Optionally, the display panel provided in this embodiment may be a display panel using organic light-emitting diode display technology, that is, an OLED (Organic Light-Emitting Diode) display panel, for example, see Figure 5 ,in, Figure 5 FIG2 is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure. In the embodiment of the present disclosure, the pixels of the display panel may include Figure 5 The light emitting element 30 and the pixel driving circuit connected to the light emitting element 30. Figure 5The basic structure of the light-emitting element 30 of the OLED display panel includes an anode 301, a light-emitting material layer 302 and a cathode 303. When the power supply supplies an appropriate voltage, the holes generated by the anode 301 and the electrons generated by the cathode 303 will combine in the light-emitting material layer 302 to generate bright light. Compared with liquid crystal displays, OLED display panels have the characteristics of high visibility and high brightness, and are more power-saving, lightweight and thin. Of course, in some other embodiments of the present invention, the display panel may also be a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc., and the present disclosure is not limited to this.

[0054] by Figure 5 Taking the display panel in as an example, the display panel includes a substrate 00, a driving layer 40, and a display layer 10, wherein the display layer 10 includes a pixel definition layer 19, and the pixel definition layer 19 defines a plurality of pixel openings; the light-emitting material layer 302 is located at least in the pixel opening, and along the direction perpendicular to the substrate 00, the anode 301 and the cathode 303 are respectively located on both sides of the light-emitting material layer 302, and the anode 301 is located on the side of the cathode 303 facing the substrate 00. Optionally, an encapsulation layer 50 is further provided on the side of the cathode 303 away from the anode 301. Optionally, the encapsulation layer 50 includes a first inorganic layer 51, an organic layer 52, and a second organic layer 53 arranged in a stacked manner. A pixel driving circuit is provided in the driving layer 40 for providing a driving voltage to the light-emitting element to drive the light-emitting element to emit light, and the pixel driving circuit includes a plurality of transistors M. The driving control line SL and the data line DL mentioned in the embodiment of the present disclosure are both used to be electrically connected to the pixel driver, and are used to provide a control signal and a data signal to the pixel driving circuit respectively. Optionally, in the driving layer 40, the gate of the transistor is arranged on the first metal layer m1, and the source and drain of the transistor are arranged on the second metal layer m2. The array substrate 10 also includes a semiconductor layer poly arranged on the side of the first metal layer m1 facing the substrate 00 and an auxiliary metal layer m0 arranged on the side of the semiconductor layer poly facing the substrate 00. It should be noted that the display panel may include a transistor with a dual-gate structure. In this case, one of the gates of the transistor may be located in the first metal layer m1, and the other gate may be located in the auxiliary metal layer m0. In the direction perpendicular to the plane where the substrate 00 is located, the first metal layer m1 and the auxiliary metal layer m0 both overlap with the semiconductor layer poly. The auxiliary metal layer m0 also has a light-shielding function to prevent light from affecting the semiconductor layer poly. Optionally, a capacitor metal layer mc is further included between the first metal layer m1 and the second metal layer m2. The capacitor metal layer mc can form a capacitor structure with the second metal layer m2. Optionally, a third metal layer m3 is further included on the side of the second metal layer m2 facing away from the substrate 00. Another metal layer can be set on the side of the third metal layer m3 facing away from the substrate according to actual needs. The present disclosure does not make specific restrictions on this, and each metal layer can be used to lay signal lines.

[0055] Figure 6 A plan view of a display panel 100' in the related art is shown, the display panel has a length along a first direction D1 larger than a length along a second direction D2, scan lines SL' extend along the second direction D2 and are arranged along the first direction D1, and data lines DL' extend along the first direction D1 and are arranged along the second direction D2. When data is refreshed, a scan mode is that the scan lines SL' are scanned row by row along the longitudinal direction (the first direction D1), which is equivalent to longitudinal screen scanning. When the number of pixel circuits connected by a scan line SL' is less than the number of a column of pixel circuits, the number of pixel circuits scanned by a scan line SL' in a single scan is small and the number of scans is large, which is not conducive to improving refresh efficiency. If the extension direction and the arrangement direction of the scan lines SL' and the data lines DL' are exchanged, the scan lines SL' extend along the first direction D1 and are arranged along the second direction D2, and the data lines DL' extend along the second direction D2 and are arranged along the first direction D1. When data is refreshed, a scan mode is that the scan lines SL' are scanned column by column along the transverse direction, which is equivalent to transverse screen scanning. At this time, a scan line scans a column of pixel driving circuits with a large number of pixel driving circuits in a single scan, and the number of scans is small, which is conducive to improving refresh efficiency. However, for a display panel in a transverse screen scanning mode, the number of data lines is usually large. If the data lines are all connected from the lower frame area of the display panel, the lower frame area of the display panel will have a large number of wirings, which is not conducive to realizing a narrow frame design of the display panel. Even if a multiplexing unit is introduced in the lower frame area of the display panel, it is still difficult to realize a narrow lower frame design because the multiplexing unit and the bonding pads connected to the multiplexing unit also occupy the space of the lower frame.

[0056] Based on the problems in the related art, the display panel in the embodiments of the present disclosure introduces a transverse screen scanning mode, please refer to Figure 1 and Figure 2 , the driving control lines SL extend along the first direction D1 and are arranged along the second direction D2, and the data lines DL extend along the second direction D2 and are arranged along the first direction D1. It should be noted that the viewing angle and the display mode of the display panel in the transverse screen scanning mode are the same as those of a conventional display panel, but the arrangement modes of the driving control lines SL and the data lines DL are different. Taking a mobile phone as an example, the longitudinal length is larger than the transverse length. In the display panel in the transverse screen scanning mode, the driving control lines SL extend along the longitudinal direction, and the data lines DL extend along the transverse direction. The number of data lines DL is large, and the number of columns of pixel circuits is less than the number of rows of pixel circuits. When data is refreshed, a driving control line SL scans a column of pixel driving circuits in a single scan, and because the number of columns of pixel circuits is small, the number of columns of pixel circuits that need to be scanned in a frame time is small, which is conducive to improving the overall refresh efficiency and is conducive to realizing high-frequency driving. Figure 7Fig. 1 shows a schematic diagram of an arrangement of a pixel driving circuit in an embodiment of the present disclosure, Figure 8 Fig. 2 shows a relative position relationship diagram of a pixel driving circuit, a driving control line, a data line and a sub-pixel, for reference Figure 7 and Figure 8 For a landscape scanning display panel, the display panel 100 can alternatively include a plurality of pixel circuit rows L0 arranged along a first direction D1 and a plurality of pixel circuit columns L1 arranged along a second direction D2, the pixel circuit rows L0 and the pixel circuit columns L1 each include a plurality of pixel driving circuits 19, and the number of pixel circuit rows L0 included in the display panel is greater than the number of pixel circuit columns L1. The pixel driving circuits 19 corresponding to each pixel circuit row L0 are electrically connected to the same data line DL, and the pixel driving circuits 19 in each pixel column L1 are electrically connected to the driving control line SL. For a landscape scanning display panel, the number of pixel circuit rows L0 is large, and the number of required data lines DL will also be large; when the number of pixel circuit columns L1 is small, the driving control line SL only needs to scan a small number of pixel circuit columns L1, thereby facilitating high-frequency driving. Alternatively, for reference Figure 8 , the display panel includes first pixel columns L11 and second pixel columns L12 arranged alternately along the second direction D2, the first pixel columns L12 include first color sub-pixels P1 and second color sub-pixels P2 arranged alternately along the first direction D1, and the second pixel columns L12 include third color sub-pixels P3 arranged along the first direction D1. Assuming that the first pixel columns L11 and the second pixel columns L12 adjacent along the second direction D2 constitute a pixel column group L00, the pixel circuits 19 corresponding to the sub-pixels in the same pixel column group L00 can be located in the same pixel circuit column L1, and the same driving control line SL can be used to scan different pixel circuits 19 in the same pixel circuit column L1.

[0057] For reference Figure 1 and Figure 2 , the present disclosure further adjusts the positions of the multiplexing unit 90 and the non-display area where the binding pad P0 is located, for reference Figure 1 and Figure 2When the drive control lines SL extend along the first direction D1 and are arranged along the second direction D2, and the data lines DL extend along the second direction D2 and are arranged along the first direction D1, the multiplexing unit 90 and the bonding pads P0 are respectively arranged in the non-display area A1 on different sides of the display area A0. The multiplexing unit 90 is located in the first non-display area A11 in the direction in which the data lines DL extend, and the bonding pads P0 are located in the second non-display area A12 in the direction in which the drive control lines SL extend. In this way, the bonding pads P0 and the multiplexing unit 90 are arranged in different non-display areas A1, avoiding their centralized arrangement in the same non-display area A1, thereby facilitating a narrow-frame design for the display panel. In addition, the embodiment of the present disclosure sets the multiplexing unit 90 and the binding pad P0 separately. Even if the number of data lines DL and the multiplexing unit 90 is increased, since the driving control line SL does not extend to the second non-display area A12, and the multiplexing unit 90 does not occupy the space of the second non-display area A12, it will not have a significant impact on the space of the border area where the second non-display area A12 is located. It is also conducive to realizing a narrow border design of the display product and improving the screen-to-body ratio of the display product.

[0058] In the present disclosure, when the multiplexing unit 90 and the bonding pad P0 are respectively disposed in the non-display area A1 on different sides of the display area A0, a first input line 20 is introduced into the display panel to achieve electrical connection between the multiplexing unit 90 and the bonding pad P0. At least a portion of the first input line 20 is located in the display area A0. That is, the first input line 20 is electrically connected to the multiplexing unit 90 in the first non-display area A11, extends to the display area A0, is routed in the display area A0, and then further extends from the display area A0 to the second non-display area A12 to electrically connect to the bonding pad P0. In this way, most of the line segments of the first input line 20 will not occupy the width of the first non-display area A11 of the display panel, thereby not affecting the width of the border where the first non-display area A11 is located. This also facilitates a narrow border design in the area where the first non-display area A11 is located.

[0059] Optionally, please continue to refer to Figure 1 and Figure 2The display panel further comprises at least two gate control lines Mux corresponding to the multiplexing units 90, a single multiplexing unit 90 comprises at least N switch elements T, the control ends of different switch elements T in the same multiplexing unit 90 are connected to different gate control lines Mux, the output ends of the switch elements T are electrically connected to the data lines DL one by one, for transmitting the data signal to the data lines DL, the input ends of different switch elements in the same multiplexing unit 90 are connected to the same first input line 20, the first input line 20 is electrically connected to the binding pad P0 in the binding area A13, and the data signal is obtained through the binding pad P0. The number of the first input line 20 is 1 / N of the total amount of the data lines DL, compared with the mode that the data signal line is directly electrically connected to the binding pad P0, the number of the binding pad P0 can be greatly reduced after the multiplexing unit 90 is introduced, thereby being beneficial to simplifying the design of the control chip bound with the binding pad P0 or the design of the flexible circuit board, and simplifying the overall design of the display product.

[0060] Please continue to refer to Figure 1 In an optional embodiment of the present disclosure, the first input line 20 comprises electrically connected first and second connection lines 21 and 22, the first connection line 21 extends along the second direction D2 and is connected to the input end of the multiplexing unit 90, and the second connection line 22 extends along the first direction D1 and is connected to the binding pad P0 in the binding area A13.

[0061] The embodiment further illustrates the wiring mode of the first input line 20 in the display panel. Specifically, the first connection line 21 included in the first input line 20 is used to be directly connected with the input end of the multiplexing unit 90, and the extension direction of the first connection line 21 is the same as the extension direction of the data line DL. The second connection line 22 included in the first input line 20 has the same extension direction as the driving control line SL. One end of the second connection line 22 is connected with the first connection line 21, and the other end is connected with the bonding pad P0. Alternatively, part of the first connection line 21 mentioned in the embodiment is located in the first non-display area A11, and part of the first connection line 21 is located in the display area A0. Part of the second connection line 22 is located in the display area A0, and part of the second connection line 22 is located in the second non-display area A12. Alternatively, the second non-display area A12 can further include a fan-out line (not shown in the figure) located between the bonding area A13 and the display area A0. The second connection line 22 can be further electrically connected with the bonding pad P0 in the bonding area A13 through the fan-out line. Alternatively, the first connection line 21 and the second connection line 22 in the first input line 20 can be located in the same film layer, or can be located in different film layers, which is not limited in the disclosure. When the first connection line 21 and the second connection line 22 are introduced in the display area A0 in the embodiment, the extension direction of the first connection line 21 and the second connection line 22 is adapted to the extension direction of the existing signal line in the display area A0, which is beneficial to simplify the overall wiring difficulty and improve the visual effect of the display panel. Moreover, the wiring of the first connection line 21 and the second connection line 22 in the display area A0 to be connected to the second non-display area A12 is beneficial to reduce the wiring in the non-display area A1 and realize the narrow frame design of the non-display area A1, compared with the wiring mode of winding from the first non-display area A11 of the display panel to the second non-display area A12 along the non-display area A1.

[0062] Please refer to Figure 1 and Figure 5 In an optional embodiment of the disclosure, when the extension direction of the first connection line 21 is the same as the extension direction of the data line DL, i.e., both extend along the second direction D2, the first connection line 21 is arranged in the same layer as the data line DL. In this way, the manufacturing of the first connection line 21 and the data line DL can be completed in the same manufacturing process, without introducing different manufacturing processes for the first connection line 21 and the data line DL, which is beneficial to simplify the manufacturing process of the display panel and improve the production efficiency. Alternatively, the first connection line 21 and the data line DL can be located Figure 5 The second metal layer m2 mentioned in the embodiment shown in the figure can also be arranged in the third metal layer m3 or other feasible metal layer according to the need, which is not limited in the disclosure.

[0063] Please continue to refer to Figure 1 and Figure 5In an optional embodiment of the present disclosure, when the extending direction of the first connecting line 21 is the same as the extending direction of the data line DL, i.e., both extend along the second direction D2, the first connecting line 21 and the data line DL can also be arranged in different layers, and the first connecting line 21 and the data line DL do not overlap in the direction perpendicular to the light-out surface of the display panel. For example, the data line DL can be arranged in the second metal layer m2 of the film layer shown in the figure, and the first connecting line 21 can be arranged in the third metal layer m3 or the capacitor metal layer mc, etc. When the data line DL and the first connecting line 21 are arranged in different film layers, the embodiment further limits that the two do not overlap in the direction perpendicular to the light-out surface of the display panel, which is beneficial to reduce or avoid the signal coupling between the data line DL and the first connecting line 21, thereby being beneficial to improve the stability of the signals transmitted on the first connecting line 21 and the data line DL. Figure 5 The second metal layer m2 in the film layer shown in the figure, and the first connecting line 21 is arranged in the third metal layer m3 or the capacitor metal layer mc, etc. When the data line DL and the first connecting line 21 are arranged in different film layers, the embodiment further limits that the two do not overlap in the direction perpendicular to the light-out surface of the display panel, which is beneficial to reduce or avoid the signal coupling between the data line DL and the first connecting line 21, thereby being beneficial to improve the stability of the signals transmitted on the first connecting line 21 and the data line DL.

[0064] Figure 9 Another planar schematic diagram of the display panel provided by the embodiment of the present disclosure is shown in the figure, Figure 10 A relative position reference schematic diagram of part of the first auxiliary line L1 and part of the first connecting line 21 in the display panel is shown in the figure. It should be noted that, in order to clearly distinguish the first auxiliary line L1 and the first connecting line 21, Figure 10 The embodiment shown in the figure schematically shows the first auxiliary line L1 by using a dashed line, which does not represent the actual structure of the first auxiliary line L1. Please refer to Figure 9 and Figure 10 In an optional embodiment of the present disclosure, the display panel further includes a plurality of first auxiliary lines L1 extending along the second direction D2, the first auxiliary line L1 and the first connecting line 21 are arranged in the same layer and are insulated; along the first direction D1, the spacing between adjacent first auxiliary lines L1 is S01, and the spacing between adjacent first auxiliary lines L1 and the first connecting line 21 is S02, S01=S02.

[0065] In the present disclosure, when the multiplexing unit 90 and the binding pad P0 are arranged in the non-display area A1 on different sides of the display area A0, a first input line 20 needs to be introduced in the display panel to realize the electrical connection between the multiplexing unit 90 and the binding pad P0 in the binding area A13. The first input line 20 includes a first connection line 21 extending along the second direction D2, which is equivalent to a newly introduced signal line in the display area A0. When the first connection line 21 is introduced only in part of the display area A0, it may cause uneven metal distribution in the display panel, affecting the display effect. Therefore, in the present embodiment, a first auxiliary line L1 is introduced in the display panel at the same layer as the first connection line 21 and is insulated. The first connection line 21 and the first auxiliary line L1 are arranged uniformly in the film layer where they are located, that is, in the corresponding film layer, the spacing between adjacent traces is equal. In this way, even if the first connection line 21 is introduced in the display area A0, it will not affect the overall wiring uniformity of the display area A0, thereby facilitating the improvement of the overall display uniformity of the display panel. In actual production, the first connection line 21 and the first auxiliary line L1 can be formed at the same time in the same process, avoiding the introduction of different production processes for the first connection line 21 and the first auxiliary line L1, thereby facilitating the simplification of the production process of the display panel and improving the production efficiency.

[0066] Please continue to refer to Figure 9 and Figure 10 To improve the uniformity of metal distribution, in the present disclosure, when the first connection line 21 and the first auxiliary line L1 are introduced at the same time, in an optional embodiment of the present disclosure, at least part of the first auxiliary line L1 is electrically connected with a fixed potential signal. When the first auxiliary line L1 is introduced in the display panel, if the first auxiliary line L1 is floating (not connected with other signals), static electricity may be introduced, affecting the display reliability of the display panel. Therefore, in the present embodiment, when at least part of the first auxiliary line L1 is connected with a fixed potential signal line, the first auxiliary signal line receives a constant potential signal, which is conducive to avoiding the influence of static electricity on the display panel through the first auxiliary line L1.

[0067] It should be noted that the first auxiliary line can be connected with an existing fixed potential signal line in the display panel, for example, it can be connected with a power voltage signal line, or a reset signal line, etc., which is not limited in the present disclosure.

[0068] Please refer to Figure 1 and Figure 3When the first input line 20 is introduced in the display panel to electrically connect the multiplexing unit 90 and the bonding pad P0 in the bonding area A13, the first input line 20 includes a second connection line 22 extending along the first direction D1. In an optional embodiment of the present disclosure, the second connection line 22 is arranged in the same layer as the driving control line SL, or the second connection line 22 is arranged in a layer different from the driving control line SL, and the second connection line 22 does not overlap the driving control line SL along the direction perpendicular to the light-emitting surface of the display panel.

[0069] Since the second connection line 22 has the same extension direction as the driving control line SL, when the second connection line 22 is arranged in the same layer as the driving control line SL, the two can be formed in the same process, without the need to introduce different manufacturing processes respectively, thus being conducive to simplifying the manufacturing process of the display panel and improving production efficiency. When the second connection line 22 is arranged in the same layer as the driving control line SL, the two can be located in the first metal layer m1 of the film layer structure shown in the figure, or in the capacitor metal layer mc, or in other feasible metal film layers, which are not specifically limited by the present disclosure. Figure 5

[0070] In addition, the second connection line 22 and the driving control line SL can also be arranged in different film layers according to actual needs, and the second connection line 22 does not overlap the driving control line SL along the direction perpendicular to the display panel, which is conducive to avoiding the coupling interference between the second connection line 22 and the driving control line SL, and improving the stability of the signals transmitted on the second connection line 22 and the driving control line SL.

[0071] Figure 11 Fig. 4 shows another planar schematic diagram of the display panel provided by the embodiment of the present disclosure, Figure 12 Fig. 5 shows a relative position reference schematic diagram of part of the second auxiliary line L2 and part of the second connection line 22 in the display panel, and it should be noted that, in order to clearly distinguish the second auxiliary line L2 and the second connection line 22, Figure 12 The embodiment shown in the figure represents the second auxiliary line L2 in the form of a dashed line, but it does not represent the actual structure of the second auxiliary line L2. Please refer to Figure 11 and Figure 12 In an optional embodiment of the present disclosure, the display panel further includes a plurality of second auxiliary lines L2 extending along the first direction D1, and the second auxiliary lines L2 are arranged in the same layer as the second connection line 22; along the second direction D2, the spacing between adjacent second auxiliary lines L2 is S11, and the spacing between the adjacent second auxiliary lines L2 and the second connection line 22 is S12, and S11=S12.

[0072] ​In the present disclosure, when the multiplexing unit 90 and the binding pad P0 are arranged in the non-display area A1 on different sides of the display area A0, a first input line 20 needs to be introduced in the display panel to realize the electrical connection between the multiplexing unit 90 and the binding pad P0 in the binding area A13. The first input line 20 includes a second connection line 22 extending along the first direction D1, which is equivalent to a newly introduced signal line in the display area A0. When the second connection line 22 is introduced only in part of the display area A0, it may cause uneven metal distribution in the display panel, affecting the display effect. Therefore, in the present embodiment, a second auxiliary line L2 is introduced in the display panel at the same layer as the second connection line 22 and is insulated. The second connection line 22 and the second auxiliary line L2 are arranged uniformly in the film layer where they are located, that is, in the corresponding film layer, the spacing between adjacent traces is equal. In this way, even if the second connection line 22 is introduced in the display area A0, it will not affect the overall wiring uniformity of the display area A0, thereby facilitating the improvement of the overall display uniformity of the display panel. In actual production, the second connection line 22 and the second auxiliary line L2 can be formed at the same time in the same process, avoiding the introduction of different production processes for the second connection line 22 and the second auxiliary line L2, thereby facilitating the simplification of the production process of the display panel and improving the production efficiency.

[0073] To improve the metal distribution uniformity, when the second connection line 22 and the second auxiliary line L2 are introduced at the same time, in an optional embodiment of the present disclosure, at least one second auxiliary line L2 is electrically connected with a fixed potential signal. When the second auxiliary line L2 is introduced in the display panel, if the second auxiliary line L2 is floating (not connected with other signals), static electricity may be introduced, affecting the display reliability of the display panel. Therefore, in the present embodiment, at least part of the second auxiliary line L2 is connected with a fixed potential signal line, so that the second auxiliary signal line receives a constant potential signal, which is conducive to avoiding the influence of static electricity on the display panel through the second auxiliary line L2.

[0074] It should be noted that the second auxiliary line can be connected with the existing fixed potential signal line in the display panel, for example, it can be connected with the power voltage signal line, or connected with the reset signal line, etc., which is not limited in the present disclosure.

[0075] Please continue to refer to Figure 1 and Figure 2In the plurality of multiplexing units 90 provided by the present disclosure, a single multiplexing unit 90 includes N output terminals, that is, N switching elements T, the output terminals of the switching elements T are electrically connected to the data lines DL one by one, and the input terminals of the N switching elements T in the single multiplexing unit 90 are connected to the same first input line 20 to obtain the data signal through the first input line 20. The ratio of the number of the first input lines 20 to the number of the data lines DL is 1:N, so that the number of the bonding pads P0 coupled to the data lines DL in the binding area A13 can be reduced. In an optional embodiment of the present disclosure, N≤5. The larger the value of N is, the fewer the number of the first input lines 20 introduced in the display panel is, and the more conducive to simplifying the overall manufacturing process. However, it is found through research that if N≥6, under high-frequency driving, the time for the data line DL to write the data signal to the pixel driving circuit is reduced, which causes insufficient charging and may affect the display effect. Therefore, in the embodiments of the present disclosure, the value of N is set to be greater than or equal to 2 and less than or equal to 5, which is conducive to reducing the number of the first input lines 20, simplifying the overall manufacturing process of the display panel, and also conducive to ensuring the normal transmission of the data signal and improving the display accuracy of the display panel. The embodiments of the present disclosure take N=4 as an example for description, and in some other embodiments, N can also be 2, 3 or 5.

[0076] Figure 13 Fig. 4 shows a connection diagram of the multiplexing unit 90 and the data line DL, and a pixel arrangement of the display panel is exemplarily illustrated. Please refer to Figure 13 In an optional embodiment of the present disclosure, the multiplexing unit 90 is connected to the N data lines DL arranged continuously along the first direction D1.

[0077] In the embodiment, the display panel includes first pixel rows L01 and second pixel rows L02 arranged alternately along a first direction D1, the first pixel rows L01 include first color sub-pixels P1 and second color sub-pixels P2, and the first color sub-pixels P1 and the second color sub-pixels P2 are arranged alternately along a second direction D2 in the first pixel rows L01. The second pixel rows L02 only include third color sub-pixels P3, and the third color sub-pixels P3 in the second pixel rows L02 are arranged along the second direction D2. The total number of data lines DL in the display panel is the same as the total number of the first pixel rows L01 and the second pixel rows L02, and the data lines DL include first data lines DL1 and second data lines DL2, wherein the first data lines DL1 are electrically connected to the pixel driving circuits corresponding to the first pixel rows L01, and are used to provide data signals to the pixel driving circuits corresponding to the first color sub-pixels P1 and the second color sub-pixels P2; the second data lines DL2 are electrically connected to the pixel driving circuits corresponding to the second pixel rows L02, and are used to provide data signals to the pixel driving circuits corresponding to the third color sub-pixels P3. The first data lines DL and the second data lines DL are arranged alternately along the first direction D1. Optionally, the first color sub-pixels P1 are red sub-pixels, the second color sub-pixels P2 are blue sub-pixels, and the third color sub-pixels P3 are green sub-pixels. It should be noted that Figure 13 The embodiments shown only exemplify one possible way of pixel arrangement, and do not limit the actual arrangement manner and the shape of the sub-pixels. In some other embodiments of the present disclosure, other possible arrangement manners can also be used.

[0078] Please refer to Figure 1 , Figure 2 , Figure 8 and Figure 13 When the plurality of multiplexing units 90 are introduced into the display panel, the multiplexing units 90 are electrically connected to at least two data lines DL arranged continuously along the first direction D1, Figure 13 The embodiments take the multiplexing units 90 connected to four data lines DL arranged continuously as an example for illustration, for example, the first to fourth data lines DL arranged along the first direction D1 are connected to the first multiplexing unit 90, the fifth to eighth data lines DL arranged along the first direction D1 are connected to the second multiplexing unit 90, and so on. In this way, the connection complexity between the multiplexing units 90 and the data lines DL is simplified. Figure 14 The working timing diagram of the multiplexing unit 90 in Figure 13 is shown, please refer to Figure 13 and Figure 14In the embodiment, the display panel is provided with four gate control lines, namely Mux1, Mux2, Mux3 and Mux4, and the control ends of the four switch elements T in the multiplexing unit 90 are connected to different gate control lines Mux1, Mux2, Mux3 and Mux4. In the display panel, one sub-pixel P is electrically connected to one pixel driving circuit 19, and the corresponding relationship between the sub-pixel and the data line DL is clearly shown, Figure 13 The connection between the sub-pixel P and the data line DL is shown, and actually, the pixel driving circuit 19 corresponding to the corresponding sub-pixel P is connected to the data line DL. Please continue to refer to Figure 13 and Figure 14 During data refreshing, the four gate control lines can send valid level signals in time, so that the four switch elements T in the multiplexing unit 90 are sequentially turned on, and then the first input line 20 is electrically connected to the corresponding data line DL in time.

[0079] For example, when the gate control line Mux1 outputs a valid level signal, the first switch element T in the two multiplexing units 90 is turned on, Figure 13 Among the two first input lines 20, the first input line Source1 will be electrically connected to the first data line DL arranged along the first direction D1, and the second input line Source2 will be electrically connected to the fifth data line DL arranged along the first direction D1. At this time, the signals transmitted on each first input line 20 are all data signals transmitted to the pixel circuits in the first pixel column L11, wherein the first color sub-pixel P1 and the second color sub-pixel P2 in the first pixel column L11 are arranged alternately along the first direction D1, and correspondingly, the two input lines Source1 and Source2 both transmit data signals to the data line DL corresponding to the first color sub-pixel P1 in the first pixel column L11.

[0080] Similarly, when the gate control line Mux2 inputs a valid level signal, the first input line Source1 will be electrically connected to the second data line DL arranged along the first direction D1, and the second input line Source2 will be electrically connected to the sixth data line DL arranged along the first direction D1. Correspondingly, in the second pixel column L12, the two input lines Source1 and Source2 both transmit data signals to the data line DL connected to the third color sub-pixel P3. Among them, in the second pixel column L12, a plurality of third color sub-pixels P3 are arranged alternately along the first direction D1.

[0081] When the active level signal is input to the selection control line Mux3, the first input line Source1 is electrically connected to the third data line DL arranged along the first direction D1, and the second input line Source2 is electrically connected to the seventh data line DL arranged along the first direction D1. In the first pixel column L11, the two input lines Source1 and Source2 both transmit data signals to the data line DL connected to the second color sub-pixel P2.

[0082] When the active level signal is input to the selection control line Mux4, the first input line Source1 is electrically connected to the fourth data line DL arranged along the first direction D1, and the second input line Source2 is electrically connected to the eighth data line DL arranged along the first direction D1. In the second pixel column L12, the two input lines Source1 and Source2 both transmit data signals to the data line DL corresponding to the remaining third color sub-pixel P3.

[0083] In this way, the data signals are sequentially provided to the data lines DL corresponding to the first color sub-pixel P1, the third color sub-pixel P3, the second color sub-pixel P2, and the third color sub-pixel P3 in the first pixel column L11 and the second pixel column L12. After the data signals are written to the corresponding data lines DL, the data writing module in the pixel driving circuit is turned on by the control signal Scan1 or Scan2, and then the data signals are written to the corresponding pixel driving circuit. It should be noted that the time for writing data to the pixel driving circuit can be set according to actual needs, Figure 14 The embodiment shown in the figure takes the start time of the active level signal sent by the selection control line Mux4 as an example to send the active level signal of Scan1 or Scan2 for data writing, but it is not limited thereto.

[0084] Figure 15 The figure shows a connection diagram of the multiplexing unit 90 and the data line DL, and illustrates a pixel arrangement of the display panel, Figure 15 and Figure 13 the pixel arrangement in the figure, and this embodiment will not be described again. In an optional embodiment of the present disclosure, the plurality of multiplexing units 90 includes a first multiplexing unit 91 and a second multiplexing unit 92. The first multiplexing unit 91 is connected to the N odd-numbered data lines DL arranged adjacent to each other along the first direction D1, and the second multiplexing unit 92 is connected to the N even-numbered data lines DL arranged adjacent to each other along the first direction D1.

[0085] Figure 15 The difference between the embodiment shown in Figure 13 The difference between the embodiment shown in Figure 15 In the embodiment shown, the first multiplexing unit 91 and the second multiplexing unit 92 are alternately arranged along the first direction D1, the first multiplexing unit 91 is connected with the first odd data line DL among the N continuous data lines, for example, Figure 15 The embodiment shows that the first multiplexing unit 91 is connected with the first, third, fifth and seventh data lines DL arranged along the first direction D1; the second multiplexing unit 92 is connected with the first even data line DL among the N continuous data lines, for example, Figure 15 The embodiment shows that the second multiplexing unit 92 is connected with the second, fourth, sixth and eighth data lines DL arranged along the first direction D1. Figure 16 The timing diagram of the multiplexing unit 90 in Figure 15 The difference between the timing diagram shown in Figure 15 is that the starting time of the write data is different, but the timing shown in Figure 14 may also be used, Figure 13 The corresponding embodiment can also use the timing of Figure 16 The present disclosure does not make specific limitations on this. In the display panel, one sub-pixel P is electrically connected with one pixel driving circuit 19, to clearly show the corresponding relationship between the sub-pixel and the data line DL, Figure 15 The connection between the sub-pixel P and the data line DL is shown schematically, and in fact, the pixel driving circuit 19 corresponding to the corresponding sub-pixel P is connected with the data line DL.

[0086] Please refer to Figure 15 and Figure 16 In the embodiment, the display panel is provided with four gate control lines, namely Mux1, Mux2, Mux3 and Mux4, and the control ends of the four switching elements in the multiplexing unit 90 are connected to different gate control lines. The four gate control lines can send effective level signals in time, so that the four switching elements in the multiplexing unit 90 are sequentially turned on, and then the first input line 20 is electrically connected with the corresponding data line DL in time.

[0087] For example, when the active level signal is output by the selection control line Mux1, the first switch element T in the first of the two multiplexing units 90 is turned on, and the first data line DL connected to the first multiplexing unit 91 and the second data line DL connected to the second multiplexing unit 92 receive the data signals transmitted by the first input line Source1 and Source2, respectively. Taking the first pixel column L11 and the second pixel column L22 as examples, the data line DL corresponding to the first color sub-pixel P1 in the first row in the first pixel column L11 and the third color sub-pixel P3 in the first row in the second pixel column L12 receive the data signals. Figure 13 or Figure 15 On the basis of the above, the data lines DL arranged from top to bottom in the first direction D1 are arranged in sequence from top to bottom as the first, second, …, and eighth data lines.

[0088] Similarly, when the active level signal is output by the selection control line Mux2, the second switch element T in the first of the two multiplexing units 90 is turned on, and the third data line DL connected to the first multiplexing unit 91 and the fourth data line DL connected to the second multiplexing unit 92 receive the data signals transmitted by the first input line Source1 and Source2, respectively. Taking the first pixel column L11 and the second pixel column L22 as examples, the data line DL corresponding to the second color sub-pixel P2 in the second row in the first pixel column L11 and the third color sub-pixel P3 in the second row in the second pixel column L12 receive the data signals.

[0089] When the active level signal is output by the selection control line Mux3, the third switch element T in the first of the two multiplexing units 90 is turned on, and the fifth data line DL connected to the first multiplexing unit 91 and the sixth data line DL connected to the second multiplexing unit 92 receive the data signals transmitted by the first input line Source1 and Source2, respectively. Taking the first pixel column L11 and the second pixel column L22 as examples, the data line DL corresponding to the first color sub-pixel P1 in the third row in the first pixel column L11 and the third color sub-pixel P3 in the third row in the second pixel column L12 receive the data signals.

[0090] When the selected pass-through control line Mux4 outputs a valid level signal, the fourth switch element T in the two multiplexing units 90 is turned on, the seventh data line DL connected with the first multiplexing unit 91 and the eighth data line DL connected with the second multiplexing unit 92 receive the data signals transmitted by the first input line Source1 and Source2 respectively, taking the first pixel column L11 and the second pixel column L22 as examples, the data lines DL corresponding to the second color sub-pixel P2 in the fourth row in the first pixel column L11 and the third color sub-pixel P3 in the fourth row in the second pixel column L12 receive the data signals.

[0091] In this way, the first input line Source1 connected with the first multiplexing unit 91 is only used for transmitting data signals to the first color sub-pixel P1 or the second color sub-pixel P2, and the first input line Source2 connected with the second multiplexing unit 92 is only used for transmitting data signals to the third color sub-pixel P3, which is conducive to reducing the overall power consumption of the display panel.

[0092] Figure 17 Another plane schematic diagram of the display panel provided by the embodiment of the present disclosure is shown, please refer to Figure 17 In an optional embodiment of the present disclosure, the display panel further comprises a gate driving circuit 80, the gate driving circuit 80 is electrically connected with the driving control line SL, and the gate driving circuit 80 is located in the first non-display area A11; the gate driving circuit 80 is electrically connected with the driving control line SL through a second input line 82, the second input line 82 extends along the second direction D2 and is arranged in a layer different from the driving control line SL, and the second input line 82 is at least partially located in the display area A0.

[0093] In the embodiment of the present disclosure, the gate driving circuit 80 is located in the first non-display area A11, and the first non-display area A11 is located on both sides of the display area A0 along the second direction D2. Considering that the driving control line SL extends along the first direction D1, the gate driving circuit 80 is not located in the extension direction of the driving control line SL. Therefore, in the embodiment of the present disclosure, the second input line 82 extending along the second direction D2 is introduced into the display panel for connecting the corresponding driving control line SL and the gate driving circuit 80, and the second input line 82 is at least partially located in the display area A0. Since the purpose of the second input line 82 is to electrically connect the driving control line SL extending along the first direction D1 and the gate driving circuit 80 located in the first non-display area A11, most of the line segments of the second input line 82 are located in the display area A0, and the space occupied by the second input line 82 in the first non-display area A11 is relatively small. Therefore, even if the second input line 82 is introduced into the display panel, it will not affect the width of the first non-display area A11, which is conducive to realizing the narrow frame design of the display panel.

[0094] It should be noted that the number of driving control lines SL and gate driving circuits 80 shown in the drawings of the present disclosure is only illustrative, and does not limit the actual number of driving control lines SL and gate driving circuits 80 contained in the display panel.

[0095] Please refer to Figure 17 and Figure 5 When the second input line 82 is introduced in the display panel to realize the electrical connection of the driving control line SL and the gate driving circuit 80, in an optional embodiment of the present disclosure, the second input line 82 is arranged in the same layer as the data line DL. Considering that the extension direction of the second input line 82 is the same as that of the data line DL, when they are arranged in the same metal layer, in this way, the second input line 82 and the data line DL can be formed in the same manufacturing process, without introducing different manufacturing processes for the two, and without introducing a new film layer structure for the second input line 82, so as to be beneficial to simplify the manufacturing process and the film layer structure of the display panel, and to improve the production efficiency. Alternatively, the second input line 82 and the data line DL can be located in the second metal layer m2 or the third metal layer m3, and can also be located in other feasible metal film layers, which are not limited in the present disclosure. It should be noted that when the second input line 82 and the data line DL are arranged in the same film layer, the second input line 82 is arranged between adjacent data lines DL. Alternatively, the number of data lines DL contained between every two second input lines 82 is the same or close to the same, so that the second input line 82 and the data line DL are as evenly distributed as possible, thereby being beneficial to improve the overall display uniformity of the display panel.

[0096] Of course, in some other embodiments of the present disclosure, when the second input line 82 is introduced in the display panel to realize the electrical connection of the driving control line SL and the gate driving circuit 80, the second input line 82 can also be arranged in different layers from the data line DL, and the second input line 82 and the data line DL do not overlap in the direction perpendicular to the light-emitting surface of the display panel. In this way, it is beneficial to avoid signal coupling between the second input line 82 and the data line DL, and to improve the accuracy of signal transmission on the second input line 82 and the data line DL. When the second input line 82 and the data line DL are arranged in different film layers, the data line DL can be arranged in the second metal layer m2 in the film layer shown in Figure 5 , and the second input line 82 can be arranged in the third metal layer m3 or other feasible film layers such as the capacitor metal layer mc, which are not limited in the present disclosure.

[0097] It should be noted that when the second input line 82 and the data line DL are arranged in different layers, a third auxiliary line L3 arranged in the same layer as the second input line 82 can also be introduced, for example, please refer to Figure 18 , Figure 18As shown in the layout diagram of the second input line 82 and the third auxiliary line L3, for the purpose of distinguishing the second input line 82 from the third auxiliary line L3, the third auxiliary line L3 is shown in a dashed line form in this embodiment, but the actual structure of the third auxiliary line L3 is not limited. The second input line 82 and the third auxiliary line L3 both extend along the second direction D2 and are arranged along the first direction D1, the interval between adjacent second input lines 82 and the interval between adjacent third auxiliary lines L3 are equal, so that the second input line 82 and the third auxiliary line L3 are uniformly arranged in the metal film layer, thereby facilitating the improvement of the overall display uniformity of the display panel.

[0098] Figure 19 As shown in the layout diagram of the first input line 20 and the second input line 82 in the display panel, please refer to Figure 19 In an optional embodiment of the present disclosure, the second input line 82 is arranged in the same layer as the first connection line 21; at least part of the second input line 82 is located in the extension direction of the first connection line 21, and along the second direction D2, the first connection line 21 and the second input line 82 located in the extension direction thereof have a first interval JG.

[0099] When the first input line 20 is introduced in the display panel to realize the electrical connection between the multiplexing unit 90 and the binding pad P0, and the second input line 82 is introduced to realize the electrical connection between the gate driving circuit 80 and the driving control line SL, the second input line 82 and the first connection line 21 in the first input line 20 both extend along the second direction D2, at this time, when the second input line 82 and the first connection line 21 are laid out, part of the second input line 82 can be laid out in the extension direction of the first connection line 21, in actual production, a signal line extending along the second direction D2 can be broken to obtain two line segments, the two line segments are insulated by the first interval, and the two line segments are the second input line 82 and the first connection line 21 respectively, this arrangement can complete the production of the second input line 82 and the first connection line 21 in one production process, which is conducive to simplifying the production process, and can also reasonably utilize the wiring space of the display panel and improve the space utilization.

[0100] Figure 20 and Figure 21 As shown in another planar layout diagram of the display panel provided by the embodiments of the present disclosure, please refer to Figure 20 and Figure 21 In an optional embodiment of the present disclosure, the display area A0 includes the first display area A01, the third display area A03 and the second display area A02 arranged in sequence along the direction away from the second non-display area A12; the gate driving circuit 80 is located in the first non-display area A11 adjacent to the third display area A03 and / or the second display area A02.

[0101] In the embodiment, the display area A0 is divided into three display areas A0 arranged in sequence along the first direction D1, wherein the display area A0 adjacent to the second non-display area A12 is the first display area A01, the display area A0 farthest from the second non-display area A12 is the second display area A02, and the display area A0 between the first display area A01 and the second display area A02 is the third display area A03, that is, the second display area A02 and the third display area A03 are located on the side of the first display area A01 away from the second non-display area A12, and the first non-display area A11 adjacent to the second display area A02 and the third display area A03 is also far from the second non-display area A12. Figure 20 The embodiment shown shows a scheme of arranging the gate drive circuit 80 in the first non-display area A11 adjacent to the second display area A02, so that the gate drive circuit 80 will not occupy the space of the first non-display area A11 adjacent to the first display area A01 and the third display area A03, and this part of space can be used for the layout of other structures, for example, global signal lines such as power signal lines for transmitting global signals can be arranged in this part of space, which will be specifically described in subsequent embodiments. Figure 21 The embodiment shown shows a scheme of arranging the gate drive circuit 80 in the first non-display area A11 adjacent to the second display area A02 and the third display area A03, so that the gate drive circuit 80 will not occupy the space of the first non-display area A11 adjacent to the first display area A01, and this part of space can be used for power signal lines and other global signal lines for transmitting global signals. When the gate drive circuit 80 is avoided in the first non-display area A11 adjacent to the first display area A01, or in the first non-display area A11 adjacent to the first display area A01 and the third display area A03, the space released can be used to arrange the global signal lines as described above, so as to increase the area occupied by this type of signal line in the display panel, reduce the impedance of this part of signal line, and thus be beneficial to improve the voltage drop of the signal transmitted by this part of signal line. It should be noted that, Figure 20 and Figure 21 The embodiments shown respectively show a scheme of arranging the gate drive unit 80 in the first non-display area A11 adjacent to the second display area A02, and a scheme of arranging the gate drive unit 80 in the first non-display area A11 adjacent to the third display area A03, in some other embodiments of the present disclosure, the gate drive unit 80 can also be located in the first non-display area A11 adjacent to the second display area A02 and the first non-display area A11 adjacent to the third display area A03 at the same time.

[0102] Please continue to refer to Figure 20 and Figure 21In an optional embodiment of the present disclosure, at least part of the second input line 82 is located in the third display area A03 and / or the second display area A02. When the gate drive circuit 80 is located only in the first non-display area A11 adjacent to the second display area A02, the second input line 82 can be routed in the second display area A02, and extended from the second display area A02 to the first non-display area A11 adjacent to the second display area A02 to achieve connection with the gate drive circuit 80. In this way, the second input line 82 can achieve the connection without or with less winding, which is conducive to simplifying the manufacturing process. Similarly, when the gate drive circuit 80 is located in the first non-display area A11 adjacent to the second display area A02 and the third display area A03, the second input line 82 can be routed in the second display area A02 and the third display area A03, respectively, and extended from the second display area A02 and the third display area A03 to the first non-display area A11 adjacent to the second display area A02 and the third display area A03 to achieve connection with the gate drive circuit 80. Similarly, this is conducive to reducing the winding of the second input line 82, and thus is also conducive to simplifying the manufacturing process.

[0103] For reference Figure 20 and Figure 21 In an optional embodiment of the present disclosure, along the second direction D2, the gate drive circuit 80 is arranged opposite to the multiplexing unit 90 in different first non-display areas A11. When the gate drive circuit 80 is introduced in the display panel, the gate drive circuit 80 can be arranged in the first non-display area A11 while the gate drive circuit 80 and the multiplexing unit 90 are arranged on two sides of the display area A0 along the second direction D2. In this way, it is conducive to reasonably arranging the space of the first non-display area A11 on both sides of the display area A0, making the widths of the two first non-display areas A11 consistent or close to consistent, and thus is conducive to improving the overall visual effect of the display panel.

[0104] The above embodiments show the manner of electrically connecting the drive control line SL with one gate drive circuit 80. In some other embodiments of the present disclosure, one drive control line SL can also be electrically connected with two gate drive circuits 80, and the two gate drive circuits 80 provide drive signals to the same drive control line SL. For example, please refer to Figure 22 , Figure 22Fig. 6 shows another plan view of the display panel provided by the embodiment of the present disclosure. Optionally, the gate driving circuit 80 comprises a first driving circuit group Z1 and a second driving circuit group Z2, the first driving circuit group Z1 comprises a plurality of first driving circuits 801, the second driving circuit group Z2 comprises a plurality of second driving circuits 802, and at least one driving control line SL is electrically connected with the first driving circuit 801 and the second driving circuit 802. Specifically, the embodiment shows a scheme of introducing two sets of driving circuits in the display panel, the driving control line SL is connected with the first driving circuit 801 and the second driving circuit 802, and the first driving circuit 801 and the second driving circuit 802 can simultaneously provide driving signals to the corresponding driving control line SL, which is conducive to improving the driving capability of the gate driving circuit 80 as a whole.

[0105] Please continue to refer to Figure 22 In an optional embodiment of the present disclosure, the display area A0 comprises a first display area A01, a third display area A03 and a second display area A02 arranged in sequence in a direction away from the second non-display area A12; the first driving circuit group Z1 and the second driving circuit group Z2 are respectively located in the first non-display area A11 arranged oppositely on two sides of the third display area A03 and / or the second display area A02 along the second direction D2. When the first driving circuit group Z1 and the second driving circuit group Z2 are introduced in the display panel, the first driving circuit group Z1 and the second driving circuit group Z2 can be respectively arranged on the opposite sides of the display area A0 along the second direction D2, for example, the first driving circuit group Z1 is located in the first non-display area A11 opposite to the multiplexing unit 90, and the second driving circuit group Z2 is arranged in the first non-display area A11 on the same side of the display area A0 as the multiplexing unit 90. The arrangement of the first driving circuit group Z1 and the second driving circuit group Z2 on the two sides of the display area is conducive to reasonably arranging the space of the first non-display area A11, and avoiding that more peripheral circuits are arranged in the first non-display area A11 on one side to affect the narrow frame design. In addition, when the first driving circuit group Z1 and the second driving circuit group Z2 are introduced, the first non-display area A11 where the first driving circuit 801 and the second driving circuit group Z2 are located is adjacent to the second display area A02 and / or the third display area A03, rather than being adjacent to the first display area A01, so that other line structures can be arranged in the first non-display area A11 adjacent to the first display area A01 to reasonably utilize the space of the first non-display area A11 of the display panel and improve the space utilization of the display panel.

[0106] Figure 23 Fig. 7 shows another plan view of the display panel provided by the embodiment of the present disclosure. Compared with the embodiment shown in Fig. 6, the difference between the embodiments lies in the area where the gate driving circuit 80 is located in the first non-display area A11. Figure 22

[0107] Please refer to​Figure 23 In an optional embodiment of the present disclosure, the display area A0 includes the first display area A01, the third display area A03 and the second display area A02 arranged in sequence in the direction away from the second non-display area A12; the first drive circuit group Z1 is located at one side of the second display area A02 along the second direction D2, and along the second direction D2, the first drive circuit group Z1 is arranged on the different side of the display area A0 opposite to the multiplexing unit 90; the second drive circuit group Z2 is located at one side of the first display area A01 along the second direction D2, and along the second direction D2, the second drive circuit group Z2 is located on the same side of the display area A0 as the multiplexing unit 90.

[0108] When the first drive circuit group Z1 and the second drive circuit group Z2 are introduced in the display panel, and the drive control line SL is electrically connected with the first drive circuit 801 in the first drive circuit group Z1 and the second drive circuit 802 in the second drive circuit group Z2, the embodiment shows that the first drive circuit group Z1 is arranged in the first non-display area A11 adjacent to the second display area A02 and arranged on the different side of the display area A0 opposite to the multiplexing unit 90, and the second drive circuit group Z2 is arranged in the first non-display area A11 adjacent to the first display area A01 and located on the same first non-display area A11 as the multiplexing unit 90. At this time, the second input line 82 connected with the first drive circuit group Z1 is located in the second display area A02, and the second input line 82 can be electrically connected with the end of the drive control line SL away from the second non-display area A12, and the second input line 82 connected with the second drive circuit group Z2 is located in the first display area A01, and the second input line 82 can be electrically connected with the end of the drive control line SL close to the second non-display area A12, in this way, the first drive circuit 801 in the first drive circuit group Z1 transmits the drive signal to the drive control line SL from the end of the drive control line SL away from the second non-display area A12, and the second drive circuit 802 in the second drive circuit group Z2 transmits the drive signal to the drive control line SL from the end of the drive control line SL close to the second non-display area A12, in this way, it is beneficial to reduce the difference of the drive signals received by different areas on the drive control line SL, and it is beneficial to improve the consistency of the driving effect of the drive control line SL on the pixel driving circuit connected therewith.

[0109] Please continue to refer to Figure 23In an optional embodiment of the present disclosure, the second input line 82 comprises a first sub-line 821 and a second sub-line 822, the first driving circuit 801 is electrically connected with the driving control line SL through the first sub-line 821, and the second driving circuit 802 is electrically connected with the driving control line SL through the second sub-line 822; at least part of the first sub-line 821 is located in the second display area A02, and at least part of the second sub-line 822 is located in the first display area A01. When the first driving circuit group Z1 is arranged in the first non-display area A11 adjacent to the second display area A02, at least part of the first sub-line 821 is routed in the second display area A02, which is beneficial to simplify the connection between the first sub-line 821 and the first driving circuit 801, reduce or avoid the winding of the first sub-line 821, and also make the first sub-line 821 connected with the end of the driving control line SL away from the second non-display area A12, so as to input the driving signal to the driving control line SL from the end of the driving control line SL away from the second non-display area A12. Similarly, when the second driving circuit group Z2 is arranged in the first non-display area A11 adjacent to the first display area A01, at least part of the second sub-line 822 is routed in the first display area A01, which is beneficial to simplify the connection between the second sub-line 822 and the second driving circuit 802, reduce or avoid the winding of the second sub-line 822, and also make the second sub-line 822 connected with the end of the driving control line SL close to the second non-display area A12, so as to input the driving signal to the driving control line SL from the end of the driving control line SL close to the second non-display area A12. In this way, the first sub-line 821 and the second sub-line 822 cooperate to provide the driving signal from both ends of the driving control line SL, thereby being beneficial to improve the uniformity of the driving signal transmitted on the driving control line SL and improve the driving uniformity of the driving control line SL on the pixel driving circuit connected therewith.

[0110] Figure 24 A layout schematic diagram of a power signal line and a gate driving circuit 80 in a display panel is shown. Please refer to Figure 24In an optional embodiment of the present disclosure, the display area A0 includes the first display area A01, the third display area A03 and the second display area A02 arranged in sequence in a direction away from the second non-display area A12; at least part of the gate drive circuit 80 is located in the first non-display area A11 adjacent to the second display area A02 and / or the third display area A03, and the gate drive circuit 80 is arranged on both sides of the display area A0 opposite to the multiplexing unit 90 in the second direction D2; the display panel further includes a power supply sub-line 71 and a power supply bus 72 electrically connected to the power supply sub-line 71, at least part of the power supply sub-line 71 is located in the display area A0, and the power supply bus 72 is located in the non-display area A1; at least part of the power supply bus 72 is located in the same first non-display area A11 as the gate drive circuit 80, and the power supply bus 72 is located between the gate drive circuit 80 and the second non-display area A12 in the first direction D1. Optionally, the power supply bus 72 and the power supply sub-line 71 mentioned in the present embodiment can correspond to the positive power supply signal line PVDD in the display panel, and optionally, the display panel further includes a negative power supply signal line PVEE. It should be noted that when the negative power supply signal line PVEE is introduced in the display panel, the negative power supply signal line PVEE can be located on the side of the power supply bus 72 close to the edge of the display panel in the non-display area.

[0111] The power supply sub-line 71 mentioned in the present embodiment can be routed in the display area A0, for example, to form a grid-shaped routing structure for providing power supply signals to the pixel driving circuit, which is beneficial to reduce the total impedance of the power supply line and reduce the difference in the power supply signals transmitted by the power supply sub-lines 71 in different areas of the display panel. The present disclosure further introduces a power supply bus 72 in the non-display area A1 for providing power supply signals to the power supply sub-lines 71 in the display area A0, and the line width of the power supply bus 72 is greater than that of the power supply sub-line 71. When the gate drive circuit 80 is arranged in the first non-display area A11 adjacent to the second display area A02 and / or the third display area A03, there will be a space between the gate drive circuit 80 and the second non-display area A12 to arrange the power supply bus 72, so that a power supply bus 72 with a larger area can be arranged in the non-display area A1, thereby reducing the overall impedance of the power supply bus 72 and the power supply sub-line 71, improving the rate of power supply signal transmission from the power supply bus 72 to the power supply sub-line 71, reducing the difference in power supply signals received by the pixel driving circuits in different areas, and improving the overall display uniformity of the display panel.

[0112] Based on the same inventive concept, the present disclosure also provides a display device, Figure 25 As shown is a structural schematic diagram of a display device provided by an embodiment of the present disclosure, please refer to Figure 25The display device 200 includes the display panel 100 of any of the above-mentioned embodiments. The display device 200 provided in the embodiments of the present disclosure can be any electronic device with a display function, such as a tablet computer with touch and display functions, a display product in a display cabinet, a mobile phone, a television, or an in-vehicle display device. The display device 200 provided in the embodiments of the present disclosure has the beneficial effects of the display panel 100 provided in the embodiments of the present disclosure. For details, please refer to the detailed description of the display panel 100 in the above-mentioned embodiments, and will not be repeated in this embodiment.

[0113] It is understandable that Figure 25 The display device is illustrated only in a rectangular structure. In some other embodiments of the present disclosure, the display device 200 may also be embodied in any other feasible shape such as a rounded rectangle, and the present disclosure does not specifically limit this.

[0114] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0115] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a non-display area located outside the display area, wherein the non-display area comprises a first non-display area and a second non-display area, wherein the second non-display area is located on one side of the display area along a first direction, and the first non-display area is located on two opposite sides of the display area along a second direction; the second non-display area comprises a binding area, and the binding area comprises a binding pad; the display panel comprises: a plurality of drive control lines, the drive control lines extending along the first direction and arranged along a second direction, the first direction and the second direction intersecting; a plurality of data lines, the data lines extending along the second direction and arranged along the first direction; Multiple multiplexing units are located in the first non-display area, each of the multiplexing units includes an input end and N output ends, the N output ends are respectively connected to the N data lines, N ≥ 2, the input end of the multiplexing unit is connected to the first input line, at least part of the first input line is located in the display area, and the first input line is configured to obtain a data signal from the binding pad.

2. The display panel according to claim 1, wherein: The first input line includes a first connection line and a second connection line that are electrically connected. The first connection line extends along the second direction and is connected to the input terminal of the multiplexing unit. The second connection line extends along the first direction and is connected to the bonding pad of the bonding area.

3. The display panel according to claim 2, wherein: The first connecting line and the data line are arranged in the same layer.

4. The display panel according to claim 2, wherein: The first connecting line and the data line are arranged in different layers, and along a direction perpendicular to the light emitting surface of the display panel, the first connecting line and the data line do not overlap.

5. The display panel according to claim 2, wherein: It also includes multiple first auxiliary lines extending along the second direction, the first auxiliary lines and the first connecting lines are in the same layer and are insulated; along the first direction, the spacing between adjacent first auxiliary lines is S01, and the spacing between adjacent first auxiliary lines and the first connecting lines is S02, S01=S02.

6. The display panel according to claim 5, wherein: At least a portion of the first auxiliary lines is electrically connected to a fixed potential signal.

7. The display panel according to claim 2, wherein: The second connecting line and the driving control line are arranged in the same layer, or the second connecting line and the driving control line are arranged in different layers, and the second connecting line and the driving control line do not overlap along a direction perpendicular to the light emitting surface of the display panel.

8. The display panel according to claim 7, wherein: It also includes multiple second auxiliary lines extending along the first direction, and the second auxiliary lines are arranged in the same layer as the second connecting lines; along the second direction, the spacing between adjacent second auxiliary lines is S11, and the spacing between adjacent second auxiliary lines and second connecting lines is S12, S11=S12.

9. The display panel according to claim 8, wherein: At least one of the second auxiliary lines is electrically connected to a fixed potential signal.

10. The display panel according to claim 1, wherein N≤5。 11. The display panel according to claim 10, wherein: The multiplexing unit is connected to the N data lines arranged continuously along the first direction.

12. The display panel according to claim 10, wherein: The multiple multiplexing units include a first multiplexing unit connected to N odd-numbered data lines arranged adjacently along the first direction, and a second multiplexing unit connected to N even-numbered data lines arranged adjacently along the first direction.

13. The display panel according to claim 2, wherein: It also includes a gate driving circuit, the gate driving circuit is electrically connected to the driving control line, and the gate driving circuit is located in the first non-display area; The gate driving circuit is electrically connected to the driving control line through a second input line. The second input line extends along the second direction and is arranged in a different layer from the driving control line. The second input line is at least partially located in the display area.

14. The display panel according to claim 13, wherein: The second input line and the data line are arranged in the same layer, or the second input line and the data line are arranged in different layers, and the second input line and the data line do not overlap along a direction perpendicular to the light emitting surface of the display panel.

15. The display panel according to claim 13, wherein: The second input line is arranged in the same layer as the first connecting line; at least part of the second input line is located in the extension direction of the first connecting line, and along the second direction, there is a first gap between the first connecting line and the second input line located in its extension direction.

16. The display panel according to claim 13, wherein: The display area includes a first display area, a third display area, and a second display area arranged in sequence in a direction away from the second non-display area; the gate driving circuit is located in the first non-display area adjacent to the third display area and / or the second display area.

17. The display panel according to claim 16, wherein: At least a portion of the second input line is located in the third display area and / or the second display area.

18. The display panel according to claim 13, wherein: The gate drive circuit includes a first drive circuit group and a second drive circuit group, the first drive circuit group includes multiple first drive circuits, the second drive circuit group includes multiple second drive circuits, and at least one drive control line is electrically connected to the first drive circuit and the second drive circuit.

19. The display panel according to claim 18, wherein: The display area includes a first display area, a third display area and a second display area which are sequentially arranged in a direction away from the second non-display area; The first driving circuit group and the second driving circuit group are respectively located in the first non-display area opposite to each other on both sides of the third display area and / or the second display area along the second direction.

20. The display panel according to claim 18, wherein The display area includes a first display area, a third display area and a second display area which are sequentially arranged in a direction away from the second non-display area; The first driving circuit group is located on one side of the second display area along the second direction. Along the second direction, the first driving circuit group and the multiplexing unit are arranged on different sides of the display area. The second driving circuit group is located at one side of the first display area along the second direction. Along the second direction, the second driving circuit group and the multiplexing unit are located at the same side of the display area.

21. The display panel according to claim 20, wherein: The second input line includes a first sub-line and a second sub-line, the first drive circuit is electrically connected to the drive control line through the first sub-line, and the second drive circuit is electrically connected to the drive control line through the second sub-line; The first sub-line is at least partially located in the second display area, and the second sub-line is at least partially located in the first display area.

22. The display panel according to claim 13, wherein: Along the second direction, the gate driving circuit and the multiplexing unit are arranged opposite to each other in different first non-display areas.

23. The display panel according to claim 13, wherein: The display area includes a first display area, a third display area, and a second display area sequentially arranged in a direction away from the second non-display area; at least part of the gate drive circuit is located in the first non-display area adjacent to the second display area and / or the third display area, and along the second direction, the gate drive circuit and the multiplexing unit are arranged opposite to each other on both sides of the display area; The display panel also includes a power sub-line and a power bus electrically connected to the power sub-line, at least part of the power sub-line is located in the display area, and the power bus is located in the non-display area; at least part of the power bus and the gate drive circuit are located in the same first non-display area, and along the first direction, the power bus is located between the gate drive circuit and the second non-display area.

24. The display panel according to claim 1, wherein The display panel includes a plurality of pixel circuit rows arranged along the first direction and a plurality of pixel circuit columns arranged along the second direction. The pixel circuit rows and the pixel circuit columns each include a plurality of pixel driving circuits. The number of the pixel circuit rows is greater than the number of the pixel circuit columns.

25. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 24.

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