Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a pixel circuit, wherein the pixel circuit comprises a driving transistor, a light emitting control transistor and a light emitting device; the driving transistor is electrically connected with a power supply voltage end and the light-emitting control transistor respectively; the light-emitting control transistor is electrically connected with the light-emitting device, and a grid electrode of the light-emitting control transistor is connected with a light-emitting control signal line and receives a light-emitting control signal transmitted by the light-emitting control signal line; the plurality of pulses of the light-emitting control signal comprise a first pulse and a second pulse, and the non-enable level length of the first pulse is greater than the non-enable level length of the second pulse; in the first display mode, one picture refresh frame of the display panel comprises a data write-in frame, and in the data write-in frame, the frequency of the light-emitting control signal is greater than the reference refresh frequency of the display panel. According to the scheme, the problem that in the prior art, for a display screen with low fundamental frequency, flicker is easily perceived by human eyes due to the unequal-width design of light-emitting control signals is solved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In existing display panels, the light control signal of the pixel driving circuit mostly adopts a multi-pulse design. The number of pulses and the pulse width of the light control signal will affect the display effect of the display panel. For display panels with a low base frequency, if there is a difference in the width between different pulses of the light control signal in a display cycle, it may cause flickering to be recognized by the user, affecting the user experience. Summary of the invention

[0003] The main purpose of the present application is to provide a display panel and a display device to solve the problem in the prior art that for display screens with low fundamental frequencies, the unequal width design of the light control signal is easily perceived by the human eye as flickering.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a display panel is provided, comprising a pixel circuit, the pixel circuit comprising a driving transistor, a light-emitting control transistor and a light-emitting device; the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the first electrode of the light-emitting control transistor; the second electrode of the light-emitting control transistor is electrically connected to one electrode of the light-emitting device, and the gate of the light-emitting control transistor is connected to a light-emitting control signal line to receive a light-emitting control signal transmitted by the light-emitting control signal line; within a cycle of the light-emitting control signal, the light-emitting control signal comprises a plurality of pulses, one of the pulses comprises an adjacent non-enable level and an enable level, the plurality of pulses of the light-emitting control signal comprises a first pulse and a second pulse, the non-enable level duration of the first pulse is S1, the non-enable level duration of the second pulse is S2, S1>S2; the reference refresh frequency of the display panel is F0, and in the first display mode, a picture refresh frame of the display panel comprises a data writing frame, in the data writing frame, the frequency of the light-emitting control signal is F1, F1>F0.

[0005] Optionally, within a cycle of the light emitting control signal, the number of the first pulses of the light emitting control signal is N1, and the number of the second pulses is N2, N2=k1×N1, k1 is a positive integer, and k1≥2.

[0006] Optionally, N1 is negatively correlated with F0, and N2 is positively correlated with F0.

[0007] Optionally, a cycle of the light emitting control signal includes a plurality of groups of pulses, and any group of pulses includes one first pulse and a plurality of second pulses following the first pulse.

[0008] Optionally, in the first display mode, a picture refresh frame of the display panel further includes M light-emitting holding frames, M≥1; in the light-emitting holding frame, the frequency of the light-emitting control signal is F1.

[0009] Optionally, F1=k2×F0, k2 is a positive integer, and k2≥2.

[0010] Optionally, S1=k3×S2, k3 is a positive integer, and k3≥2.

[0011] Optionally, the pixel circuit also includes a data writing transistor and a bias adjustment transistor; the first electrode of the data writing transistor is electrically connected to the data line, and the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor; the first electrode of the bias adjustment transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the bias adjustment transistor is electrically connected to the bias adjustment signal line, and the gate of the bias adjustment transistor is electrically connected to the first scanning signal line to receive the first scanning signal; in the data writing frame, the number of cycles of the light emitting control signal is N, N≥2; a pulse of the first scanning signal includes an enable level and a disable level; the enable level of the first scanning signal overlaps with the disable level of the first pulse of the light emitting control signal.

[0012] Optionally, a reference refresh frequency F0 of the display panel is ≤90 Hz.

[0013] Optionally, the reference refresh frequency F0 of the display panel is 60 Hz or 45 Hz.

[0014] Optionally, the display panel also includes a driving circuit, the driving circuit includes a light-emitting driver, the light-emitting driver is used to generate the light-emitting control signal, the light-emitting driver includes multiple stages, each of the multiple stages receives an input signal, a first clock signal, a second clock signal, a first power supply voltage and a second power supply voltage, and outputs a light-emitting control signal, wherein each of the multiple stages includes: an input module, receiving and responding to the input signal and the first clock signal to transmit to the previous output stage; a first output control module, receiving the first power supply voltage and the second power supply voltage, and generating a first node voltage in response to the first clock signal and the second clock signal; a second output control module, receiving the first power supply voltage and the second power supply voltage, and generating a second node voltage in response to the first clock signal and the second clock signal; an output module, receiving the first power supply voltage and the second power supply voltage, and generating the light-emitting control signal in response to the first node voltage and the second node voltage.

[0015] Optionally, the input module includes a first switch tube, a control end of the first switch tube receives the first clock signal, a first end of the first switch tube receives the input signal, and a second end of the first switch tube is an output end.

[0016] Optionally, the first output control module includes a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube, wherein the control end of the second switch tube receives the first clock signal, the second end of the second switch tube and the control end of the fourth switch tube receive the second power supply voltage, the first end of the second switch tube is respectively connected to the control end of the third switch tube and the first end of the fourth switch tube, the first end of the third switch tube is connected to the second end of the fourth switch tube and the first end of the fifth switch tube, the second end of the third switch tube and the control end of the fifth switch tube receive the second clock signal, the second end of the fifth switch tube is connected to the second end of the sixth switch tube, the first end of the sixth switch tube receives the first power supply voltage, the control end of the sixth switch tube is connected to the output end of the input module, wherein the second end of the sixth switch tube outputs the first node voltage.

[0017] Optionally, the first output control module further includes a first capacitor, a first plate of the first capacitor is connected to the second end of the fourth switch tube, and a second plate of the first capacitor is connected to the first end of the third switch tube.

[0018] Optionally, the second output control module includes: a first processing submodule and a second processing submodule, wherein the first processing submodule receives the first power supply voltage and outputs a first processing signal and a second processing signal in response to the first clock signal and the second clock signal, wherein the first processing signal is applied to the first output control module and the second processing signal is applied to the second processing submodule; the second processing submodule receives the second power supply voltage and generates the second node voltage in response to the first clock signal, the second clock signal, the second processing signal and the output of the input module.

[0019] Optionally, the first processing submodule includes a seventh switch tube, an eighth switch tube and a ninth switch tube, wherein the second end of the seventh switch tube and the control end of the eighth switch tube are both connected to the output end of the input module, the control end of the seventh switch tube receives the second clock signal, the first end of the seventh switch tube is connected to the first end of the ninth switch tube, the second end of the ninth switch tube receives the first power supply voltage, the control end of the ninth switch tube is connected to the first end of the eighth switch tube, the second end of the eighth switch tube receives the first clock signal, the first end of the eighth switch tube outputs the first processing signal, and the second end of the seventh switch tube outputs the second processing signal.

[0020] Optionally, the second processing submodule includes a tenth switch tube, an eleventh switch tube and a twelfth switch tube, wherein the control end of the tenth switch tube and the first end of the eleventh switch tube are connected to the output end of the input module, the second end of the eleventh switch tube is connected to the output module, the control end of the eleventh switch tube receives the second power supply voltage, the first end of the tenth switch tube is connected to the first end of the twelfth switch tube, the second end of the tenth switch tube receives the second clock signal, and the control end of the twelfth switch tube receives the first clock signal, wherein the second end of the eleventh switch tube outputs the second node voltage.

[0021] Optionally, the output module includes a thirteenth switch tube and a fourteenth switch tube, the control end of the thirteenth switch tube receives the first node voltage, the first end of the thirteenth switch tube receives the first power supply voltage, the second end of the thirteenth switch tube is connected to the first end of the fourteenth switch tube, the control end of the fourteenth switch tube receives the second node voltage, the second end of the fourteenth switch tube receives the second power supply voltage, and the common node between the second end of the thirteenth switch tube and the first end of the fourteenth switch tube outputs the light-emitting control signal.

[0022] Optionally, the output module further includes a second capacitor, a first electrode plate of the second capacitor is connected to the control end of the fourteenth switch tube, and a second electrode plate of the second capacitor is connected to the second output control module.

[0023] Optionally, the output module further includes a third capacitor, a first plate of the third capacitor is connected to the control end of the thirteenth switch tube, and a second plate of the third capacitor receives the first power supply voltage.

[0024] Optionally, the first clock signal and the second clock signal have the same frequency, and there is a phase difference between the second clock signal and the first clock signal.

[0025] Optionally, the switch tubes included in each stage are all PMOS tubes.

[0026] According to another aspect of the present application, a display device is provided, comprising any one of the display panels described above.

[0027] Applying the technical solution of the present application, the display panel includes a pixel circuit, the pixel circuit includes a driving transistor, a light-emitting control transistor and a light-emitting device; the first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the first electrode of the light-emitting control transistor; the second electrode of the light-emitting control transistor is electrically connected to one electrode of the light-emitting device, and the gate of the light-emitting control transistor is connected to the light-emitting control signal line to receive the light-emitting control signal transmitted by the light-emitting control signal line; within a cycle of a light-emitting control signal, the light-emitting control signal includes multiple pulses, and one pulse includes an adjacent non-enable level and an enable level. The multiple pulses of the light-emitting control signal include a first pulse and a second pulse, the non-enable level duration of the first pulse is S1, and the non-enable level duration of the second pulse is S2, S1>S2; the reference refresh frequency of the display panel is F0, and in the first display mode, a screen refresh frame of the display panel includes a data writing frame, and in the data writing frame, the frequency of the light-emitting control signal is F1, F1>F0. The present application scheme solves the problem in the prior art that for display screens with low base frequencies, the unequal width design of the light control signal is easily perceived by the human eye as flickering, by setting the non-enable level duration of the first pulse and the second pulse in the light control signal, and setting the frequency of the light control signal in the data writing frame to be higher than the reference refresh frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0029] Figure 1A schematic diagram of a circuit structure of a pixel circuit of a display panel according to an embodiment of the present application is shown;

[0030] Figure 2 A schematic diagram of a light emitting control signal of a pixel circuit of a display panel according to an embodiment of the present application is shown;

[0031] Figure 3 A schematic diagram of a light emitting control signal when the reference refresh frequency of a pixel circuit of a display panel according to an embodiment of the present application is 60 Hz is shown;

[0032] Figure 4 A schematic diagram of a light emitting control signal when the reference refresh frequency of a pixel circuit of a display panel according to an embodiment of the present application is 45 Hz is shown;

[0033] Figure 5 A schematic diagram of a light-emission holding frame of a light-emission control signal of a pixel circuit of a display panel according to an embodiment of the present application is shown;

[0034] Figure 6 A schematic diagram of various signals of a pixel circuit of a display panel according to an embodiment of the present application is shown;

[0035] Figure 7 A schematic diagram of the circuit structure of a driving circuit of a display panel according to an embodiment of the present application is shown;

[0036] Figure 8 A schematic diagram of the circuit structure of two stages of a light emitting driver of a display panel according to an embodiment of the present application is shown;

[0037] Fig. 9 A timing design diagram of a light emitting control signal of a driving circuit of a display panel according to an embodiment of the present application is shown;

[0038] Fig.10 A schematic diagram of the circuit structure of another display panel driving circuit according to an embodiment of the present application is shown;

[0039] Fig.11 A schematic diagram of the circuit structure of a driving circuit of another display panel according to an embodiment of the present application is shown;

[0040] Fig.12 A schematic diagram of a display device according to an embodiment of the present application is shown.

[0041] The above drawings include the following reference numerals:

[0042] 10. Input module; 20. First output control module; 30. Second output control module; 301. First processing submodule; 302. Second processing submodule; 40. Output module; 100. Display panel. DETAILED DESCRIPTION

[0043] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0044] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0045] It should be noted that the terms "upper", "lower", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on this patent. The terms "first" and "second" are only used for the convenience of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. "Multiple" means two or more, unless otherwise clearly and specifically defined. In addition, terms such as "horizontal", "vertical", and "overhanging" do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0046] It should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] In order to illustrate the technical solution of the present application, a detailed description is given below in conjunction with specific drawings and embodiments.

[0048] An embodiment of the present application provides a display panel, the display panel comprising a pixel circuit, Figure 1 is a circuit structure diagram of a pixel circuit of a display panel according to an embodiment of the present application, such as Figure 1As shown, the pixel circuit includes a driving transistor T3, a light emitting control transistor T6 and a light emitting device OLED; the first electrode of the driving transistor T3 is electrically connected to the power supply voltage terminal PVDD, the second electrode of the driving transistor T3 is electrically connected to the first electrode of the light emitting control transistor T6; the second electrode of the light emitting control transistor T6 is electrically connected to one electrode of the light emitting device OLED, the gate of the light emitting control transistor T6 is connected to the light emitting control signal line, and receives the light emitting control signal EM transmitted by the light emitting control signal line; Figure 2 As shown, within a cycle of a light-emitting control signal, the light-emitting control signal includes a plurality of pulses pulse, a pulse includes an adjacent non-enable level stage DL and an enable level stage EL, the plurality of pulses of the light-emitting control signal include a first pulse and a second pulse, the non-enable level duration of the first pulse is S1, the non-enable level duration of the second pulse is S2, S1>S2; the reference refresh frequency of the display panel is F0, in the first display mode, a picture refresh frame of the display panel includes a data writing frame, in the data writing frame, the frequency of the light-emitting control signal is F1, F1>F0. Optionally, the electrical connection between the first electrode of the driving transistor T3 and the power supply voltage terminal PVDD can be that the first electrode of the driving transistor T3 is electrically connected to the power supply voltage terminal PVDD by turning on the transistor T1, or it can be other ways, as long as the first electrode of the driving transistor T3 can be electrically connected to the power supply voltage terminal PVDD at least at a certain moment, and the signal can be transmitted.

[0049] Specifically, the display panel in the embodiment of the present application can adopt organic light-emitting diode (OLED) technology, and its basic component unit is a pixel circuit, which is used to control the light-emitting state of each pixel. Each pixel circuit includes: a driving transistor (for controlling current), a light-emitting device (OLED unit) and a light-emitting control transistor connected in series between the driving transistor and the light-emitting device. It can be understood that the display panel of the present application can also adopt a micro light-emitting diode (Micro Light Emitting Diode, micro LED), a light-emitting diode (Light Emitting Diode, LED) display panel or other types.

[0050] Driving transistor: Its first electrode (usually the source or drain, depending on the circuit design) is electrically connected to the power supply voltage terminal to receive the power supply voltage; the second electrode is electrically connected to the first electrode (also the source or drain) of the light-emitting control transistor. The second electrode of the light-emitting control transistor is connected to one electrode of the light-emitting device to control whether the driving current flows to the OLED unit, thereby controlling the light-emitting state of the OLED unit. The light-emitting control signal line is connected to the gate of the light-emitting control transistor to transmit a control signal to determine whether the light-emitting control transistor is turned on or off, thereby controlling the light-emitting state of the OLED unit.

[0051] The enable level of the light emitting control signal refers to the level that controls the corresponding transistor to be turned on, and the non-enable level refers to the level that controls the corresponding transistor to be turned off. When the light emitting control transistor is a P-type transistor, the enable level of the light emitting control signal refers to a low level, and the non-enable level refers to a high level. The light emitting control signal contains multiple pulses in one cycle, and each pulse consists of a non-enable level (a high level when the light emitting control transistor is a P-type transistor) and a subsequent enable level (a low level when the light emitting control transistor is a P-type transistor).

[0052] The pulses of the light-emitting control signal include two types of pulses, namely, the first pulses and the second pulses, that is, the pulses of the light-emitting control signal include multiple first pulses and multiple second pulses, and the main difference between them is that the duration of the non-enable level is different. The non-enable level duration of the first pulse is S1, and the non-enable level duration of the second pulse is S2, and the non-enable level duration S1 of the first pulse is greater than the non-enable level duration S2 of the second pulse.

[0053] The inventor of the present application has found through research that when a light-emitting control signal is set to adopt a multi-pulse design, since the pixel circuit includes working stages such as data signal writing and threshold capture, the non-enable level time of the first pulse of the light-emitting control signal will be set longer, and the non-enable level time of the second and subsequent pulses will be shorter, that is, the duration of the enable level in one cycle of a light-emitting control signal will be different. For display screens with higher base frequencies, such as 120Hz, the unequal width of the light-emitting control signal is not easy to be perceived by the human eye, but for some display screens with lower base frequencies, such as 60Hz and 45Hz, this unequal width design is easy to be perceived by the human eye as flickering. The design of the present application can be used to reduce the flickering effect by adjusting the duration of the pulse of the light-emitting control signal, especially during the data writing frame. In the usual data writing process, the longer non-enable level duration is related to data writing and signal transmission, and after the data writing is completed, shortening the non-enable level duration can increase the effective light-emitting time of the OLED unit and adjust the display brightness.

[0054] The reference refresh rate F0 is the frequency at which the display panel updates the screen in normal display mode, measured in Hertz (Hz). It directly affects the smoothness of the display, the response speed, and the possible flicker perception. A higher refresh rate generally means a smoother display effect and less motion blur. In the embodiment of the present application, the reference refresh rate F0 of the display panel is ≤90Hz, that is, by limiting the application of the technology to display panels of 90Hz or below, it emphasizes its innovation and practicality in low to medium refresh rate application scenarios. The technical effect of the present application is more obvious in panels with low base frequencies, and the applicable scenarios of the present application are further refined, especially 60Hz and 45Hz as two typical refresh rates. 60Hz is the refresh rate of many standard monitors and laptops, while 45Hz is even lower and may appear in specific low-power display devices, such as some electronic ink screen devices. This specific refresh rate range highlights the optimization role of the present application in these common low refresh rate applications, especially for display panels with refresh rates of 60Hz and 45Hz, which can significantly reduce the flicker problem caused by unequal width pulses of the light control signal.

[0055] In the first display mode, a refresh frame (or frame period) of the display panel includes a data writing frame, wherein the frame is calculated based on the minimum period of a light-emitting stage, and the data writing frame is the time from the first row of pixel data writing time of the first frame to the end of the last row of pixel data writing time. At this time, the frequency F1 of the light-emitting control signal is higher than the reference refresh frequency F0. This means that during the data writing frame, the pulse frequency of the light-emitting control signal will increase, thereby increasing the frequency of the pulses of the light-emitting control signal, improving the flicker problem at low frequencies, making it difficult for the human eye to detect flicker.

[0056] In general, the visual quality of the display panel is improved, especially in low refresh rate mode, by adjusting the pulse timing and frequency of the light control signal, especially during the data writing frame. By increasing the pulse frequency of the light control signal to be higher than the flicker threshold that can be recognized by the human eye, the flicker phenomenon is significantly reduced, providing a smoother and more comfortable viewing experience.

[0057] In a cycle of the light emitting control signal, the number of the first pulses of the light emitting control signal is N1, and the number of the second pulses is N2, N2=k1×N1, k1 is a positive integer, and k1≥2. Figure 2 , N1=4, N2=12.

[0058] The light-emitting control signal is a signal that controls whether the pixel in the light-emitting device display emits light or not. It will experience multiple on and off times in a complete working cycle, that is, multiple conversions from the non-enable level (in the embodiment of the present application, a high level is used as an example to indicate on) to the enable level (in the embodiment of the present application, a low level is used as an example to indicate off). The pulse sequence and duration of the signal in this cycle determine the light-emitting duration and intensity of the pixel, thereby affecting the display effect of the entire display panel.

[0059] In a cycle of a light-emitting control signal, the number of first pulses is N1, and the number of second pulses is N2. It is mentioned here that the number of second pulses is k1 times the number of first pulses, where k1 is a positive integer, and k1 ≥ 2, which means that in each cycle, the number of second pulses is at least twice the number of first pulses. This design is to ensure that after the data is written, there are more pulses used to control the light emission of the pixel, thereby increasing the light emission time as a whole and reducing the flickering caused by uneven pulse width (especially under low refresh rate conditions).

[0060] Through the above design, even at a low refresh rate, such as 60Hz or lower, the effective frequency of the light control signal will be increased due to the increase in the number of second pulses, so that the cycle frequency between two adjacent identical pulses (i.e., second pulses) is greater than 60Hz. This can take advantage of the fact that the human eye is not easily aware of flicker at frequencies higher than 60Hz, thereby significantly improving the display effect and providing a smoother, flicker-free viewing experience.

[0061] By setting non-enable level pulses of different lengths in the light-emitting control signal and ensuring that the number of second pulses is at least twice that of the first pulses, this technology can increase the refresh frequency of the display panel at a low refresh rate to reduce visible flicker and optimize the visual effect.

[0062] certainly, Figure 2 This is just an illustrative statement. Figure 2 There are 16 pulses in a cycle of one light emitting control signal. In other implementations, there may be 32 pulses in a cycle of one light emitting control signal. Specifically, N1=4 and N2=28 are set.

[0063] Specifically, the number N1 of the first pulses is negatively correlated with the reference refresh frequency F0, and the number N2 of the second pulses is positively correlated with the reference refresh frequency F0.

[0064] That is to say, the total number of pulses within a period of a light-emitting control signal is fixed. For different reference refresh frequencies, if you want to achieve a flicker that is not easily perceived by the human eye under the adjusted refresh frequency, the higher the reference refresh frequency, the fewer the number of first pulses and the more the number of second pulses. Conversely, the lower the reference refresh frequency, the more the number of first pulses and the fewer the number of second pulses.

[0065] It should be noted that the number of first pulses should not be set too many, as long as the flicker is not easily perceived by the human eye under the adjusted refresh frequency. The control of the light-emitting time needs to be considered simultaneously, that is, the number of second pulses should not be too small.

[0066] Specifically, the number N1 of the first pulses is negatively correlated with the reference refresh frequency F0, that is, as the reference refresh frequency increases, the number of first pulses decreases; as the reference refresh frequency decreases, the number of first pulses increases. It takes a certain amount of time to display each frame (i.e., picture), and the length of this time is directly related to the refresh frequency (reference refresh frequency) of the display panel. The higher the refresh frequency, the shorter the display time of each frame, and vice versa. The first pulse is usually closely related to the data writing process, that is, at the beginning of each frame, a longer pulse width of the light emitting control signal is required to support the data writing of the pixel circuit.

[0067] After the data is written, the second pulse is used to control the light emission of the pixel, and usually has a shorter non-enable level duration to increase the light emission time. Under high refresh rate conditions, since the display time of each frame is short, in order to fully display the picture, it is necessary to quickly perform multiple light emission controls in each frame, which means that more second pulses are needed. Therefore, the number of second pulses will increase with the increase of the reference refresh frequency, forming a positive correlation. Under low refresh rate conditions, the display time of each frame is longer, and fewer second pulses can be used to control the light emission without sacrificing the display effect. Therefore, the number of second pulses will decrease with the decrease of the refresh frequency.

[0068] Overall, this design is used to improve display quality, especially to reduce flicker that may occur at low refresh rates, such as 60Hz or lower. By adjusting the number of first pulses and second pulses in the light-emitting control signal, the process of data writing and light-emitting control can be optimized, ensuring the smoothness of the display effect and reducing flicker even under low refresh rate conditions, thereby providing a better visual experience. This mechanism can dynamically adjust the light-emitting control signal pulse sequence in application scenarios with different refresh rates, ensuring data transmission efficiency while increasing the effective light-emitting time and reducing flicker that can be perceived by the human eye.

[0069] Figure 3 The figure shows the schematic diagram of the light control signal when the reference refresh frequency is 60Hz. Figure 3 As shown, there are two first pulses (longer non-enable level time) of the light emitting control signal. Here, setting the first pulse to be two means that the number of subsequent second pulses (shorter non-enable level time) will be k1 times of the first pulse, and k1 is usually a positive integer and at least 2. Therefore, Figure 3 In the embodiment, if there are two first pulses, the number of second pulses is at least 4, so that the cycle frequency between the first pulse and the subsequent identical pulse reaches 120 Hz, which is higher than the reference refresh frequency of 60 Hz, so as to reduce flicker.

[0070] Similarly, Figure 4 The figure shows the schematic diagram of the light control signal when the reference refresh frequency is 45Hz. Figure 4 As shown, there are four first pulses (longer non-enable level time) of the light emitting control signal, following the same multiple relationship, if there are four first pulses, then the number of second pulses is at least twice that of the first pulses, that is, at least 8. In this way, the cycle frequency between the first pulse and the subsequent identical pulses can reach 180Hz, which is also higher than the reference refresh frequency, so as to achieve the effect of reducing flicker at a refresh rate of 45Hz.

[0071] The possibility of human eyes recognizing flicker above 60Hz is greatly reduced. Based on this feature, by adding the same or similar light control signal pulses within a screen refresh frame of the display panel, so that the frequency of these pulses is higher than the recognition threshold of the human eye, that is, higher than 60Hz, the display effect can be significantly improved, and the flicker perceptible to the human eye can be reduced or eliminated. Under low refresh rate conditions, such as 45Hz, by increasing the number of first pulses and reducing the number of second pulses, it is possible to ensure that the cycle frequency of the light control signal pulses is higher than 60Hz, thereby providing a smooth and flicker-free display effect even at low refresh rates.

[0072] In summary, Figure 3 and Figure 4 It shows how to adjust the pulse structure of the light control signal according to different reference refresh frequencies to optimize the display effect and reduce the flicker that can be perceived by the human eye. By increasing the number of first pulses and increasing the number of second pulses according to a specific ratio, it can ensure that the periodic frequency of the light control signal pulse is higher than the threshold of the human eye to detect flicker, providing a better visual experience. This mechanism can dynamically adjust the light control signal pulse sequence in application scenarios with different refresh rates, optimize the process of data writing and light control, reduce flicker, and improve display quality.

[0073] It can be understood that a cycle of a light emitting control signal includes multiple groups of pulses, and any group of pulses includes a first pulse and multiple second pulses after the first pulse.

[0074] In a complete cycle of a light-emitting control signal, the signal is divided into multiple groups of pulses (which can be understood as multiple subsequences), each of which contains a specific combination of the first pulse and the second pulse. This grouping strategy allows for more refined control and can adjust the pulse combination under different operating conditions (such as different refresh rates) to achieve the best display effect.

[0075] like Figure 2 As shown, the signal is divided into four groups of pulses. In any group of pulses, there will be a first pulse with a longer non-enable level duration, which is mainly used to support data writing and signal processing. Immediately after the first pulse, there will be three second pulses with a shorter non-enable level duration, which are mainly used to control pixel luminescence, and the number of these second pulses is k1 times the first pulse, where k1 is a positive integer and is at least 2. This design ensures that after the data is written, sufficient effective luminescence time is guaranteed, reducing the flickering feeling while ensuring the display effect.

[0076] By setting multiple groups of pulses including the first pulse and the second pulse in one cycle, the cycle frequency of the signal can be adjusted so that the cycle frequency from the start of the first pulse to the start of the next identical first pulse is higher than the frequency at which the human eye can detect flicker, usually higher than 60Hz. Even under low refresh rate conditions, this design can ensure that the cycle frequency of the signal is high enough, thereby significantly improving display quality and reducing flicker.

[0077] In this way, the technical solution can improve the visual comfort of the display panel without sacrificing data writing efficiency, especially in low refresh rate usage scenarios, such as 60Hz or lower refresh rates, providing a smoother and flicker-free viewing experience.

[0078] Furthermore, in the first display mode, one picture refresh frame of the display panel further includes M light-emitting holding frames, where M≥1; in the light-emitting holding frames, the frequency of the light-emitting control signal is F1.

[0079] Specifically, the display panel can have multiple display modes, which can be adjusted based on different performance requirements or usage scenarios. In one screen refresh frame, the display panel completes a screen update, including data writing and actual display time. In the first display mode, in addition to the data writing frame, such as Figure 5 As shown, a picture refresh frame also includes M light-emitting keep frames, where M is at least 1.

[0080] The light-maintaining frame is a series of frames used to maintain the stability of the brightness of the display screen after the data is written. In this part of the frame, the frequency of the light-emitting control signal is still set to F1, which is already mentioned in the data writing frame and is higher than the reference refresh frequency of the display panel. By maintaining the high frequency of the light-emitting control signal in the light-maintaining frame, it can ensure that the light-emitting control of the pixel is smoother when displaying the picture, reduce the flicker caused by the low signal frequency, and provide a more continuous and stable display effect.

[0081] The light-emitting control signal plays a key role in driving the display panel. It determines when the pixel circuit starts to emit light and the duration of the light emission. In the first display mode, by optimizing the pulse structure of the light-emitting control signal in the data writing frame and maintaining the high frequency F1 of the light-emitting control signal in the subsequent M light-maintaining frames, it can be ensured that even under low refresh rate conditions, a flicker frequency that is not easily perceived by the human eye can be achieved. This optimization strategy is particularly aimed at situations where the reference refresh frequency is low, such as 60Hz or 45Hz. By increasing the frequency of the light-emitting control signal, the cycle frequency of the signal is greater than 60Hz, thereby significantly improving the display effect and reducing or eliminating flicker that can be perceived by the human eye.

[0082] By introducing the light-holding frames in the first display mode and maintaining the high frequency of the light-control signal in these frames, the present application can dynamically adjust the frequency and pulse structure of the light-control signal according to different display modes and refresh frequency requirements to achieve the best display effect. This dynamic adjustment mechanism can improve the display smoothness and visual comfort without affecting the data writing efficiency, especially in the low refresh rate mode, to provide a higher quality display experience.

[0083] In summary, the embodiment of the present application proposes a solution to optimize the display effect and reduce flicker in the first display mode by adding a light-maintaining frame in the picture refresh frame and maintaining a high frequency of the light-control signal in these frames. This design enables the display effect that is not easily perceived by the human eye to be achieved by increasing the frequency of the light-control signal even at a low refresh rate, providing a more continuous and smooth viewing experience.

[0084] Specifically, F1=k2×F0, k2 is a positive integer, and k2≥2.

[0085] The frequency F1 of the light control signal should be k2 times the reference refresh frequency F0, where k2 is a positive integer and k2 ≥ 2. This means that the frequency of the light control signal is at least twice the reference refresh frequency. For example, when the reference refresh frequency F0 is 60 Hz, the frequency F1 of the light control signal will be at least 120 Hz. Specifically, Figure 4As shown, when the reference refresh frequency F0 is 45 Hz and k2 is 4, the frequency of the light emitting control signal F1 = 4×45 = 180 Hz.

[0086] The purpose of this design is to reduce or eliminate flicker at low refresh rates, such as 60Hz or lower, and to improve the visual comfort of the display effect. The human eye's perception of flicker at frequencies above 60Hz is significantly reduced. Therefore, by increasing the frequency of the light-emitting control signal to at least twice the reference refresh frequency, it can be ensured that during the light-holding frame, the switching frequency of the signal is high enough so that the human eye can hardly perceive the flicker, providing a smoother and more natural display effect. The flicker phenomenon is usually caused by the mismatch between the signal frequency and the refresh rate of the display panel. Under low refresh rate conditions, if the frequency of the light-emitting control signal is also low, the periodic changes in the signal may be captured by the human eye, resulting in a sense of flicker. In the embodiment of the present application, by increasing the frequency of the light-emitting control signal to at least twice the reference refresh frequency, the visual fusion effect of fast pulse switching is used, so that even in low refresh rate mode, the display effect can achieve higher continuity and stability, greatly reducing the perception of flicker.

[0087] By setting the multiple relationship between the frequency F1 of the light control signal and the reference refresh frequency F0, this embodiment provides a flexible display optimization solution. In display modes with different refresh rates, by simply adjusting the value of k2, different display requirements can be adapted to ensure that a low-flicker display effect can be achieved in any mode, providing a user-friendly visual experience, whether in standard refresh rate or low power consumption mode.

[0088] In summary, the technical point of this embodiment is that by setting the frequency F1 of the light control signal in the light-maintaining frame to at least twice the reference refresh frequency F0, the human eye is insensitive to high-frequency changes, which significantly reduces the flickering phenomenon of the display panel at a low refresh rate and provides a smoother and more comfortable viewing experience. This design not only optimizes the display effect, but also enhances the adaptability and flexibility of the display panel in different refresh rate modes.

[0089] Furthermore, S1=k3×S2, k3 is a positive integer, and k3≥2.

[0090] The light-emitting control signal controls the light-emitting state of the pixel through periodic pulses, in which the width of the pulse is crucial to the control effect. The first pulse is usually closely related to the data writing process, and has a longer non-enable level duration S1 to ensure accurate data writing. The second pulse is a pulse used to control the pixel light emission after the data writing is completed, and its non-enable level duration S2 is shorter to increase the effective light-emitting time.

[0091] In the embodiment of the present application, the non-enable level duration S1 of the first pulse is k3 times the non-enable level duration S2 of the second pulse, where k3 is a positive integer and k3 ≥ 2. This means that the non-enable level duration of the first pulse is at least twice the non-enable level duration of the second pulse. For example, Figure 2 As shown, the non-enable level duration of the first pulse is four times that of the second pulse. If the non-enable level duration S2 of the second pulse is 2 microseconds, then the non-enable level duration S1 of the first pulse is 8 microseconds.

[0092] The ratio of the non-enable level duration of the first pulse to the second pulse is set to optimize the display effect of the display panel in different operation modes. The first pulse is usually at the beginning of the signal cycle and is closely related to the data writing process. It takes enough time to ensure that the data is accurately written into the pixel circuit. The second pulse appears after the data is written and is mainly used to control the light-emitting state of the pixel. By setting the non-enable level duration S1 of the first pulse to at least twice the non-enable level duration S2 of the second pulse, the effective light-emitting time can be increased while ensuring the data writing efficiency, reducing the flickering phenomenon caused by the periodic change of the signal, and providing a more continuous and stable display effect. The root cause of the flickering phenomenon is that the periodic change of the signal does not match the display refresh frequency, causing the human eye to be able to recognize the fluctuation of the brightness. Increasing the non-enable level duration ratio between the first pulse and the second pulse can adjust the signal cycle to ensure that even under low refresh rate conditions, the signal cycle frequency is high enough so that the human eye is not easy to detect flicker. At the same time, by setting a plurality of shorter second pulses after the data write frame, it can be ensured that the pixel has enough time to emit light in the enable level state, thereby increasing the effective light-emitting time and reducing the flickering feeling.

[0093] By setting a specific ratio of the duration of the non-enable level of the first pulse to the second pulse, in different refresh rates or display modes, only the value of k3 needs to be adjusted to meet various brightness, contrast and refresh rate requirements without major modifications to the hardware circuit. This mechanism enables the display panel to flexibly achieve the best display effect under different operating conditions, especially in low refresh rate mode, reducing flicker and improving the viewing experience.

[0094] See also Figure 1, the pixel circuit further includes a data writing transistor T2 and a bias adjusting transistor T8; the first electrode of the data writing transistor T2 is electrically connected to the data line to receive the data signal DATA; the second electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T3 to write the data voltage to the gate of the driving transistor to control the luminous intensity of the pixel; the first electrode of the bias adjusting transistor T8 is electrically connected to the first electrode of the driving transistor T3, and the second electrode of the bias adjusting transistor T8 is electrically connected to the bias adjusting signal line to receive the bias adjusting signal DVH; the gate of the bias adjusting transistor T8 is electrically connected to the first scanning signal line to receive the first scanning signal SP*, and the function of the bias adjusting transistor is to adjust the bias voltage of the pixel circuit to compensate for the influence of various environmental factors (such as temperature changes, power supply voltage fluctuations, etc.) on the display effect; in the data writing frame, the number of cycles of the light emitting control signal EM is N, N≥2; Figure 6 As shown, one pulse of the first scanning signal SP* includes an enable level phase and a non-enable level phase; the enable level of the first scanning signal SP* overlaps with the non-enable level of the first pulse of the light emitting control signal EM.

[0095] Specifically, in the data writing frame, the number of cycles N of the light emitting control signal is at least 2. This means that in each data writing frame cycle, the light emitting control signal will undergo at least two alternations of enable and disable levels to control the light emitting state and cycle of the pixel. Each wide light emitting control signal EM corresponds to the first scanning signal SP* being turned on, which is equivalent to the frequency of the first scanning signal SP* also being increased accordingly. In some other implementations, the starting moment of the enable level of the first scanning signal SP* is after the starting moment of the disable level of the first pulse of the light emitting control signal EM, and the ending moment of the enable level of the first scanning signal SP* is before the ending moment of the disable level of the first pulse of the light emitting control signal EM. If there are N light emitting control signal cycles in the data writing frame, then there are N first pulses, and the corresponding first scanning signal SP* also has N enable level stages.

[0096] A pulse of the first scanning signal includes an enable level and a disable level. The enable level is used to activate the bias adjustment transistor and the data writing transistor for data writing and bias voltage adjustment; and the disable level is the off state of the transistor, stopping data writing and bias voltage adjustment. In the data writing frame, there is an overlapping time period between the enable level of the first scanning signal and the disable level of the first pulse of the light emitting control signal. The purpose of this overlapping design is to ensure that the data writing transistor and the bias adjustment transistor are activated at the same time during the data writing period, to ensure that the data can be accurately written to the driving transistor, and to adjust the bias voltage at the same time, so as to ensure the stable operation of the pixel circuit and consistent display effect.

[0097] The above design improves the display quality and efficiency of the display panel under different conditions. The coordinated work of the data writing transistor and the bias adjustment transistor enables accurate data writing and fine adjustment of the bias voltage even under complex environmental conditions. The number of cycles of the light-emitting control signal N ≥ 2 and the overlap with the enable level of the first scanning signal ensure that while controlling the light-emitting state of the pixel, effective data writing and bias voltage adjustment are also performed, which improves the continuity and stability of the display and reduces the flicker caused by periodic changes in the signal. This optimization is not only applicable to displays under standard refresh rate conditions, but especially at low refresh rates, such as 60Hz or lower. By ensuring the efficient completion of data writing and bias adjustment, the clarity and smoothness of the display can be further improved, flicker can be reduced, and a more comfortable and natural viewing experience can be provided. By finely adjusting the signal interaction in the pixel circuit, the control of the light-emitting control signal is effectively optimized, and the accuracy of data writing and the consistency of the display effect are improved.

[0098] The display panel in the embodiment of the present application also includes a driving circuit, which is responsible for controlling the display operation of the pixels on the panel, including data writing, brightness adjustment, and refresh control, etc. Among them, the light driver is the core part of the driving circuit, which generates a signal for controlling whether the pixel emits light, namely, a light control signal. Figure 7 The circuit structure diagram of a driving circuit of a display panel according to an embodiment of the present application is shown. The driving circuit includes a light-emitting driver, which is used to generate the light-emitting control signal. The light-emitting driver includes multiple stages. Figure 8 The circuit structure diagram of two stages of the light-emitting driver is shown. The light-emitting driver adopts a multi-stage cascade design. Each stage receives a specific input signal and control signal to generate the final light-emitting control signal. This cascade structure helps to stably transmit and amplify the signal, ensuring that each pixel can receive an accurate control signal. Figure 8 The OUT signal output by the previous driver is used as the IN signal of the next driver. After being processed by the first driver, it is converted into an OUT signal. Subsequently, the OUT signal is used as the IN signal of the next driver and is processed again until the signal is transmitted to the downstream of the drive circuit, forming a signal transmission chain. This transmission method ensures the accuracy and synchronization of the signal.

[0099] See Figure 7, the input terminal IN of each of the above-mentioned multiple stages receives an input signal, a first clock signal CK, a second clock signal XCK, a first power supply voltage VGH and a second power supply voltage VGL, and outputs a light-emitting control signal at an output terminal OUT, wherein each of the above-mentioned stages includes an input module 10, a first output control module 20, a second output control module 30 and an output module 40. The input module receives and responds to the above-mentioned input signal and the above-mentioned first clock signal to transmit to the previous output stage; the first output control module receives the above-mentioned first power supply voltage and the above-mentioned second power supply voltage, and generates a first node voltage in response to the above-mentioned first clock signal and the above-mentioned second clock signal; the second output control module receives the above-mentioned first power supply voltage and the above-mentioned second power supply voltage, and generates a second node voltage in response to the above-mentioned first clock signal and the above-mentioned second clock signal; the output module receives the above-mentioned first power supply voltage and the above-mentioned second power supply voltage, and generates the above-mentioned light-emitting control signal in response to the above-mentioned first node voltage and the above-mentioned second node voltage.

[0100] It should be noted that the first clock signal and the second clock signal have the same frequency, and there is a phase difference between the second clock signal and the first clock signal. The first clock signal and the second clock signal have the same frequency, which means that the periods of the first clock signal and the second clock signal are the same, and their waveforms repeat the same pattern in the same time. The same frequency means that the number of times the waveforms of the first clock signal and the second clock signal are repeated per second is the same, which is a prerequisite for ensuring that the two signals can coordinate with each other and operate synchronously in the circuit. There is a phase difference between the second clock signal and the first clock signal, and the phase difference refers to the timing difference between the two clock signals. Although the first clock signal and the second clock signal have the same frequency, their waveforms will not completely overlap in time, but there is a certain offset. The introduction of this phase difference is usually to meet the timing requirements of different parts of the circuit, or to achieve more sophisticated signal control. In the display drive circuit, by adjusting the phase difference between the first clock signal and the second clock signal, time-sharing processing of data can be achieved, or more precise control can be achieved in the signal generation process, such as in the generation of the light control signal pulse, ensuring the precise alignment and stable periodicity of the signal, thereby reducing flicker and improving display quality.

[0101] The use of phase difference is particularly critical in display driver circuit design. For example, when the display panel operates at a low refresh rate, such as 60Hz or 45Hz, the generation of the light control signal and its periodicity are crucial to reducing flicker. By adjusting the phase of the second clock signal relative to the first clock signal, the triggering timing of the switch tube in the output module can be controlled to ensure that the generation of the light control signal matches the refresh rate of the display panel, avoiding display quality problems caused by inconsistent signal timing.

[0102] Furthermore, if Figure 7 As shown, the input module 10 includes a first switch tube M1, a control end of the first switch tube M1 receives the first clock signal CK, a first end of the first switch tube M1 receives the input signal, and a second end of the first switch tube M1 is an output end.

[0103] Specifically, in the input module, the first switch tube plays the role of signal transmission and control. When it receives the control signal, it can control the flow of the signal according to the state of the input signal, thereby determining whether to transmit the signal to the subsequent circuit module. The control end (usually the gate) of the first switch tube receives the first clock signal CK. The clock signal is an important signal for controlling the signal processing rhythm in the digital circuit, and it alternates between high level and low level at a predetermined frequency. When the first clock signal CK is at a low level, the first switch tube is triggered to turn on; conversely, when the first clock signal CK is at a high level, the first switch tube is closed. This mechanism ensures the precise opening and closing of the signal, thereby controlling the transmission of the signal. The first end of the first switch tube (usually one of the source or drain) is connected to the input signal. The input signal can be the OUT signal from the previous driver, or the initialization signal sent by the control circuit, which carries information for controlling the display state of the pixel. When the first switch tube is turned on, the input signal can be transmitted to the second end of the switch tube through the first end, and further transmitted to the output end of the input module, preparing for subsequent signal processing. The second end of the first switch tube (usually the other end of the drain or source) is the output end of the input module, that is, the interface for transmitting the signal to the subsequent circuit. When the first switch tube is turned on under the control of the first clock signal, the input signal flows from the first end of the first switch tube to the second end, and is finally transmitted to the subsequent signal processing module, such as the first output control module or the second output control module, for further processing and generating the required light control signal.

[0104] In the input module, the first switch tube acts as a "gate" or "bridge" for the signal, and its state (on or off) is controlled by the first clock signal CK. When the first clock signal CK is at a low level, the first switch tube is turned on, allowing the input signal to pass through, flowing from the first end of the first switch tube to the second end, and then to the output end of the input module. Subsequently, the signal will be passed to the downstream circuit of the input module, such as the first output control module, to generate a node voltage. When the first clock signal CK is at a high level, the first switch tube is turned off, preventing the transmission of the signal and entering a state of waiting for the next clock cycle. This design ensures the precise control and timing transmission of the signal, and is the basis for the drive circuit to operate stably and accurately control the display panel.

[0105] In applications with low refresh rates of display panels, such as 60Hz or 45Hz, by precisely controlling the opening and closing of the first switch tube and the transmission of the input signal, the signal processing process can be optimized, signal delay and distortion can be reduced, thereby optimizing the generation of the light-emitting control signal, reducing flicker, and improving display quality.

[0106] See also Figure 7 The first output control module 20 includes a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5 and a sixth switch tube M6, wherein a control end of the second switch tube M2 receives the first clock signal CK, a second end of the second switch tube M2 and a control end of the fourth switch tube M4 receive the second power supply voltage VGL, a first end of the second switch tube M2 is respectively connected to a control end of the third switch tube M3 and a first end of the fourth switch tube M4, a first end of the third switch tube M3 is connected to a second end of the fourth switch tube M4 and a first end of the fifth switch tube M5, a second end of the third switch tube M3 and a control end of the fifth switch tube M5 receive the second clock signal XCK, a second end of the fifth switch tube M5 is connected to a second end of the sixth switch tube M6, a first end of the sixth switch tube M6 receives the first power supply voltage VGH, a control end of the sixth switch tube M6 is connected to an output end of the input module 10, and a second end of the sixth switch tube M6 outputs the first node voltage through a first node n1.

[0107] In the first output control module, the first node voltage is generated by accurately controlling the first clock signal CK and the second clock signal XCK in combination with the first power supply voltage VGH and the second power supply voltage VGL. Specifically:

[0108] The control end of the second switch tube M2 receives the first clock signal CK, which indicates that the opening and closing of the second switch tube M2 is controlled by the first clock signal CK. The second end of the second switch tube M2 and the control end of the fourth switch tube M4 receive the second power supply voltage VGL, which means that when the second switch tube M2 is turned on, the second power supply voltage VGL can be transmitted to the internal circuit. The first end of the second switch tube M2 is connected to the control end of the third switch tube M3 and the first end of the fourth switch tube M4. Such a connection means that a signal path is formed between the second switch tube M2, the third switch tube M3 and the fourth switch tube M4.

[0109] The first end of the third switch tube M3 is connected to the second end of the fourth switch tube M4 and the first end of the fifth switch tube M5, and the second end of the third switch tube M3 and the control end of the fifth switch tube M5 receive the second clock signal XCK. In this connection mode of the third switch tube M3 and the fourth switch tube M4, the second clock signal cooperates with the XCK signal to control the further transmission of the signal inside the circuit and the control of the subsequent fifth switch tube M5. The second end of the fifth switch tube M5 is connected to the second end of the sixth switch tube M6, which means that the fifth switch tube M5 and the sixth switch tube M6 form a signal output path. The second clock signal XCK controls the fifth switch tube M5 to turn on, and cooperates with the sixth switch tube M6 to convert the voltage difference between the first power supply voltage VGH and the second power supply voltage VGL into a first node voltage. The generation of this voltage depends on the working state of the fifth switch tube M5 and the sixth switch tube M6 and the timing control of the first clock signal CK and the second clock signal XCK.

[0110] Through this complex switch tube connection and timing control, the first output control module can accurately generate the first node voltage for subsequent circuit control, such as adjusting the high level time of the light emitting control signal or affecting the data writing process in the pixel circuit. This design is an important part of signal control and conversion in the driving circuit, and plays a key role in optimizing the display effect of the display panel, especially in reducing flicker at low refresh rates, such as 60Hz or 45Hz.

[0111] In a low refresh rate display device, by precisely controlling the state of the switch tube in the first output control module and the transmission of the signal, the timing and intensity of the signal can be optimized to ensure the stable generation of the light-emitting control signal, thereby improving the display quality and reducing the flicker perception caused by periodic changes in the signal.

[0112] See also Figure 7 The first output control module 20 further includes a first capacitor C1, a first electrode plate of the first capacitor C1 is connected to the second end of the fourth switch tube M4, and a second electrode plate of the first capacitor C1 is connected to the first end of the third switch tube M3.

[0113] It is understandable that the design of adding the first capacitor in the first output control module is to further stabilize and accurately control the voltage of the first node. Capacitors play an important role in storing charges, smoothing voltage fluctuations and filtering in circuit design.

[0114] The first electrode plate of the first capacitor is connected to the second end of the fourth switch tube M4, and the second electrode plate is connected to the first end of the third switch tube M3. This connection method means that the capacitor is located on the signal path between the fourth switch tube M4 and the third switch tube M3, and the influence of the power supply voltage and the signal transmission between the switch tubes are used for charge storage and voltage regulation. When the second switch tube M2 is turned on, so that the fourth switch tube M4 is affected by the second power supply voltage VGL, the first capacitor starts to charge and store charge. When the third switch tube M3 and the fifth switch tube M5 are turned on under the control of the second clock signal XCK, the first capacitor releases the stored charge, smoothes the voltage fluctuation, and ensures the stable generation of the first node voltage. The first capacitor helps to reduce voltage transients and improve signal quality when the switch tube state is converted.

[0115] During the signal processing process, especially when the switch tube changes from on to off or from off to on, the voltage and signal may change instantaneously, which will affect the final display effect. The first capacitor can smooth these transients, reduce the noise in the signal, and improve the purity of the first node voltage through its charging and discharging characteristics, thereby optimizing the generation of the light-emitting control signal. The first capacitor can also introduce a certain signal delay, which is necessary in circuit design to ensure that the signal propagates between the various switch tubes in the correct timing. This delay helps stabilize the signal and avoids unstable states caused by rapid signal changes, such as voltage spikes or signal distortion, which is particularly important for maintaining the normal operation of the display panel and avoiding flickering.

[0116] In summary, the first capacitor C1 in the first output control module adjusts and smoothes the voltage between the fourth switch tube M4 and the third switch tube M3 through its specific position in the circuit and its charge and discharge characteristics, ensuring the stable generation of the first node voltage. This design not only improves the signal quality, but also increases the stability and accuracy of signal transmission, which is of great significance for optimizing the display effect, especially reducing flicker in display panels with low refresh rates, such as 60Hz or 45Hz. Through the filtering and smoothing effect of the first capacitor C1, the signal can be kept pure and stable even in complex signal processing and switch tube state conversion processes, ensuring the optimization of display quality.

[0117] like Figure 7As shown, the second output control module 30 includes a first processing submodule 301 and a second processing submodule 302, wherein the first processing submodule receives the first power supply voltage and outputs a first processing signal and a second processing signal in response to the first clock signal and the second clock signal, wherein the first processing signal is applied to the first output control module, and the second processing signal is applied to the second processing submodule; the second processing submodule receives the second power supply voltage, and generates the second node voltage in response to the first clock signal, the second clock signal, the second processing signal and the output of the input module.

[0118] Specifically, the first processing submodule receives the first power supply voltage VGH, that is, the first processing submodule can work according to the level state of the first power supply voltage VGH. The first clock signal CK and the second clock signal XCK are control signals, which are used to accurately adjust the working rhythm of the first processing submodule to ensure that the generation and transmission of the signal are coordinated with the timing of the entire display driving circuit. Under the control of the first clock signal CK and the second clock signal XCK, the first processing submodule will generate two processing signals. The first processing signal is applied to the first output control module, which can be used to assist in generating the first node voltage or adjust the working state of the first output control module; the second processing signal is sent to the second processing submodule for the generation process of the second node voltage.

[0119] The second processing submodule receives a second power supply voltage VGL, which provides a ground level or a negative voltage for the off state of the transistor, or as a reference voltage in the circuit. The second processing submodule not only relies on timing control (the first clock signal and the second clock signal), but also requires the second processing signal and the signal transmitted from the input module as input to generate a second node voltage. The second node voltage is the main output of the second processing submodule, which will be used in subsequent circuits to control a specific state of the pixel.

[0120] The second output control module generates a second node voltage through the cooperation of the first processing submodule and the second processing submodule. First, the first processing submodule outputs two processing signals according to the level of VGH under the timing control of the first clock signal CK and the second clock signal XCK: the first processing signal is used for feedback control or adjustment of the state of the first output control module; the second processing signal provides the necessary input for the second processing submodule. Subsequently, after receiving the second power supply voltage VGL, the first clock signal CK, the second clock signal XCK, the second processing signal and the signal from the input module, the second processing submodule generates the second node voltage by integrating this information. The generation of the second node voltage should not only consider the influence of the second power supply voltage VGL, but also accurately respond to the rhythm of the clock signal and the signal state from the first processing submodule to ensure the stability and accuracy of the second node voltage.

[0121] In low refresh rate display devices, such as panels with a base frequency of 60Hz or 45Hz, the precise operation of the second output control module is essential for generating a stable and accurate light control signal. Through the interaction between the first processing submodule and the second processing submodule, the circuit can optimize the signal processing flow, reduce signal delay and distortion, thereby reducing the flicker caused by periodic changes in the signal and improving the display quality. This design ensures that when controlling the light-emitting state of the pixel, the high and low level times of the light control signal can be accurately adjusted, thereby stabilizing the brightness of the display panel and reducing the flicker or brightness changes that the user may perceive.

[0122] like Figure 7 As shown, the first processing submodule 301 includes a seventh switch tube M7, an eighth switch tube M8 and a ninth switch tube M9, wherein the second end of the seventh switch tube M7 and the control end of the eighth switch tube M8 are both connected to the output end of the input module 10, the control end of the seventh switch tube M7 receives the second clock signal, the first end of the seventh switch tube M7 is connected to the first end of the ninth switch tube M9, the second end of the ninth switch tube M9 receives the first power supply voltage VGH, the control end of the ninth switch tube M9 is connected to the first end of the eighth switch tube M8, the second end of the eighth switch tube M8 receives the first clock signal, the first end of the eighth switch tube M8 outputs the first processing signal, and the second end of the seventh switch tube M7 outputs the second processing signal.

[0123] The second end of the seventh switch tube M7 is connected to the output end of the input module, and receives the signal transmitted from the upper circuit. The control end of the seventh switch tube M7 receives the second clock signal XCK, which is used to control the opening and closing of the seventh switch tube M7. The first end of the seventh switch tube M7 is connected to the first end of the ninth switch tube M9. When the seventh switch tube M7 is turned on, the signal can be transmitted to the ninth switch tube M9, affecting the generation of the first node voltage. The second end of the seventh switch tube M7 is also used to output the second processing signal, which means that it not only participates in the internal processing of the signal, but also feeds back part of the signal to other parts of the second output control module.

[0124] The control end of the eighth switch tube M8 is connected to the output end of the input module, and receives the signal transmitted from the upper circuit. The first end of the eighth switch tube M8 is connected to the control end of the ninth switch tube M9, and is also the output end of the first processing signal. When the eighth switch tube M8 is turned on, it can affect the state of the ninth switch tube M9, thereby affecting the generation of the first node voltage. The second end of the eighth switch tube M8 receives the first clock signal CK, which not only controls the opening and closing of the eighth switch tube M8, but also affects its internal state as a reference voltage when the eighth switch tube M8 is turned off.

[0125] The first end of the ninth switch tube M9 is connected to the first end of the seventh switch tube M7 to receive a signal. The second end of the ninth switch tube M9 receives a first power supply voltage VGH, which is the power supply when the ninth switch tube M9 is turned on, and is used to generate or adjust the voltage. The control end of the ninth switch tube M9 is connected to the first end of the eighth switch tube M8 to receive a first processing signal. The level state of the first processing signal will determine whether the ninth switch tube M9 is turned on and how to affect the generation of the first node voltage.

[0126] When the second clock signal XCK controls the seventh switch tube M7 to turn on, it receives the signal from the input module and transmits it to the first end of the ninth switch tube M9, and also outputs the second processing signal. At the same time, the first clock signal CK controls the eighth switch tube M8 to turn on, and the signal at its first end can affect the state of the ninth switch tube M9, causing the ninth switch tube M9 to turn on or off, thereby adjusting the generation of the first node voltage. Under the control of the first clock signal CK and the second clock signal XCK, the first processing signal and the second processing signal are output by the first end of the eighth switch tube M8 and the second end of the seventh switch tube M7, respectively. The first processing signal is mainly used to affect the ninth switch tube M9, thereby adjusting the first node voltage; the second processing signal is used for feedback control, or affects other parts of the second output control module, such as the second processing submodule, to generate the second node voltage.

[0127] This design utilizes the precise control of the first clock signal CK and the second clock signal XCK, combined with the use of the first power supply voltage VGH and the second power supply voltage VGL, to generate and transmit the first processing signal and the second processing signal through the switching action of the transistor, which is used to accurately control the first node voltage, ensuring that the display panel can emit light stably at different refresh rates, such as 60Hz or 45Hz, and reduce flicker. At the same time, the generation and transmission of the second processing signal provides coordination and feedback for other parts of the display drive circuit, which contributes to the stable operation of the entire display drive circuit and the precise control of the signal. This fine signal control mechanism is the key to optimizing the display effect and improving the display quality, especially in low refresh rate applications, it can effectively reduce the visual discomfort caused by periodic changes in the signal.

[0128] See also Figure 7 The second processing submodule 302 includes a tenth switch tube M10, an eleventh switch tube M11 and a twelfth switch tube M12, wherein the control end of the tenth switch tube M10 and the first end of the eleventh switch tube M11 are connected to the output end of the input module 10, the second end of the eleventh switch tube M11 is connected to the output module, the control end of the eleventh switch tube M11 receives the second power supply voltage, the first end of the tenth switch tube M10 is connected to the first end of the twelfth switch tube M12, the second end of the tenth switch tube M10 receives the second clock signal, and the control end of the twelfth switch tube M12 receives the first clock signal, wherein the second end of the eleventh switch tube M11 outputs the second node voltage through the second node n2.

[0129] In the above connection relationship, the control end of the tenth switch tube M10 is connected to the output end of the input module 10, and receives the signal or data transmitted from the input module 10, and the signal will be used for subsequent signal processing. The first end of the tenth switch tube M10 is connected to the first end of the twelfth switch tube M12. When the tenth switch tube M10 is turned on, it can transmit the signal to the twelfth switch tube M12 and participate in the generation of the second node voltage. The second end of the tenth switch tube M10 receives the second clock signal XCK, and the second clock signal XCK is used to control the opening and closing of the tenth switch tube M10, ensuring that the signal is transmitted to the twelfth switch tube M12 at the correct time point, thereby affecting the generation of the second node voltage.

[0130] The first end of the eleventh switch tube M11 is connected to the output end of the input module 10 to receive a signal or data. The second end of the eleventh switch tube M11 directly outputs the second node voltage, is connected to the output module 40, and transmits the generated second node voltage to the subsequent circuit or the pixel circuit of the display panel. The control end of the eleventh switch tube M11 receives the second power supply voltage VGL, and the second power supply voltage VGL is used as a reference voltage or ground level. When the eleventh switch tube M11 is turned on, the second power supply voltage VGL can affect the output second node voltage through the eleventh switch tube M11, helping to provide a stable reference point in the generation of the second node voltage.

[0131] The first end of the twelfth switch tube M12 is connected to the first end of the tenth switch tube M10 to receive a signal. The control end of the twelfth switch tube M12 receives the first clock signal CK, and the first clock signal CK is used to control the on or off of the twelfth switch tube M12, affecting the generation of the second node voltage. The second end of the twelfth switch tube M12 is connected to the second end of the eleventh switch tube M11. When the twelfth switch tube M12 is turned on, it can work in conjunction with the eleventh switch tube M11 to generate and output the second node voltage.

[0132] In the second processing submodule, the signal processing and the generation of the second node voltage mainly depend on the timing control of the first clock signal CK and the second clock signal XCK, as well as the reference voltage function of the second power supply voltage VGL. Specifically, the second clock signal XCK controls the tenth switch tube M10 to turn on, and the signal is transmitted from the input module to the twelfth switch tube M12 and the eleventh switch tube M11 via the tenth switch tube M10. At the same time, the first clock signal CK controls the twelfth switch tube M12 to turn on, and works in conjunction with the signal of the tenth switch tube M10 and the state of the eleventh switch tube M11 to generate the second node voltage. The eleventh switch tube M11 maintains a stable reference point under the action of the second power supply voltage VGL, and adjusts the level of the second node voltage according to the signal transmitted from the tenth switch tube M10 and the twelfth switch tube M12.

[0133] This design ensures the accurate generation and control of the second node voltage, which not only depends on the signal received from the input module, but also is affected by the timing control of the first clock signal and the second clock signal, as well as the stabilization of the second power supply voltage. The generation and control of the second node voltage is crucial for the driving of the display panel, and it can directly affect the working state of the pixel circuit. In low refresh rate display applications such as 60Hz or 45Hz, accurate second node voltage generation helps reduce flicker and improve display quality.

[0134] In summary, the second processing submodule generates and outputs the second node voltage through the coordinated work of the tenth switch tube M10, the eleventh switch tube M11 and the twelfth switch tube M12, under the precise timing control of the first clock signal CK and the second clock signal XCK, combined with the stable reference of the second power supply voltage VGL. This is a key step in controlling the pixel state of the display panel and optimizing the display effect.

[0135] It should be noted that the switch tubes included in each of the above stages are all PMOS tubes. PMOS tubes are P-channel metal oxide semiconductor field effect transistors. PMOS tubes are semiconductor devices whose working principle is different from that of N-channel MOS tubes, i.e., NMOS tubes. In PMOS tubes, when the gate voltage is lower than the source and drain voltages, the PMOS tube is turned on, allowing current to flow from the source to the drain. Conversely, when the gate voltage is higher, the PMOS tube is turned off, preventing current from passing. This characteristic of PMOS tubes makes it often used in digital circuits to construct logic circuits, such as inverters, logic gates, etc., and as current control elements in power supply circuits. The display drive circuit is responsible for controlling the pixels on the display panel so that it displays according to the predetermined image information. In the circuit, the function of the switch tube is to connect or disconnect the path between the power supply and the load (such as OLED pixels) according to the logic state of the control signal, thereby controlling the light emission of the pixel. Using a PMOS tube as a switch tube means that when the control signal level is low, the PMOS tube is turned on, allowing current to pass, which is usually used to control the opening of the OLED pixel in the drive circuit, i.e., the light emission state. On the contrary, when the control signal level is high, the PMOS tube is cut off and the pixel is in a non-luminous state. In the display drive circuit, multi-stage cascade switch tubes are usually designed to control the step-by-step transmission and processing of the signal. If all the switch tubes at all levels are PMOS tubes, it will facilitate the layout of the circuit and the coordination of the signal, ensuring that the signal is stably and accurately transmitted in the multi-stage circuit, thereby achieving high-quality display effects.

[0136] In short, the use of PMOS tubes as switch tubes in the display panel drive circuit is based on the consideration of voltage control, power efficiency and signal integrity in circuit design. Through the low-level conduction characteristics of PMOS tubes, precise control of display signals can be achieved, ensuring that the display panel can provide high-quality and stable display effects under various working conditions.

[0137] The timing design diagram of the light emitting control signal is as follows: Fig. 9As shown, the IN signal usually represents input data or control signal. It can be a data signal from the previous level circuit, or a control signal used to start the operation of the entire circuit. The change of the IN signal will trigger specific operations of the circuit, such as data writing, state switching, etc. The CK signal, i.e. the first clock signal, is the key to synchronous operation in the circuit. It is usually a periodic square wave signal used to synchronize the operation of various parts of the circuit to ensure that the signal is processed and transmitted at the correct time point. The high level and low level of the first clock signal represent the activation and waiting states of signal processing, respectively, which helps the circuit to achieve accurate reading and writing of data. The XCK signal, i.e. the second clock signal, is an extended clock signal with a different period or phase from the first clock signal. The introduction of the second clock signal is to meet the special timing requirements of certain parts of the circuit, such as requiring a longer or shorter time to complete data processing or state switching. In this embodiment, the cooperation of the second clock signal with the first clock signal can realize more complex circuit operations and signal control. The OUT signal is the output signal of the circuit, which is a processed data signal, or a control signal finally generated by the circuit, such as a light-emitting control signal. The change of the OUT signal reflects the result of the internal processing of the circuit and is the final output of the circuit function. In this embodiment, the generation and change of the OUT signal depends on the timing control of the IN signal, the CK signal and the XCK signal.

[0138] In circuit design, especially in display driver circuits, accurate timing control is very important because it directly affects the synchronization of signals and the stability of display effects. By analyzing the timing diagrams of IN signals, CK signals, XCK signals, and OUT signals, we can understand how the circuit processes input signals, how it is controlled by clock signals, and how it generates output signals, which is crucial for understanding the working principle of the circuit, optimizing the design, and troubleshooting.

[0139] Please see again Figure 7 The output module 40 includes a thirteenth switch tube M13 and a fourteenth switch tube M14, the control end of the thirteenth switch tube M13 receives the first node voltage, the first end of the thirteenth switch tube M13 receives the first power supply voltage VGH, the second end of the thirteenth switch tube M13 is connected to the first end of the fourteenth switch tube M14, the control end of the fourteenth switch tube M14 receives the second node voltage, the second end of the fourteenth switch tube M14 receives the second power supply voltage VGL, and a common node between the second end of the thirteenth switch tube M13 and the first end of the fourteenth switch tube M14 outputs the light-emitting control signal.

[0140] Specifically, the control end of the thirteenth switch tube M13 receives the first node voltage, which is a key signal for controlling the on or off state of the thirteenth switch tube M13. When the first node voltage reaches a certain level value, the thirteenth switch tube M13 will be turned on to allow current or voltage to pass. The first end of the thirteenth switch tube M13 receives the first power supply voltage VGH, which is the positive power supply of the circuit, usually a higher voltage level. When the thirteenth switch tube M13 is turned on by the first node voltage signal, the first power supply voltage VGH will pass through the thirteenth switch tube M13, affecting the voltage state of the subsequent circuit. The second end of the thirteenth switch tube M13 is connected to the first end of the fourteenth switch tube M14, and the node formed by the second end of the thirteenth switch tube M13 and the first end of the fourteenth switch tube M14 is the output point of the light-emitting control signal.

[0141] The control end of the fourteenth switch tube M14 receives the second node voltage, which is another key signal for controlling the on or off state of the fourteenth switch tube M14. The level value of the second node voltage will determine whether the fourteenth switch tube M14 is turned on. The first end of the fourteenth switch tube M14 is connected to the second end of the thirteenth switch tube M13, and receives the signal or voltage passing through the thirteenth switch tube M13. This end point is also the output point of the light-emitting control signal. The second end of the fourteenth switch tube M14 receives the second power supply voltage VGL, which is the negative power supply or ground level of the circuit. When the fourteenth switch tube M14 is turned on by the second node voltage signal, the second power supply voltage VGL will affect the generation of the light-emitting control signal.

[0142] The node where the second end of the thirteenth switch tube M13 and the first end of the fourteenth switch tube M14 are connected is the output point of the light-emitting control signal. The generation of the light-emitting control signal depends on the states of the thirteenth switch tube M13 and the fourteenth switch tube M14, that is, whether they are turned on by the corresponding first node voltage and second node voltage signals. When the thirteenth switch tube M13 and the fourteenth switch tube M14 are turned on at the same time, the light-emitting control signal will be the difference between the first power supply voltage VGH and the second power supply voltage VGL or a certain state, and this state will be used to control the light emission or non-light emission of the pixels in the display panel, thereby affecting the display effect.

[0143] The generation of the light-emitting control signal needs to be combined with the control of the first node voltage and the second node voltage. Specifically, when the first node voltage reaches a sufficient level to turn on the thirteenth switch tube M13, the first power supply voltage VGH will reach the common node through the thirteenth switch tube M13. Subsequently, the level state of the second node voltage will determine whether the fourteenth switch tube M14 is turned on. If the fourteenth switch tube M14 is also turned on, the second power supply voltage VGL will reach the common node through the fourteenth switch tube M14. When both the thirteenth switch tube M13 and the fourteenth switch tube M14 are turned on, the common node will generate a light-emitting control signal to instruct the pixel circuit to start emitting light.

[0144] This design ensures accurate generation and control of the light-emitting control signal, enabling the display panel to stably display images at different refresh rates and reduce flickering caused by signal timing mismatch or voltage instability. The synergy of the thirteenth and fourteenth switch tubes is the key to generating accurate light-emitting control signals in the drive circuit, which directly affects the quality of the display effect and the user's visual experience. In low refresh rate applications, such as 60Hz or 45Hz display panels, this precise control is particularly important because it can effectively reduce flicker and improve display comfort and clarity.

[0145] Please continue to see Figure 7 The output module 40 further includes a second capacitor C2 and a third capacitor C3, wherein a first plate of the second capacitor C2 is connected to the control terminal of the fourteenth switch tube M14, and a second plate of the second capacitor C2 is connected to the second output control module 30. A first plate of the third capacitor C3 is connected to the control terminal of the thirteenth switch tube M13, and a second plate of the third capacitor C3 receives the first power supply voltage VGH.

[0146] It is understandable that the first plate of the second capacitor is connected to the control terminal of the fourteenth switch tube M14, that is, the port receiving the second node voltage. The second plate of the second capacitor is connected to the second output control module, and can be directly or indirectly connected to the second node voltage signal source, or other parts of the circuit related to the second node voltage signal. The first plate of the third capacitor is connected to the control terminal of the thirteenth switch tube M13, which means that the third capacitor will directly participate in the regulation of the control signal (first node voltage) of the thirteenth switch tube M13. The second plate of the third capacitor receives the first power supply voltage VGH, which indicates that one end of the third capacitor is fixed to the positive power supply potential of the circuit.

[0147] The main function of the second capacitor is to smooth and stabilize the second node voltage. When the second node voltage signal changes rapidly, the second capacitor can mitigate these changes, ensuring that the voltage fluctuation at the control end of the fourteenth switch tube M14 will not be too severe, thereby improving the stability and reliability of the light-emitting control signal. One of the main functions of the third capacitor is to smooth the voltage fluctuation at the control end of the thirteenth switch tube M13 (the port receiving the first node voltage signal). Since the first node voltage signal changes rapidly in a short time, this change will cause the control state of the thirteenth switch tube M13 to be unstable, thereby affecting the generation of the light-emitting control signal. By introducing the third capacitor between the control end of the thirteenth switch tube M13 and the first power supply voltage VGH, it is possible to absorb or release charges when the signal changes, mitigate the rapid fluctuations of the first node voltage signal, and ensure a smooth transition of the control state of the thirteenth switch tube M13. When the first node voltage signal needs to be maintained at a certain level for a period of time to control the state of the thirteenth switch tube M13, the third capacitor can help maintain this level. Even if the voltage of the first node voltage signal source fluctuates, the third capacitor can help maintain the voltage of the control end of the thirteenth switch tube M13 stable by storing and releasing charges, ensuring that the state of the switch tube will not change due to instantaneous voltage fluctuations.

[0148] In low refresh rate display applications, such as 60Hz or 45Hz, the period and stability of the light-emitting control signal are crucial to reducing flicker. The addition of the second capacitor can ensure that the level of the light-emitting control signal changes more smoothly when the signal period changes, avoiding the instability of the light-emitting control signal caused by the rapid change of the second node voltage signal, thereby improving the display effect and reducing flicker. The second plate of the second capacitor is connected to the second output control module, which means that it not only affects the control of the fourteenth switch tube M14, but also interacts with other circuit elements to participate in a wider range of signal processing and control. This connection method shows that the second capacitor not only plays a role in the local circuit, but also participates in the overall coordination and feedback control of the circuit.

[0149] The third capacitor indirectly affects the generation of the light-emitting control signal by stabilizing the control terminal voltage of the thirteenth switch tube. In low refresh rate display applications, such as 60Hz or 45Hz, accurate control of the light-emitting control signal is crucial to reducing flicker and improving display quality. The presence of the third capacitor can ensure that the state change of the thirteenth switch tube M13 is more controllable when receiving the interaction between the first power supply voltage VGH and the first node voltage signal, thereby generating a more stable and accurate light-emitting control signal.

[0150] In summary, the main purpose of adding the second capacitor to the output module is to stabilize and optimize the second node voltage, thereby ensuring that the generation and control of the light-emitting control signal are more accurate, and reducing the flickering phenomenon that may occur in low refresh rate display applications. Through the connection with the fourteenth switch tube and the second output control module, the second capacitor plays a key signal regulation role in the circuit, and is an important part of improving the stability and quality of the display effect in the display drive circuit design. The core purpose of adding the third capacitor to the output module is to smooth and stabilize the control signal (first node voltage) of the thirteenth switch tube, ensuring that the thirteenth switch tube is not affected by voltage fluctuations when controlling the generation of the light-emitting control signal, thereby optimizing the working performance of the display panel, especially reducing flickering in low refresh rate applications and improving display quality. This design detail reflects a deep understanding of the signal control accuracy and circuit stability requirements in the display drive circuit.

[0151] In other embodiments, it is also possible to select Fig.10 and Fig.11 The driving circuit in generates a light emitting control signal.

[0152] Based on the above, the present application also provides a display device, see Fig.12 , Fig.12 1 is a schematic diagram of a display device provided by the present application, and the display device includes any one of the above-mentioned display panels 100. The display device can be at least one of a wearable device, a camera, a mobile phone, a tablet computer, a display screen, a television, and a vehicle-mounted display terminal. The display device includes the display panel provided by the above-mentioned embodiment, so the display device has all the beneficial effects of the above-mentioned display panel.

[0153] The above descriptions are only some specific embodiments disclosed in this application and are not intended to limit this application. For those skilled in the art, this application may have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application shall be included in the protection scope of this application.

Claims

1. A display panel, characterized in that: A pixel circuit includes a driving transistor, a light emitting control transistor and a light emitting device; The first electrode of the driving transistor is electrically connected to the power supply voltage terminal, and the second electrode of the driving transistor is electrically connected to the first electrode of the light emitting control transistor; The second electrode of the light emitting control transistor is electrically connected to one electrode of the light emitting device, and the gate of the light emitting control transistor is connected to the light emitting control signal line to receive the light emitting control signal transmitted by the light emitting control signal line; In a cycle of the light-emitting control signal, the light-emitting control signal includes a plurality of pulses, one of the pulses includes an adjacent non-enable level and an enable level, the plurality of pulses of the light-emitting control signal include a first pulse and a second pulse, the non-enable level duration of the first pulse is S1, the non-enable level duration of the second pulse is S2, and S1>S2; The reference refresh frequency of the display panel is F0. In the first display mode, a picture refresh frame of the display panel includes a data writing frame. In the data writing frame, the frequency of the light emitting control signal is F1, and F1>F0.

2. The display panel according to claim 1, characterized in that: In one cycle of the light emitting control signal, the number of the first pulses of the light emitting control signal is N1, the number of the second pulses is N2, N2=k1×N1, k1 is a positive integer, and k1≥2.

3. The display panel according to claim 2, characterized in that: N1 is negatively correlated with F0, and N2 is positively correlated with F0.

4. The display panel according to claim 2, characterized in that: A cycle of the light emitting control signal includes a plurality of groups of pulses, and any group of pulses includes one first pulse and a plurality of second pulses following the first pulse.

5. The display panel according to claim 4, characterized in that: In the first display mode, one picture refresh frame of the display panel further includes M light-emitting holding frames, where M≥1; in the light-emitting holding frame, the frequency of the light-emitting control signal is F1.

6. The display panel according to claim 1, characterized in that: F1=k2×F0, k2 is a positive integer, and k2≥2.

7. The display panel according to claim 1, characterized in that: S1=k3×S2, k3 is a positive integer, and k3≥2.

8. The display panel according to claim 1, characterized in that: The pixel circuit also includes a data writing transistor and a bias adjustment transistor; a first electrode of the data writing transistor is electrically connected to a data line, and a second electrode of the data writing transistor is electrically connected to a first electrode of the driving transistor; a first electrode of the bias adjustment transistor is electrically connected to a first electrode of the driving transistor, and a second electrode of the bias adjustment transistor is electrically connected to a bias adjustment signal line, and a gate of the bias adjustment transistor is electrically connected to a first scanning signal line to receive a first scanning signal; in the data writing frame, the number of cycles of the light emitting control signal is N, and N≥2; a pulse of the first scanning signal includes an enable level and a disable level; the enable level of the first scanning signal overlaps with the disable level of the first pulse of the light emitting control signal.

9. The display panel according to claim 1, characterized in that: The reference refresh frequency F0 of the display panel is ≤90 Hz.

10. The display panel according to claim 9, characterized in that: The reference refresh frequency F0 of the display panel is 60 Hz or 45 Hz.

11. The display panel according to claim 1, characterized in that: The display panel further includes a driving circuit, the driving circuit includes a light emitting driver, the light emitting driver is used to generate the light emitting control signal, the light emitting driver includes a plurality of stages, each of the plurality of stages receives an input signal, a first clock signal, a second clock signal, a first power supply voltage and a second power supply voltage, and outputs a light emitting control signal, wherein each of the plurality of stages includes: an input module, receiving and responding to the input signal and the first clock signal to transmit to the previous output stage; a first output control module, receiving the first power supply voltage and the second power supply voltage, and generating a first node voltage in response to the first clock signal and the second clock signal; a second output control module, receiving the first power supply voltage and the second power supply voltage, and generating a second node voltage in response to the first clock signal and the second clock signal; The output module receives the first power supply voltage and the second power supply voltage, and generates the light emitting control signal in response to the first node voltage and the second node voltage.

12. The display panel according to claim 11, characterized in that: The input module includes a first switch tube, a control end of the first switch tube receives the first clock signal, a first end of the first switch tube receives the input signal, and a second end of the first switch tube is an output end.

13. The display panel according to claim 11, characterized in that: The first output control module includes a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube, Among them, the control end of the second switch tube receives the first clock signal, the second end of the second switch tube and the control end of the fourth switch tube receive the second power supply voltage, the first end of the second switch tube is respectively connected to the control end of the third switch tube and the first end of the fourth switch tube, the first end of the third switch tube is connected to the second end of the fourth switch tube and the first end of the fifth switch tube, the second end of the third switch tube and the control end of the fifth switch tube receive the second clock signal, the second end of the fifth switch tube is connected to the second end of the sixth switch tube, the first end of the sixth switch tube receives the first power supply voltage, and the control end of the sixth switch tube is connected to the output end of the input module, wherein the second end of the sixth switch tube outputs the first node voltage.

14. The display panel according to claim 13, characterized in that: The first output control module further includes a first capacitor, a first plate of the first capacitor is connected to the second end of the fourth switch tube, and a second plate of the first capacitor is connected to the first end of the third switch tube.

15. The display panel according to claim 11, characterized in that: The second output control module includes: a first processing submodule and a second processing submodule, The first processing submodule receives the first power supply voltage and outputs a first processing signal and a second processing signal in response to the first clock signal and the second clock signal, wherein the first processing signal is applied to the first output control module and the second processing signal is applied to the second processing submodule; The second processing submodule receives the second power supply voltage, and generates the second node voltage in response to the first clock signal, the second clock signal, the second processing signal, and the output of the input module.

16. The display panel according to claim 15, characterized in that: The first processing submodule includes a seventh switch tube, an eighth switch tube and a ninth switch tube, Among them, the second end of the seventh switch tube and the control end of the eighth switch tube are both connected to the output end of the input module, the control end of the seventh switch tube receives the second clock signal, the first end of the seventh switch tube is connected to the first end of the ninth switch tube, the second end of the ninth switch tube receives the first power supply voltage, the control end of the ninth switch tube is connected to the first end of the eighth switch tube, the second end of the eighth switch tube receives the first clock signal, and the first end of the eighth switch tube outputs the first processing signal, and the second end of the seventh switch tube outputs the second processing signal.

17. The display panel according to claim 15, characterized in that: The second processing submodule includes a tenth switch tube, an eleventh switch tube and a twelfth switch tube, Among them, the control end of the tenth switch tube and the first end of the eleventh switch tube are connected to the output end of the input module, the second end of the eleventh switch tube is connected to the output module, the control end of the eleventh switch tube receives the second power supply voltage, the first end of the tenth switch tube is connected to the first end of the twelfth switch tube, the second end of the tenth switch tube receives the second clock signal, and the control end of the twelfth switch tube receives the first clock signal, wherein the second end of the eleventh switch tube outputs the second node voltage.

18. The display panel according to claim 11, characterized in that: The output module includes a thirteenth switch tube and a fourteenth switch tube, the control end of the thirteenth switch tube receives the first node voltage, the first end of the thirteenth switch tube receives the first power supply voltage, the second end of the thirteenth switch tube is connected to the first end of the fourteenth switch tube, the control end of the fourteenth switch tube receives the second node voltage, the second end of the fourteenth switch tube receives the second power supply voltage, and the common node between the second end of the thirteenth switch tube and the first end of the fourteenth switch tube outputs the light-emitting control signal.

19. The display panel according to claim 18, characterized in that: The output module further includes a second capacitor, a first electrode plate of the second capacitor is connected to the control end of the fourteenth switch tube, and a second electrode plate of the second capacitor is connected to the second output control module.

20. The display panel according to claim 18, characterized in that: The output module further includes a third capacitor, a first plate of the third capacitor is connected to the control end of the thirteenth switch tube, and a second plate of the third capacitor receives the first power supply voltage.

21. The display panel according to any one of claims 11 to 20, characterized in that: The first clock signal and the second clock signal have the same frequency, and there is a phase difference between the second clock signal and the first clock signal.

22. The display panel according to any one of claims 12 to 20, characterized in that: The switch tubes included in each stage are all PMOS tubes.

23. A display device, characterized in that: A display panel comprising any one of claims 1 to 22.

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