Three-port SRAM circuit
By designing a three-port SRAM circuit and adding specific transistor components, the high-speed reading function of port B and port C is realized, solving the problem of slow reading speed in the prior art and the need for an inverter to determine the storage state, and improving the performance and efficiency of the system.
Patent Information
- Application Number
- CN202311085606.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-25
- Publication Date
- 2025-02-25
AI Technical Summary
The prior art is difficult to realize high-speed operation of the system when reading port B and port C, and it is necessary to use an inverter to determine the storage status.
A three-port SRAM circuit is designed, and by adding the third P-type transistor P3 and the fourth P-type transistor P4, as well as the fifth N-type transistor N5 and the sixth N-type transistor N6, the high-speed reading function of the B-port and the C-port is realized, and the dependence on the inverter is avoided through synchronous holding/discharging.
It realizes high-speed operation of the system when reading port B and port C, simplifies the storage state judgment process, and improves the performance and efficiency of the system.
Smart Images
Figure CN119517114A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to semiconductor circuit design technology, and in particular to a three-port SRAM (Static Random Access Memory) circuit. Background Art
[0002] Among volatile memories, SRAM (Static Random Access Memory) has the characteristics of low power consumption and high performance, and DRAM (Dynamic Random Access Memory) has the characteristics of low cost and large storage capacity.
[0003] In order to improve system performance, various memory circuits are currently embedded in SOC (system on a chip). In particular, SRAM (static random access memory) circuits are compatible with the current CMOS process and are usually used in L1 / L2 cache (first-level / second-level high-speed cache) in computing chips, making them the first choice for embedded memory.
[0004] There is a 6T SP (6Transistor single port) SRAM such as Figure 1 As shown, the data state is stored by the first node n1 and the second node n2. When the word line WL=1, the first P-type transistor P1 and the second P-type transistor P2 are turned on, and the first bit line BL1 and the second bit line BL2 are used for writing or reading. The first bit line BL1 and the second bit line BL2 are located at the same port (1port), and the functions are writable and readable, and the operation speed is average. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide a three-port SRAM circuit, which is beneficial for the system to operate peripheral circuits and read the B port and the C port at high speed at the same time.
[0006] To solve the above technical problems, the present invention provides a three-port SRAM circuit, which includes a first P-type transistor P1, a second P-type transistor P2, a third P-type transistor P3, a fourth P-type transistor P4, a first N-type transistor N1, a second N-type transistor N2, a third N-type transistor N3, a fourth N-type transistor N4, a fifth N-type transistor N5 and a sixth N-type transistor N6;
[0007] The source terminals of the first P-type transistor P1 and the second P-type transistor P2 are connected to the working voltage Vdd;
[0008] The gate terminal of the first P-type transistor P1, the drain terminal of the second P-type transistor P2, the gate terminal of the first N-type transistor N1, the drain terminal of the second N-type transistor N2 and the gate terminal of the fifth N-type transistor N5 are connected to the second node n2;
[0009] The gate terminal of the second P-type transistor P2, the drain terminal of the first P-type transistor P1, the gate terminal of the second N-type transistor N2, the drain terminal of the first N-type transistor N1 and the gate terminal of the third P-type transistor P3 are connected to the first node n1;
[0010] The gate terminals of the third N-type transistor N3 and the fourth N-type transistor N4 are connected to the A-word line A-WL;
[0011] The source and drain of the third N-type transistor N3 are respectively connected to the first node n1 and the first bit line BL1;
[0012] The source and drain of the fourth N-type transistor N4 are respectively connected to the second node n2 and the second bit line BL2;
[0013] A fourth P-type transistor P4, whose gate terminal is connected to the C-word line C-WL, and whose source and drain are respectively connected to the source terminal of the third P-type transistor P3 and the C-port bit line;
[0014] a sixth N-type transistor N6, whose gate terminal is connected to the B-word line B-WL, and whose source and drain are respectively connected to the drain terminal of the fifth N-type transistor N5 and the B-port bit line;
[0015] The source terminal of the first N-type transistor N1, the source terminal of the second N-type transistor N2, the drain terminal of the third P-type transistor P3 and the source terminal of the fifth N-type transistor N5 are connected to the common ground Vss.
[0016] Preferably, the A-word line A-WL, the first bit line BL1 and the second bit line BL2 belong to the A port;
[0017] The C-word line C-WL and the C-port bit line belong to the C-port;
[0018] The B word line B-WL and the B port bit line belong to the B port.
[0019] Preferably, the third P-type transistor P3 and the fourth P-type transistor P4 are field effect transistors FET;
[0020] The fifth N-type transistor N5 and the sixth N-type transistor N6 are field effect transistors FETs.
[0021] Preferably, the third P-type transistor P3 , the fourth P-type transistor P4 , the fifth N-type transistor N5 , and the sixth N-type transistor N6 are junction field effect transistors FET or metal oxide semiconductor field effect transistors FET.
[0022] Preferably, the first P-type transistor P1 and the second P-type transistor P2 are PMOS transistors;
[0023] The first N-type transistor N1 , the second N-type transistor N2 , the third N-type transistor N3 and the fourth N-type transistor N4 are NMOS transistors.
[0024] Preferably, the fourth P-type transistor P4 has a source terminal connected to the C-port bit line, and a drain terminal connected to the source terminal of the third P-type transistor P3;
[0025] The sixth N-type transistor N6 has a source connected to the drain of the fifth N-type transistor N5 and a drain connected to the B-port bit line.
[0026] Preferably, the first P-type transistor P1 is located on the left side of the second P-type transistor P2;
[0027] The first N-type transistor N1 and the third N-type transistor N3 are located on the left side of the first P-type transistor P1, and the first N-type transistor N1 is located in front of the third N-type transistor N3;
[0028] The third P-type transistor P3 and the fourth P-type transistor P4 are located on the left side of the first N-type transistor N1 and the third N-type transistor N3, and the third P-type transistor P3 is located in front of the fourth P-type transistor P4;
[0029] The second N-type transistor N2 and the fourth N-type transistor N4 are located on the right side of the second P-type transistor P2, and the second N-type transistor N2 is located on the rear side of the fourth N-type transistor N4;
[0030] The fifth N-type transistor N5 and the sixth N-type transistor N6 are located at the right side of the second N-type transistor N2 and the fourth N-type transistor N4, and the fifth N-type transistor N5 is located at the rear side of the sixth N-type transistor N6.
[0031] Preferably, the left-right center lines of the first P-type transistor P1, the first N-type transistor N1, the third P-type transistor P3, the fourth N-type transistor N4, the sixth N-type transistor N6 and the gate polysilicon are on the same straight line;
[0032] The left-right center lines of the gate polysilicon of the second P-type transistor P2, the third N-type transistor N3, the fourth P-type transistor P4, the second N-type transistor N2 and the fifth N-type transistor N5 are on the same straight line.
[0033] The three-port SRAM circuit of the present invention, the storage states of the first node n1 and the second node n2 of the 6T SP (6Transistor single port) SRAM circuit are opposite, so that the third P-type transistor P3 whose gate end corresponds to the first node n1 and the fifth N-type transistor N5 whose gate end corresponds to the second node n2 can be turned on / off at the same time. When the system is in the reading state, that is, when the sixth N-type transistor N6 and the fourth P-type transistor P4 are both turned on, the C-port bit line C-BL and the B-port bit line B-BL can be synchronously maintained / discharged, so as to facilitate the system to operate the peripheral circuit and read the B port and the C port at high speed at the same time, and the system does not need to use an inverter to judge the storage state when operating the peripheral circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0035] Figure 1 This is an existing 6T SP SRAM circuit diagram;
[0036] Figure 2 is a circuit diagram of an embodiment of a three-port SRAM circuit of the present invention;
[0037] Figure 3 It is a high-speed read port holding state of a three-port SRAM circuit of an embodiment of the present invention;
[0038] Figure 4 It is a high-speed read port discharge state of an embodiment of a three-port SRAM circuit of the present invention;
[0039] Figure 5 FIG. 4 is a chip layout of a three-port SRAM circuit according to an embodiment of the present invention. DETAILED DESCRIPTION
[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0041] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.
[0042] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.
[0043] Embodiment 1
[0044] like Figure 2 As shown, a three-port SRAM (Static Random Access Memory) circuit includes a first P-type transistor P1, a second P-type transistor P2, a third P-type transistor P3, a fourth P-type transistor P4, a first N-type transistor N1, a second N-type transistor N2, a third N-type transistor N3, a fourth N-type transistor N4, a fifth N-type transistor N5 and a sixth N-type transistor N6;
[0045] The source terminals of the first P-type transistor P1 and the second P-type transistor P2 are connected to the working voltage Vdd;
[0046] The gate terminal of the first P-type transistor P1, the drain terminal of the second P-type transistor P2, the gate terminal of the first N-type transistor N1, the drain terminal of the second N-type transistor N2 and the gate terminal of the fifth N-type transistor N5 are connected to the second node n2;
[0047] The gate terminal of the second P-type transistor P2, the drain terminal of the first P-type transistor P1, the gate terminal of the second N-type transistor N2, the drain terminal of the first N-type transistor N1 and the gate terminal of the third P-type transistor P3 are connected to the first node n1;
[0048] The gate terminals of the third N-type transistor N3 and the fourth N-type transistor N4 are connected to the A-word line A-WL;
[0049] The source and drain of the third N-type transistor N3 are respectively connected to the first node n1 and the first bit line BL1;
[0050] The source and drain of the fourth N-type transistor N4 are respectively connected to the second node n2 and the second bit line BL2;
[0051] A fourth P-type transistor P4, whose gate terminal is connected to the C word line C-WL, and whose source and drain are respectively connected to the source terminal of the third P-type transistor P3 and the C port bit line C-BL;
[0052] A sixth N-type transistor N6, whose gate terminal is connected to the B word line B-WL, and whose source and drain are respectively connected to the drain terminal of the fifth N-type transistor N5 and the B port bit line B-BL;
[0053] The source terminal of the first N-type transistor N1, the source terminal of the second N-type transistor N2, the drain terminal of the third P-type transistor P3 and the source terminal of the fifth N-type transistor N5 are connected to the common ground Vss.
[0054] The A-word line A-WL, the first bit line BL1 and the second bit line BL2 belong to the A port;
[0055] The C-word line C-WL and the C-port bit line belong to the C-port;
[0056] The B word line B-WL and the B port bit line belong to the B port.
[0057] The three-port SRAM circuit of the first embodiment is a 10T 3P (10Transistor 3port, 10 transistor three-port) SRAM architecture, which adds two read ports (read ports) on the basis of a 6T SP (6Transistor single port, 6 transistor single port) SRAM circuit. The A port is a 6T single port (6T SP) in the middle of the circuit, which can be written and read, and has a normal operating speed; the B port is a high-speed read port (read port) including two N-type transistors, a fifth N-type transistor N5 and a sixth N-type transistor N6, the gate terminal of the fifth N-type transistor N5 is connected to the second node n2, and is used for high-speed reading through the B-port bit line B-BL; the C port is a high-speed read port (read port) including two P-type transistors, a third P-type transistor P3 and a fourth P-type transistor P4, the gate terminal of the third P-type transistor P3 is connected to the first node n1, and is used for high-speed reading through the C-port bit line C-BL.
[0058] If n1=1, n2=0, the B word line (B-WL)=1, then the sixth N transistor N6 is turned on, the B port bit line B-BL is kept, and the B port is read as 1;
[0059] If n1=0, n2=1, the B word line (B-WL)=1, then the sixth N transistor N6 is turned on, the B port bit line B-BL is discharged, and the B port is read as 0;
[0060] If n1=1, n2=0, C word line (C-WL)=0, the fourth P transistor P4 is turned on, the C port bit line C-BL is kept, and the C port is read as 1;
[0061] If n1=0, n2=1, the C word line (B-WL)=0, then the fourth P transistor P4 is turned on, the C port bit line C-BL is discharged, and the C port is read as 0;
[0062] The C port and the B port are connected to the first node n1 and the second node n2 inside the 6T single port (6T SP) respectively, which is a complementary matching method to achieve the functions of simultaneous opening and closing.
[0063] When n1=0, n2=1 (the internal storage data state of 6T SP is 0), the connection corresponds to the gate end of the fifth N-type transistor N5 to turn on the fifth N-type transistor N5, and the connection corresponds to the gate end of the third P-type transistor P3 to turn on the third P-type transistor P3; the C port and the B port simultaneously read the storage data 0, as shown in Table 1 and Figure 3 shown.
[0064] Table 1
[0065]
[0066] When n1=1, n2=0 (the internal storage data state of 6T SP is 1), the corresponding connection is to the gate end of the fifth N-type transistor N5 to turn off the fifth N-type transistor N5, and the corresponding connection is to the gate end of the third P-type transistor P3 to turn off the third P-type transistor P3. The storage data 1 read by the C port and the B port at the same time is shown in Table 2 and Figure 4 shown.
[0067] Table 2
[0068]
[0069] In the three-port SRAM circuit of the first embodiment, the storage states of the first node n1 and the second node n2 of the 6T SP (6Transistor single port) SRAM circuit are opposite, so that the third P-type transistor P3 with the gate terminal corresponding to the first node n1 and the fifth N-type transistor N5 with the gate terminal corresponding to the second node n2 can be turned on at the same time.
[0070] When the system is in the reading state, that is, when the sixth N-type transistor N6 and the fourth P-type transistor P4 are both turned on, the C-port bit line C-BL and the B-port bit line B-BL can be synchronously maintained / discharged, so that the system can operate the peripheral circuit to read the B port and the C port at high speed at the same time, and the system can operate the peripheral circuit without using an inverter to determine the storage state.
[0071] Embodiment 2
[0072] Based on the three-port SRAM circuit of the first embodiment, the third P-type transistor P3 and the fourth P-type transistor P4 are field effect transistors FET;
[0073] The fifth N-type transistor N5 and the sixth N-type transistor N6 are field effect transistors FETs.
[0074] Preferably, the third P-type transistor P3 , the fourth P-type transistor P4 , the fifth N-type transistor N5 , and the sixth N-type transistor N6 are junction field effect transistors JFET or metal oxide semiconductor field effect transistors MOSFET.
[0075] Preferably, the first P-type transistor P1 and the second P-type transistor P2 are PMOS transistors;
[0076] The first N-type transistor N1 , the second N-type transistor N2 , the third N-type transistor N3 and the fourth N-type transistor N4 are NMOS transistors.
[0077] Preferably, the fourth P-type transistor P4 has a source terminal connected to the C-port bit line, and a drain terminal connected to the source terminal of the third P-type transistor P3;
[0078] The sixth N-type transistor N6 has a source connected to the drain of the fifth N-type transistor N5 and a drain connected to the B-port bit line.
[0079] In the three-port SRAM circuit of the second embodiment, the B port uses two P-type field effect transistor FET components, and the C port uses two N-type field effect transistor FET components.
[0080] Embodiment 3
[0081] Based on the three-port SRAM circuit of the first embodiment, as Figure 5 As shown, the chip layout structure is:
[0082] The first P-type transistor P1 is located on the left side of the second P-type transistor P2;
[0083] The first N-type transistor N1 and the third N-type transistor N3 are located on the left side of the first P-type transistor P1, and the first N-type transistor N1 is located in front of the third N-type transistor N3;
[0084] The third P-type transistor P3 and the fourth P-type transistor P4 are located on the left side of the first N-type transistor N1 and the third N-type transistor N3, and the third P-type transistor P3 is located in front of the fourth P-type transistor P4;
[0085] The second N-type transistor N2 and the fourth N-type transistor N4 are located on the right side of the second P-type transistor P2, and the second N-type transistor N2 is located on the rear side of the fourth N-type transistor N4;
[0086] The fifth N-type transistor N5 and the sixth N-type transistor N6 are located at the right side of the second N-type transistor N2 and the fourth N-type transistor N4, and the fifth N-type transistor N5 is located at the rear side of the sixth N-type transistor N6.
[0087] Preferably, the left-right center lines of the first P-type transistor P1, the first N-type transistor N1, the third P-type transistor P3, the fourth N-type transistor N4, the sixth N-type transistor N6 and the gate polysilicon are on the same straight line;
[0088] The left-right center lines of the gate polysilicon of the second P-type transistor P2, the third N-type transistor N3, the fourth P-type transistor P4, the second N-type transistor N2 and the fifth N-type transistor N5 are on the same straight line.
[0089] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A three-port SRAM circuit, characterized in that: It includes a first P-type transistor (P1), a second P-type transistor (P2), a third P-type transistor (P3), a fourth P-type transistor (P4), a first N-type transistor (N1), a second N-type transistor (N2), a third N-type transistor (N3), a fourth N-type transistor (N4), a fifth N-type transistor (N5) and a sixth N-type transistor (N6); The source terminals of the first P-type transistor (P1) and the second P-type transistor (P2) are connected to an operating voltage (Vdd); The gate terminal of the first P-type transistor (P1), the drain terminal of the second P-type transistor (P2), the gate terminal of the first N-type transistor (N1), the drain terminal of the second N-type transistor (N2) and the gate terminal of the fifth N-type transistor (N5) are connected to the second node (n2); The gate terminal of the second P-type transistor (P2), the drain terminal of the first P-type transistor (P1), the gate terminal of the second N-type transistor (N2), the drain terminal of the first N-type transistor (N1) and the gate terminal of the third P-type transistor (P3) are connected to the first node (n1); The gate terminals of the third N-type transistor (N3) and the fourth N-type transistor (N4) are connected to the A-word line (A-WL); The source and drain of the third N-type transistor (N3) are respectively connected to the first node (n1) and the first bit line (BL1); The source and drain of the fourth N-type transistor (N4) are respectively connected to the second node (n2) and the second bit line (BL2); a fourth P-type transistor (P4), whose gate terminal is connected to the C-word line (C-WL), and whose source and drain are respectively connected to the source terminal of the third P-type transistor (P3) and the C-port bit line; a sixth N-type transistor (N6), whose gate terminal is connected to the B-word line (B-WL), and whose source and drain are respectively connected to the drain terminal of the fifth N-type transistor (N5) and the B-port bit line; The source terminal of the first N-type transistor (N1), the source terminal of the second N-type transistor (N2), the drain terminal of the third P-type transistor (P3) and the source terminal of the fifth N-type transistor (N5) are connected to a common ground (Vss).
2. The three-port SRAM circuit according to claim 1, characterized in that: The A-word line (A-WL), the first bit line (BL1) and the second bit line (BL2) belong to the A port; The C-word line (C-WL) and C-port bit lines belong to the C-port; The B word line (B-WL) and the B port bit line belong to the B port.
3. The three-port SRAM circuit according to claim 1, characterized in that: The third P-type transistor (P3) and the fourth P-type transistor (P4) are field effect transistors; The fifth N-type transistor (N5) and the sixth N-type transistor (N6) are field effect transistors.
4. The three-port SRAM circuit according to claim 1, characterized in that: The third P-type transistor (P3), the fourth P-type transistor (P4), the fifth N-type transistor (N5), and the sixth N-type transistor (N6) are junction field effect transistors or metal oxide semiconductor field effect transistors.
5. The three-port SRAM circuit according to claim 1, characterized in that: The first P-type transistor (P1) and the second P-type transistor (P2) are PMOS transistors; The first N-type transistor (N1), the second N-type transistor (N2), the third N-type transistor (N3) and the fourth N-type transistor (N4) are NMOS transistors.
6. The three-port SRAM circuit according to claim 1, characterized in that: The fourth P-type transistor (P4) has a source terminal connected to the C-port bit line and a drain terminal connected to the source terminal of the third P-type transistor (P3); The sixth N-type transistor (N6) has a source connected to the drain of the fifth N-type transistor (N5) and a drain connected to the B-port bit line.
7. The three-port SRAM circuit according to claim 1, characterized in that: The chip layout structure is: The first P-type transistor (P1) is located on the left side of the second P-type transistor (P2); The first N-type transistor (N1) and the third N-type transistor (N3) are located on the left side of the first P-type transistor (P1), and the first N-type transistor (N1) is located in front of the third N-type transistor (N3); The third P-type transistor (P3) and the fourth P-type transistor (P4) are located on the left side of the first N-type transistor (N1) and the third N-type transistor (N3), and the third P-type transistor (P3) is located in front of the fourth P-type transistor (P4); The second N-type transistor (N2) and the fourth N-type transistor (N4) are located on the right side of the second P-type transistor (P2), and the second N-type transistor (N2) is located on the rear side of the fourth N-type transistor (N4); The fifth N-type transistor (N5) and the sixth N-type transistor (N6) are located on the right side of the second N-type transistor (N2) and the fourth N-type transistor (N4), and the fifth N-type transistor (N5) is located behind the sixth N-type transistor (N6).
8. The three-port SRAM circuit according to claim 7, characterized in that: The chip layout structure is: The left-right center lines of the first P-type transistor (P1), the first N-type transistor (N1), the third P-type transistor (P3), the fourth N-type transistor (N4), the sixth N-type transistor (N6) and the gate polysilicon are on the same straight line; The left-right center lines of the gate polysilicon of the second P-type transistor (P2), the third N-type transistor (N3), the fourth P-type transistor (P4), the second N-type transistor (N2) and the fifth N-type transistor (N5) are on the same straight line.