Nonvolatile memory and reading method thereof
By designing a clock signal processing circuit in nonvolatile memory, the input clock signal is subject to anti-interference and filtering, and clock signals of different quality are provided, which solves the problem of clock signals being affected by the environment and improves the stability and timeliness of the memory.
Patent Information
- Application Number
- CN202411496199.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2025-02-25
AI Technical Summary
In complex application environments, clock signals of nonvolatile memory are susceptible to factors such as temperature and humidity, which leads to the impact of stability and timeliness, which in turn affect the performance of electronic systems.
A nonvolatile memory is designed, including a clock signal processing circuit, which processes the input clock signal through anti-interference and filtering processing, obtains clock signals of different quality, and provides clock signals of corresponding quality according to the needs of different working circuits.
By processing the clock signal, the stability of the readout operation and the timeliness of the output of the non-volatile memory during the data reading process are improved, thereby improving the product performance of the memory.
Smart Images
Figure CN119517122A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor memory, and in particular to a non-volatile memory and a reading method thereof. Background Art
[0002] Non-volatile memory (NVM) is a type of memory that can retain stored information even after power is turned off. It is widely used in many electronic systems that require long-term data storage, such as computer systems and mobile devices.
[0003] During the operation of the non-volatile memory, various working circuits inside the memory usually rely on clock signals to work in coordination, thereby completing operations such as writing and reading data.
[0004] The clock signal is usually a pulse signal with a certain frequency and duty cycle. In some complex application environments, the clock signal is very susceptible to disturbances caused by factors such as temperature and humidity, which affects the stability and timeliness of the non-volatile memory and further has a negative impact on the performance of the electronic system. Summary of the invention
[0005] In view of the above problems, the purpose of the present application is to provide a non-volatile memory and a reading method thereof, so as to improve the performance of the non-volatile memory.
[0006] According to one aspect of the present application, a non-volatile memory is provided, which includes: a clock signal processing circuit, which performs anti-interference processing on an input clock signal to obtain a first clock signal, and performs filtering processing on the first clock signal to obtain a second clock signal; a first circuit unit, which includes at least a storage array for providing storage data, and the first circuit unit outputs the corresponding storage data according to a corresponding instruction signal at the timing of the second clock signal; and a second circuit unit, which includes at least an interface circuit for providing an output signal of the non-volatile memory, and the second circuit unit latches and outputs the storage data as the output signal at the timing of the first clock signal.
[0007] Optionally, a delay of the second clock signal compared to the input clock signal is greater than a delay of the first clock signal compared to the input clock signal; and a noise of the second clock signal is less than a noise of the first clock signal.
[0008] Optionally, the clock signal processing circuit includes: an anti-interference module, performing anti-interference processing on the input clock signal to obtain the first clock signal; and a filtering module, performing filtering processing on the first clock signal to obtain the second clock signal.
[0009] Optionally, the clock signal processing circuit further includes: a high-voltage isolation module, which receives the input clock signal and provides the input clock signal after high-voltage isolation to the anti-interference module.
[0010] Optionally, the second circuit unit includes: an output latch unit that latches the storage data in one of a high level state and a low level state of the first clock signal; and outputs the latched storage data in another level state.
[0011] Optionally, the first circuit unit further includes: a timing control unit, which provides a corresponding timing control signal according to the second clock signal and the instruction signal; and a data flow unit, which outputs the corresponding stored data according to the corresponding timing control signal.
[0012] According to another aspect of the present application, a method for reading a non-volatile memory is provided, which includes: performing anti-interference processing on an input clock signal to obtain a first clock signal; performing filtering processing on the first clock signal to obtain a second clock signal; outputting corresponding storage data in a storage array according to a corresponding instruction signal at the timing of the second clock signal; and latching and outputting the storage data as an output signal of the non-volatile memory at the timing of the first clock signal.
[0013] Optionally, a delay of the second clock signal compared to the input clock signal is greater than a delay of the first clock signal compared to the input clock signal; and a noise of the second clock signal is less than a noise of the first clock signal.
[0014] Optionally, before obtaining the first clock signal, the non-volatile memory reading method further includes performing high voltage isolation on the input clock signal.
[0015] Optionally, the method of latching and outputting the stored data comprises: latching the stored data in one of a high level state and a low level state of the first clock signal; and outputting the latched stored data in another level state.
[0016] According to the non-volatile memory and the reading method thereof provided by the present application, the input clock signal is processed differently to provide a clock signal of corresponding quality according to the working requirements of different working circuits inside the non-volatile memory. Therefore, the stability of the read operation and the timeliness of the output can be taken into account during the data read process of the non-volatile memory, thereby improving the product performance of the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0018] Figure 1 A schematic block diagram of a non-volatile memory according to an embodiment of the present application is shown;
[0019] Figure 2 Show Figure 1 A schematic block diagram of a clock signal processing circuit shown;
[0020] Figure 3 Show Figure 1 A schematic block diagram of the first circuit unit shown;
[0021] Figure 4 Show Figure 1 A schematic block diagram of the second circuit unit shown;
[0022] Figure 5 A schematic flow chart of a non-volatile memory reading method according to an embodiment of the present application is shown. DETAILED DESCRIPTION
[0023] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.
[0024] At the same time, certain words are used in this specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.
[0025] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.
[0026] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.
[0027] It should also be noted that, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.
[0028] The clock signal is a necessary signal in the working process of the non-volatile memory. When the non-volatile memory is working, it provides an accurate time reference for its internal working circuits, so that these working circuits can work together to complete data transmission and processing.
[0029] However, the clock signal is usually a pulse signal with a preset frequency and duty cycle, which can be easily affected by factors such as temperature changes, humidity changes or other factors, resulting in frequency changes or signal distortion, thereby causing the operation of the non-volatile memory (such as read or write operations) to fail, greatly affecting the working stability of the non-volatile memory.
[0030] The present application provides a non-volatile memory, which obtains at least two clock signals of different qualities by setting a clock signal processing circuit to perform different processing on an input clock signal, and provides a clock signal of corresponding quality to each working circuit according to the requirements of different working circuits inside the non-volatile memory, thereby improving the performance of each working circuit inside the non-volatile memory.
[0031] Figure 1 A schematic block diagram of a non-volatile memory according to an embodiment of the present application is shown; Figure 2 Show Figure 1 A schematic block diagram of a clock signal processing circuit shown; Figure 3 Show Figure 1 A schematic block diagram of the first circuit unit shown; Figure 4 Show Figure 1 The schematic block diagram of the second circuit unit is shown below. Figures 1 to 4 The non-volatile memory provided in this application is described in detail.
[0032] For ease of description, the non-volatile memory is used as an example to perform a read operation in this specification. Figure 1 As shown, the non-volatile memory 100 provided by the present application includes, for example: a clock signal processing circuit 110, a first circuit unit 120 and a second circuit unit 130. Among them, the clock signal processing circuit 110 is used to receive an input clock signal CLK and process the input clock signal CLK to obtain at least two clock signals of different qualities; the first circuit unit 120 is used to read out corresponding storage data according to a corresponding instruction signal; the second circuit unit 130 is used to latch and output the read storage data as an output signal of the non-volatile memory. And because the first circuit unit 120 requires a clock signal with less noise during operation to make the read operation more stable and reliable; the second circuit unit 130 requires a clock signal with a smaller delay during operation to make the signal output more timely, so in Figure 1 In the illustrated embodiment, it is taken as an example that the clock signal processing circuit 110 provides two clock signals (a first clock signal ICLK1 and a second clock signal ICLK2 ).
[0033] Specifically, Figure 2 As shown, the clock signal processing circuit 110 includes, for example, a high-voltage isolation module 111 , an anti-interference module 112 and a filtering module 113 which are connected in sequence.
[0034] The anti-interference module 112 is used to perform anti-interference processing on the input clock signal CLK to obtain the first clock signal ICLK1. Figure 1 In the embodiment shown, the first clock signal ICLK1 is provided to the second circuit unit 130 so that the second circuit unit 130 latches and outputs the read storage data at the timing of the first clock signal. Therefore, in order to ensure the timeliness requirement of the output signal, the delay of the first clock signal ICLK1 compared to the input clock signal CLK should be less than the preset time length.
[0035] That is to say, in Figure 1 In the illustrated embodiment, any low-delay circuit with certain anti-interference capability in the prior art may be selected for the anti-interference module 112. Accordingly, since the delay time is less than the preset time, it means that the processing flow of the input clock signal CLK is less, and thus the first clock signal ICLK1 may still have flip ringing and short glitches.
[0036] Furthermore, due to Figure 1In the embodiment shown, the second clock signal ICLK2 is provided to the first circuit unit 120 so that the first circuit unit 120 reads out the corresponding stored data according to the corresponding instruction signal at the timing of the second clock signal. Therefore, in order to meet the requirements for the reliability of the read operation, the second clock signal ICLK2 should be more reliable and stable. Figure 2 As shown, the clock signal processing circuit further includes a filtering module 113 to further filter the first clock signal ICLK1 to obtain a second clock signal ICLK2 that is more stable and reliable but has a longer delay. (That is, the delay of the second clock signal ICLK2 compared to the input clock signal CLK is greater than the delay of the first clock signal ICLK1 compared to the input clock signal CLK, and the noise of the second clock signal ICLK is less than the noise of the first clock signal ICLK).
[0037] Similarly, in Figure 2 In the embodiment shown, the filter module 113 may use any strong filter circuit in the prior art with a filtering capability greater than the preset requirement. Accordingly, less noise means that the processing flow of the first clock signal ICLK1 is more complicated, so the second clock signal ICLK2 may have a longer delay than the input clock signal CLK.
[0038] In addition, since the disturbed input clock signal CLK may suddenly change (for example, the current or voltage of the clock signal suddenly increases), the subsequent current may be damaged. Therefore, the clock signal processing circuit 110 in the embodiment of the present application also includes a high-voltage isolation module 111. The input clock signal CLK is provided to the anti-interference module 112 after high-voltage isolation by the high-voltage isolation module 111, thereby avoiding damage to the non-volatile memory.
[0039] The first circuit unit 120 at least includes a storage array 122 for providing storage data to output corresponding storage data according to a corresponding instruction signal at the timing of the second clock signal ICLK2.
[0040] In addition, the first circuit unit 120 should also include a plurality of sub-functional circuits that cooperate with the storage array 122 to enable the storage array to perform operations such as erase / write / read. Figure 3 The sub-functional circuits including the timing control unit 121, the row decoder 123, the column decoder 124 and the data flow unit (including the detection unit 125 and the data amplification unit 126) are shown. However, it should be understood that Figure 3 Not all of the above sub-functional circuits are shown. For example, in some embodiments, the first circuit unit 120 further includes sub-functional circuits such as a multiplexer corresponding to the storage array.
[0041] The timing control unit 121 provides a corresponding timing control signal according to the second clock signal ICLK2 and the command signal CMD. It should be understood that the timing control signal is a general term for a type of signal rather than a single signal. For example, see Figure 3 The timing control signals include a word selection signal WLP, a column selection signal BLP, a detection enable signal SE, and a data amplification enable signal RE (which will be described in detail below).
[0042] The memory array 122 includes, for example, a plurality of memory cells MC arranged in an array. Each memory cell MC has a capacitor that holds data as a charge and a transistor that is a switching element and connected between the capacitor and the corresponding bit line BL, and the gate of the transistor is connected to the corresponding word line WL. The row decoder 123 and the column decoder 124 read the corresponding memory cell according to the corresponding row and column address WADD / column address BADD and the timing control signal (including the word selection signal WLP and the column selection signal BLP). The data flow unit (for example, including the detection unit 125 and the data amplification unit 126) outputs the storage data corresponding to the memory cell according to the reading result of the memory cell and the corresponding timing control signal (for example, including the detection enable signal SE and the data amplification enable signal RE).
[0043] Specifically, during the active level of the word selection signal WLP, the row decoder 123 activates the word line WL corresponding to the row address WADD. The detection unit 125 is enabled by the active level of the detection enable signal SE to detect the voltage difference of the plurality of column lines BL associated with the word line.
[0044] During the active level of the column select signal BLP, the column decoder 124 activates the column line BL corresponding to the column address BADD. The data amplifier unit 126 is enabled by the active level of the data amplification enable signal RE, amplifies and outputs the signal on the corresponding column line as the read storage data.
[0045] Since the second clock signal ICLK2 has less noise, the working stability of each unit and each module in the first circuit unit 120 is improved, making the read storage data Data more reliable.
[0046] The second circuit unit 130 at least includes an interface circuit for providing an output signal of the non-volatile memory. The second circuit unit 130 latches and outputs the storage data output by the first circuit unit 130 at the timing of the first clock signal ICLK1 as the output signal of the non-volatile memory.
[0047] like Figure 4 As shown, the interface circuit of the second circuit unit 130 includes an output latch unit 131 and a driving enhancement unit 132 which are connected in sequence.
[0048] Specifically, the output latch unit 131 outputs / latches the storage data Data read out by the first circuit unit 120 at the timing of the first clock signal ICLK1. In some embodiments, since the first clock signal ICLK1 may still have flip ringing and glitches, the output latch unit 131 works in a level latching manner. That is, the latch unit 131 latches the storage data Data read out by the data processing unit 120 in one of the high level state and the low level state of the first clock signal ICLK1, and reads the latched data as the output signal of the non-volatile memory in the other of the high level state and the low level state of the first clock signal ICLK1. In this way, when the first clock signal ICLK1 is unstable, only the latch module that needs to be turned on is latched and output for a short time (it can be understood that the data that was originally output and latched at one time is latched and output multiple times), and the latched data itself at this time is the data that needs to be output, so it does not affect the correctness of the output signal.
[0049] In addition, in some embodiments, the second circuit unit 130 further includes a driving enhancement unit 132 to enhance the driving capability of the second circuit unit 130, so that the output signal is more stable and accurate, which is beneficial to reduce the error probability of the output signal, thereby improving the performance of the non-volatile memory.
[0050] It should be noted that in Figure 1 In the illustrated embodiment, only the circuit modules related to data readout are shown and the corresponding clock signals ICLK2 and ICLK1 are provided according to the readout workflow. However, it should be understood that the present application should not be limited thereto. For example, each first circuit unit 120 or second circuit unit 130 may be further subdivided into modules to provide a clock signal that better meets the requirements. Accordingly, it should also be understood that the clock signal processing circuit 110 may also provide more clock signals of different qualities.
[0051] According to the non-volatile memory provided by the present application, the input clock signal is processed differently to provide a clock signal of corresponding quality according to the working requirements of different working circuits inside the non-volatile memory. Therefore, the stability of the read operation and the timeliness of the output can be taken into account during the data read process of the non-volatile memory, thereby improving the product performance of the non-volatile memory.
[0052] The present application also provides a method for reading a non-volatile memory. Figure 5 FIG. 1 is a schematic flow chart of a non-volatile memory reading method according to an embodiment of the present application. Figure 5 As shown, the non-volatile memory reading method provided by the present application includes the following steps:
[0053] In step S11, anti-interference processing is performed on the input clock signal to obtain a first clock signal;
[0054] In step S12, filtering is performed on the first clock signal to obtain a second clock signal;
[0055] In step S13, the corresponding stored data is read out according to the corresponding instruction signal at the timing of the second clock signal; and
[0056] In step S14, the read storage data is latched and output as an output signal of the nonvolatile memory at the timing of the first clock signal.
[0057] In the reading method of the non-volatile memory provided in the present application, a clock signal with less noise is required in the process of reading the stored data to make the reading operation more stable and reliable; a clock signal with less delay is required in the process of outputting the stored data to make the timeliness of the signal output higher. Therefore, in an embodiment of the present application, at least a second clock signal and a first clock signal of different qualities are provided. Among them, the delay of the second clock signal compared to the input clock signal is greater than the delay of the first clock signal compared to the input clock signal, and the noise of the second clock signal is less than the noise of the first clock signal.
[0058] Among them, the anti-interference processing of the first clock signal can select any signal anti-interference processing method in the prior art, but since the first clock signal is used to provide the output timing of the non-volatile memory, it should be understood that the delay of the first clock signal compared with the external signal should be less than the preset duration. Accordingly, since the delay duration is less than the preset duration, it means that the detailed processing steps of the anti-interference processing method are fewer, so in some cases (such as extremely harsh environments), the first clock signal may still have flip ringing and short glitches.
[0059] In order to avoid the influence of possible flip ringing and short glitches on the accuracy of the output signal. In some embodiments, the method of latching and outputting the stored data includes a level latching method. That is, the read stored data is latched in one of the high level state and the low level state of the first clock signal, and the latched data is read out in the other level state of the high level state and the low level state of the first clock signal as the output signal of the non-volatile memory. In this way, when the first clock signal is unstable, only the latch module that needs to be turned on is latched and output for a short time (it can be understood that the data that was originally output and latched at one time is latched and output multiple times), and the latched data itself at this time is the data that needs to be output, so it does not affect the correctness of the output signal.
[0060] In addition, the filtering method for filtering the first clock signal to obtain the second clock signal can also adopt any filtering method in the prior art. However, it should also be understood that since the second clock signal is used to provide the operation timing of data reading, the stability of the second clock signal has higher requirements. Therefore, the filtering method used when filtering the first clock signal should provide a filtering capacity greater than the preset requirement. Correspondingly, a stronger filtering capacity also means a more complex filtering process, so the delay of the second clock signal compared to the input clock signal is longer.
[0061] Furthermore, in some embodiments, in order to prevent the non-volatile memory from being damaged due to mutations (or spikes) caused by disturbances in the clock signal, the input clock signal needs to be isolated at high voltage before anti-interference processing is performed on the input clock signal.
[0062] According to the non-volatile memory reading method provided by the present application, the input clock signal is processed differently to provide a clock signal of corresponding quality according to the working requirements of different working circuits inside the non-volatile memory. Therefore, the stability of the read operation and the timeliness of the output can be taken into account during the data read process of the non-volatile memory, thereby improving the product performance of the non-volatile memory.
[0063] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.
Claims
1. A non-volatile memory, wherein: include: A clock signal processing circuit, performing anti-interference processing on an input clock signal to obtain a first clock signal, and performing filtering processing on the first clock signal to obtain a second clock signal; A first circuit unit at least comprises a storage array for providing storage data, wherein the first circuit unit outputs the corresponding storage data according to the corresponding instruction signal at the timing of the second clock signal; as well as The second circuit unit at least includes an interface circuit for providing the non-volatile memory output signal, and the second circuit unit latches and outputs the stored data as the output signal at the timing of the first clock signal.
2. The nonvolatile memory according to claim 1, wherein: The delay of the second clock signal compared to the input clock signal is greater than the delay of the first clock signal compared to the input clock signal; The second clock signal has less noise than the first clock signal.
3. The nonvolatile memory according to claim 2, wherein: The clock signal processing circuit comprises: an anti-interference module, performing anti-interference processing on the input clock signal to obtain the first clock signal; and A filtering module is used to filter the first clock signal to obtain the second clock signal.
4. The nonvolatile memory according to claim 3, wherein: The clock signal processing circuit also includes: The high-voltage isolation module receives the input clock signal and provides the input clock signal after high-voltage isolation to the anti-interference module.
5. The nonvolatile memory according to claim 3, wherein: The second circuit unit comprises: An output latch unit latches the storage data in one of a high level state and a low level state of the first clock signal; and outputs the latched storage data in another level state.
6. The nonvolatile memory according to claim 1, wherein: The first circuit unit further includes: a timing control unit, providing a corresponding timing control signal according to the second clock signal and the instruction signal; and The data flow unit outputs the corresponding stored data according to the corresponding timing control signal.
7. A method for reading a non-volatile memory, wherein: include: Performing anti-interference processing on the input clock signal to obtain a first clock signal; filtering the first clock signal to obtain a second clock signal; outputting corresponding storage data in the storage array according to the corresponding instruction signal at the timing of the second clock signal; as well as The stored data is latched and output as an output signal of the nonvolatile memory at the timing of the first clock signal.
8. The method for reading a non-volatile memory according to claim 7, wherein: The delay of the second clock signal compared to the input clock signal is greater than the delay of the first clock signal compared to the input clock signal; The second clock signal has less noise than the first clock signal.
9. The method for reading a non-volatile memory according to claim 7, wherein: Before obtaining the first clock signal, the non-volatile memory reading method further includes performing high voltage isolation on the input clock signal.
10. The method for reading a non-volatile memory according to claim 7, wherein: The method of latching and outputting the stored data comprises: latching the storage data in one of a high level state and a low level state of the first clock signal; and The latched storage data is outputted in another level state.