Method for determining timing parameters of storage chip, controller, device, and medium

Abstract

The present application discloses a method for determining the timing parameters of a memory chip, and a controller, device, and medium, and relates to the field of chip testing technology. The method includes determining the storage position by performing a row and column position determination process based on the current transmission delay determined by the initial transmission delay and the initial step value; updating the update delay test range and the update step value according to the verification result obtained by the read-write verification based on the storage position and the test pattern; the update delay test range includes a third end value and a fourth end value greater than the third end value; when the current step value is greater than or equal to the preset step threshold, performing a row and column position determination process, a read-write verification process, and an update process based on the update transmission delay determined by the third end value and the update step value and less than the fourth end value; until the update step value is less than the preset step threshold, the minimum reference value of the timing parameters of the memory chip is determined. It can improve the test efficiency and accuracy of the minimum reference value of the timing parameters of the memory chip.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a method for determining timing parameters of a memory chip, a controller, a device, and a medium. Background Art

[0002] DDR (Double Data Rate) chip is a synchronous dynamic random access memory. In DDR chip, the storage location is determined in the data storage unit through the row address strobe control signal and the column address strobe control signal. In the process of addressing and determining the storage location, the row address strobe control signal is usually sent first. After a certain time interval, the DDR chip is ensured to have enough time to precharge and open the required row, and the row address strobe control signal is stable. Then the column address strobe control signal is sent to select the storage location. This time interval is an important timing parameter of the DDR chip, which is used to indicate the transmission delay between the sending of the row address strobe control signal and the sending of the column address strobe control signal. If this timing parameter is configured too small, the column address strobe control signal may be sent before the row address strobe control signal is stable. In this way, the DDR chip will not be able to correctly receive the column address strobe control signal, and cannot correctly identify the combination of rows and columns, resulting in the inability to completely and correctly write data to the target storage location. In addition, the timing parameter t of different DDR chips is different, and there are different requirements for the timing parameters of DDR chips on different platforms. Some platforms are not compatible with some DDR chips. Therefore, before the DDR chips leave the factory, they need to be tested one by one and the value of the timing parameter t of the DDR chips needs to be determined, so as to select the DDR chips suitable for the platform. Usually, the delay to be tested needs to be verified one by one to determine the target delay as the timing parameter t, but this test method is inefficient and it is difficult to ensure the accuracy of the test. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for determining the timing parameters of a memory chip, a controller, a device, and a medium, which can improve the test efficiency and accuracy of the minimum reference value of the timing parameters of the memory chip, and provide a reliable reference in the process of screening the memory chip adapted for the platform.

[0004] In a first aspect, an embodiment of the present application provides a method for determining timing parameters of a memory chip, comprising:

[0005] Adding the initial transmission delay determined by the preconfigured initial delay test range to the preset initial step value to obtain the current transmission delay;

[0006] Performing row and column position determination processing based on the current sending delay to determine a storage position;

[0007] Based on the storage location and the test pattern, a read-write verification process is performed on the storage chip to be tested to obtain a verification result;

[0008] According to the verification result, a first update process is performed on the current delay test range to obtain an updated delay test range, and a second update process is performed on the initial step value to determine an updated step value; the updated delay test range includes a third end value and a fourth end value greater than the third end value;

[0009] When the current step value is greater than or equal to the preset step value, the third end value and the update step value are added to obtain the update transmission delay; when the update transmission delay is less than the fourth end value, the row and column position determination process, the read and write verification process, the first update process, and the second update process are sequentially performed based on the update transmission delay;

[0010] Until the update step value is less than the preset step threshold, the update sending delay that most recently made the verification result pass is determined as the target sending delay, and the target sending delay is output as the minimum reference value of the timing parameter of the memory chip.

[0011] According to some embodiments of the present application, the performing row and column position determination processing based on the current transmission delay to determine the storage position includes:

[0012] Sending a row address strobe control signal to determine the row address;

[0013] After the current sending delay, sending a column address strobe control signal to determine the column address;

[0014] The storage location is determined according to the row address and the column address.

[0015] According to some embodiments of the present application, the step of performing a read-write verification process on the memory chip to be tested based on the storage position and the test pattern to obtain a verification result includes:

[0016] Writing the preset test pattern into the storage location;

[0017] After storing the test pattern in the storage location, performing a read operation on the storage location to obtain a read-back pattern;

[0018] When the test code pattern is consistent with the readback code pattern, the verification result is judged as: verification passed;

[0019] When the test code pattern is inconsistent with the readback code pattern, the verification result is determined to be: verification error.

[0020] According to some embodiments of the present application, the current delay test range includes a first end value and a second end value greater than the first end value;

[0021] The performing a first update process on the current delay test range to obtain an updated delay test range includes:

[0022] When the verification result is: verification passed, the current delay test range is determined;

[0023] Determine the current sending delay as an updated second end value;

[0024] The second end value of the current delay test range is updated according to the updated second end value to obtain the updated delay test range; the updated delay test range is determined according to the first end value of the current delay test range and the updated second end value.

[0025] According to some embodiments of the present application, the current delay test range includes a first end value and a second end value greater than the first end value;

[0026] The performing a first update process on the current delay test range to obtain an updated delay test range includes:

[0027] When the verification result is: verification error, determining the current delay test range;

[0028] Determine the current sending delay as an updated first end value;

[0029] The first end value of the current delay test range is updated according to the updated first end value to obtain the updated delay test range; the updated delay test range is determined according to the updated first end value and the second end value of the current delay test range.

[0030] According to some embodiments of the present application, the verification result is: verification passed or verification error;

[0031] The performing a second update process on the initial step value to determine the update step value comprises:

[0032] When the verification result is: verification passed, the first control coefficient is determined to be 0, the second control coefficient is determined to be 1, and the verification result is the verification pass number of the read-write verification process; the update step value is calculated according to the preset step value update formula, the first control coefficient, the second control coefficient, and the verification result is the verification pass number of the read-write verification process;

[0033] When the verification result is: verification error, it is determined that the first control coefficient is 1 and the second control coefficient is 0, and the update step value is calculated according to the preset step value update formula, the first control coefficient, and the second control coefficient.

[0034] According to some embodiments of the present application, the preset step value update formula is:

[0035] ;

[0036] in, is the update step value, is the initial step value, is the first control coefficient, is the second control coefficient; n is the number of times the read-write verification process passes the verification result.

[0037] In a second aspect, an embodiment of the present application provides a controller comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the timing parameter determination method of the memory chip as described in any one of the embodiments of the first aspect.

[0038] In a third aspect, an embodiment of the present application provides an electronic device, comprising a controller as described in the embodiment of the second aspect.

[0039] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute a method for determining timing parameters of a storage chip as described in any one of the embodiments of the first aspect.

[0040] The embodiment of the present application includes: in the process of determining the timing parameters of the memory chip by using the controller test, first, the initial transmission delay determined by the pre-configured initial delay test range is added to the preset initial step value to obtain the current transmission delay; secondly, based on the current transmission delay, a row and column position determination process is performed to determine the storage position; then, based on the storage position and the test pattern, a read and write verification process is performed on the memory chip to be tested to obtain a verification result; the verification result is used to provide a reference for the subsequent first update process and the second update process; then, according to the verification result, a first update process is performed on the current delay test range to obtain an updated delay test range, and the initial step value is determined. The update delay test range includes a third end value and a fourth end value greater than the third end value; when the current step value is greater than or equal to the preset step threshold, the third end value and the update step value are added to obtain the update sending delay; when the update sending delay is less than the fourth end value, the row and column position determination processing, the read and write verification processing, the first update processing, and the second update processing are sequentially performed based on the update sending delay; finally, until the update step value is less than the preset step threshold, the update sending delay with the most recent verification result as the verification pass is determined as the target sending delay, and the target sending delay is output as the minimum reference value of the timing parameters of the storage chip. Compared with the determination of the target sending delay by verifying the delay to be tested one by one in the initial delay test range based on a fixed step value, the present application continuously updates the initial step value through a step value update mechanism to obtain an update step value, thereby enabling efficient testing, and at the same time, more accurately determining the timing parameters of the storage chip, providing a reliable reference in the process of selecting storage chips suitable for the platform. That is to say, the embodiments of the present application can improve the test efficiency and accuracy of the minimum reference value of the timing parameter of the test memory chip, and provide a reliable reference in the process of screening the memory chip adapted for the platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a structural schematic diagram of a test system for determining timing parameters of a memory chip provided by an embodiment of the present application;

[0042] Figure 2 It is a flowchart of a method for determining timing parameters of a memory chip provided by an embodiment of the present application;

[0043] Figure 3 It is a schematic flow chart of the steps of the first update process when the verification result is verification passed provided by an embodiment of the present application;

[0044] Figure 4 It is a flowchart of the steps of the first update process when the verification result is a verification error provided by an embodiment of the present application;

[0045] Figure 5is a schematic flow chart of the steps of the second update process provided by an embodiment of the present application;

[0046] Figure 6 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0048] It should be understood that in the description of the present application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0049] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0051] The present application provides a method for determining the timing parameters of a memory chip, a controller, an electronic device, and a computer-readable storage medium, and relates to the field of memory chip testing technology. The method includes determining the storage position by performing a row and column position determination process based on the current transmission delay determined by the initial transmission delay and the initial step value; updating the update delay test range and the update step value according to the verification result obtained by the read-write verification based on the storage position and the test pattern; the update delay test range includes a third end value and a fourth end value greater than the third end value; when the current step value is greater than or equal to the preset step threshold, performing a row and column position determination process, a read-write verification process, and an update process based on the update transmission delay determined by the third end value and the update step value and less than the fourth end value; until the update step value is less than the preset step threshold, the minimum reference value of the timing parameters of the memory chip is determined. It can improve the test efficiency and accuracy of the minimum reference value of the timing parameters of the memory chip.

[0052] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0053] like Figure 1 As shown, the test system includes: a controller, a memory chip to be tested, the memory chip includes: an address latch, a memory unit; the controller is electrically connected to the address latch and the memory unit respectively; the memory unit is a memory array.

[0054] Specifically, the memory chip is a DDR (Double Data Rate) chip, which is a synchronous dynamic random access memory.

[0055] Specifically, the address latch is used to receive a row address selection control signal and select a row address indicated in the row address selection control signal so as to access a specific row in the storage unit; it is also used to receive a column address selection control signal and select a column address indicated in the column address selection control signal so as to access a specific column in the storage unit and determine the storage location to be accessed in the storage unit.

[0056] Specifically, the storage unit is used to store data.

[0057] Specifically, the controller is used to execute the method for determining the timing parameters of the memory chip provided in the embodiment of the present application, so as to improve the test efficiency and accuracy of the minimum reference value of the timing parameters of the memory chip, and provide a reliable reference in the process of screening the memory chip adapted for the platform. It should be noted that the controller capable of executing the method for determining the timing parameters of the memory chip provided in the embodiment of the present application can be a controller inside the memory chip, or a controller inside or outside the memory chip (for example, a controller in a host computer or a test machine). The present application does not specifically limit the type of controller.

[0058] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0059] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0060] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0061] Based on the above system structure, various embodiments of the method for determining timing parameters of the memory chip of the present application are proposed below.

[0062] First, as Figure 2 As shown, the timing parameter determination method of the memory chip can be applied to Figure 1 In the controller shown, the method for determining the timing parameters of the memory chip may include but is not limited to steps S110 to S160.

[0063] Step S110: Add the initial transmission delay determined by the preconfigured initial delay test range to the preset initial step value to obtain the current transmission delay.

[0064] Step S120: performing row and column position determination processing based on the current transmission delay to determine the storage position.

[0065] Step S130: Based on the storage position and the test code pattern, a read-write verification process is performed on the memory chip to be tested to obtain a verification result.

[0066] Step S140: According to the verification result, a first update process is performed on the current delay test range to obtain an updated delay test range, and a second update process is performed on the initial step value to determine an updated step value; the updated delay test range includes a third end value and a fourth end value greater than the third end value.

[0067] Step S150: When the current step value is greater than or equal to the preset step threshold, the third end value and the update step value are added to obtain the update sending delay; when the update sending delay is less than the fourth end value, and based on the update sending delay, the row and column position determination processing, the read and write verification processing, the first update processing, and the second update processing are performed in sequence.

[0068] Step S160: until the update step value is less than the preset step threshold, the update transmission delay that makes the verification result pass the most recent time is determined as the target transmission delay, and the target transmission delay is output as the minimum reference value of the timing parameter of the memory chip.

[0069] Specifically, the initial delay test range is 0 to a preset maximum test value; the initial transmission delay is 0. The initial step value is greater than the preset step threshold. The preset maximum test value can be preconfigured, and the current transmission delay of the test does not exceed the preset maximum test value; this application does not impose specific restrictions on the value of the preset maximum test value.

[0070] Specifically, the preset step threshold is the minimum step value allowed by the protocol.

[0071] Specifically, the test pattern is preset by the tester through the configuration interface. The test pattern can be: 0XA5A5A5A5A5, or 0XFFFFFFFF, etc. Therefore, the present application does not make any specific restrictions on the type of the test pattern.

[0072] In one embodiment, the method for determining the timing parameters of a memory chip further includes: after obtaining the update transmission delay, when the update transmission delay is greater than or equal to the fourth end value of the update delay test range, the update transmission delay that most recently made the verification result pass is determined as the target transmission delay, and the target transmission delay is output as the minimum reference value of the timing parameters of the memory chip.

[0073] It is understandable that the timing parameters of the memory chip obtained by the test of the embodiment of the present application are used to indicate the transmission delay between the sending of the row address selection control signal and the sending of the column address selection control signal. Different platforms have different requirements for this timing parameter t of the memory chip. For example, a certain platform requires that the reference value of the timing parameter of the memory chip is at least 10ns, then the memory chip with a timing parameter greater than or equal to the reference value of 10ns can be applied to the platform; and the memory chip with a timing parameter less than the reference value of 10ns cannot be applied to the platform. It can be seen that after step S160, the timing parameters of the memory chip obtained by the test can provide a reliable reference for the assembler in the process of screening the memory chip adapted for the platform.

[0074] Through steps S110 to S160, in the process of using the controller to test and determine the timing parameters of the storage chip, first, the initial transmission delay determined by the pre-configured initial delay test range is added to the preset initial step value to obtain the current transmission delay; secondly, the row and column position determination processing is performed based on the current transmission delay to determine the storage position; then, based on the storage position and the test pattern, the memory chip to be tested is subjected to a read and write verification processing to obtain a verification result; the verification result is used to provide a reference for the subsequent first update processing and second update processing; then, according to the verification result, the current delay test range is subjected to a first update processing to obtain an updated delay test range, and the memory chip to be tested is subjected to a read and write verification processing to obtain a verification result; The initial step value is subjected to a second update process to determine the update step value; the update delay test range includes a third end value and a fourth end value greater than the third end value; when the current step value is greater than or equal to the preset step threshold, the third end value and the update step value are added to obtain the update transmission delay; when the update transmission delay is less than the fourth end value, the row and column position determination process, the read and write verification process, the first update process, and the second update process are sequentially performed based on the update transmission delay; finally, until the update step value is less than the preset step threshold, the update transmission delay with the most recent verification result of passing the verification is determined as the target transmission delay, and the target transmission delay is output as the minimum reference value of the timing parameters of the storage chip. Compared with the determination of the target transmission delay by verifying the delay to be tested one by one in the initial delay test range based on a fixed step value, the present application continuously updates the initial step value through a step value update mechanism to obtain an update step value, thereby enabling efficient testing, and at the same time, more accurately determining the timing parameters of the storage chip, providing a reliable reference in the process of selecting storage chips suitable for the platform. Therefore, the embodiments of the present application can improve the test efficiency and accuracy of the minimum reference value of the timing parameter of the test memory chip, and provide a reliable reference in the process of screening the memory chip adapted for the platform.

[0075] According to some embodiments of the present application, step S120 is further described. Step S120: performing row and column position determination processing to determine a storage position based on the current transmission delay includes but is not limited to steps S121 to S123.

[0076] Step S121: Send a row address strobe control signal to determine the row address.

[0077] Step S122: after the current sending delay, send a column address strobe control signal to determine the column address.

[0078] Step S123: Determine the storage location according to the row address and the column address.

[0079] It is understandable that the row address strobe control signal indicates the row address of the storage location to be accessed, and the column address strobe control signal indicates the column address of the storage location to be accessed. The tester can set the storage location according to the requirements, so this application does not make specific restrictions on the row address and column address.

[0080] It is understandable that if the current transmission delay value is too small, the row address strobe control signal is not yet stable, the memory chip to be tested has not had enough time to precharge and open the required row, it is difficult to correctly receive the column address strobe control signal, and it is impossible to determine the correct storage location, resulting in errors in the subsequent read-write verification processing based on the storage location. Therefore, the embodiment of the present application sends the row address strobe control signal and the column address strobe control signal in succession based on the current transmission delay through steps S121 to S123 to determine the storage location, laying the foundation for the subsequent read-write verification processing.

[0081] According to some embodiments of the present application, step S130 is further described. Step S130: based on the storage position and the test code pattern, a read-write verification process is performed on the memory chip to be tested to obtain a verification result, including but not limited to steps S131 to S134.

[0082] Step S131: writing a preset test pattern into a storage location.

[0083] Step S132: After storing the test pattern in the storage location, a read operation is performed on the storage location to obtain a read-back pattern.

[0084] Step S133: When the test code pattern is consistent with the readback code pattern, the verification result is judged as: verification passed.

[0085] Step S134: When the test code pattern is inconsistent with the readback code pattern, the verification result is judged to be: verification error.

[0086] Specifically, after the storage location is determined, a preset test pattern is written into the storage location through a write operation, and then a read operation is performed on the storage location to obtain a readback pattern, and a verification result is determined based on the test pattern and the readback pattern.

[0087] Specifically, when judging whether the test code pattern is consistent with the readback code pattern, the following methods can be used: First, the test code pattern and the readback code pattern can be directly compared to judge whether they are consistent. Second, perform an XOR operation on the test code pattern and the readback code pattern bit by bit, and judge whether the test code pattern and the readback code pattern are consistent based on the XOR operation result. If the XOR operation result is all 0, then the test code pattern is judged to be consistent with the readback code pattern; otherwise, the test code pattern is judged to be inconsistent with the readback code pattern. Third, calculate the first check value of the test code pattern and the second check value of the readback code pattern respectively through the CRC check algorithm. When the first check value is equal to the second check value, it is judged that the test code pattern is consistent with the readback code pattern; when the first check value is not equal to the second check value, it is judged that the test code pattern is inconsistent with the readback code pattern. Therefore, the present application does not make specific restrictions on the method used to judge whether the test code pattern and the readback code pattern are consistent.

[0088] It is understandable that the timing parameters of the memory chip have a certain range of values. Generally, the platform will require the reference value of the timing parameters of the memory chip to be minimum. In order to subsequently screen out the memory chip adapted to the platform based on the timing parameters, the embodiment of the present application tests and determines the minimum reference value of the timing parameters. Specifically, step S133 and step S134 are further explained. When the verification result is: verification passed, it is determined that the current transmission delay used in step S122 is an available value of the timing parameter of the memory chip to be tested; when the verification result is: verification error, it is determined that the current transmission delay used in step S122 is an unavailable value of the timing parameter of the memory chip to be tested.

[0089] Through steps S131 to S134, a verification result can be obtained to determine whether the current sending delay is desirable, thereby laying a reference foundation for the subsequent first update processing and the second update processing.

[0090] Furthermore, the first update process and the second update process in step S140 are further described. The current delay test range includes a first end value and a second end value greater than the first end value.

[0091] According to some embodiments of the present application, Figure 3 As shown, a first update process is performed on the current delay test range to obtain an updated delay test range, including but not limited to steps S210 to S230.

[0092] Step S210: When the verification result is: verification passed, determine the current delay test range.

[0093] Step S220: determine the current sending delay as the updated second end value.

[0094] Step S230: updating the second end value of the current delay test range according to the updated second end value to obtain an updated delay test range.

[0095] It can be understood that after completing the read and write verification processing, when the verification result is: verification passed, it is determined that the current sending delay used in step S122 is an available value of the timing parameter of the memory chip to be tested; the current sending delay is determined as the updated second end value, and the updated delay test range is determined according to the first end value of the current delay test range and the updated second end value; the values ​​at the left and right ends of the updated delay test range are recorded as: the third end value (equivalent to the first end value of the current delay test range) and the fourth end value (equivalent to the updated second end value).

[0096] Through step S210 to step S230, when the verification result is: verification passed, the update delay test range is determined, laying a foundation for determining the update sending delay.

[0097] According to some embodiments of the present application, Figure 4 As shown, a first update process is performed on the current delay test range to obtain an updated delay test range, including but not limited to steps S310 to S330.

[0098] Step S310: When the verification result is: verification error, determine the current delay test range.

[0099] Step S320: determine the current sending delay as the updated first end value.

[0100] Step S330: updating the first end value of the current delay test range according to the updated first end value to obtain an updated delay test range.

[0101] It can be understood that after completing the read and write verification processing, when the verification result is: verification error, it is determined that the current sending delay used in step S122 is an unusable value of the timing parameter of the memory chip to be tested; the previous sending delay is determined as the updated first end value, and the updated delay test range is determined according to the updated first end value and the second end value of the current delay test range; the values ​​at the left and right ends of the updated delay test range are recorded as: the third end value (equivalent to the updated first end value) and the fourth end value (equivalent to the second end value of the current delay test range).

[0102] Through step S310 to step S330, when the verification result is: verification error, the update delay test range is determined, laying a foundation for determining the update sending delay.

[0103] According to some embodiments of the present application, the verification result is: verification passed or verification error; Figure 5 As shown, the initial step value is subjected to a second update process to determine the updated step value, including but not limited to steps S410 to S420.

[0104] Step S410: When the verification result is: verification passed, determine that the first control coefficient is 0, the second control coefficient is 1, and count the number of verification passes for the read-write verification processing with the verification result being verification passed; calculate the update step value based on the preset step value update formula, the first control coefficient, the second control coefficient, and the number of verification passes for the read-write verification processing with the verification result being verification passed.

[0105] Step S420: When the verification result is: verification error, determine that the first control coefficient is 1 and the second control coefficient is 0, and calculate the updated step value according to the preset step value update formula, the first control coefficient, and the second control coefficient.

[0106] According to some embodiments of the present application, the preset step value update formula is:

[0107] ;

[0108] in, To update the step value, is the initial step value, is the first control coefficient, is the second control coefficient; n is the number of times the read-write verification process passes the verification result.

[0109] It is understandable that based on the fixed step value, the target transmission delay is determined by checking the delay to be tested one by one in the initial delay test range. If the fixed step value is too small, although the minimum reference value of the timing parameter of the memory chip obtained by the test will be more accurate, multiple tests are required to determine the minimum reference value, and the overall test efficiency is low; if the fixed step value is too large, although a reference value of an available timing parameter can be obtained by testing relatively quickly, due to the large step value, a smaller reference value of the timing parameter may be omitted and not tested, resulting in a large deviation between the obtained reference value and the actual minimum reference value, which is inaccurate. The present application implements a dynamic step value update mechanism through steps S410 to S420, and continuously updates the initial step value through the verification results of each read-write verification process to obtain an updated step value, so that it can take into account efficient testing and more accurately determine the minimum reference value of the timing parameter of the memory chip.

[0110] An example is given to illustrate the overall process of the method for determining the timing parameters of the memory chip provided in the embodiment of the present application.

[0111] Step S501, the pre-configured initial delay test range is 0 to 50ns, the initial transmission delay T0 is 0, and the preset initial step value is The preset step threshold is 0.5ns.

[0112] Step S502, add the initial transmission delay and the initial step value of 5ns to obtain the current transmission delay T1 of 5ns.

[0113] Step S503, based on the current transmission delay T1 of 5ns, after performing row and column position determination processing to determine the storage position, a read and write verification process is performed to obtain a verification result.

[0114] Step S504: When the verification result is wrong, perform the first update process: determine the current delay test range as the initial delay test range (0 to 50ns), determine the current transmission delay T1 = 5ns as the updated first end value, and determine the updated delay test range (5ns to 50ns) based on the updated first end value (5ns) and the second end value (50ns) of the current delay test range. Perform the second update process: determine the first control coefficient is 1, the second control coefficient is 0, and is substituted into the preset step value update formula:

[0115] ;

[0116] Get the update step value Equal to the initial step value , the value is 5ns; update the step value (5ns) is greater than the preset step threshold (0.5ns); thus, the third end value of the update delay test range, 5ns, is updated with the update step value (5ns) added together, the current transmission delay T1 is 10ns.

[0117] Step S505: Based on the current transmission delay T1 of 10ns, after performing row and column position determination processing to determine the storage position, perform read and write verification processing to obtain the verification result. If the verification result is a verification error, perform the same first update processing as step S504 to obtain the update delay test range (10ns to 50ns), and perform the same second update processing as step S504 to determine the update step value. (5ns), thus updating the third end value of the delay test range 10ns and the update step value (5ns) added together, the current transmission delay T1 is 15ns.

[0118] Step S506: Based on the current transmission delay T1 of 15ns, after performing row and column position determination processing to determine the storage position, perform read and write verification processing to obtain the verification result. If the verification result is a verification error, perform the same first update processing as step S504 to obtain the update delay test range (15ns to 50ns), and perform the same second update processing as step S504 to determine the update step value. (5ns), thus updating the third end value of the delay test range 15ns and the update step value (5ns) added together, the current transmission delay T1 is 20ns.

[0119] Step S507: Based on the current transmission delay T1 of 20ns, after performing row and column position determination processing to determine the storage position, perform read and write verification processing to obtain the verification result. If the verification result is a verification error, perform the same first update processing as step S504 to obtain the update delay test range (20ns to 50ns), and perform the same second update processing as step S504 to determine the update step value. (5ns), thus updating the third end value of the delay test range 20ns and the update step value (5ns) added together, the current transmission delay T1 is 25ns.

[0120] Step S508, based on the current transmission delay T1 of 25ns, after determining the storage position, perform read and write verification processing to obtain the verification result. When the verification result is that the verification passes, perform the first update processing: based on step S507, determine that the current delay test range is 20ns to 50ns, and determine the current transmission delay T1=25ns as the updated second end value, and determine the updated delay test range (20ns to 25ns) based on the updated second end value (25ns) and the first end value (20ns) of the current delay test range. Perform the second update processing: Determine the first control coefficient is 0, the second control coefficient is 1, and the statistical verification result is the verification pass number n=1 for the read-write verification process; substitute it into the preset step value update formula:

[0121] ;

[0122] The updated step value is t1=(t0)*1 / 2, t0 is 5ns, then the updated step value is (2.5ns), and update the step value (2.5ns) is greater than the preset step threshold (0.5ns); thus, the third end value 20ns of the updated delay test range (20ns to 25ns) is updated with the updated step value (2.5ns) added together, the current transmission delay T1 is 22.5ns.

[0123] Step S509: Based on the current transmission delay T1 of 22.5ns, after determining the storage position, perform read and write verification to obtain the verification result. If the verification result is verification passed, refer to step S508 to perform the first update process to obtain the update delay test range (20ns to 22.5ns), perform the same second update process as step S508, determine the verification pass number to be 2, and determine the update step value. 1.25ns, thus updating the third end value of the delay test range of 20ns and the update step value (1.25ns) added together, the current transmission delay T1 is 21.25ns.

[0124] Step S510: Based on the current transmission delay T1 of 21.25ns, after determining the storage position, perform read and write verification to obtain the verification result. If the verification result is passed, refer to step S508 to perform the first update process to obtain the update delay test range (20ns to 21.25ns), perform the same second update process as step S508, determine the number of verification passes to be 3, and determine the update step value. 0.625ns, thus updating the third end value of the delay test range of 20ns and the update step value (0.625ns) added together, the current sending delay T1 is 20.625ns.

[0125] Step S511, based on the current transmission delay T1 of 20.625ns, after determining the storage position, perform read and write verification processing to obtain the verification result. If the verification result is verification passed, refer to step S508 to perform the first update processing to obtain the update delay test range (20ns to 20.625ns), perform the same second update processing as step S508, determine the verification pass number is 4, and determine the update step value It is 0.3125ns. At this time, 0.3125ns is less than the preset step threshold (0.5ns), so the updated sending delay of 20.625ns that made the verification result pass the most recent time is determined as the target sending delay, and the output target sending delay is the minimum reference value of the timing parameter of the memory chip to be tested.

[0126] In addition, if the verification result of the read-write verification process based on the current transmission delay T1 of 21.25ns in step S510 is a verification error, the same first update process as step S504 should be performed to obtain the updated delay test range (21.25ns to 22.5ns), and the same second update process as step S504 should be performed to determine the updated step value. (5ns), thus updating the third end value of the delay test range of 21.25ns and the update step value (5ns) is added to obtain the current transmission delay T1 of 26.25ns. At this time, it has exceeded the fourth end value 22.5ns of the update delay test range (21.25ns to 22.5ns), so the update transmission delay (22.5ns) with the most recent verification result of the previous step S509 that passed the verification is determined as the target transmission delay, and the output target transmission delay is the minimum reference value of the timing parameter of the memory chip.

[0127] It is understandable that when the minimum reference value of the timing parameter of a memory chip to be tested is about 20.625ns, the minimum reference value of the timing parameter can be determined by a total of eight read-write verification processes from step S501 to step S511 of the embodiment of the present application. If the transmission delay is determined stepwise from 0 using a fixed step value of 0.5ns, and the row and column position determination process is performed based on the transmission delay to determine the storage position, and then a read-write verification process is performed to obtain the verification result; 41 read-write verification processes are required. It can be seen that the embodiment of the present application can improve the test efficiency and accuracy of the minimum reference value of the timing parameter of the test memory chip.

[0128] like Figure 6 As shown, the present invention also provides a controller, comprising:

[0129] The processor 601 may be implemented by a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0130] The memory 602 may be implemented in the form of a read-only memory, a static storage device, a dynamic storage device, or a random access memory. The memory 602 may store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 602, and the processor 601 calls and executes the timing parameter determination method of the memory chip in the embodiment of this application;

[0131] Input / output interface 603, used to implement information input and output;

[0132] Communication interface 604, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0133] A bus 605 that transmits information between various components of the device (e.g., processor 601, memory 602, input / output interface 603, and communication interface 604);

[0134] The processor 601 , the memory 602 , the input / output interface 603 and the communication interface 604 are connected to each other in communication within the device via a bus 605 .

[0135] An embodiment of the present application also provides an electronic device, comprising the controller as described above.

[0136] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the timing parameter determination method of the above-mentioned storage chip is implemented.

[0137] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0138] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0139] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A method for determining timing parameters of a memory chip, characterized in that: include: Adding the initial transmission delay determined by the preconfigured initial delay test range to the preset initial step value to obtain the current transmission delay; Performing row and column position determination processing based on the current sending delay to determine a storage position; Based on the storage location and the test pattern, a read-write verification process is performed on the storage chip to be tested to obtain a verification result; According to the verification result, a first update process is performed on the current delay test range to obtain an updated delay test range, and a second update process is performed on the initial step value to determine an updated step value; the updated delay test range includes a third end value and a fourth end value greater than the third end value; When the current step value is greater than or equal to the preset step value, the third end value and the update step value are added to obtain the update transmission delay; when the update transmission delay is less than the fourth end value, the row and column position determination process, the read and write verification process, the first update process, and the second update process are sequentially performed based on the update transmission delay; Until the update step value is less than the preset step threshold, the update sending delay that most recently made the verification result pass is determined as the target sending delay, and the target sending delay is output as the minimum reference value of the timing parameter of the memory chip.

2. The method for determining timing parameters of a memory chip according to claim 1, characterized in that: The performing row and column position determination processing based on the current transmission delay to determine the storage position includes: Sending a row address strobe control signal to determine the row address; After the current sending delay, sending a column address strobe control signal to determine the column address; The storage location is determined according to the row address and the column address.

3. The method for determining timing parameters of a memory chip according to claim 1, characterized in that: The step of performing a read / write verification process on the memory chip to be tested based on the storage position and the test pattern to obtain a verification result includes: Writing the preset test pattern into the storage location; After storing the test pattern in the storage location, performing a read operation on the storage location to obtain a read-back pattern; When the test code pattern is consistent with the readback code pattern, the verification result is judged as: verification passed; When the test code pattern is inconsistent with the readback code pattern, the verification result is determined to be: verification error.

4. The method for determining timing parameters of a memory chip according to claim 3, characterized in that: The current delay test range includes a first end value and a second end value greater than the first end value; The performing a first update process on the current delay test range to obtain an updated delay test range includes: When the verification result is: verification passed, the current delay test range is determined; Determine the current sending delay as an updated second end value; The second end value of the current delay test range is updated according to the updated second end value to obtain the updated delay test range; the updated delay test range is determined according to the first end value of the current delay test range and the updated second end value.

5. The method for determining timing parameters of a memory chip according to claim 3, characterized in that: The current delay test range includes a first end value and a second end value greater than the first end value; The performing a first update process on the current delay test range to obtain an updated delay test range includes: When the verification result is: verification error, determining the current delay test range; Determine the current sending delay as an updated first end value; The first end value of the current delay test range is updated according to the updated first end value to obtain the updated delay test range; the updated delay test range is determined according to the updated first end value and the second end value of the current delay test range.

6. The method for determining timing parameters of a memory chip according to claim 1 or 3, characterized in that: The verification result is: verification passed or verification error; The performing a second update process on the initial step value to determine the update step value comprises: When the verification result is: verification passed, the first control coefficient is determined to be 0, the second control coefficient is determined to be 1, and the verification result is the verification pass number of the read-write verification process; the update step value is calculated according to the preset step value update formula, the first control coefficient, the second control coefficient, and the verification result is the verification pass number of the read-write verification process; When the verification result is: verification error, it is determined that the first control coefficient is 1 and the second control coefficient is 0, and the update step value is calculated according to the preset step value update formula, the first control coefficient, and the second control coefficient.

7. The method for determining timing parameters of a memory chip according to claim 6, characterized in that: The preset step value update formula is: ； in, is the update step value, is the initial step value, is the first control coefficient, is the second control coefficient; n is the number of times the read-write verification process passes the verification result.

8. A controller, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the timing parameter determination method of the memory chip as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising a controller as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for determining timing parameters of a memory chip as described in any one of claims 1 to 7.

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