Memory device including repair circuit, method of operating same, and memory system

Abstract

A memory device including a repair circuit, an operating method of the memory device, and a memory system are provided. The operating method includes: outputting a signal representing a pre-decoded faulty row address based on pre-decoding the faulty row address; outputting a signal representing the pre-decoded row address based on pre-decoding the row address; outputting a hit signal based on comparing the bit value of the pre-decoded faulty row address with the bit value of the pre-decoded row address; outputting a repair enable signal based on the hit signal; and performing a row repair operation based on the repair enable signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0111516 filed on August 24, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a memory device, and more particularly, to a memory device including a repair circuit using pre-decoding and an operating method of the memory device. Background Art

[0004] Semiconductor chips are manufactured by semiconductor manufacturing processes and then tested by test equipment in wafer, bare die or packaged states. Through testing, failed components or chips are selected. When some memory devices have faults, repair operations are performed to remedy the semiconductor wafer. As the microprocessing of semiconductor chips (such as dynamic random access memory (DRAM) chips) continues, the possibility of errors occurring in the manufacturing process increases. Even if no errors are detected in the initial test phase, errors may occur during chip operation.

[0005] The demand for high-capacity DRAM is increasing to reliably and quickly process large amounts of data in real time. The performance of DRAM may vary over time. Memory systems may expect reliability, availability, and serviceability (RAS) characteristics for DRAM. Therefore, some DRAMs detect failed memory cells in a memory cell array (MCA) during a test operation on the MCA, perform a repair operation to replace the failed memory cell with a redundant memory cell, and may include a repair circuit that performs the repair operation.

[0006] The repair circuit can store a failure address of a failed memory cell detected during a test operation and generate a repair control signal for instructing to perform a repair operation on the failed address. According to the repair control signal, the DRAM can perform a repair operation to replace a failed word line selected by the failed address with a redundant word line, or to replace a failed bit line selected by the failed address with a redundant bit line. Summary of the invention

[0007] The inventive concept provides a memory device including a repair circuit, which has low power consumption by using pre-decoding, and an operating method of the memory device.

[0008] According to various aspects of the inventive concept, there is provided an operating method of a memory device. The operating method includes: outputting a signal indicating a pre-decoded faulty row address based on pre-decoding a faulty row address; outputting a signal indicating a pre-decoded row address based on pre-decoding a row address; outputting a hit signal based on comparing a bit value of the pre-decoded faulty row address with a bit value of the pre-decoded row address; outputting a repair enable signal based on the hit signal; and performing a row repair operation based on the repair enable signal.

[0009] According to aspects of the present invention, a memory device is provided, comprising: a memory cell array comprising redundant memory cells; and a repair circuit configured to perform a row repair operation by replacing a faulty row address with a redundant row address based on a repair enable signal, wherein the repair circuit comprises: a first register configured to store the faulty row address, a second register configured to store the row address, and a repair control circuit, and wherein the repair control circuit comprises: a predecoder circuit configured to predecode the faulty row address and output a signal representing the predecoded faulty row address, and to predecode the row address and output a signal representing the predecoded row address; a comparison circuit configured to compare a bit value of the predecoded faulty row address with a bit value of the predecoded row address, and output a hit signal based on a result of the comparison; and a combinational logic circuit configured to output a repair enable signal based on the hit signal.

[0010] According to various aspects of the present invention, there is provided a memory system including a host device configured to send a command for a repair operation and a memory device configured to perform the repair operation in response to the command, wherein the memory device includes a repair control circuit configured to: pre-decode a fault row address and output a signal indicating the pre-decoded fault row address, pre-decode a row address and output a signal indicating the pre-decoded row address, compare a bit value of the pre-decoded fault row address with a bit value of the pre-decoded row address and output a hit signal based on a result of the comparison, and output a repair enable signal based on the hit signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0012] In the figure:

[0013] Figure 1 is a block diagram of a test system for testing a memory device according to some embodiments;

[0014] Figure 2A and Figure 2B It is shown by Figure 1 A diagram of a repair operation performed by a repair circuit in FIG.

[0015] Figure 3 is a block diagram illustrating a memory device including a repair circuit according to some embodiments;

[0016] Figure 4 It is shown Figure 3 A diagram of a repair address storage circuit in FIG.

[0017] Figure 5 is a circuit diagram of a unit circuit that generates a repair enable signal related to a failed row address among a plurality of unit circuits forming a repair control circuit of a first repair circuit according to some embodiments;

[0018] Figure 6 is a diagram of a pre-decoder circuit among a plurality of unit circuits forming a repair control circuit of a first repair circuit according to some embodiments;

[0019] Fig. 7A is a diagram illustrating an equivalent circuit of a first row predecoder circuit included in a predecoder circuit according to some embodiments;

[0020] Figure 7B is a diagram illustrating the operation of a first row pre-decoder circuit according to some embodiments;

[0021] Figure 7C is a diagram showing an equivalent circuit of a first fuse pre-decoder circuit included in a pre-decoder circuit according to some embodiments;

[0022] Fig.7D is a diagram illustrating the operation of a first fuse pre-decoder circuit according to some embodiments;

[0023] Fig. 8A is a diagram showing an equivalent circuit of a first sub-comparison circuit included in a comparison circuit according to some embodiments;

[0024] Figure 8B is a diagram illustrating the operation of a first sub-comparison circuit according to some embodiments;

[0025] Fig. 9 is a flowchart of a method of operating a memory device according to some embodiments; and

[0026] Fig.10 is a block diagram illustrating a system of an electronic device including a memory device according to some embodiments. DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments are described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram of a test system for testing memory devices according to some embodiments.

[0029] Reference Figure 1 A test method in which a test apparatus 110 tests a memory device 120 in a test system 100 (also referred to as a memory system) is described. The test apparatus 110 may include a test host 112 that tests the memory device 120 corresponding to a device under test (DUT). The test host 112 may include a central processing unit (CPU) 114 that controls hardware, software, and / or firmware to perform a test operation on the memory device 120. The test host 112 may transmit a test signal from the CPU 114 to the memory device 120, or transmit a test result value for a test signal output from the memory device 120 to the CPU 114. Here, the test host 112 may be referred to as a host device.

[0030] The test host 112 may be implemented by a test program. The test program may include a test algorithm or mode for performing a test operation. For example, the test host 112 may store specific data in a storage area of ​​the DUT (i.e., the memory cell array 122), then read the specific data, and then determine the pass or fail of the test operation based on whether the read data is the same as the specific data. The test host 112 may measure changes in voltage, current, and / or frequency of the memory device 120 under various driving conditions, and may test whether the change is within a tolerance range.

[0031] The memory device 120 may include a dynamic random access memory (DRAM), but is not limited thereto. For example, the memory device 120 may correspond to a double data rate synchronous DRAM (DDR SDRAM), a low power DDR (LPDDR) SDRAM, a graphic DDR (GDDR) SDRAM, or a Rambus DRAM (RDRAM). For example, the memory device 120 may include a static RAM (SRAM), a high bandwidth memory (HBM), or a processor in memory (PIM).

[0032] According to some embodiments, the memory device 120 may include a nonvolatile memory device. For example, the memory device 120 may include a flash memory or a resistive memory such as a phase change RAM (PRAM), a magnetic RAM (MRAM), or a resistive RAM (RRAM).

[0033] The test host 112 may test the memory device 120 through the channel 130. The channel 130 may include a bus and / or a signal line that physically and / or electrically connects the test host 112 to the memory device 120. For example, the memory device 120 may receive a clock signal CK through a clock bus, the memory device 120 may receive a command and an address CA through a command / address bus, and data DQ may be exchanged between the test host 112 and the memory device 120 through a data bus. Test signals may be exchanged between the test host 112 and the memory device 120 through a test signal line. For simplicity of the drawings, it is shown that a signal is transmitted through a single signal line between the test host 112 and the memory device 120. However, each bus may actually include one or more signal lines to transmit signals through it.

[0034] The test host 112 may provide commands to the memory device 120 to test memory operations. Non-limiting examples of commands for memory may include timing commands for controlling the timing of various operations, access commands for accessing memory such as a read command for performing a read operation and a write command for performing a write operation, mode register write and read commands for performing write and read operations on a mode register, and repair commands.

[0035] When the test host 112 provides a write command and an associated address to the memory device 120 during testing, the memory device 120 may receive the write command and the associated address, and perform a write operation by writing write data from the test host 112 to a memory location corresponding to the associated address. The write data may be provided from the test host 112 to the memory device 120 according to a timing associated with the receipt of the write command. For example, when the write data is provided from the test host 112 to the memory device 120, the timing may be based on a write latency (WL) value indicating the number of clock cycles after the write command. The test host 112 may program the WL value to a mode register set (MRS) of the memory device 120. As is known, the MRS of the memory device 120 may be programmed with information for setting various operating modes and / or for selecting characteristics of memory operations. Information for the test operation of the memory device 120 may be stored in a test MRS (TMRS).

[0036] When a read command and an associated address are provided from the test host 112 to the memory device 120 during testing, the memory device 120 may receive the read command and the associated address, and perform a read operation by outputting read data from a memory location corresponding to the associated address. The read data may be provided from the memory device 120 to the test host 112 according to a timing associated with the receipt of the read command. For example, when the read data is provided from the memory device 120 to the test host 112, the timing may be based on a read delay (RL) value indicating the number of clock cycles after the read command. The test host 112 may set the RL value in the memory device 120. For example, the RL value may be programmed to an MRS of the memory device 120.

[0037] The test host 112 may provide a repair command and a fault address to the memory device 120. The repair command may include a post-package repair (PPR) command. The PPR command may instruct that a fault address detected after the memory device 120 is packaged is stored in a non-volatile memory (e.g., a fuse array) of the memory device 120, and a repair operation is performed on the fault address. In response to the PPR command, the memory device 120 may perform a PPR operation by replacing a faulty word line selected by the faulty address with a redundant word line or replacing a faulty bit line selected by the faulty address with a redundant bit line.

[0038] The memory device 120 may include a memory cell array 122 and a repair circuit 124. The memory cell array 122 may include a plurality of rows, a plurality of columns, and a plurality of memory cells at the intersections of the rows and the columns, respectively. The memory cells of the memory cell array 122 may correspond to volatile memory cells, such as DRAM cells. The memory cell array 122 may include redundant rows and / or redundant columns connected to the redundant memory cells for repairing faulty memory cells having defects or failures therein. As used herein, "element A is connected to element B" (or similar language) means that element A is physically and / or electrically connected to element B.

[0039] The repair circuit 124 may be configured to repair a failed memory cell detected in the memory cell array 122 by using a redundant memory cell. The repair circuit 124 may repair a failed cell detected by an electrical die sort (EDS) test after a semiconductor manufacturing process for the memory device 120. The repair circuit 124 may also perform a PPR operation by repairing a defective memory cell (occurring during a packaging / modularization / installation test of the memory device 120) using a redundant memory cell.

[0040] Figure 2A and Figure 2B It is shown by Figure 1 Schematic diagram of the repair operation performed by the repair circuit 124.

[0041] The repair circuit 124 may perform a repair operation by replacing the failed row address FRA and / or the failed column address FCA with the redundant row address RRA and / or the redundant column address RCA, respectively.

[0042] Reference Figure 2A , the repair circuit 124 can use the redundant row address RRA to repair the faulty row address FRA associated with the faulty memory cell. The memory cell array 122 may include a normal memory cell array NMCA and a redundant memory cell array RMCA. The normal memory cell array NMCA may include memory cells connected to word lines and bit lines. The redundant memory cell array RMCA may include memory cells connected to redundant word lines and / or redundant bit lines. The repair circuit 124 may include a row repair decoder circuit 210, which determines the redundant row address RRA so that the redundant resources used to repair the faulty row address FRA do not overlap with each other. According to some embodiments, the row repair decoder circuit 210 may sequentially or randomly set the redundant row address RRA in the redundant memory cell array RMCA to repair the faulty row address FRA.

[0043] The row repair decoder circuit 210 may perform a row repair operation so that the redundant row address RRA is selected instead of the fault row address FRA. When the access row address applied to the memory device 120 specifies the fault row address FRA in the normal memory cell array NMCA, the redundant memory cell corresponding to the redundant row address RRA in the redundant memory cell array RMCA may be selected. The row repair decoder circuit 210 may deactivate the word line corresponding to the fault row address FRA and activate the redundant word line corresponding to the redundant row address RRA. Therefore, the redundant memory cell corresponding to the redundant row address RRA may be selected, and the memory cell corresponding to the fault row address FRA may not be selected.

[0044] Reference Figure 2B , the repair circuit 124 may perform a column repair operation so that the redundant column address RCA is selected instead of the fault column address FCA. The repair circuit 124 may include a column repair decoder circuit 220 that determines the redundant column address RCA so that the redundant resources used to repair the fault column address FCA do not overlap with each other. According to some embodiments, the column repair decoder circuit 220 may sequentially or randomly set the redundant column address RCA in the redundant memory cell array RMCA to repair the fault column address FCA.

[0045] The column repair decoder circuit 220 may perform a column repair operation so that a redundant column address RCA is selected instead of a fault column address FCA. When an access column address applied to the memory device 120 specifies a fault column address FCA in a normal memory cell array NMCA, a redundant memory cell corresponding to the redundant column address RCA in the redundant memory cell array RMCA may be selected. The column repair decoder circuit 220 may not select a bit line corresponding to the fault column address FCA, but may select a redundant bit line corresponding to the redundant column address RCA. Therefore, a redundant memory cell corresponding to the redundant column address RCA may be selected, but a memory cell corresponding to the fault column address FCA may not be selected.

[0046] The repair circuit 124 may perform a repair operation and store redundant mapping information indicating that a failed address (e.g., a failed row address FRA and / or a failed column address FCA) is replaced by a redundant address (e.g., a redundant row address RRA and / or a redundant column address RCA). The repair circuit 124 may perform a repair operation and store redundant mapping information indicating that a failed address (e.g., a failed row address FRA and / or a failed column address FCA) is replaced by a redundant address (e.g., a redundant row address RRA and / or a redundant column address RCA). Figure 4 The repair circuit 124 may compare the access address applied to the memory device 120 with the fault address stored in the fuse array, and when it is determined as a result of the comparison that the access address is the same as the fault address, the redundant memory cell corresponding to the redundant address to be selected may be controlled without controlling the memory cell corresponding to the fault address.

[0047] Figure 3 is a block diagram illustrating a memory device 120 including a repair circuit 124 according to some embodiments. Figure 4 It is shown Figure 3 Schematic diagram of the repair address storage circuit in .

[0048] Combination Figures 1 to 2B Reference Figure 3 , the memory device 120 may include a memory cell array 122, a control logic circuit 302, and a repair circuit 124. Figure 3 Although not shown, the memory device 120 may further include a row decoder, a word line driver, a column decoder, a read / write circuit, a clock circuit, an address buffer, an MRS, and an input / output (I / O) circuit. Figure 3 The configuration of the memory device 120 does not indicate or imply limitation of the present inventive concept.

[0049] The memory cell array 122 may include first to fourth memory banks BANK1 to BANK4. A row decoder and a column decoder may be provided corresponding to each of the first to fourth memory banks BANK1 to BANK4. A row decoder and a column decoder connected to a memory bank corresponding to a memory bank address may be activated. Each of the first to fourth memory banks BANK1 to BANK4 may include a plurality of memory cells provided in a matrix of rows and columns, and redundant memory cells connected to redundant rows and / or redundant columns.

[0050] The control logic circuit 302 may receive a command CMD through a command / address bus of the channel 130 and generate a control signal corresponding to the command CMD. The control logic circuit 302 may control operation timing of the memory device 120 when performing a memory operation.

[0051] The repair circuit 124 may receive the address ADDR through the command / address bus of the channel 130 and perform an operation corresponding to the control signal of the control logic circuit 302 .

[0052] The repair circuit 124 may include first to fourth repair circuits 124(1) to 124(4) corresponding to the first to fourth memory banks BANK1 to BANK4, respectively. Each of the first to fourth repair circuits 124(1) to 124(4) may include a row repair decoder circuit 210, a column repair decoder circuit 220, a repair control circuit 300, and a repair address storage circuit 350. The row repair decoder circuit 210 (e.g., referring to Figure 2A ) and column repair decoder circuit 220 (eg, see Figure 2B ) can perform a repair operation based on the repair control signal generated by the repair control circuit 300 so that a redundant address (e.g., a redundant row address RRA or a redundant column address RCA) is selected instead of a failed address (e.g., a failed row address FRA or a failed column address FCA). Each of the first repair circuit 124(1) to the fourth repair circuit 124(4) can replace the failed row address FRA and / or the failed column address FCA of the current memory bank with the redundant row address RRA and / or the redundant column address RCA by using the row repair decoder circuit 210 and / or the column repair decoder circuit 220.

[0053] The repair control circuit 300 may include a pre-decoder circuit 310, a fault address memory (FAM) 320, a comparison circuit 330, and a combinational logic circuit 340. The repair control circuit 300 may receive a fault address from the test host 112 and store the fault address in a register (e.g., Figure 5 The fault address stored in FAM 320 may correspond to the fault address in the above reference. Figure 2A and Figure 2B The repair control circuit 300 may store the fault address stored in the FAM 320 in a fuse array (eg, Figure 4 Among the 400).

[0054] Reference Figure 4 The repair address storage circuit 350 may include a fuse array 400 including a plurality of antifuses 410, level shifters 420_1 to 420_m each generating a high voltage for changing a resistance state of the antifuses 410, and a sense amplifier 430 that senses and amplifies information stored in the fuse array 400. The repair address storage circuit 350 may further include a register 440 storing fuse data generated by reading information stored in the fuse array 400.

[0055] The fuse array 400 may include a plurality of fuses. Information may be stored in each fuse. The fuse array 400 may include a laser fuse or an electric fuse, the connection of the laser fuse being controlled by laser irradiation, and the connection of the electric fuse being controlled by an electrical signal. The fuse array 400 may include an anti-fuse, characterized in that it changes from a high resistance state to a low resistance state in response to an electrical signal (e.g., a high voltage signal). Any of the above types may be applied to the fuse array 400. In the following, it is assumed that the fuse array 400 corresponds to an anti-fuse array including anti-fuses. The fuse array 400 may be used interchangeably with the anti-fuse array 400 (i.e., the fuse array 400 may also be referred to as the anti-fuse array 400). The information stored in the anti-fuse or the data read from the anti-fuse may be referred to as fuse data.

[0056] The antifuse array 400 may have an array structure in which the antifuses 410 are located at the intersections of rows and columns, respectively. For example, when the antifuse array 400 has "m" rows and "n" columns, the antifuse array 400 may have m×n antifuses 410. The antifuse array 400 may include "m" word lines WL1 to WLm for accessing the antifuses 410 in "m" rows and "n" bit lines BL1 to BLn arranged corresponding to "n" columns to transmit information read from the antifuses 410 to the sense amplifier 430.

[0057] The antifuse array 400 can be programmed by applying one of the voltage signals VS1 to VSm from the level shifters 420_1 to 420_m, respectively, to each antifuse 410 to change the state of each of the antifuses 410. Each antifuse 410 can be changed from a high resistance state to a low resistance state by a programming operation, and thus information can be stored. The antifuse 410 can have a capacitor structure, that is, a structure having two conductive layers and a dielectric layer between the two conductive layers, and can be programmed by applying a high voltage between the two conductive layers to break through the dielectric layer.

[0058] After the antifuse array 400 is programmed, a read operation may be performed on the antifuse array 400 while the memory device 120 is driven. The read operation on the antifuse array 400 may be performed simultaneously with the driving of the memory device 120, or may be performed at a specific time after the driving of the memory device 120. A word line selection signal may be applied to the antifuse array 400 through the word lines WL1 to WLm of the antifuse array 400, and information stored in the selected antifuses 410 may be provided to the sense amplifier 430 through the bit lines BL1 to BLn. Due to the characteristics of the array structure, the information of the antifuse array 400 may be randomly accessed by driving the word lines WL1 to WLm and the bit lines BL1 to BLn.

[0059] For example, when the word lines WL1 to WLm are sequentially driven, the antifuses 410 in the first row to the mth row of the antifuse array 400 can be sequentially accessed. Information of the antifuses 410 accessed sequentially can be provided to the sense amplifier 430. The sense amplifier 430 can include at least one sense amplifier circuit. For example, when the antifuse array 400 has "n" columns, the sense amplifier 430 can include "n" sense amplifier circuits corresponding to the "n" columns, respectively. The "n" sense amplifier circuits can be connected to the "n" bit lines BL1 to BLn, respectively.

[0060] The sense amplifier 430 may sense and amplify information accessed in the antifuse array 400, and may output the amplified information. The fuse data OUT1 to OUTn outputted from the sense amplifier 430 may be provided to the register 440. The register 440 may receive the fuse data OUT1 to OUTn in units of rows of the antifuse array 400. For example, when a row of the antifuse array 400 is selected, the fuse data OUT1 to OUTn respectively from the antifuses 410 connected to the word line corresponding to the selected row may be provided to the register 440 in parallel. The fuse data OUT1 to OUTn stored in the register 440 may include information for repair information (e.g., a fault address F_ADDR), which indicates a fault row address (e.g., Figure 2AFRA in ) and / or the faulty column address (e.g. Figure 2B in FCA).

[0061] Figure 3 The repair circuit 124 in the memory device 120 may compare the access row address applied to the memory device 120 with the fault row address FRA stored in the repair address storage circuit 350. When the access row address is the same as the fault row address FRA, the repair circuit 124 may perform a row repair operation by selecting the redundant row address RRA instead of the fault row address FRA using the row repair decoder circuit 210, such as Figure 2A The repair circuit 124 may compare the access column address applied to the memory device 120 with the fault column address FCA. When the access column address is the same as the fault column address FCA, the repair circuit 124 may perform a column repair operation by selecting the redundant column address RCA instead of the fault column address FCA using the column repair decoder circuit 220, as shown in FIG. Figure 2B as shown in .

[0062] In some embodiments, the repair circuit 124 may perform a row repair operation based on the repair enable signal PRENi. The repair circuit 124 may perform a column repair operation based on the repair enable signal PRENi. For example, the repair circuit 124 may perform a row repair operation based on the repair enable signal PRENi at a high logic level. For example, the repair circuit 124 may perform a column repair operation based on the repair enable signal PRENi at a high logic level. The repair enable signal PRENi will be described in detail below with reference to the accompanying drawings.

[0063] The pre-decoder circuit 310 may receive N signals, each of which represents one of a plurality of bits representing an address (eg, a plurality of bits of a row address or a column address), and may output a 2-bit signal having the same value as the N signals. N One of the bit states corresponds to a bit value of 2 N Sub-signals. 2 N Among the sub-signals, only one sub-signal can have a bit value of 1, and the bit value of N The bit value represented by the sub-signal can be called a pre-decoded address. Figure 5 8 describe the operation of the memory device 120 including the predecoder circuit 310 that predecodes two (N=2) signals. However, the following description is not limited to the case of N=2, but can be applied to any case where N is an integer of at least 2. That is, N can be an integer greater than or equal to 2.

[0064] For example, the predecoder circuit 310 may decode the access row address provided to the repair circuit 124 into the predecoded row address PRA, and may decode the fault row address FRA stored in the repair address storage circuit 350 into the predecoded fault row address PFRA. The predecoder circuit 310 may also decode the access column address provided to the repair circuit 124 into the predecoded column address PCA, and may decode the fault column address FCA stored in the repair address storage circuit 350 into the predecoded fault column address PFCA.

[0065] In some embodiments, the repair circuit 124 may compare the pre-decoded row address PRA with the pre-decoded fault row address PFRA. When the pre-decoded row address PRA is the same as the pre-decoded fault row address PFRA, the repair circuit 124 may perform a row repair operation by using the row repair decoder circuit 210 so that the redundant row address RRA is selected instead of the fault row address FRA, such as Figure 2A The repair circuit 124 may compare the pre-decoded column address PCA with the pre-decoded fault column address PFCA. When the pre-decoded column address PCA is the same as the pre-decoded fault column address PFCA, the repair circuit 124 may perform a column repair operation by using the column repair decoder circuit 220 so that the redundant column address RCA is selected instead of the fault column address FCA, as shown in FIG. Figure 2B shown.

[0066] Figure 5 is a circuit diagram of a unit circuit 500 generating a repair enable signal PRENi related to a failed row address among a plurality of unit circuits forming the repair control circuit 300 of the first repair circuit 124 ( 1 ) according to some embodiments.

[0067] Reference Figure 5 The operation of the first repair circuit 124 ( 1 ) corresponding to the first memory bank BANK1 is described.

[0068] Reference Figure 3 and Figure 5, the unit circuit 500 generating a repair enable signal PRENi may include a pre-decoder circuit 310, a FAM 320 including a first register 510 and a second register 520, a comparison circuit 330 including a first sub-comparison circuit 531 to a seventh sub-comparison circuit 537, and a combinational logic circuit 340 including a first NAND logic circuit 541 to a third NAND logic circuit 543, a NOR logic circuit 544 and a first inverter 545 (also referred to as a first inverter circuit). For example, the unit circuit 500 may include a circuit that operates using a 14-bit row address (e.g., RA<15:2>) excluding a lower 2-bit row address (e.g., RA<1:0>) from a 16-bit row address (e.g., RA<15:0>). The example of the unit circuit 500 for a 14-bit row address (RA<15:2>) does not indicate or imply limitation of the inventive concept. According to some embodiments, the unit circuit may also be applied to an address having fewer or more bits than those described in the present embodiment.

[0069] In some embodiments, each of the first to fourth memory banks BANK1 to BANK4 of the memory cell array 122 may include a plurality of memory blocks connected to 64 word lines, each word line corresponding to a row address (RA<15:0>), a main word line driver connected to the memory blocks, and a sub-word line driver connected to the memory blocks, respectively. The main word line driver may be connected to a row decoder, and may activate a main word line drive signal corresponding to a decoded 14-bit row address (RA<15:2>), and may activate a sub-word line drive signal corresponding to a decoded lower 2-bit row address (RA<1:0>). For example, the sub-word line driver may include an inverter circuit including a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel MOS (NMOS) transistor. The main word line drive signal may be applied to respective gates of the PMOS transistor and the NMOS transistor, the sub-word line drive signal may be applied to the source of the PMOS transistor, and the sub-word line is connected to the drain of the PMOS transistor. According to these structures of the main word line driver and the sub-word line driver, the word line of each of the first memory bank BANK1 to the fourth memory bank BANK4 can be dominantly activated in response to the main word line drive signal. Therefore, the word line of each of the first memory bank BANK1 to the fourth memory bank BANK4 can be interpreted as being accessed by the 14-bit row address (RA<15:2>).

[0070] The FAM 320 may include a first register 510 and a second register 520 each implemented as a register array. The first register 510 may store a first address provided from the repair address storage circuit 350. The first address may be composed of 14 bits <15:2>. The second register 520 may store a second address corresponding to an access address applied to the memory device 120. Similar to the first address, the second address may be composed of 14 bits <15:2>. Bits <15:2> of each of the first address and the second address stored in the first register 510 and the second register 520, respectively, may be provided to the pre-decoder circuit 310. Hereinafter, the first address stored in the first register 510 may be referred to as a fault row address FRA. The access address or access row address stored in the second register 520 may be referred to as a row address RA.

[0071] The pre-decoder circuit 310 may receive N signals, each of which represents one of a plurality of address bits stored in a register (eg, the first register 510 or the second register 520), and may output 2 N Sub-signals. 2 N The bit value of the sub-signal can correspond to 2 of the N address bits. N A bit state may refer to any one of all combinations of bit values ​​of N bits. For example, in the case of two bits, "00", "01", "10" or "11" may be referred to as one of the bit states of the two bits, and the two bits may have a total of four bit states.

[0072] In other words, the pre-decoder circuit 310 may receive N signals each representing one address bit, and may decode the N signals into a 2-bit signal having the same value as the N address bits. N One of the bit states corresponds to a bit value of 2 N A signal.

[0073] In some embodiments, the pre-decoder circuit 310 may receive N signals, each of which represents one of a plurality of bits of a row address, and may output a 2-bit bit having the same value as the N signals. N One of the bit states corresponds to a bit value of 2 N A sub-signal.

[0074] In some embodiments, the predecoder circuit 310 may receive two signals each representing one bit of the row address RA, and may decode the two signals into four sub-signals (PRA<3:0>) having a one-bit value corresponding to one of four bit states of the two bits of the row address RA. Here, the four sub-signals may correspond to the predecoded row address PRA<3:0>.

[0075] In some embodiments, the pre-decoder circuit 310 may receive N signals, each of which represents one of a plurality of bits of the fail row address FRA, and may output a 2-bit bit having the same value as the N signals. N One of the bit states corresponds to a bit value of 2 N A sub-signal.

[0076] The pre-decoder circuit 310 may receive two signals each representing one bit of the failure row address FRA, and may decode the two signals into four sub-signals (PFRA<3:0>) having one bit value corresponding to one of four bit states of the two bits of the failure row address FRA. Here, the four sub-signals may correspond to the pre-decoded failure row address PFRA<3:0>.

[0077] Figure 6 is a diagram of a pre-decoder circuit 310 among a plurality of unit circuits of a repair control circuit 300 forming a first repair circuit 124 ( 1 ) according to some embodiments.

[0078] Reference Figure 6 , the pre-decoder circuit 310 may include first to seventh row pre-decoder circuits 611 to 617 and first to seventh fuse pre-decoder circuits 621 to 627 .

[0079] Each of the first row predecoder circuit 611 to the seventh row predecoder circuit 617 may receive two signals each representing one bit of the row address RA, and may decode the two signals into four sub-signals (PRA<3:0>) having one bit value corresponding to one of four bit states of the two bits of the row address RA. Here, the four sub-signals may correspond to the predecoded row address PRA<3:0>.

[0080] The first row pre-decoder circuit 611 may receive a signal RA indicating a first bit of a row address RA. <2> and a signal RA indicating the second bit of the row address RA <3> And four sub-signals (PRA 2 / 3<3:0>) indicating the bit states of the first bit and the second bit of the row address RA can be output.

[0081] In other words, the first row pre-decoder circuit 611 may receive a signal RA indicating the first bit of the row address RA. <2> and a signal RA indicating the second bit of the row address RA <3> , and the bits <3:0> of the first pre-decoded row address PRA 2 / 3 may be output. Here, the bits <3:0> of the first pre-decoded row address PRA 2 / 3 may correspond to four sub-signals having a one-bit value, and the four sub-signals may be respectively referred to as a first sub-signal PRA 2 / 3 0, a second sub-signal PRA 2 / 3 1, a third sub-signal PRA 2 / 3 2, and a fourth sub-signal PRA 2 / 3 3.

[0082] Similarly, the second row pre-decoder circuit 612 may receive a signal RA indicating the third bit of the row address RA. <4> and a signal RA indicating the fourth bit of the row address RA <5> , and can output bits <3:0> of the second pre-decoded row address PRA 4 / 5. The third row pre-decoder circuit 613 can receive a signal RA indicating the fifth bit of the row address RA. <6> and a signal RA indicating the sixth bit of the row address RA <7> , and may output bits <3:0> of the third pre-decoded row address PRA 6 / 7. The fourth row pre-decoder circuit 614 may receive a signal RA indicating the seventh bit of the row address RA. <8> and a signal RA indicating the eighth bit of the row address RA <9> , and may output bits <3:0> of the fourth pre-decoded row address PRA 8 / 9. The fifth row pre-decoder circuit 615 may receive a signal RA indicating the ninth bit of the row address RA. <10> and a signal RA indicating the tenth bit of the row address RA <11> , and may output bits <3:0> of the fifth pre-decoded row address PRA 10 / 11. The sixth row pre-decoder circuit 616 may receive a signal RA indicating the eleventh bit of the row address RA. <12> and a signal RA indicating the twelfth bit of the row address RA <13> , and can output bits <3:0> of the sixth pre-decoded row address PRA 12 / 13. The seventh row pre-decoder circuit 617 can receive a signal RA indicating the thirteenth bit of the row address RA. <14> and a signal RA indicating the fourteenth bit of the row address RA <15> , and bits <3:0> of the seventh pre-decoded row address PRA 14 / 15 may be output.

[0083] Each of the first to seventh fuse predecoder circuits 621 to 627 may receive two signals each representing one bit of the fail row address FRA, and may decode the two signals into four sub-signals (PFRA<3:0>) having one bit value corresponding to one of four bit states of the two bits of the fail row address FRA. Here, the four sub-signals may correspond to the pre-decoded fail row address PFRA<3:0>.

[0084] The first fuse pre-decoder circuit 621 may receive a signal FRA indicating a first bit of a failed row address FRA. <2> and a signal FRA indicating the second bit of the fault row address FRA <3> , and can output four sub-signals (PFRA 2 / 3<3:0>) indicating the bit states of the first bit and the second bit of the fail row address FRA.

[0085] In other words, the first fuse pre-decoder circuit 621 may receive a signal FRA indicating the first bit of the failed row address FRA. <2> and a signal FRA indicating the second bit of the fault row address FRA <3> , and bits <3:0> of the first pre-decoded fail row address PFRA 2 / 3 may be output. Here, bits <3:0> of the first pre-decoded fail row address PFRA 2 / 3 may correspond to four sub-signals having one bit value, and the four sub-signals may be respectively referred to as a fifth sub-signal PFRA 2 / 3 0, a sixth sub-signal PFRA 2 / 3 1, a seventh sub-signal PFRA 2 / 3 2, and an eighth sub-signal PFRA 2 / 3 3.

[0086] Similarly, the second fuse pre-decoder circuit 622 may receive a signal FRA indicating the third bit of the failed row address FRA. <4> and a signal FRA indicating the fourth bit of the fault row address FRA <5> The third fuse pre-decoder circuit 623 may receive a signal FRA indicating the fifth bit of the fail row address FRA. <6> and a signal FRA indicating the sixth bit of the failed row address FRA <7> , and may output bits <3:0> of the third pre-decoded fail row address PFRA 6 / 7. The fourth fuse pre-decoder circuit 624 may receive a signal FRA indicating the seventh bit of the fail row address FRA. <8> and a signal FRA indicating the eighth bit of the fault row address FRA <9> , and may output bits <3:0> of the fourth pre-decoded fail row address PFRA 8 / 9. The fifth fuse pre-decoder circuit 625 may receive a signal FRA indicating the ninth bit of the fail row address FRA. <10> and a signal FRA indicating the tenth bit of the fault row address FRA <11> , and may output bits <3:0> of the fifth pre-decoded fail row address PFRA 10 / 11. The sixth fuse pre-decoder circuit 626 may receive a signal FRA indicating the eleventh bit of the fail row address FRA. <12> and a signal FRA indicating the twelfth bit of the fault row address FRA <13> , and may output bits <3:0> of the sixth pre-decoded fail row address PFRA 12 / 13. The seventh fuse pre-decoder circuit 627 may receive a signal FRA indicating the thirteenth bit of the fail row address FRA. <14> and a signal FRA indicating the fourteenth bit of the fault row address FRA <15> , and bits <3:0> of the seventh pre-decoded fail row address PFRA 14 / 15 may be output.

[0087] Fig. 7A is a diagram illustrating an equivalent circuit of the first row pre-decoder circuit 611 included in the pre-decoder circuit 310 according to some embodiments. Figure 7B is a diagram illustrating the operation of the first row pre-decoder circuit 611 according to some embodiments. Figure 7C is a diagram illustrating an equivalent circuit of the first fuse pre-decoder circuit 621 included in the pre-decoder circuit 310 according to some embodiments. Fig.7D is a diagram illustrating the operation of the first fuse pre-decoder circuit 621 according to some embodiments.

[0088] Reference Fig. 7A , the first row pre-decoder circuit 611 may include a second inverter circuit 701a, a third inverter circuit 702a, and first to fourth AND logic circuits 703a to 706a.

[0089] The second inverter circuit 701a may be connected between the first node N61a and the second node N62a. The signal RA indicating the first bit of the row address RA <2> is applied to the first node N61a. The third inverter circuit 702a may be connected between the third node N63a and the fourth node N64a. The signal RA representing the second bit of the row address RA <3> is applied to the third node N63a. The first AND logic circuit 703a may be connected to the second node N62a, the fourth node N64a, and the first output node, and the first output node outputs the first sub-signal PRA 2 / 3 0 representing the first bit among the bits <3:0> of the first pre-decoded row address PRA 2 / 3. The second AND logic circuit 704a may be connected to the first node N61a, the fourth node N64a, and the second output node, and the second output node outputs the second sub-signal PRA 2 / 3 1 representing the second bit among the bits <3:0> of the first pre-decoded row address PRA 2 / 3. The third AND logic circuit 705a may be connected to the second node N62a, the third node N63a, and the third output node, and the third output node outputs the third sub-signal PRA 2 / 3 2 representing the third bit among the bits <3:0> of the first pre-decoded row address PRA 2 / 3. The fourth AND logic circuit 706a may be connected to the first node N61a, the third node N63a, and a fourth output node that outputs a fourth sub-signal PRA 2 / 3 3 representing a fourth bit among bits <3:0> of the first predecoded row address PRA 2 / 3.

[0090] Figure 7B 1 shows that, for a signal RA representing the first bit of a row address RA input to the first row predecoder circuit 611, <2> and the signal RA indicating the second bit of the row address RA <3> The bit value of the first sub-signal PRA 2 / 3 0, the bit value of the second sub-signal PRA 2 / 3 1, the bit value of the third sub-signal PRA 2 / 3 2 and the bit value of the fourth sub-signal PRA 2 / 3 3 output from the first row predecoder circuit 611.

[0091] Reference Figure 7B, it can be seen that when the first bit (RA <2> ) bit value is 0 and the second bit (RA <3> ) has a bit value of 0, according to the operation of the first row predecoder circuit 611, the bit value of the first sub-signal PRA 2 / 3 0 representing the first bit among the bits <3:0> of the first predecoded row address PRA 2 / 3 becomes 1, and the bit value of each of the second sub-signal PRA 2 / 3 1, the third sub-signal PRA 2 / 3 2, and the fourth sub-signal PRA 2 / 3 3 becomes 0. It can also be seen that when the first bit (RA <2> ) has a bit value of 1 and the second bit (RA <3> ) is 0, according to the operation of the first row predecoder circuit 611, the bit value of the second sub-signal PRA 2 / 3 1 representing the second bit among the bits <3:0> of the first predecoded row address PRA 2 / 3 becomes 1, and the bit value of each of the first sub-signal PRA 2 / 3 0, the third sub-signal PRA 2 / 3 2, and the fourth sub-signal PRA 2 / 3 3 becomes 0. It can also be seen that when the first bit (RA <2> ) bit value is 0 and the second bit (RA <3> ) is 1, according to the operation of the first row predecoder circuit 611, the bit value of the third sub-signal PRA 2 / 3 2 representing the third bit among the bits <3:0> of the first predecoded row address PRA 2 / 3 becomes 1, and the bit value of each of the first sub-signal PRA 2 / 3 0, the second sub-signal PRA 2 / 3 1, and the fourth sub-signal PRA 2 / 3 3 becomes 0. It can also be seen that when the first bit (RA <2> ) has a bit value of 1 and the second bit (RA <3> ) is 1, according to the operation of the first row predecoder circuit 611, the bit value of the fourth sub-signal PRA 2 / 3 3 representing the fourth bit among the bits <3:0> of the first predecoded row address PRA 2 / 3 becomes 1, and the bit value of each of the first sub-signal PRA 2 / 3 0, the second sub-signal PRA 2 / 3 1 and the third sub-signal PRA 2 / 3 2 becomes 0.

[0092] In other words, the first row predecoder circuit 611 can decode the row address RA having two bits into the predecoded row address PRA having four bits, so that the bit value of only one sub-signal among the four sub-signals representing the bit states of the two bits of the row address RA becomes 1.

[0093] Reference Figure 7C , the first fuse pre-decoder circuit 621 may include a fourth inverter circuit 701b, a fifth inverter circuit 702b, and fifth to eighth AND logic circuits 703b to 706b.

[0094] The fourth inverter circuit 701b may be connected between the fifth node N61b and the sixth node N62b. A signal FRA indicating the first bit of the fail row address FRA <2> is applied to the fifth node N61b. The fifth inverter circuit 702b may be connected between the seventh node N63b and the eighth node N64b. The signal FRA indicating the second bit of the fail row address FRA <3> is applied to the seventh node N63b. The fifth AND logic circuit 703b may be connected to the sixth node N62b, the eighth node N64b, and the fifth output node, and the fifth output node outputs the fifth sub-signal PFRA 2 / 3 0 representing the first bit among the bits <3:0> of the first pre-decoded fail row address PFRA 2 / 3. The sixth AND logic circuit 704b may be connected to the fifth node N61b, the eighth node N64b, and the sixth output node, and the sixth output node outputs the sixth sub-signal PFRA 2 / 3 1 representing the second bit among the bits <3:0> of the first pre-decoded fail row address PFRA 2 / 3. The seventh AND logic circuit 705b may be connected to the sixth node N62b, the seventh node N63b, and the seventh output node, and the seventh output node outputs the seventh sub-signal PFRA 2 / 3 2 representing the third bit among the bits <3:0> of the first pre-decoded fail row address PFRA 2 / 3. The eighth AND logic circuit 706b may be connected to the fifth node N61b, the seventh node N63b, and an eighth output node that outputs an eighth sub-signal PFRA 2 / 3 3 representing a fourth bit among bits <3:0> of the first predecoded fail row address PFRA 2 / 3.

[0095] Fig.7D 1 shows that, for a signal FRA indicating the first bit of a failed row address FRA input to the first fuse pre-decoder circuit 621, <2> and a signal FRA indicating the second bit of the fault row address FRA <3> , the bit value of the fifth sub-signal PFRA 2 / 3 0, the bit value of the sixth sub-signal PFRA 2 / 3 1, the bit value of the seventh sub-signal PFRA 2 / 3 2, and the bit value of the eighth sub-signal PFRA 2 / 3 3 output from the first fuse predecoder circuit 621.

[0096] Reference Fig.7D, it can be seen that when the first bit (FRA <2> ) bit value is 0 and the second bit (FRA <3> ) is 0, according to the operation of the first fuse predecoder circuit 621, the bit value of the fifth sub-signal PFRA 2 / 3 0 indicating the first bit among the bits <3:0> of the first predecoded fail row address PFRA 2 / 3 becomes 1, and the bit value of each of the sixth sub-signal PFRA 2 / 3 1, the seventh sub-signal PFRA 2 / 3 2, and the eighth sub-signal PFRA 2 / 3 3 becomes 0. It can also be seen that when the first bit (FRA <2> ) bit value is 1 and the second bit (FRA <3> ) is 0, according to the operation of the first fuse predecoder circuit 621, the bit value of the sixth sub-signal PFRA 2 / 3 1 indicating the second bit among the bits <3:0> of the first predecoded fail row address PFRA 2 / 3 becomes 1, and the bit value of each of the fifth sub-signal PFRA 2 / 3 0, the seventh sub-signal PFRA 2 / 3 2, and the eighth sub-signal PFRA 2 / 3 3 becomes 0. It can also be seen that when the first bit (FRA <2> ) bit value is 0 and the second bit (FRA <3> ) is 1, according to the operation of the first fuse predecoder circuit 621, the bit value of the seventh sub-signal PFRA 2 / 3 2 indicating the third bit among the bits <3:0> of the first predecoded fail row address PFRA 2 / 3 becomes 1, and the bit value of each of the fifth sub-signal PFRA 2 / 3 0, the sixth sub-signal PFRA 2 / 3 1, and the eighth sub-signal PFRA 2 / 3 3 becomes 0. It can also be seen that when the first bit (FRA <2> ) bit value is 1 and the second bit (FRA <3> ), according to the operation of the first fuse predecoder circuit 621, the bit value of the eighth sub-signal PFRA 2 / 33 indicating the fourth bit among the bits <3:0> of the first predecoded fail row address PFRA 2 / 3 becomes 1, and the bit value of each of the fifth sub-signal PFRA 2 / 3 0, the sixth sub-signal PFRA 2 / 3 1, and the seventh sub-signal PFRA2 / 3 2 becomes 0.

[0097] In other words, the first fuse pre-decoder circuit 621 may output four sub-signals such that the bit value of only one sub-signal among the four sub-signals representing the bit states of two bits of the fail row address FRA becomes 1.

[0098] Return to reference Figure 5 , the comparison circuit 330 can convert the 2 N The bit value of the sub-signal is equal to the 2 bits representing the pre-decoded faulty row address. NThe bit values ​​of the N bits of the failed row address are compared with the bit values ​​of the N bits of the row address, and a hit signal indicating a match or mismatch between the bit values ​​of the N bits of the failed row address and the bit values ​​of the N bits of the row address can be output, where N is a natural number.

[0099] Reference Figure 5 , the comparison circuit 330 may include first to seventh sub-comparison circuits 531 to 537. Each of the first to seventh sub-comparison circuits 531 to 537 may compare the bit value of the bit <3:0> of the predecoded row address PRA with the bit value of the bit <3:0> of the predecoded fail row address PFRA, and may output a hit signal HIT, and may receive a bit value from the predecoder circuit 310.

[0100] The pre-decoded row address PRA may represent a plurality of bits (eg, bits) of the row address RA stored in the second register 520. <2> and Bit <3> The pre-decoded fault row address PFRA may represent a plurality of bits (eg, bits) about the fault row address FRA stored in the first register 510. <2> and Bit <3> ). When the corresponding bit values ​​of the plurality of bits of the pre-decoded fault row address (e.g., PFRA 2 / 3<3:0>) match the corresponding bit values ​​of the plurality of bits of the pre-decoded row address (e.g., PRA 2 / 3<3:0>), one hit signal HIT (e.g., HIT 2 / 3) may be output at a high logic level, and when the bit values ​​of the bits of the pre-decoded fault row address do not match the bit values ​​of the bits of the pre-decoded row address, one hit signal HIT (e.g., HIT 2 / 3) may be output at a low logic level. However, the embodiment is not limited thereto. For example, in some other embodiments, when corresponding bit values ​​of multiple bits of the predecoded fault row address (e.g., PFRA2 / 3<3:0>) match corresponding bit values ​​of multiple bits of the predecoded row address (e.g., PRA 2 / 3<3:0>), a hit signal HIT (e.g., HIT 2 / 3) may be output at a low logic level, and when there is a mismatch between the bit values ​​of the bits of the predecoded fault row address and the bit values ​​of the bits of the predecoded row address, a hit signal HIT (e.g., HIT 2 / 3) may be output at a high logic level.

[0101] Reference Figure 5, the first sub-comparison circuit 531 may compare the corresponding bit values ​​of the bits <3:0> of the first predecoded row address PRA 2 / 3 received from the predecoder circuit 310 with the corresponding bit values ​​of the bits <3:0> of the first predecoded fail row address PFRA 2 / 3 received from the predecoder circuit 310, and may output a first hit signal HIT 2 / 3. At this time, the bits <3:0> of the first predecoded row address PRA 2 / 3 may represent information about the bits <3:2> of the row address RA stored in the second register 520. The bits <3:0> of the first predecoded fail row address PFRA 2 / 3 may represent information about the bits <3:2> of the fail row address FRA stored in the first register 510. When the corresponding bit value of the bit <3:0> of the first pre-decoded row address PRA 2 / 3 matches the corresponding bit value of the bit <3:0> of the first pre-decoded fault row address PFRA 2 / 3, the first hit signal HIT 2 / 3 may be output at a high logic level, and when there is a mismatch between the bit values, the first hit signal HIT 2 / 3 may be output at a low logic level. However, the embodiment is not limited thereto. For example, in some other embodiments, when the corresponding bit value of the bit <3:0> of the first pre-decoded row address PRA 2 / 3 matches the corresponding bit value of the bit <3:0> of the first pre-decoded fault row address PFRA 2 / 3, the first hit signal HIT 2 / 3 may be output at a low logic level, and when there is a mismatch between the bit values, the first hit signal HIT 2 / 3 may be output at a high logic level.

[0102] The second sub-comparison circuit 532 may compare the corresponding bit values ​​of the bits <3:0> of the second pre-decoded row address PRA4 / 5 received from the pre-decoder circuit 310 with the corresponding bit values ​​of the bits <3:0> of the second pre-decoded fail row address PFRA4 / 5 received from the pre-decoder circuit 310, and may output a second hit signal HIT 4 / 5. At this time, the bits <3:0> of the second pre-decoded row address PRA 4 / 5 may represent information about the bits <5:4> of the row address RA stored in the second register 520. The bits <3:0> of the second pre-decoded fail row address PFRA 4 / 5 may represent information about the bits <5:4> of the fail row address FRA stored in the first register 510.

[0103] The third sub-comparison circuit 533 may compare the corresponding bit values ​​of the bits <3:0> of the third pre-decoded row address PRA6 / 7 received from the pre-decoder circuit 310 with the corresponding bit values ​​of the bits <3:0> of the third pre-decoded fail row address PFRA6 / 7 received from the pre-decoder circuit 310, and may output a third hit signal HIT 6 / 7. At this time, the bits <3:0> of the third pre-decoded row address PRA 6 / 7 may represent information about the bits <7:6> of the row address RA stored in the second register 520. The bits <3:0> of the third pre-decoded fail row address PFRA 6 / 7 may represent information about the bits <7:6> of the fail row address FRA stored in the first register 510.

[0104] The fourth sub-comparison circuit 534 may compare the corresponding bit values ​​of the bits <3:0> of the fourth predecoded row address PRA8 / 9 received from the predecoder circuit 310 with the corresponding bit values ​​of the bits <3:0> of the fourth predecoded fail row address PFRA8 / 9 received from the predecoder circuit 310, and may output a fourth hit signal HIT 8 / 9. At this time, the bits <3:0> of the fourth predecoded row address PRA 8 / 9 may represent information about the bits <9:8> of the row address RA stored in the second register 520. The bits <3:0> of the fourth predecoded fail row address PFRA 8 / 9 may represent information about the bits <9:8> of the fail row address FRA stored in the first register 510.

[0105] The fifth sub-comparison circuit 535 may compare the corresponding bit values ​​of the bits <3:0> of the fifth pre-decoded row address PRA10 / 11 received from the pre-decoder circuit 310 with the corresponding bit values ​​of the bits <3:0> of the fifth pre-decoded fail row address PFRA 10 / 11 received from the pre-decoder circuit 310, and may output a fifth hit signal HIT 10 / 11. At this time, the bits <3:0> of the fifth pre-decoded row address PRA 10 / 11 may represent information about the bits <11:10> of the row address RA stored in the second register 520. The bits <3:0> of the fifth pre-decoded fail row address PFRA 10 / 11 may represent information about the bits <11:10> of the fail row address FRA stored in the first register 510.

[0106] The sixth sub-comparison circuit 536 may compare the corresponding bit values ​​of the bits <3:0> of the sixth pre-decoded row address PRA 12 / 13 received from the pre-decoder circuit 310 with the corresponding bit values ​​of the bits <3:0> of the sixth pre-decoded fail row address PFRA 12 / 13 received from the pre-decoder circuit 310, and may output a sixth hit signal HIT 12 / 13. At this time, the bits <3:0> of the sixth pre-decoded row address PRA 12 / 13 may represent information about the bits <13:12> of the row address RA stored in the second register 520. The bits <3:0> of the sixth pre-decoded fail row address PFRA 12 / 13 may represent information about the bits <13:12> of the fail row address FRA stored in the first register 510.

[0107] The seventh sub-comparison circuit 537 may compare the corresponding bit values ​​of the bits <3:0> of the seventh predecoded row address PRA 14 / 15 received from the predecoder circuit 310 with the corresponding bit values ​​of the bits <3:0> of the seventh predecoded fail row address PFRA 14 / 15 received from the predecoder circuit 310, and may output a seventh hit signal HIT 14 / 15. At this time, the bits <3:0> of the seventh predecoded row address PRA 14 / 15 may represent information about the bits <15:14> of the row address RA stored in the second register 520. The bits <3:0> of the seventh predecoded fail row address PFRA 14 / 15 may represent information about the bits <15:14> of the fail row address FRA stored in the first register 510.

[0108] When the bit value of the bit <3:0> of the predecoded row address PRA input to one of the first to seventh sub-comparison circuits 531 to 537 and the bit value of the bit <3:0> of the predecoded fail row address PFRA match each other, each of the hit signals HIT 2 / 3 to HIT 14 / 15 of the comparison circuit 330 may be output at a high logic level, and when there is a mismatch between the bit values, each of the hit signals HIT 2 / 3 to HIT 14 / 15 of the comparison circuit 330 may be output at a low logic level. However, the embodiment is not limited thereto. For example, in some other embodiments, when the bit value of bits <3:0> of the predecoded row address PRA input to one of the first sub-comparison circuit 531 to the seventh sub-comparison circuit 537 and the bit value of bits <3:0> of the predecoded fault row address PFRA match each other, each of the hit signals HIT 2 / 3 to HIT 14 / 15 of the comparison circuit 330 can be output at a low logic level, and when there is a mismatch between the bit values, each of the hit signals HIT 2 / 3 to HIT 14 / 15 of the comparison circuit 330 can be output at a high logic level.

[0109] Fig. 8A is a diagram illustrating an equivalent circuit of the first sub-comparison circuit 531 included in the comparison circuit 330 according to some embodiments. Figure 8B is a diagram illustrating the operation of the first sub-comparison circuit 531 according to some embodiments.

[0110] The first sub-comparison circuit 531 may include an inverter circuit (eg, 801a, 801b, 801c, and 801d), a P-type transistor (eg, 802a, 802b, 802c, and 802d), and an N-type transistor (eg, 803a, 803b, 803c, and 803d).

[0111] Reference Fig. 8A The first sub-comparison circuit 531 may include a sixth inverter circuit 801a, a seventh inverter circuit 801b, an eighth inverter circuit 801c, a ninth inverter circuit 801d, a first P-type transistor 802a, a second P-type transistor 802b, a third P-type transistor 802c, a fourth P-type transistor 802d, a first N-type transistor 803a, a second N-type transistor 803b, a third N-type transistor 803c and a fourth N-type transistor 803d.

[0112] The sixth inverter circuit 801a may be connected between the ninth node N81a to which the fifth sub-signal PFRA 2 / 3 0 is applied and the gate terminal of the first P-type transistor 802a. The gate terminal of the first P-type transistor 802a may be connected to the output terminal of the sixth inverter circuit 801a. The first terminal of the first P-type transistor 802a may be connected to the tenth node N82a to which the first sub-signal PRA 2 / 3 0 is applied. The second terminal of the first P-type transistor 802a may be connected to the eleventh node N83 from which the first hit signal HIT 2 / 3 is output. The gate terminal of the first N-type transistor 803a may be connected to the ninth node N81a to which the fifth sub-signal PFRA 2 / 3 0 is applied. The first terminal of the first N-type transistor 803a may be connected to the tenth node N82a to which the first sub-signal PRA 2 / 3 0 is applied. The second terminal of the first N-type transistor 803a may be connected to the eleventh node N83 from which the first hit signal HIT 2 / 3 is output.

[0113] The seventh inverter circuit 801b may be connected between the twelfth node N81b to which the sixth sub-signal PFRA 2 / 3 1 is applied and the gate terminal of the second P-type transistor 802b. The gate terminal of the second P-type transistor 802b may be connected to the output terminal of the seventh inverter circuit 801b. The first terminal of the second P-type transistor 802b may be connected to the thirteenth node N82b to which the second sub-signal PRA 2 / 3 1 is applied. The second terminal of the second P-type transistor 802b may be connected to the eleventh node N83 from which the first hit signal HIT 2 / 3 is output. The gate terminal of the second N-type transistor 803b may be connected to the twelfth node N81b to which the sixth sub-signal PFRA 2 / 3 1 is applied. The first terminal of the second N-type transistor 803b may be connected to the thirteenth node N82b to which the second sub-signal PRA 2 / 3 1 is applied. The second terminal of the second N-type transistor 803b may be connected to the eleventh node N83 from which the first hit signal HIT 2 / 3 is output.

[0114] The eighth inverter circuit 801c may be connected between the fourteenth node N81c to which the seventh sub-signal PFRA 2 / 3 2 is applied and the gate terminal of the third P-type transistor 802c. The gate terminal of the third P-type transistor 802c may be connected to the output terminal of the eighth inverter circuit 801c. The first terminal of the third P-type transistor 802c may be connected to the fifteenth node N82c to which the third sub-signal PRA 2 / 3 2 is applied. The second terminal of the third P-type transistor 802c may be connected to the eleventh node N83 from which the first hit signal HIT 2 / 3 is output. The gate terminal of the third N-type transistor 803c may be connected to the fourteenth node N81c to which the seventh sub-signal PFRA 2 / 3 2 is applied. The first terminal of the third N-type transistor 803c may be connected to the fifteenth node N82c to which the third sub-signal PRA 2 / 3 2 is applied. The second terminal of the third N-type transistor 803c may be connected to the eleventh node N83 from which the first hit signal HIT 2 / 3 is output.

[0115] The ninth inverter circuit 801d may be connected between the sixteenth node N81d to which the eighth sub-signal PFRA 2 / 3 3 is applied and the gate terminal of the fourth P-type transistor 802d. The gate terminal of the fourth P-type transistor 802d may be connected to the output terminal of the ninth inverter circuit 801d. The first terminal of the fourth P-type transistor 802d may be connected to the seventeenth node N82d to which the fourth sub-signal PRA 2 / 3 3 is applied. The second terminal of the fourth P-type transistor 802d may be connected to the eleventh node N83 from which the first hit signal HIT 2 / 3 is output. The gate terminal of the fourth N-type transistor 803d may be connected to the sixteenth node N81d to which the eighth sub-signal PFRA 2 / 3 3 is applied. The first terminal of the fourth N-type transistor 803d may be connected to the seventeenth node N82d to which the fourth sub-signal PRA 2 / 3 3 is applied. The second terminal of the fourth N-type transistor 803d may be connected to the eleventh node N83 from which the first hit signal HIT 2 / 3 is output.

[0116] Figure 8B The bit values ​​of the first hit signal HIT2 / 3 of the first sub-comparison circuit 531 are shown for the bit values ​​of bits <3:0> of the first predecoded row address PRA 2 / 3 and the bit values ​​of bits <3:0> of the first predecoded fail row address PFRA 2 / 3.

[0117] Reference Figure 8B , it can be seen that when all corresponding bit values ​​of bits <3:0> of the first predecoded row address PRA 2 / 3 are the same as the corresponding bit values ​​of bits <3:0> of the first predecoded fail row address PFRA 2 / 3, the bit value of the first hit signal HIT 2 / 3 is 1. It can also be seen that when any one of the corresponding bit values ​​of bits <3:0> of the first predecoded row address PRA 2 / 3 is different from the corresponding bit value among the corresponding bit values ​​of bits <3:0> of the first predecoded fail row address PFRA 2 / 3, the bit value of the first hit signal HIT 2 / 3 is 0.

[0118] Return to reference Figure 5 , the combinational logic circuit 340 may include first to third NAND logic circuits 541 to 543, an OR logic circuit 544, and a first inverter 545. Each of the first to third NAND logic circuits 541 to 543 may receive at least one of the first to seventh hit signals HIT 2 / 3 to HIT 14 / 15 from the comparison circuit 330. The OR logic circuit 544 may output a pre-repair enable signal PRENiB. The first inverter 545 may output a repair enable signal PRENi.

[0119] The first NAND logic circuit 541 may receive the first hit signal HIT 2 / 3, the second hit signal HIT 4 / 5, and the third hit signal HIT 6 / 7. The second NAND logic circuit 542 may receive the fourth hit signal HIT 8 / 9, the fifth hit signal HIT 10 / 11, and the sixth hit signal HIT 12 / 13. The third NAND logic circuit 543 may receive the seventh hit signal HIT14 / 15, the action master signal (ACT master), and the master fuse notification signal PFU. The action master signal and the master fuse notification signal PFU may activate the memory cell, and may be detected by the command and address CA of the test host 112 and the row address RA (for example, refer to Figure 1 ) is received. The NOR logic circuit 544 may receive the corresponding outputs of the first NAND logic circuit 541, the second NAND logic circuit 542, and the third NAND logic circuit 543, and may output a pre-repair enable signal PRENiB. The first inverter 545 may receive the pre-repair enable signal PRENiB, and output a repair enable signal PRENi.

[0120] When all of the first hit signal HIT 2 / 3 to the seventh hit signal HIT 14 / 15 are at a high logic level, the combinational logic circuit 340 may generate a pre-repair enable signal PRENiB at a high logic level and a repair enable signal PRENi at a low logic level. Based on the pre-repair enable signal PRENiB at a high logic level and the repair enable signal PRENi at a low logic level, it may be determined that the first address bit stored in the first register 510 matches the second address bit stored in the second register 520.

[0121] When any one of the first to seventh hit signals HIT 2 / 3 to HIT 14 / 15 is at a low logic level, the combinational logic circuit 340 may generate a pre-repair enable signal PRENiB at a low logic level and a repair enable signal PRENi at a high logic level. Based on the pre-repair enable signal PRENiB at a low logic level and the repair enable signal PRENi at a high logic level, it may be determined that the first address bit stored in the first register 510 does not match the second address bit stored in the second register 520.

[0122] According to some embodiments, the memory device 120 may compare the pre-decoded addresses generated by the pre-decoder circuit 310, and thus, the number of switching lines for inputting addresses may be reduced by the amount of pre-decoding. In addition, the number of hit signals to be output may also be reduced. For example, when Figure 5When the pre-decoder circuit 310 is not provided, the number of hit signals to be output is 14. However, according to some embodiments, the number of hit signals (e.g., HIT 2 / 3 to HIT 14 / 15) to be output is 7 because the memory device 120 compares the pre-decoded addresses generated by the pre-decoder circuit 310.

[0123] According to the present invention, because the number of hit signals to be output is reduced, the number of switching lines related to the hit signal output can also be reduced. As the number of lines is reduced, the related gate load can also be reduced, and therefore, the current required to repair the circuit device can also be reduced.

[0124] According to the inventive concept, due to the reduction of gate load and the reduction of the number of hit signals to be output, the combinatorial logic circuit (eg, Figure 5 The number of logic circuits in the combinatorial logic circuit 340) can be reduced, and therefore, the timing margin associated with the hit signal can be improved.

[0125] Fig. 9 is a flow chart of a method of operating a memory device according to some embodiments.

[0126] Reference Fig. 9 In operation S110, a memory device (eg, a memory device included in the memory device) Figure 5 The predecoder circuit 310 in the memory device may predecode the faulty row address and output a signal representing the predecoded faulty row address. As used herein, "output signal" (or similar language) does not necessarily mean that the signal is output from the memory device, but may refer to the signal being transmitted internally within the memory device by, for example, (one or more) components or (one or more) circuits of the memory device, unless the context clearly indicates otherwise.

[0127] In some embodiments, a memory device (e.g., a memory device included in Figure 5 The pre-decoder circuit 310 in the embodiment may receive N signals each representing one of a plurality of bits representing a failed row address, and may output 2 bits having the same value as the N signals. N One of the bit states corresponds to a bit value of 2 N Here, N is an integer of at least 2 (ie, N is an integer greater than or equal to 2).

[0128] In operation S120, a memory device (eg, a memory device included in the memory device) Figure 5 The predecoder circuit 310 in the embodiment may predecode the row address and output a signal representing the predecoded row address.

[0129] In some embodiments, a memory device (e.g., a memory device included in Figure 5 The pre-decoder circuit 310 in the embodiment may receive N signals each representing one of a plurality of bits representing a row address, and may output 2 bits having the same value as the N signals. N One of the bit states corresponds to a bit value of 2 N Here, N is an integer of at least 2 (ie, N is an integer greater than or equal to 2).

[0130] In operation S130, a memory device (eg, a memory device included in the memory device) Figure 5 The comparison circuit 330 in the memory device may compare the bit value of the pre-decoded fault row address with the bit value of the pre-decoded row address and output a hit signal. Figure 5 The comparison circuit 330 in the example may output a hit signal based on the comparison result.

[0131] In some embodiments, a memory device (e.g., a memory device included in Figure 5 The comparison circuit 330 in the embodiment may be used to represent the 2 pre-decoded row address. N The bit value of the sub-signal is equal to the 2 bits representing the pre-decoded faulty row address. N The bit values ​​of the N bits of the failed row address are compared with the bit values ​​of the N bits of the row address, and a hit signal indicating a match or mismatch between the bit values ​​of the N bits of the failed row address and the bit values ​​of the N bits of the row address is output. Here, N is an integer of at least 2 (i.e., N is an integer greater than or equal to 2).

[0132] In operation S140, a memory device (eg, a memory device included in the memory device) Figure 5 The combinational logic circuit 340 in can output a repair enable signal based on the hit signal.

[0133] In operation S150, the memory device may perform a row repair operation based on the repair enable signal. Here, the row repair operation may refer to an operation of replacing a failed row address with a redundant row address.

[0134] Fig.10 is a block diagram illustrating a system 2000 of an electronic device including a memory device according to some embodiments.

[0135] Reference Fig.10, the system 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memory devices 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor (AP) 2800. The system 2000 may correspond to a laptop computer, a mobile phone, a smart phone, a tablet computer, a personal computer (PC), a wearable device, a health care device, or an Internet of Things (IoT) device, but is not limited thereto. The system 2000 may correspond to a server or a PC.

[0136] The camera 2100 may capture a still image or video under the control of a user, and store or transmit the image / video data to the display 2200. The audio processor 2300 may process the audio data included in the content of the flash memory devices 2600a and 2600b or a network. For wired / wireless data communication, the modem 2400 may modulate a signal, transmit the modulated signal, and demodulate the received signal to restore the original signal. The I / O devices 2700a and 2700b may include devices providing digital input and / or output functions such as a universal serial bus (USB) storage unit, a digital camera, a secure digital (SD) card, a digital versatile disk (DVD), a network adapter, and a touch screen.

[0137] The AP 2800 may generally control the operation of the system 2000. The AP 2800 may include a controller 2810, an accelerator block or an accelerator chip 2820, and an interface 2830. The AP 2800 may control the display 2200 to display some of the contents stored in the flash memory devices 2600a and 2600b. When the AP 2800 receives a user input through the I / O devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may also include an accelerator block, which is a dedicated circuit for artificial intelligence (AI) data operations, or the accelerator chip 2820 may be provided separately from the AP 2800. The DRAM 2500b may be additionally mounted on the accelerator block or the accelerator chip 2820. The accelerator is a functional block that specializes in performing specific functions of the AP 2800, and may include a graphics processing unit (GPU) as a functional block that specializes in performing graphic data processing, a neural processing unit (NPU) as a functional block that specializes in performing AI calculations and inference, and a data processing unit (DPU) as a functional block that specializes in performing data transmission.

[0138] The system 2000 may include a plurality of DRAMs 2500a and 2500b. The AP 2800 may control the DRAMs 2500a and 2500b through command and mode register settings that conform to the Joint Electron Devices Engineering Council (JEDEC) standard, or may set a DRAM interface protocol and communicate with the DRAMs 2500a and 2500b to use the company's unique features such as low voltage, high speed, reliability, and cyclic redundancy check (CRC) functions, and / or error correction code (ECC) functions. For example, the AP 2800 may communicate with the DRAM 2500a through an interface that conforms to the JEDEC standard such as LPDDR4 or LPDDR5, and the accelerator block or accelerator chip 2820 may set a new DRAM interface protocol and communicate with the DRAM 2500b to control the DRAM 2500b, which has a higher bandwidth than the DRAM 2500a relative to the accelerator.

[0139] Despite Fig.10 Only DRAM 2500a and 2500b are shown in the figure, but the embodiment is not limited thereto, and any type of memory that meets the bandwidth, response speed and / or voltage requirements of AP 2800 or accelerator chip 2820, such as PRAM, static RAM (SRAM), MRAM, RRAM, ferroelectric RAM (FRAM), or hybrid RAM, may be used. DRAM 2500a and 2500b may have relatively smaller latency and bandwidth than I / O devices 2700a and 2700b or flash memory devices 2600a and 2600b. DRAM 2500a and 2500b may be initialized when system 2000 is powered on, and may be loaded with an operating system (OS) and application data to be used as a temporary storage unit for the OS and application data, or may be used as a space for executing various software codes.

[0140] Four basic arithmetic operations (i.e., addition, subtraction, multiplication and division), vector operations, address operations or fast Fourier transform (FFT) operations can be performed in DRAM 2500a and 2500b. The functions for the execution of inference can also be performed in DRAM 2500a and 2500b. At this time, inference can be performed during the deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training phase and an inference phase, in which a model is trained using various data, and in the inference phase, data is recognized using a trained model. In some embodiments, the image taken by the user through the camera 2100 may undergo signal processing and may be stored in DRAM 2500b, and the accelerator block or accelerator chip 2820 may perform AI data operations using the data stored in DRAM 2500b and the inference function for recognizing data.

[0141] System 2000 may include multiple storage units or flash memory devices 2600a and 2600b, which have a larger capacity than DRAM 2500a and 2500b. The accelerator block or accelerator chip 2820 may use flash memory devices 2600a and 2600b to perform training phases and AI data operations. In some embodiments, each of the flash memory devices 2600a and 2600b may include a memory controller 2610 and a flash memory 2620, and may allow the AP 2800 and / or the accelerator chip 2820 to use the arithmetic unit included in the memory controller 2610 to effectively perform the training phase and infer AI data operations. Flash memory devices 2600a and 2600b may store images captured by the camera 2100 or data received from a data network. For example, flash memory devices 2600a and 2600b may store augmented and / or virtual reality content, high definition (HD) content, or ultra high definition (UHD) content.

[0142] In system 2000, DRAM 2500a and 2500b can perform the operations already referred to. Figures 1 to 9 The operating method of the memory device described herein may include pre-decoding a faulty row address, generating a signal indicating the pre-decoded faulty row address, pre-decoding a row address, generating a signal indicating the pre-decoded row address, comparing a bit value of the pre-decoded faulty row address with a bit value of the pre-decoded row address, generating a hit signal, generating a repair enable signal based on the hit signal, and performing a repair operation based on the repair enable signal.

[0143] As used herein, the terms "comprise", "include", "contain", "have" and any other variations thereof specify the presence of the features, steps, operations, elements, components and / or groups, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. On the contrary, these terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element.

[0144] While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A method for operating a memory device, the method comprising: outputting a signal representing a pre-decoded failed row address based on pre-decoding the failed row address; outputting a signal representing a pre-decoded row address based on pre-decoding the row address; outputting a hit signal based on comparing a bit value of the pre-decoded failing row address with a bit value of the pre-decoded row address; outputting a repair enable signal based on the hit signal; as well as A row repair operation is performed based on the repair enable signal.

2. The operating method according to claim 1, wherein: Outputting a signal representing the pre-decoded failed row address comprises: receiving N signals, each of the N signals representing one of a plurality of bits of the failed row address, wherein N is an integer greater than or equal to 2; and The output has 2 of the N signals N The bit value corresponding to one of the bit states is 2 N A sub-signal.

3. The operating method according to claim 1, wherein: Outputting a signal representing the pre-decoded row address comprises: receiving N signals, each of the N signals representing one of a plurality of bits of the row address, wherein N is an integer greater than or equal to 2; and The output has 2 of the N signals N The bit value corresponding to one of the bit states is 2 N A sub-signal.

4. The operating method according to claim 1, wherein: Outputting the hit signal includes: The 2 representing the pre-decoded row address N The bit value of the sub-signal is equal to the bit value of the pre-decoded fault row address. N comparing the bit values ​​of the sub-signals; and outputting a hit signal indicating a match or mismatch between the bit values ​​of the N bits of the fault row address and the bit values ​​of the N bits of the row address, Here, N is an integer greater than or equal to 2.

5. A memory device comprising: a memory cell array including redundant memory cells; as well as a repair circuit configured to perform a row repair operation by replacing a failed row address with a redundant row address based on a repair enable signal, Wherein, the repair circuit comprises: a first register configured to store the fault row address; a second register configured to store a row address; and Repair the control circuit, and Wherein, the repair control circuit comprises: a predecoder circuit configured to predecode the failed row address and output a signal representing the predecoded failed row address, and to predecode the row address and output a signal representing the predecoded row address; a comparison circuit configured to compare a bit value of the pre-decoded fail row address with a bit value of the pre-decoded row address and output a hit signal based on a result of the comparison; and A combinatorial logic circuit is configured to output the repair enable signal based on the hit signal.

6. The memory device according to claim 5, wherein: The predecoder circuit includes a first row predecoder circuit configured to: receiving N signals, each of the N signals representing one of a plurality of bits of the row address, wherein N is an integer greater than or equal to 2; and The output has 2 of the N signals N The bit value corresponding to one of the bit states is 2 N A sub-signal.

7. The memory device according to claim 6, wherein: 2 N Only one of the sub-signals has a bit value of 1.

8. The memory device according to claim 5, wherein: The predecoder circuit includes a first row predecoder circuit configured to: receiving a signal representing a first bit of the row address and a signal representing a second bit of the row address, and Four sub-signals indicating bit states of the first bit and the second bit of the row address are output.

9. The memory device according to claim 8, wherein: The bit states represented by the respective bit values ​​of the four sub-signals correspond to a first predecoded row address included in the predecoded row addresses.

10. The memory device according to claim 9, wherein: The first row pre-decoder circuit comprises: a second inverter circuit electrically connected between a first node and a second node, the first node being configured to cause a signal representing the first bit of the row address to be applied to the first node; a third inverter circuit electrically connected between a third node and a fourth node, the third node being configured to cause a signal representing the second bit of the row address to be applied to the third node; a first AND logic circuit electrically connected to the second node, the fourth node, and a first output node, the first output node being configured to output a first sub-signal representing a first bit of the first pre-decoded row address; a second AND logic circuit electrically connected to the first node, the fourth node, and a second output node, the second output node being configured to output a second sub-signal representing a second bit of the first pre-decoded row address; a third AND logic circuit electrically connected to the second node, the third node, and a third output node, the third output node being configured to output a third sub-signal representing a third bit of the first pre-decoded row address; and A fourth AND logic circuit is electrically connected to the first node, the third node and a fourth output node, wherein the fourth output node is configured to output a fourth sub-signal representing a fourth bit of the first pre-decoded row address.

11. The memory device according to claim 5, wherein: The pre-decoder circuit includes a first fuse pre-decoder circuit configured to: receiving N signals, each of the N signals representing one of a plurality of bits of the failed row address, wherein N is an integer greater than or equal to 2; and The output has 2 of the N signals N The bit value corresponding to one of the bit states is 2 N A sub-signal.

12. The memory device according to claim 11, wherein: 2 N Only one of the sub-signals has a bit value of 1.

13. The memory device according to claim 5, wherein: The pre-decoder circuit includes a first fuse pre-decoder circuit configured to: receiving a signal indicating a first bit of the failed row address and a signal indicating a second bit of the failed row address, and Four sub-signals indicating bit states of the first bit and the second bit of the fail row address are output.

14. The memory device according to claim 13, wherein: The bit states represented by the respective bit values ​​of the four sub-signals correspond to a first pre-decoded failing row address included in the pre-decoded failing row addresses.

15. The memory device according to claim 5, wherein: The comparison circuit comprises a first sub-comparison circuit, which is configured as follows: receiving four sub-signals respectively representing bits of a first pre-decoded row address included in the pre-decoded row address and four sub-signals respectively representing bits of a first pre-decoded faulty row address included in the pre-decoded faulty row address, and A first hit signal among the hit signals is output.

16. The memory device of claim 15, wherein: The first sub-comparison circuit includes a sixth inverter circuit, a seventh inverter circuit, an eighth inverter circuit, a ninth inverter circuit, a first P-type transistor, a second P-type transistor, a third P-type transistor, a fourth P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor and a fourth N-type transistor, wherein the four sub-signals respectively representing bits of the first pre-decoded row address include a first sub-signal representing a first bit of the first pre-decoded row address, a second sub-signal representing a second bit of the first pre-decoded row address, a third sub-signal representing a third bit of the first pre-decoded row address, and a fourth sub-signal representing a fourth bit of the first pre-decoded row address, and Among them, the four sub-signals respectively representing the bits of the first predecoded fault row address include a fifth sub-signal representing the first bit of the first predecoded fault row address, a sixth sub-signal representing the second bit of the first predecoded fault row address, a seventh sub-signal representing the third bit of the first predecoded fault row address, and an eighth sub-signal representing the fourth bit of the first predecoded fault row address.

17. The memory device of claim 16, wherein: The sixth inverter circuit is electrically connected between a ninth node and a gate terminal of the first P-type transistor, and the ninth node is configured so that the fifth sub-signal is applied to the ninth node. wherein the gate terminal of the first P-type transistor is electrically connected to the output terminal of the sixth inverter circuit, wherein the first terminal of the first P-type transistor is electrically connected to a tenth node, and the tenth node is configured such that the first sub-signal is applied to the tenth node, wherein the second terminal of the first P-type transistor is electrically connected to an eleventh node, and the eleventh node is configured to output the first hit signal, wherein the gate terminal of the first N-type transistor is electrically connected to the ninth node, wherein the first terminal of the first N-type transistor is electrically connected to the tenth node, and The second terminal of the first N-type transistor is electrically connected to the eleventh node.

18. The memory device according to claim 5, wherein: The combinational logic circuit comprises: a first NAND logic circuit configured to receive a first hit signal, a second hit signal, and a third hit signal among the hit signals; a second NAND logic circuit configured to receive a fourth hit signal, a fifth hit signal, and a sixth hit signal of the hit signals; a third NAND logic circuit configured to receive a seventh hit signal among the hit signals; an NOR logic circuit configured to receive the output of the first NAND logic circuit, the output of the second NAND logic circuit, and the output of the third NAND logic circuit, the NOR logic circuit being further configured to output a pre-repair enable signal; and A first inverter circuit is configured to receive the pre-repair enable signal and output the repair enable signal.

19. A memory system comprising: a host device configured to send commands for a repair operation; as well as a memory device configured to perform the repair operation in response to the command, Wherein, the memory device comprises a repair control circuit, which is configured to: pre-decode the faulty row address and output a signal representing the pre-decoded faulty row address, pre-decodes the row address and outputs a signal representing the pre-decoded row address, comparing the bit value of the pre-decoded failed row address with the bit value of the pre-decoded row address, and outputting a hit signal based on the comparison result, and A repair enable signal is output based on the hit signal.

20. The memory system of claim 19, wherein: The repair control circuit includes a first row pre-decoder circuit configured to: receiving N signals, each of the N signals representing one of a plurality of bits of the row address, wherein N is an integer greater than or equal to 2; and The output has 2 of the N signals N The bit value corresponding to one of the bit states is 2 N A sub-signal.

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