Semiconductor device, integrated circuit device and manufacturing method thereof

Abstract

A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on the semiconductor chip and toward the dielectric substrate. This thermal management method is particularly effective when used in conjunction with buried rail and backside power delivery. The TEC may be located in a layer including a solder connection between two device layers of the IC package. Optionally, the TEC may be located in a metal interconnect structure over the semiconductor substrate, such as in a passivation stack at the top of the metal interconnect structure. The TEC at any of these locations may be formed by wafer level processing. The embodiment of the invention also relates to a semiconductor device, an integrated circuit device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices, integrated circuit devices, and methods for manufacturing the same. Background Art

[0002] As semiconductor technology continues to advance, there is an increasing demand for higher performance devices with smaller form factors. To meet these demands, three-dimensional integrated circuit (3D-IC) technology has become a promising solution. 3D-IC technology allows multiple integrated circuit (IC) layers to be stacked vertically within a single package. This approach provides increased device density and performance while reducing the overall footprint.

[0003] Heat, if not properly managed, can degrade the performance of IC devices, reduce their lifespan, or even cause catastrophic failure. In 3D-IC devices, thermal management becomes even more difficult due to the stacking and close proximity of multiple active layers and interconnects. Existing thermal management techniques for 3D-IC devices include the use of heat sinks, fans, and thermal interface materials (TIMs). Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor device, comprising: a semiconductor substrate having a first side and a second side, wherein the second side is opposite to the first side; a dielectric substrate; and a thermoelectric cooler located between the dielectric substrate and the semiconductor substrate, wherein the thermoelectric cooler is configured to transfer heat from the semiconductor substrate to the dielectric substrate.

[0005] Other embodiments of the present application provide an integrated circuit (IC) device, comprising: a first substrate having a first side and a second side, wherein the second side is opposite to the first side; a solder connection located above the first side; and a thermoelectric cooler located in a layer having the solder connection, such that the thermoelectric cooler is transverse to the solder connection, wherein the thermoelectric cooler is configured to draw heat away from the first substrate.

[0006] Some other embodiments of the present application provide a method for manufacturing an integrated circuit (IC) device, the method comprising: forming a metallization layer over a first side of a substrate; forming a first connection layer over the metallization layer, wherein the first connection layer comprises a first conductive line; depositing a dielectric layer over the first connection layer; patterning a first hole in the dielectric layer; filling the first hole with a first semiconductor having a P-type doping to form a P-type via; patterning a second hole in the dielectric layer; filling the second hole with a second semiconductor having an N-type doping to form an N-type via; performing planarization, wherein the planarization provides a planarized surface, and the planarized surface comprises the dielectric layer, the P-type via, and the N-type via; and forming a second connection layer over the planarized surface, wherein the second connection layer comprises a second conductive line; wherein the first conductive line forms a first connection between the P-type via and the N-type via; and the second conductive line forms a second connection between the P-type via and the N-type via. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, aspects of the disclosed embodiments can be best understood from the following detailed description. According to standard industry practice, the components are not drawn to scale. In addition, the sizes of the individual components within the independent drawings can be arbitrarily increased or reduced relative to each other to facilitate illustration or provide emphasis.

[0008] Figure 1 A cross-sectional view of an apparatus including a 3D integrated circuit (3D-IC) device according to an embodiment of the present disclosure is shown.

[0009] Figure 2 Shows Figure 1 An expanded view of a portion of .

[0010] Figure 3 is a three-dimensional diagram of a thermoelectric cooler (TEC).

[0011] Figure 4 A cross-sectional view of a device having a 3D-IC according to another embodiment is shown.

[0012] Figure 5 Shows Figure 4 An expanded view of a portion of the chip.

[0013] Fig. 6A According to another embodiment Figure 5 Variants of the chip.

[0014] Figure 6B According to another embodiment Figure 5 Variants of the chip.

[0015] Figure 7An apparatus having an IC device according to another embodiment is shown.

[0016] Figure 8 Shows Figure 7 An expanded view of a portion of the chip.

[0017] Fig. 9 According to another embodiment Figure 8 Variants of the chip.

[0018] Fig.10 An apparatus having an IC device according to another embodiment is shown.

[0019] Fig.11 Shows Fig.10 An expanded view of a portion of the chip.

[0020] Fig.12 According to another embodiment Fig.10 Variants of the chip.

[0021] Figures 13 to 42 A process according to some aspects of an embodiment of the present disclosure is shown.

[0022] Figure 43 to Figure 46 According to another embodiment Figures 13 to 42 Variation of the process.

[0023] Fig.47 A wafer according to an embodiment of the present disclosure is shown.

[0024] Fig.48 A die of a wafer is shown according to another embodiment.

[0025] Figures 49 to 51 A process according to another embodiment is shown.

[0026] Figure 52 to Figure 55 Flowcharts of processes according to various embodiments of the present disclosure are provided. DETAILED DESCRIPTION

[0027] The disclosed embodiments provide many different embodiments or examples for realizing the different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0028] Spatial relative terms such as "under ... ", "below ... ", "bottom", "above ... ", "upper" may be used herein to describe the relationship between an element or component as shown in the figure and another (or other) element or component. In addition to the orientation depicted in the figure, these spatial relative terms are intended to include different orientations of the device or apparatus in use or operation. The device or apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. The terms "first", "second", "third", "fourth", etc. are merely general identifiers, and therefore may be interchangeable in various embodiments. For example, although in some embodiments, an element (e.g., an opening) may be referred to as a "first" element, in other embodiments, an element may be referred to as a "second" element.

[0029] A heat sink with a fan or liquid coolant may provide adequate cooling for the IC package as a whole, but may not provide adequate cooling locally. 3D-IC packages are particularly susceptible to this uneven heat distribution and the formation of local hot spots. Some aspects of the disclosed embodiments involve using a thermoelectric cooler (TEC) to extract heat within a device that includes an IC package to address this problem.

[0030] In some embodiments, the TEC is positioned to move heat away from the chip including the semiconductor substrate and toward the dielectric substrate. The dielectric substrate can be a dielectric substrate of an interposer or a carrier substrate. In some embodiments, the dielectric substrate is a substrate of a printed circuit board. Although these dielectric substrates are not generally considered to be heat sinks, they can operate as heat sinks due to their large size compared to the size of a particular hot spot.

[0031] Some aspects of the disclosed embodiments relate to placing a TEC between two substrates in an apparatus including an IC package. The TEC can be configured to draw heat away from the semiconductor substrate and toward the dielectric substrate. In some embodiments, the TEC is located in a metal interconnect structure above the semiconductor substrate. In some embodiments, the TEC is located in a passivation stack at the top of the metal interconnect structure. In some embodiments, the TEC is located between two device layers. In some embodiments, the TEC is located in a layer containing a solder connection. There can be multiple TECs, and two or more of the TECs can be stacked to increase the temperature difference.

[0032] Some aspects of the disclosed embodiments relate to a TEC in a passivation stack disposed at the top of a metal interconnect structure on a chip. The TEC can be integrated into the passivation stack during wafer-level processing. The chip can be packaged so that the passivation stack faces another substrate or device layer. In some embodiments, a bottom thermally conductive dielectric layer is formed under the TEC. The bottom thermally conductive dielectric layer facilitates the transfer of heat to the cold side of the TEC, particularly when the TEC occupies only a portion of the passivation stack area. The TEC may occupy only a portion of the passivation stack area to leave room for other structures (such as vias) in the passivation stack. In some embodiments, a top thermally conductive dielectric layer is formed above the TEC. The top thermally conductive dielectric layer facilitates the diffusion of heat from the top side of the TEC along the interface with the second substrate and then across the interface with the second substrate.

[0033] Some aspects of the disclosed embodiments relate to a TEC disposed within a layer comprising a solder connection between two substrates. It has been found that these solder connection layers can be a significant barrier to heat transfer. In some embodiments, the TEC is disposed between solder bumps. The solder bumps can be located in an array. In some embodiments, the array is a ball grid array (BGA). In some embodiments, the solder bumps are located in a controlled collapse chip connection (C4) array. For BGA, the TEC is placed during packaging. For a C4 array, the TEC can be formed during wafer level processing.

[0034] Some aspects of the disclosed embodiments relate to an IC device in which a semiconductor device on the front side of a semiconductor substrate is supplied with power from the back side of the semiconductor substrate. A buried rail may be provided on the front side so that the power does not need to be routed through the front side metal interconnect structure. The buried rail may receive power from the power rail on the back side by way of a through substrate via (TSV). The TEC is positioned to draw heat away from the back side. In some embodiments, the TEC is located in a passivation stack at the top of the back side metal interconnect structure. In some embodiments, the TEC is located within a solder-connected layer on the back side. In many applications, providing power from the back side combined with a TEC that draws heat away from the back side provides an effective solution for thermal management.

[0035] Some aspects of the disclosed embodiments relate to a method for manufacturing an IC device having a TEC. The method begins with front-end-of-line (FEOL) processing of a semiconductor substrate. A plurality of metallization layers are then formed over one side or the other of the semiconductor substrate. A first connection layer including a first wire is formed over the uppermost metallization layer of the plurality of metallization layers. A dielectric layer is then formed over the first connection layer. A first through hole having a P-type doped semiconductor and a second through hole having an N-type doped semiconductor are formed in the dielectric layer. A second connection layer including a second wire is then formed. The first wire and the second wire connect the group of the first through hole and the second through hole in series, thereby forming one or more TECs.

[0036] In some embodiments, a bottom thermally conductive dielectric layer is formed immediately before the first connection layer. In some embodiments, the first connection layer includes a thermally conductive dielectric between the first wires. In some embodiments, the second connection layer includes a thermally conductive dielectric between the second wires. In some embodiments, a top thermally conductive dielectric layer is formed immediately after the second connection layer.

[0037] In some embodiments, the TEC is formed on the pad layer. The first dielectric is etched around the TEC to form an opening, and solder bumps are deposited in the opening. In some embodiments, the semiconductor substrate is a wafer cut after the solder bumps are deposited. Each die may contain one or more of the TECs.

[0038] Figure 1 An apparatus 100 having a 3D-IC device 101 according to some embodiments is shown. The 3D-IC device is mounted to a printed circuit board 147. The 3D-IC device 101 has a plurality of device layers including a first wiring layer 139, a first chip 135, a second wiring layer 133, a second chip 131, and a third chip 129. The printed circuit board 147 and each of these device layers include a substrate. The printed circuit board 147 includes a board substrate 148. The first wiring layer 139 includes a first packaging substrate 141. The first chip 135 includes a first semiconductor substrate 121. The second wiring layer 133 includes a second packaging substrate 134. The second chip 131 includes a second semiconductor substrate 132. The third chip 129 includes a third semiconductor substrate 130. A high thermal conductivity underfill 137 may fill the space between the second wiring layer 133 and the first chip 135.

[0039] The first packaging substrate 141, the second packaging substrate 134 and the board substrate 148 are dielectric substrates. The dielectric substrate may be, for example, an organic polymer substrate or some other suitable dielectric material. Examples of organic polymer substrate materials include, but are not limited to, polyimide, polytetrafluoroethylene, epoxy resin, etc. The epoxy resin may be a material formed of bismaleimide-triazine resin (BT-resin), some other epoxy resin resin, etc. The dielectric substrate may be a laminate and may be reinforced with glass cloth, glass fiber, etc.

[0040] The hot spot 117 may tend to form in the first chip 135 in a region near the front side 126 of the first semiconductor substrate 121 or within the metal interconnect structure 125 on the front side 126. Heat movement upward from the hot spot 117 may be suppressed by one or more of the following structures: the first semiconductor substrate 121, the high thermal conductivity underfill 137, the second wiring layer 133, the second chip 131, and the third chip 129. Heat movement in this direction may be further suppressed by heat generation in the second chip 131 and the third chip 129.

[0041] According to an embodiment of the present disclosure, the primary path 115 for removing heat from the hot spot 117 is down to the printed circuit board 147. To reach the printed circuit board 147, the heat passes through the first wiring layer 139 and the solder connection layer 145. The solder connection layer 145 includes solder bumps 157 that form a ball grid array (BGA). The solder connection layer 145 may also include thermal paste 143.

[0042] According to an embodiment of the present disclosure, a TEC 163 is disposed in the path 115 to drive heat transfer from the hot spot 117 to the printed circuit board 147. In some embodiments, the TEC 163 is disposed in the solder connection layer 145. When power is provided, the TEC 163 transfers heat from the cold side 160 facing the hot spot 117 to the hot side facing the printed circuit board 147. Thus, the cold side 160 can be cooled. In some embodiments, the cold side 160 is cooled below the ambient temperature.

[0043] Figure 2 Provides a rough correspondence to Figure 1 200 is a cross-sectional view of a region 200A in FIG. The region 200A is located around and includes the TEC 163. Figure 2 As shown in FIG. 1 , TEC 163 includes a bottom dielectric layer 237, a first conductive line 233 in a first wiring layer 229, an N-type via 225 and a P-type via 221, an oxide layer 241, a second conductive line 213 in a second wiring layer 217, and a top dielectric layer 205. The N-type via 225 and the P-type via 221 are semiconductors having a P-type doping and an N-type doping, respectively.

[0044] Figure 3 A perspective view of the TEC 163 is shown with the oxide layer 241 cut away and the top dielectric layer 205 shown in outline. Figure 3 As can be seen in FIG. 1 , the first wire 233 and the second wire 213 connect the group of N-type vias 225, and the P-type vias 221 are connected in series between the first electrode 209 and the second electrode 251. When current flows from the first electrode 209 to the second electrode 251, it flows from the N-type vias 225 to the P-type vias 221 on the cold side 160. The charge carriers passing between the N-type vias 225 and the P-type vias 221 absorb heat to produce a cooling effect. The charge carriers pass between the P-type vias 221 on the hot side 168 to the N-type vias 225, releasing the absorbed heat. The holes in the N-type vias 225 and the electrons in the P-type vias 221 transfer heat from the cold side 160 to the hot side 168.

[0045] In some embodiments, one or both of the bottom dielectric layer 237 and the top dielectric layer 205 are high thermal conductivity dielectrics. In the disclosed embodiments, the high thermal conductivity dielectric has a thermal conductivity of at least about 10 W / mK. In contrast, silicon dioxide (SiO2) has a thermal conductivity ranging from about 1.1 W / mK to about 1.4 W / mK. Crystalline silicon nitride (Si3N4) is an example of a high thermal conductivity dielectric and can have a thermal conductivity of up to 29 W / mK. Silicon nitride (Si3N4) commonly found in semiconductor devices is amorphous and has a thermal conductivity ranging from about 2 W / mK to about 5 W / mK. An amorphous form is usually produced because it is inherently suitable for higher deposition rates than a crystalline form. In addition, a dielectric constant lower than that of an amorphous form is usually pursued. Thermal conductivity can vary continuously between a pure amorphous form and a pure crystalline form with crystallinity.

[0046] In some embodiments, one or both of the bottom dielectric layer 237 and the top dielectric layer 205 are extremely high thermal conductivity dielectrics. Extremely high thermal conductivity dielectrics have a thermal conductivity higher than that of pure crystalline silicon nitride (Si3N4), in other words, higher than 29W / mK. In some embodiments, extremely high thermal conductivity dielectrics have a thermal conductivity of at least about 100W / mK. Examples of dielectrics having a thermal conductivity of about 100W / mK or greater include, but are not limited to, aluminum nitride (AlN), crystalline boron nitride (BN), crystalline boron phosphide (BP), crystalline boron arsenide (BAs), hexagonal boron nitride (hBN), graphene, diamond, and the like. In these examples, aluminum nitride (AlN), boron nitride (BN), boron phosphide (BP), boron arsenide (BAs) have an amorphous form, a crystalline form, and an intermediate crystalline form. The form with sufficient crystallinity is an extremely high thermal conductivity dielectric. With respect to hexagonal compounds including hexagonal boron nitride (hBN) and graphene, the thermal conductivity depends on the form. The lateral form (sheet) generally provides the highest thermal conductivity. In some embodiments, the very high thermal conductivity dielectric has a thermal conductivity of at least about 1000 W / mK or greater. This can be achieved, for example, with boron arsenide (BAs), one of the carbon-based dielectrics described above, etc. These very high thermal conductivity dielectrics are particularly useful for lateral heat dissipation using only a thin layer.

[0047] Back to Figure 1, the TEC 163 may be coupled to the first wiring layer 139 by solder microbumps 161 or the like. Passive devices 171 may also be provided at the level of the solder bumps 157 and coupled to the first wiring layer 139. Alternatively, the TEC 163 may be coupled to the first wiring layer 139 by direct connection between contact pads, in which case the TEC 163 may be bonded to the first wiring layer 139 by metal-to-metal bonding, dielectric-to-dielectric bonding, or a combination of metal-to-metal and dielectric-to-dielectric bonding. Thermal paste 165 is applied to the hot side 168 to ensure good thermal contact with the printed circuit board 147.

[0048] In some embodiments, the TEC 163 is powered from the cold side 160, which in this example means that the power comes from the first wiring layer 139. Powering from the cold side 160 facilitates manufacturing. In some other embodiments, the TEC 163 is powered from the hot side 168. Powering from the hot side 168 can keep some of the heat generated when powering the TEC 163 away from the hot spot 117. Power from the printed circuit board 147 or other device layer on the hot side 168 can be provided through the bonding pads 166.

[0049] refer to Figure 2 In some embodiments, a bonding pad 166 or similar metal structure is disposed in the printed circuit board 147 adjacent to the hot side 168 without being electrically connected to the TEC 163. Such a metal structure can facilitate heat extraction from the hot side 168. Likewise, in some embodiments, a bonding pad 261 or similar metal structure that is not required for wiring or bonding is disposed in the first wiring layer 139 or similar device layer adjacent to the cold side 160 to facilitate heat transfer to the cold side 160. A thermal paste 263 can be provided between the solder microbumps 161 to facilitate heat transfer.

[0050] Figure 4 An apparatus 400 including a 3D-IC device 401 according to another embodiment is shown. The 3D-IC device 401 is similar to Figure 1 3D-IC device 101 is different in that 3D-IC device 401 has one or more TEC 463 instead of TEC 163. TEC 463 and TEC 163 are similar in structure, but are located in different positions. The difference in position may determine the difference in size and power connection. TEC 463 is set in the metal interconnect structure 125 on the first chip 135.

[0051] Figure 5 It shows that it can correspond to Figure 4 FIG. 5 is a cross-sectional view of a chip 500 of a first chip 135 in a 3D-IC device 401. Figure 5As shown in , the chip 500 includes a metal interconnect structure 125 above a first semiconductor substrate 121. A semiconductor device 563 is formed on the first semiconductor substrate 121. The semiconductor device 563 may include a transistor (such as a complementary metal oxide field effect transistor (MOSFET), a fin field effect transistor (finFET), etc.), a diode, a capacitor, a memory cell, a thyristor, a resistor, etc., or any combination thereof. The metal interconnect structure 125 includes a plurality of metallization layers 501, including an uppermost metallization layer 501u and a plurality of via layers 503. The metallization layer 501 includes a conductive line 555, and the via layer 503 includes a via 559. The TEC 463 is disposed above the uppermost metallization layer 501u.

[0052] The first contact pad 517 and the second contact pad 525 are located on top of the passivation stack 509. The first via 507 passes through the passivation stack 509 to couple the first contact pad 517 to the first conductive line 505 in the uppermost metallization layer 501u. The second via 543 passes through the passivation stack 509 to couple the second contact pad 525 to the second conductive line 553 in the uppermost metallization layer 501u.

[0053] TEC 463 is disposed in passivation stack 509. TEC 463 includes first electrode 510 and second electrode 537, which may be wiring in second wiring layer 217. Third via 511 couples first contact pad 517 to first electrode 510. Fourth via 527 couples second contact pad 525 to second electrode 537.

[0054] The passivation stack 509 is a dielectric structure that may include various layers, for example, a lower etch stop layer 551, a lower thermally conductive dielectric layer 547, an oxide layer 241, an upper etch stop layer 539, and a barrier layer 535. The lower etch stop layer 551 and the upper etch stop layer 539 are optional, and each may be a material such as silicon nitride (SiN), silicon carbide (SIC), silicon carbonitride (SICN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), combinations thereof, and the like. The lower thermally conductive dielectric layer 547 is also optional. The lower thermally conductive dielectric layer 547 may be a high thermal conductivity dielectric or an extremely high thermal conductivity dielectric.

[0055] The oxide layer 241 is a dielectric that provides electrical insulation between the N-type via 225 and the P-type via 221 of the TEC 463 and between the chip 500 and the external environment. In some embodiments, the oxide layer 241 is silicon dioxide (SiO2). In some embodiments, the oxide layer 241 is a low-k dielectric, such as can be used as an interlayer dielectric 557 in the metal interconnect structure 125. The low-k dielectric can be, for example, an organic silicate glass (OSG), such as carbon-doped silicon dioxide, fluorinated quartz glass (FSG), porous silicate glass, etc.

[0056] In some embodiments, barrier layer 535 is a high thermal conductivity dielectric. In some embodiments, barrier layer 535 is silicon nitride (Si3N4) or the like. Silicon nitride (Si3N4) provides better moisture resistance and has greater mechanical strength than silicon dioxide (SiO2). If an upper etch stop layer 539 is provided, it has a different composition than barrier layer 535. In some embodiments, barrier layer 535 is an extremely high thermal conductivity dielectric. Barrier layer 535 (and lower thermally conductive dielectric layer 547, if also included)) can extend over an area larger than TEC 463.

[0057] In some embodiments, the passivation stack 509 has a thickness in a range from about 0.5 μm to about 3 μm. In some embodiments, the passivation stack 509 has a thickness in a range from about 1.9 μm to about 2.2 μm. In some embodiments, the etch stop layer 551 has a thickness in a range from about 5 nm to about 50 nm. In some embodiments, the barrier layer 535 has a thickness of at least about 0.2 μm. The barrier layer 535 is much thicker than any etch stop layer in the metal interconnect structure 125.

[0058] The height H1 of the N-type via 225 and the P-type via 221 in the TEC 463 and other TECs according to the embodiments of the present disclosure is a design parameter that can be adjusted to improve performance. In some embodiments, the height H1 is at least about 0.3 μm. In some embodiments, the height H1 is at least about 1 μm. In some embodiments, the thickness of the oxide layer 241 is equal to the height H2 of the TEC 463. The height H2 of the TEC 463 is equal to the height H1 plus the thickness of the first wiring layer 229 and the second wiring layer 217. In some embodiments, the oxide layer 241 is made thicker than the height H2 to provide greater electrical insulation. In some embodiments, the TEC 463 is completely located within the passivation stack 509, so that the height of the TEC 463 is limited by the thickness of the passivation stack 509. In some embodiments, the TEC 463 extends downward into the metal interconnect structure 125. Extending the TEC 463 downward into the metal interconnect structure 125 allows the height H1 to be made greater than the thickness of the passivation stack 509.

[0059] The width W1 of the N-type via 225, the width W2 of the P-type via 221, and the pitch P1 between the N-type via 225 and the P-type via 221 are also design parameters that can be adjusted to improve performance. In some embodiments, the width W1 and / or the width W2 are in a range from about 1 μm to about 100 μm. In some embodiments, the width W1 and / or the width W2 are in a range from about 5 μm to about 50 μm. In some embodiments, the pitch P1 and / or the width W2 are in a range from about 0.1 μm to about 10 μm.

[0060] The first contact pad 517 and the second contact pad 525 are located in the bonding layer 513 above the passivation stack 509. The dielectric 521 of the bonding layer 513 surrounds and isolates the first contact pad 517 and the second contact pad 525. In some embodiments, the dielectric 521 is a high thermal conductivity dielectric. In some embodiments, the dielectric 521 is an extremely high thermal conductivity dielectric.

[0061] Fig. 6A shows a cross-sectional view of a chip 600, which may correspond to Figure 4 Another chip of the first chip 135 in the 3D-IC device 401. The chip 600 may be similar to Figure 5 The difference is that the chip 600 has a TEC 663 instead of a TEC 463. The TEC 663 is similar to Figure 5 TEC 463, except that, in TEC 663, first electrode 510 extends laterally so that first through hole 507 passes through and contacts first electrode 510. Similarly, second electrode 537 extends laterally so that second through hole 531 passes through and contacts second electrode 537. This allows the third through hole 511 to be omitted (see Figure 5 ), fourth through hole 527 and upper etch stop layer 539. Chip 600 may be larger than Figure 5 The chip 500 is easier to manufacture.

[0062] Figure 6B shows a cross-sectional view of a chip 620, which may correspond to Figure 4 Another chip of the first chip 135 in the 3D-IC device 401. The chip 620 is similar to Figure 5 663B. Any of the embodiments of the present disclosure may be modified to include vertically stacked TECs. Vertically stacking TECs may allow for a greater temperature difference to be generated between the hot side and the cold side. A high thermal conductivity dielectric layer 601 may be provided between adjacent TECs in the stack. In some embodiments, an extremely high thermal conductivity dielectric is provided between the vertically stacked TECs.

[0063] Figure 7 An apparatus 700 including an IC device 701 according to another embodiment is shown. The IC device 701 is attached to a printed circuit board 147. The IC device 701 has multiple device layers including a wiring layer 763 and a chip 769. The chip 769 includes a semiconductor substrate 747, a carrier substrate 709, a front side metal interconnect structure 737 located between the semiconductor substrate 747 and the carrier substrate 709, and a back side metal interconnect structure 751 located on an opposite side of the semiconductor substrate 747. The wiring layer 763 includes a dielectric substrate 759. A C4 connection layer 755 couples the chip 769 to the wiring layer 763. The solder connection layer 145 couples the wiring layer 763 to the printed circuit board 147.

[0064] V SS Rail 723 and V DD The rails 727 are disposed in the backside metal interconnect structure 751. One or more TECs 463 are disposed in the backside metal interconnect structure 751 and are positioned to facilitate heat transfer from hot spots to the printed circuit board 147, which may be connected to the V SS Rail 723 or V DD Rail 727 or by V SS Rail 723 or V DD The TEC 463 is provided in the backside metal interconnect structure 751 and is configured to draw heat in a direction opposite to the lid 703.

[0065] Figure 8 It shows that it can correspond to Figure 7 8 is a cross-sectional view of a chip 800 of a chip 769. The chip 800 includes a semiconductor substrate 747, a carrier substrate 709, a front side metal interconnect structure 737, and a back side metal interconnect structure 751. A semiconductor device such as a FinFET 801 may be disposed on a front side 825 of the semiconductor substrate 747. SS Rail 723 and V DD Rail 727 is disposed in a backside metal interconnect structure 751, which is located on the backside 821 of semiconductor substrate 747. Buried rail 803 is disposed near front side 825. FinFET 801 is powered by buried rail 803. Buried rail 803 is in turn powered by V SS Rail 723 and V DD Rail 727 supplies power. Buried rail 803 is connected to V SS Rail 723 and V DD Track 727.

[0066] TEC 463 is disposed in passivation stack 811, which is the outermost portion of backside metal interconnect structure 751. TEC 463 may be coupled to C4 solder bump 809 via contact pad 807. The structure, surrounding structure, and connections of TEC 463 may be as shown. Figure 5 The same as in chip 500, or Fig. 6A The chip 600 is in the way of the TEC 663.

[0067] Fig. 9 shows a cross-sectional view of a chip 900, which may correspond to Figure 7 Another chip of chip 769. Chip 900 is similar to Figure 8 The chip 800 is different in that, in the chip 900, the dielectric 901 of the first wiring layer 229 and the dielectric 903 of the second wiring layer 217 have different compositions from the oxide layer 241. In some embodiments, one or both of the dielectric 901 and the dielectric 903 are high thermal conductivity dielectrics. In some embodiments, one or both of the dielectric 901 and the dielectric 903 are extremely high thermal conductivity dielectrics.

[0068] Fig.10 An apparatus 1000 including an IC device 1001 according to another embodiment is shown. The IC device 1001 is similar to Figure 7 1, except that instead of having a TEC 463 disposed in the backside metal interconnect structure 751, the IC device 1001 has a TEC 463 in the C4 connection layer 755. Optionally, there may be a TEC 463 in these locations and also in the solder connection layer 145.

[0069] Fig.11 It shows that it can correspond to Fig.10 FIG. 1 is a cross-sectional view of chip 1100 of chip 769 in IC device 1001. Fig.11 As shown in FIG. 1 , the first electrode 1113 and the second electrode 1103 of the TEC 463 may be disposed between the first C4 solder bump 809A and the second C4 solder bump 809B in the C4 connection layer 755. In the chip 1100, the TEC 463 has a high thermal conductivity dielectric 1107 on the hot side 168 opposite the backside metal interconnect structure 751. The first C4 solder bump 809A and the first electrode 1113 may both abut the first contact pad 1115, and the second C4 solder bump 809B and the second electrode 1101 may both abut the second electrode 1103, whereby the TEC 463 may be powered through the first C4 solder bump 809A and the second C4 solder bump 809B.

[0070] Fig.12shows a cross-sectional view of a chip 1200, which may correspond to Fig.10 Another chip of chip 769 in IC device 1000. In chip 1200, TEC 463 is connected to V in backside metal interconnect structure 751. SS Rail 723 and V DD Rail 727 draws power.

[0071] Figures 13 to 42 A series of cross-sectional views 1300-4200 are provided showing an integrated circuit device according to an embodiment of the present disclosure at various stages of fabrication according to a process according to some embodiments. Figures 13 to 42 , but it should be understood that in some cases, the order of the steps can be changed and that this series of steps is applicable to structures other than the structure shown. In some embodiments, some of these steps can be omitted in whole or in part. In addition, with respect to a series of steps described Figures 13 to 42 , should understand, Figures 13 to 42 The structure shown in is not limited to the manufacturing method, but can exist independently as a structure independent of the method.

[0072] like Fig.13 As shown in the cross-sectional view 1300 of , the process can start with forming semiconductor fins 1301 on the front side 825 of the semiconductor substrate 747. The dielectric 1303 fills the gaps between the semiconductor fins 1301. The semiconductor substrate 747 can be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate. At least the upper portion of the semiconductor substrate 747 is a semiconductor. The semiconductor can be silicon (Si), a III-V semiconductor (e.g., GaAs) or some other binary semiconductor, a ternary semiconductor (e.g., AlGaAs), a higher order semiconductor, etc., or any other suitable semiconductor. In some embodiments, the bulk semiconductor is silicon (Si) or the like. The semiconductor fins 1301 can be different types of semiconductors epitaxially grown on the front side 825. The dielectric 1303 can be silicon dioxide (SiO2) or the like or some other suitable dielectric.

[0073] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1400 , the process can continue to form a mask 1401 and etch to form a trench 1403. The trench 1403 passes through the dielectric 1303 and extends into the semiconductor substrate 747 below the semiconductor fin 1301. The mask 1401 and other masks used in the process of the disclosed embodiment can be or include photoresist, hard mask, a combination thereof, etc. The mask 1401 and other masks used in the process can be patterned by photolithography, ion beam lithography, etc., or some other suitable process. The etching process can be dry etching such as plasma etching, etc., or some other suitable etching process. After the etching process, the mask 1401 can be stripped.

[0074] like Fig.15 As shown in the cross-sectional view 1500 of , metal can be deposited to fill the trench 1403 and form a buried rail 803. The buried rail 803 can be isolated from the semiconductor substrate by a dielectric liner (not shown). The metal is selected for its ability to withstand front-end process (FEOL) processing and its low sensitivity to electromigration. The metal can be, for example, ruthenium (Ru), tungsten (W), molybdenum (Mo), a combination thereof, or an alloy thereof. The metal can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, chemical plating, etc., or any other suitable process. Excess metal can be removed by a planarization process. The planarization process can be, for example, chemical mechanical polishing (CMP), etc., or any other suitable process.

[0075] like Fig.16 As shown in the cross-sectional view 1600 of , an etching process is performed to recess the buried rail 803. The etching process can reduce or eliminate the need for a planarization process to remove excess metal. The etching process can be a dry etching process or a wet etching process.

[0076] like Fig.17 As shown in the cross-sectional view 1700 of , FEOL processing can be completed after the buried rail 803 is formed. FEOL processing can form finFET 801, which includes a gate electrode 1707 above the semiconductor fin 1301. FEOL processing can also or alternatively form other semiconductor devices on the front side 825. FEOL processing includes forming transistor-level metal interconnects 1711. Transistor-level metal interconnects 1711 include vias 1701 that contact the buried rail 803, vias 1703 that contact the gate electrode 1707, and wires 1709. Some of the wires 1709 can couple the buried rail 803 to the gate electrode 1707. Other wires 1709 (not shown) can couple the source / drain regions (not shown) of the finFET 801 to the buried rail 803. Subsequent processing will provide TSV 733 (see Figure 7 ), buried rail 803 is connected to a power source through TSV 733. In this way, buried rail 803 allows finFET 801 to be powered from back side 821, thereby reducing heat generated on front side 825 by IR losses.

[0077] like Fig.18As shown in the cross-sectional view 1800 of FIG. 1 , a back-end-of-line (BEOL) process may be performed to form a front-side metal interconnect structure 737 above the transistor-level metal interconnect 1711. The front-side metal interconnect structure 737 includes a plurality of metallization layers 813 and a plurality of via layers 815. The via layers 815 are disposed between adjacent pairs of the metallization layers 813. The metallization layers 813 include conductive lines 1803, and the via layers 815 include vias 1805. An interlayer dielectric 1801 fills the region between the conductive lines 1803 and the vias 1805. A via etch stop layer 1807 may be formed at the base of each via layer 815, and a conductive line etch stop layer 1809 may be formed at the base of each metallization layer 813. The front-side metal interconnect structure 737 may be formed by a damascene process, a dual damascene process, or any other suitable type of process.

[0078] Wire 1803 and via 1805 include conductive materials such as metals. Metals may be, for example, copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys of these metals, and the like. Interlayer dielectric 1801 may be silicon dioxide (SiO2), etc., low-k dielectrics or very low-k dielectrics. Low-k dielectrics have a lower dielectric constant than silicon dioxide (SiO2). Examples of low-k dielectrics include organic silicate glass (OSG), such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also referred to as fluorinated quartz glass (FSG)), organic polymer low-k dielectrics, and porous silicate glass. Very low-k dielectrics are materials having a dielectric constant of about 2.1 or less. Very low-k dielectric materials are typically low-k dielectric materials formed into a porous structure. Porosity reduces the effective dielectric constant. The via etch stop layer 1807 and the wire etch stop layer 1809 may have the same or different compositions, and each may include one or more layers of silicon nitride (SiN), silicon carbide (SIC), silicon carbonitride (SICN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), combinations thereof, or the like.

[0079] like Fig.19 As shown in the cross-sectional view 1900, Fig.18 The partially fabricated device shown in cross-sectional view 1800 may be bonded to a carrier substrate 709 via a bonding layer 714. The carrier substrate 709 may be a dielectric substrate or any other suitable type of substrate. The bonding layer 714 may be any suitable type of bonding material.

[0080] like Fig. 20As shown in the cross-sectional view 2000 of , after being bonded to the carrier substrate 709, the semiconductor substrate 747 can be thinned from the back side 821. In some embodiments, the semiconductor substrate 747 is thinned to about 50 microns or less. In some embodiments, the semiconductor substrate 747 is thinned to about 5 microns or less. In some embodiments, the semiconductor substrate 747 is thinned to about 1 micron or less. The thinner the semiconductor substrate 747, the lower the heat generation rate. The thinning can include grinding, polishing, CMP, etc. or any other suitable process.

[0081] like Fig.21 As shown in the cross-sectional view 2100 of , a dielectric layer 2101 and a mask 2103 are formed on the back side 821. The mask 2103 is used to etch a hole 2105 through which the buried rail 803 is exposed.

[0082] like Fig. 22 As shown in the cross-sectional view 2200 of FIG. 2105 , a TSV 733 is formed in the hole 2105. Forming the TSV 733 may include: depositing a dielectric liner (not shown); etching to break through the liner at the bottom of the hole 2105; depositing a conductive material to fill the hole 2105; and planarizing to remove excess conductor. In some embodiments, the conductive material is a metal. Examples of metals that may be suitable include copper (Cu), tungsten (W), aluminum (Al), combinations thereof, and the like. The metal may be deposited by PVD, CVD, ALD, electroplating, chemical plating, and the like, or any other suitable process.

[0083] like Fig.23 As shown in the cross-sectional view 2300 of FIG. 23, a backside metal interconnect structure 751 is formed on the backside 821. The backside metal interconnect structure 751 includes a plurality of metallization layers 2313 and a plurality of via layers 2315. The metallization layer 2313 includes a conductive line 2303, wherein V SS Rail 723 and V DD Track 727. Via layer 2315 includes vias 2305. Interlayer dielectric 2301 fills the area between conductive line 2303 and via 2305. A via etch stop layer 2307 may be formed at the base of each via layer 2315, and a conductive line etch stop layer 2309 may be formed at the base of each metallization layer 2313. Backside metal interconnect structure 751 may be formed using the same type of methods and materials as frontside metal interconnect structure 737.

[0084] like Fig.24As shown in the cross-sectional view 2400 of FIG. 2401 , several layers may be formed above the uppermost metallization layer 2313u of the backside metal interconnect structure 751. Several layers may include a lower etch stop layer 551, a lower thermally conductive dielectric layer 547, and a dielectric 901. Each of the lower etch stop layer 551 and the lower thermally conductive dielectric layer 547 is optional. The lower thermally conductive dielectric layer 547 may be a high thermal conductivity dielectric layer or an extremely high thermal conductivity dielectric layer. The dielectric 901 may be a conventional dielectric, such as silicon dioxide (SiO2), a high thermal conductivity dielectric layer, or an extremely high thermal conductivity dielectric layer. Each of these layers may be deposited by PVD, CVD, ALD, etc., or any other suitable process.

[0085] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 25, a mask 2501 for etching a trench 2503 in the dielectric 901 may be formed. After etching, the mask 2501 may be stripped. Fig.26 As shown in the cross-sectional view 2600 of , the groove 2503 can then be filled to form the first wire 233. The first wire 233 can be a metal or some other conductive material. The metal can be, for example, copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbide, oxide, alloys of these metals, etc. The metal can be deposited by PVD, CVD, ALD, electroplating, chemical plating, etc. or any other suitable process. Excess metal can be removed by a planarization process. The planarization process can be CVD, etc. or any other suitable process. The dielectric 901 and the first wire 233 constitute the first wiring layer 229.

[0086] like Fig. 27 As shown in the cross-sectional view 2700 of FIG. 27 , an oxide layer 241 is deposited over the first wiring layer 229. The oxide layer 241 may be silicon dioxide (SiO2), a low-k dielectric, or an ultra-low-k dielectric. The oxide layer 241 may be deposited by CVD, PVD, ALD, etc., or any other suitable process.

[0087] like Fig.28 As shown in the cross-sectional view 2800 of FIG. 28, a mask 2801 is formed for etching a first hole 2803 through the oxide layer 241. The first conductive line 233 is exposed at the bottom of the first hole 2803. The etching process may be dry etching such as plasma etching or any other suitable process. After etching, the mask 2801 may be stripped.

[0088] like Fig.29As shown in the cross-sectional view 2900 of FIG. 29 , the first hole 2803 is filled with a semiconductor material having a high thermoelectric quality factor and N-type doping to form an N-type through hole 225. A high thermoelectric quality factor is 1.0 or greater. The greater the thermoelectric quality factor, the greater the efficiency of the resulting thermoelectric cooler. Examples of semiconductor materials having a high thermoelectric coefficient include bismuth telluride-based compounds (BiTe-), antimony telluride-based compounds (SbTe-), antimony telluride-based compounds (Bi 2-y Sb y Te-), lead telluride (PbTe), silicon germanium (SiGe), skutterudite compounds, zinc antimonide (Zn3Sb3), germanium telluride (GeTe), half-Heusler compounds, etc., and other semiconductor materials. Examples of bismuth telluride-based compounds include Bi2(Te x Se 1-x )3, etc. Examples of antimony telluride-based compounds include Sb2(Te x Se 1-x )3, etc. Examples of antimony telluride bismuth-based compounds include Bi 2-y Sb y (Te x Se 1-x )3, etc. In these molecular formulas, x and y can independently have any value from 0 to 1. Examples of skutterudite compounds include cobalt antimonide (CoSb3), etc. Examples of half-Heusler compounds include hafnium nickel tin (HfNiSn), zirconium nickel tin (ZrNiSn), etc. N-type dopants can be, for example, phosphorus (P), arsenic (As), antimony (Sb), etc. The semiconductor material can be deposited by sintering, CVD, PVD, ALD, pulsed laser deposition (PLD), etc., or any other suitable process. In some embodiments, the process is PLD for low temperature compatibility. Excess semiconductor material can be removed by a planarization process such as CMP.

[0089] In some embodiments, the semiconductor material includes nanostructures that increase the thermoelectric quality factor. Using nanostructures, the thermoelectric quality factor can be increased to 2.0 or greater. Examples of nanostructures include quantum dots and superlattices. Quantum dots can be nanoparticles of semiconductors such as cadmium selenide (CdSe), cadmium telluride (CdTe), lead sulfide (PbS), indium arsenide (InAs), etc.

[0090] like Fig.30 As shown in the cross-sectional view 3000 of FIG. 3001 , a mask 3001 is formed for etching a second hole 3003 through the oxide layer 241. The first conductive line 233 is exposed at the bottom of the second hole 3003. The etching process may be dry etching such as plasma etching or any other suitable process. After etching, the mask 3001 may be stripped.

[0091] like Fig.31As shown in the cross-sectional view 3100 of FIG. 3100 , the second hole 3003 is filled with a semiconductor material having a high thermoelectric quality factor and P-type doping to form a P-type via 221. The P-type dopant may be, for example, boron (B), aluminum (Al), gallium (Ga), indium (In), etc. The P-type via 221 and the N-type via 225 may be different semiconductor materials in addition to being semiconductors with different doping types.

[0092] like Fig.32 As shown in the cross-sectional view 3200 of , dielectric 903 may be formed over P-type via 221 and N-type via 225. Dielectric 903 may be a conventional dielectric, such as silicon dioxide (SiO2), a high thermal conductivity dielectric layer, or an extremely high thermal conductivity dielectric layer, and may be deposited by PVD, CVD, ALD, or any other suitable process.

[0093] like Fig.33 As shown in the cross-sectional view 3300 of FIG. 3300 , a mask 3301 for etching a trench 3303 in the dielectric 903 may be formed. After etching, the mask 3301 may be stripped. Fig.34 As shown in the cross-sectional view 3400 of FIG. 3400 , the trench 3303 may then be filled to form the second conductive line 213. The composition and formation method for the second conductive line 213 are similar to those for the first conductive line 233. The dielectric 903 and the second conductive line 213 constitute the second wiring layer 217. Forming the second wiring layer 217 completes the formation of the TEC 463.

[0094] like Fig.35 As shown in the cross-sectional view 3500 of FIG. 35, the remaining layers of the passivation stack 811 may be deposited over the second wiring layer 217. These may include an upper etch stop layer 539 and a barrier layer 535. Each of these layers may be deposited by PVD, CVD, ALD, etc., or any other suitable process.

[0095] like Fig.36 As shown in the cross-sectional view 3600 of FIG. 36, a mask 3601 is formed for etching the first hole 3603 and the second hole 3605. The upper etch stop layer 539 and the lower etch stop layer 551 facilitate these etching processes. The etching can be a dry etch, such as a plasma etch, etc. The first hole 3603 can be partially etched before the second hole 3605, or the etching of these holes at different depths can be done in two different processes with two different masks. If the TEC is made similar to Fig. 6A TEC 663, there is no need to form the second hole 3605. After etching, the mask 3601 can be stripped.

[0096] like Fig.37As shown in the cross-sectional view 3700 of FIG. 3700 , a conductive material may be deposited to fill the first hole 3603 and the second hole 3605 and thereby form the first through hole 507, the second through hole 531, the third through hole 511 and the fourth through hole 527. The composition and deposition method for the conductive material may be as described for the through hole 2305 of the backside metal interconnect structure 751.

[0097] like Fig.38 As shown in the cross-sectional view 3800 of FIG. 3 , a pad layer 810 may be formed over the passivation stack 811. The pad layer 810 may include a dielectric 521 and a contact pad 807. The contact pad 807 may be formed by a damascene process, etc., or some other suitable process. The contact pad 807 is a metal that provides a solderable surface, and may be or include, for example, copper (Cu), tungsten (W), gold (Au), palladium (Pd), platinum (Pt), titanium (Ti), tantalum (Ta), aluminum (Al), alloys thereof, etc.

[0098] like Fig.39 As shown in the cross-sectional view 3900 of FIG. 39, C4 solder bumps 809 can be placed on contact pads 807. C4 solder bumps 809 can be alloys of metals such as lead (Pb), tin (Sn), copper (Cu), silver (Ag), gold (Au), nickel (Ni), etc. In some embodiments, C4 solder bumps 809 are eutectic alloys. In some embodiments, C4 solder bumps 809 have a width W3 in a range from about 10 microns to about 100 microns. In some embodiments, C4 solder bumps 809 have a pitch P2 in a range from about 10 microns to about 300 microns.

[0099] like Fig.40 As shown in the cross-sectional view 4000, Fig.39 The partially fabricated device shown in cross-sectional view 3900 of FIG. 39 (which includes semiconductor substrate 747 and carrier substrate 709) can be connected to wiring layer 763 via C4 solder bumps 809. Before placement on wiring layer 763, thermal paste 4001 can be applied around C4 solder bumps 809 to increase thermal conduction across C4 connection layer 755.

[0100] like Fig.41 As shown in the cross-sectional view 4100 of , a thermal interface material 705 can be applied over a carrier substrate 709, and then a cover 703 can be attached. The thermal interface material 705 increases the heat transfer to the cover 703, and the cover 703 helps to dissipate the heat to the surrounding environment. The cover 703 can be metal or other material with similar high thermal conductivity.

[0101] like Fig.42 As shown in the cross-sectional view 4200 of FIG. 4 , solder bumps 157 may be placed on wiring layer 763 to provide solder connection layer 145. Solder connection layer 145 may be used to connect Fig.42 The partially fabricated device shown in cross-sectional view 4200 is attached to a printed circuit board 147 to provide a Figure 7 Thermal paste 143 may be placed around solder bumps 157 to increase heat transfer from wiring layer 763 to printed circuit board 147 (see Figure 7 ).

[0102] Figure 43 to Figure 46 A variation of the above process is shown. This variation can be used to form IC devices such as Fig.10 IC device 1001, wherein TEC 463 is located in C4 connection layer 755 instead of in backside metal interconnect structure 751 (compare Figure 7 and Fig.10 )

[0103] like Fig.43 As shown in the cross-sectional view 4300, the process steps may begin at Figures 13 to 23 and Figures 35 to 38 The steps shown in FIG. 8 produce a device similar to FIG. 8A except that TEC 463 is formed in passivation stack 811. Fig.38 The device shown in the cross-sectional view 3800 (compare Fig.38 ).like Fig.44 The cross-sectional view 4400 is shown. Then execute Figures 24 to 34 The TEC 463 is formed on the pad layer 810 .

[0104] like Fig.45 As shown in the cross-sectional view 4500 of , a mask 4501 may then be formed for etching through the high thermal conductivity dielectric 1107 and the oxide layer 241 to produce an opening 4503. Fig.46 As shown in the cross-sectional view 4600 of FIG. 460 , the C4 solder bump 809 can be placed in the opening 4503. In these embodiments, the TEC 463 can have a height similar to the C4 solder bump 809. In some embodiments, the C4 solder bump 809 has a height ranging from about 10 microns to about 100 microns. Multiple TECs 463 can be stacked together to achieve this height.

[0105] Up to and including placement of C4 solder bumps 809, semiconductor substrate 747 may be in the form of wafer 4700, which is Fig.47 4700 includes scribe lines 4701 that divide the wafer 4700 into a plurality of dies 4703. Fig.47As shown in the expanded portion of FIG. 4 , each die 4703 may include multiple TECs 463 dispersed within an array of C4 solder bumps 809. After placing the C4 solder bumps 809, the wafer 4700 may be separated into dies by dicing along scribe lines 4701. After dicing, processing may continue, such as Figure 42 to Figure 44 4000 - 4200. If desired, wafer 4700 may be separated into dies prior to placement of C4 solder bumps 809.

[0106] The C4 solder bumps 809 and TEC 463 may have any suitable arrangement in the C4 connection layer 755 (see Fig.10 ). Fig.48 A plan view of a die 4800 is provided in which the TECs 463 are clustered in the center and the C4 solder bumps 809 are arranged around the periphery. The TECs 463 clustered in the center may be merged into one TEC 463 that is wider than any C4 solder bump 809.

[0107] The above-described process provides an IC device having a TEC that can be formed during wafer level processing. Figures 49 to 51 A process of integrating a separately fabricated TEC into a 3D-IC package is shown.

[0108] like Fig.49 As shown in the cross-sectional view 4900 of , the process may begin by placing solder microbumps 161 on the first wiring layer 139. Fig.50 As shown in the cross-sectional view 5000 of FIG. 5 , the TEC 163 may be placed on the first wiring layer 139 and connected to the first wiring layer 139 via solder microbumps 161. Thermal paste 5001 may be applied to increase heat transfer from the first wiring layer 139 to the TEC 163. At this stage of the process, the passive device 171 may also be placed on the first wiring layer 139 and connected to the first wiring layer 139 via solder microbumps 161.

[0109] like Fig.51 As shown in the cross-sectional view 5100 of , solder bumps 157 may be placed on the first wiring layer 139 adjacent to or around the TEC 163 to form a BGA in the solder connection layer 145. Thermal paste 143 may be applied around the solder bumps 157. Fig.51 The structure shown in the cross-sectional view 5100 corresponds to Figure 1 3D-IC device 101. 3D-IC device 101 can be attached to printed circuit board 147 to produce Figure 1 device 100.

[0110] Fig.52A flow chart of a method 5200 for forming an apparatus including an IC device is provided. Although the method 5200 is shown and described below as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be interpreted as limiting. For example, some steps may occur in a different order and / or occur simultaneously with other steps or events other than those shown and / or described herein. In addition, not all of the steps shown may be necessary to implement one or more aspects or embodiments described herein. In addition, one or more of the steps depicted herein may be performed in one or more different steps and / or stages.

[0111] Method 5200 may begin at step 5201, FEOL processing of a semiconductor substrate. In some embodiments, this includes forming a buried rail. Figures 13 to 17 Examples are provided in cross-sectional views 1300-1700.

[0112] The method may continue to step 5203, BEOL processing. BEOL processing forms metal interconnect structures on the front side of the semiconductor substrate. Fig.18 An example is provided in cross-sectional view 1800 .

[0113] Step 5205 is to attach the semiconductor substrate to a carrier substrate. Connections are made through metal interconnect structures so that the carrier substrate is located on the front side of the semiconductor substrate. Fig.19 An example is provided in cross-sectional view 1900 .

[0114] Step 5207 is to thin the semiconductor substrate from the back side. Fig. 20 An example is provided in cross-sectional view 2000 .

[0115] Step 5209 is to form TSVs through the thinned semiconductor substrate from the back side. Figure 21 to Figure 22 Examples are provided in cross-sectional views 2100-2200.

[0116] Step 5211 is to form a backside metal interconnect structure to a certain extent before forming a passivation layer. Fig.23 An example is provided in cross-sectional view 2300 .

[0117] Step 5213 is to form a passivation layer over the backside metal interconnect structure with the TEC. Figures 24 to 37 The cross-sectional views 2400-3700 of FIG. 2 provide examples. Fig.54 Method 5400 describes the process of forming a TEC in more detail.

[0118] Step 5215 is to form a pad layer above the passivation layer. Fig.38 An example is provided in cross-sectional view 3800 .

[0119] Step 5217 is to deposit C4 solder bumps on the pad layer. Fig.39 An example is provided in cross-sectional view 3900 .

[0120] Step 5219 is to cut the partially manufactured semiconductor device. So far, the semiconductor substrate is in the form of a wafer. Fig.47 A plan view of a wafer is shown, showing the locations of the scribe lines used to cut the wafer.

[0121] Step 5221 is to bond to the interposer via a C4 solder connection. Fig.40 An example is provided in cross-sectional view 4000 .

[0122] Step 5223 is to apply thermal interface material and attach the cover. Fig.41 An example is provided in cross-sectional view 4100 .

[0123] Step 5225 is the placement of the BGA. Fig.42 An example is provided in cross-sectional view 4200. Step 5227 is attachment to a printed circuit board via a BGA.

[0124] Fig.53 A flow chart for method 5300 is provided. Method 5300 and Fig.52 The method 5300 is similar to the method 5200, in which a pad layer is formed through step 5215, except that, in the method 5300, the step of forming a TEC in the passivation stack of the backside metal interconnect structure is postponed. Fig.43 Cross-sectional view 4300 provides an example of the resulting structure.

[0125] The method continues with step 5301, where a TEC is formed above the pad layer. This process can be similar to Fig.52 The method 5200 is the same as those used to form the TEC. Fig.44 An example is provided in cross-sectional view 4400 .

[0126] Step 5303 is masking and etching through the layer containing the TEC to form an opening. Fig.45 An example is provided in cross-sectional view 4500 of . Step 5305 is to place a C4 solder bump in the opening. Fig.46 An example is provided by the cross-sectional view 4600 of FIG. 5300 . Then, the method 5300 may be performed in the same manner as the method 5200 .

[0127] Fig.54 A flow chart of a method 5400 for forming a TEC is provided. The method 5400 can be implemented during wafer level processing.

[0128] Method 5400 begins at step 5401 by forming a bottom thermally conductive dielectric layer. In some embodiments, the dielectric is a high thermal conductivity dielectric. In some embodiments, the dielectric is an extremely high thermal conductivity dielectric. Fig.24 An example is provided in cross-sectional view 2400 .

[0129] Step 5403 is to form a first wiring layer. Figure 24 to Figure 26 Examples are provided in cross-sectional views 2400-2600.

[0130] Step 5405 is to deposit an oxide layer. The oxide layer has low thermal conductivity. Fig. 27 An example is provided in cross-sectional view 2700 .

[0131] Step 5407 is to form an N-type via in the oxide layer. Figure 28 to Figure 29 Examples are provided in cross-sectional views 2800-2900.

[0132] Step 5409 is to form a P-type via in the oxide layer. Figure 30 to Figure 31 The cross-sectional views 3000-3100 of provide examples. The order of step 5407 and step 5409 can be reversed without consequence.

[0133] Step 5411 is to form a second wiring layer. Figure 32 to Figure 34 Examples are provided in cross-sectional views 3200-3400.

[0134] Step 5413 forms a top thermally conductive dielectric layer. In some embodiments, the dielectric is a high thermal conductivity dielectric. In some embodiments, the dielectric is an extremely high thermal conductivity dielectric. Fig.35 An example is provided in cross-sectional view 3500 .

[0135] Fig.55 A flow chart of a method 5500 for forming an IC device is provided. Although method 5500 is shown and described below as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be interpreted as limiting. For example, some steps may occur in a different order and / or occur simultaneously with other steps or events other than those shown and / or described herein. In addition, not all of the steps shown may be necessary to implement one or more aspects or embodiments described herein. In addition, one or more of the steps depicted herein may be performed in one or more different steps and / or stages.

[0136] Method 5500 begins at step 5501 by forming a first portion of an IC package. The IC package includes at least one IC chip having a semiconductor substrate. Step 5503 is placing solder microbumps on one of the device layers in the package. Fig.49 An example is provided in cross-sectional view 4900 .

[0137] Step 5505 is to place at least one TEC on the microbump. During this same processing stage, passive devices can be placed on other microbumps. Fig.50 An example is provided in cross-sectional view 5000 .

[0138] Step 5507 is to place solder bumps to form a BGA in the device layer containing the TEC. The solder bumps can be placed around the TEC. Fig.51 An example is provided in cross-sectional view 5100 .

[0139] Step 5509 is to connect the IC package to the printed circuit board via BGA. Figure 1 An example of the resulting structure is provided by the device.

[0140] Some aspects of the disclosed embodiments relate to an apparatus having an integrated circuit (IC) device and a thermoelectric cooler between a dielectric substrate and a semiconductor substrate. The thermoelectric cooler (TEC) is configured to transfer heat from the semiconductor substrate to the dielectric substrate. In some embodiments, all or part of the TEC is located within a passivation stack at the top of a first metal interconnect structure disposed on a first side of the semiconductor substrate. In some embodiments, the passivation stack includes a layer of an extremely high thermal conductivity dielectric. In some embodiments, there is a cover above the semiconductor substrate. The cover covers the side of the semiconductor substrate opposite to the dielectric substrate. In some embodiments, the dielectric substrate is a printed circuit board.

[0141] In some embodiments, the semiconductor device and the second metal interconnect are disposed on opposite sides of the semiconductor substrate. A through substrate via forms a connection between a power rail in the first metal interconnect structure and the semiconductor device. In some embodiments, a buried rail is disposed in the semiconductor substrate near the first side, and the TSV is connected to the buried rail.

[0142] Some aspects of the disclosed embodiments relate to an integrated circuit (IC) device, comprising: a substrate having a solder connection located above a first side; and a TEC located in a layer having the solder connection such that the TEC is transverse to the solder connection. The TEC is configured to draw heat away from the first substrate. In some embodiments, the TEC includes a high thermal conductivity dielectric layer. In some embodiments, the TEC includes an extremely high thermal conductivity dielectric layer. In some embodiments, the TEC is located between two solder bumps in the solder connection. In some embodiments, the substrate is a wafer.

[0143] In some embodiments, the substrate has a first metal interconnect structure on a first side and a second metal interconnect structure on a second side opposite to the first side. The semiconductor device is disposed on the second side. A substrate through-hole in the substrate is connected to provide power from the first metal interconnect structure to the semiconductor device.

[0144] In some embodiments, the semiconductor substrate is bonded to the second side of the first substrate, and the solder connection comprises a BGA. In some embodiments, the BGA is located between the first substrate and the printed circuit board.

[0145] Some aspects of the disclosed embodiments relate to a method for manufacturing an integrated circuit (IC) device. The method includes: forming a metallization layer above a substrate; forming a first connection layer above the metallization layer, wherein the first connection layer includes a first wire; depositing a dielectric layer above the first connection layer; patterning a first hole in the dielectric layer; filling the first hole with a first semiconductor having a P-type doping to form a P-type via; patterning a second hole in the dielectric layer; filling the second hole with a second semiconductor having an N-type doping to form an N-type via; performing planarization, wherein the planarization provides a planarized surface, and the planarized surface includes the dielectric layer, the P-type via, and the N-type via; and forming a second connection layer above the planarized surface, wherein the second connection layer includes a second wire. The first wire forms a first connection between the P-type via and the N-type via. The second wire forms a second connection between the P-type via and the N-type via.

[0146] In some embodiments, the method further comprises: forming a layer of high thermal conductivity dielectric over the second connection layer. In some embodiments, the second connection layer comprises a high thermal conductivity dielectric.

[0147] In some embodiments, a passivation stack and a pad layer are formed over the metallization layer, and a dielectric layer is formed over the pad layer. In some embodiments, the method further comprises: etching a hole extending through the dielectric layer; and placing a solder bump in the hole.

[0148] In some embodiments, the method further comprises: forming a semiconductor device on a second side of the substrate. In these embodiments, the substrate is a semiconductor substrate, and the second side is opposite to the first side. A metal interconnect structure is formed on the second side. The semiconductor substrate is bonded to a carrier substrate via the metal interconnect structure. The semiconductor substrate is thinned from the first side, and after thinning, a second metal interconnect structure comprising a metallization layer is formed. In some embodiments, the method further comprises: forming a buried rail in the second side; coupling the semiconductor device to the buried rail; and forming a substrate through-hole, through which power can be provided to the buried rail. In some embodiments, the semiconductor substrate is a wafer.

[0149] Some embodiments of the present application provide a semiconductor device, comprising: a semiconductor substrate having a first side and a second side, wherein the second side is opposite to the first side; a dielectric substrate; and a thermoelectric cooler located between the dielectric substrate and the semiconductor substrate, wherein the thermoelectric cooler is configured to transfer heat from the semiconductor substrate to the dielectric substrate.

[0150] In some embodiments, the semiconductor device further comprises: a first metal interconnect structure disposed on the first side, wherein the first metal interconnect structure comprises a first plurality of metallization layers and a passivation stack, the passivation stack being located above the first plurality of metallization layers, and at least a portion of the thermoelectric cooler being located within the passivation stack. In some embodiments, the passivation stack comprises a layer of a very high thermal conductivity dielectric. In some embodiments, the semiconductor device further comprises: a second metal interconnect structure comprising a second plurality of metallization layers, wherein the second metal interconnect structure is disposed on the second side; a semiconductor device disposed on the second side; a power rail disposed in the first metal interconnect structure; and a substrate through-via disposed in the semiconductor substrate and coupling the power rail to the semiconductor device. In some embodiments, the semiconductor device further comprises: a cover disposed above the semiconductor substrate, wherein the cover covers a side of the semiconductor substrate opposite to the dielectric substrate.

[0151] Other embodiments of the present application provide an integrated circuit (IC) device, comprising: a first substrate having a first side and a second side, wherein the second side is opposite to the first side; a solder connection located above the first side; and a thermoelectric cooler located in a layer having the solder connection, such that the thermoelectric cooler is transverse to the solder connection, wherein the thermoelectric cooler is configured to draw heat away from the first substrate.

[0152] In some embodiments, the thermoelectric cooler includes a high thermal conductivity dielectric layer. In some embodiments, the thermoelectric cooler includes an extremely high thermal conductivity dielectric layer. In some embodiments, the solder connection includes two solder bumps, and the thermoelectric cooler is located between the two solder bumps. In some embodiments, the integrated circuit device further includes: a first metal interconnect structure and a second metal interconnect structure, the first metal interconnect structure including a first plurality of metallization layers located on the first side, and the second metal interconnect structure including a second plurality of metallization layers located on the second side; a semiconductor device disposed on the second side; and a substrate through-hole disposed in the first substrate and connected to provide power from the first metal interconnect structure to the semiconductor device. In some embodiments, the integrated circuit device further includes: a semiconductor substrate; wherein the semiconductor substrate is bonded to the second side; and the solder connection includes a ball grid array. In some embodiments, the thermoelectric cooler includes a first through-hole of an N-type semiconductor and a second through-hole of a P-type semiconductor connected in series.

[0153] Some other embodiments of the present application provide a method for manufacturing an integrated circuit (IC) device, the method comprising: forming a metallization layer over a first side of a substrate; forming a first connection layer over the metallization layer, wherein the first connection layer comprises a first conductive line; depositing a dielectric layer over the first connection layer; patterning a first hole in the dielectric layer; filling the first hole with a first semiconductor having a P-type doping to form a P-type via; patterning a second hole in the dielectric layer; filling the second hole with a second semiconductor having an N-type doping to form an N-type via; performing planarization, wherein the planarization provides a planarized surface, and the planarized surface comprises the dielectric layer, the P-type via, and the N-type via; and forming a second connection layer over the planarized surface, wherein the second connection layer comprises a second conductive line; wherein the first conductive line forms a first connection between the P-type via and the N-type via; and the second conductive line forms a second connection between the P-type via and the N-type via.

[0154] In some embodiments, the method further comprises: forming a layer of a high thermal conductivity dielectric over the second connection layer. In some embodiments, the second connection layer comprises a high thermal conductivity dielectric. In some embodiments, the method further comprises: forming a passivation stack and a pad layer over the metallization layer, wherein the dielectric layer is formed over the pad layer. In some embodiments, the method further comprises: etching a hole extending through the dielectric layer; and placing a solder bump in the hole. In some embodiments, the method further comprises: forming a semiconductor device on a second side of the substrate, wherein the substrate is a semiconductor substrate and the second side is opposite to the first side; forming a metal interconnect structure on the second side; bonding the semiconductor substrate to a carrier substrate through the metal interconnect structure; and thinning the semiconductor substrate from the first side before forming the metallization layer on the first side. In some embodiments, the method further comprises: forming a buried rail in the second side; coupling the semiconductor device to the buried rail; and forming a substrate through hole, through which power can be provided to the buried rail. In some embodiments, the substrate is a wafer.

[0155] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device comprising: a semiconductor substrate having a first side and a second side, wherein the second side is opposite to the first side; a dielectric substrate; and A thermoelectric cooler is located between the dielectric substrate and the semiconductor substrate, wherein the thermoelectric cooler is configured to transfer heat from the semiconductor substrate to the dielectric substrate.

2. The semiconductor device according to claim 1, further comprising: A first metal interconnect structure is disposed on the first side, wherein the first metal interconnect structure includes a first plurality of metallization layers and a passivation stack, the passivation stack is located above the first plurality of metallization layers, and at least a portion of the thermoelectric cooler is located within the passivation stack.

3. The semiconductor device according to claim 2, wherein: The passivation stack includes a layer of very high thermal conductivity dielectric.

4. The semiconductor device according to claim 2, further comprising: a second metal interconnect structure comprising a second plurality of metallization layers, wherein the second metal interconnect structure is disposed on the second side; a semiconductor device disposed on the second side; a power rail located in the first metal interconnect structure; and A through substrate via is located in the semiconductor substrate and couples the power rail to the semiconductor device.

5. The semiconductor device according to claim 1, further comprising: A cover is located over the semiconductor substrate, wherein the cover covers a side of the semiconductor substrate opposite to the dielectric substrate.

6. An integrated circuit (IC) device comprising: a first substrate having a first side and a second side, wherein the second side is opposite to the first side; a solder connection over the first side; and A thermoelectric cooler is located in a layer having the solder connection such that the thermoelectric cooler is lateral to the solder connection, wherein the thermoelectric cooler is configured to draw heat away from the first substrate.

7. The integrated circuit device according to claim 6, wherein: The thermoelectric cooler includes a high thermal conductivity dielectric layer.

8. The integrated circuit device according to claim 6, wherein: The thermoelectric cooler includes a very high thermal conductivity dielectric layer.

9. The integrated circuit device according to claim 6, wherein: The solder connection includes two solder bumps, and the thermoelectric cooler is located between the two solder bumps.

10. A method of manufacturing an integrated circuit (IC) device, the method comprising: forming a metallization layer over the first side of the substrate; forming a first connection layer above the metallization layer, wherein the first connection layer comprises a first conductive line; depositing a dielectric layer over the first connecting layer; patterning a first hole in the dielectric layer; Filling the first hole with a first semiconductor having a P-type doping to form a P-type through hole; patterning a second hole in the dielectric layer; filling the second hole with a second semiconductor having N-type doping to form an N-type through hole; performing planarization, wherein the planarization provides a planarized surface, and the planarized surface includes the dielectric layer, the P-type via, and the N-type via; and forming a second connection layer over the planarized surface, wherein the second connection layer includes a second conductive line; wherein the first conductive line forms a first connection between the P-type through hole and the N-type through hole; and The second conductive line forms a second connection between the P-type via and the N-type via.

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